JP2011043658A - Semiconductor integrated circuit device and image processing system - Google Patents

Abstract

A semiconductor integrated circuit device and an image processing system that can reduce the amount of data transfer and do not require an external distribution unit.
An input unit, a dividing unit that divides image data input from the input unit into a desired size, and a semiconductor integrated circuit that outputs one output of the dividing unit to the outside are newly provided. An output means 5 and a processing means 6 for processing the other output of the dividing means 4 in the semiconductor integrated circuit are provided. Further, the output means of one semiconductor integrated circuit device 12 and the input means of another semiconductor integrated circuit device 13 are connected to each other to be processed in a subordinate manner.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit device and an image processing system, and more particularly to a semiconductor integrated circuit device and an image processing system that can reduce a data transfer amount and do not require an external distribution unit.

  At present, the driving circuit of a liquid crystal TV is generally realized by an integrated circuit, but has been complicated and diversified due to a demand for high added value. FIG. 10 shows a conventional panel drive LSI (Patent Document 1), which is a panel drive LSI equipped with a function of doubling the frame frequency (hereinafter referred to as a double speed function).

  The operation will be described with reference to FIG. In the panel display drive LSI 41, the image data from the previous stage LSI is input to the input buffer 42 and passed to the input processing unit 43. The input processing unit 43 performs data processing so that the main signal processing circuit 44 in the subsequent stage can perform processing, and outputs the processed data. In the main signal processing circuit 44, the frame frequency is doubled by a double speed functional block (not shown) and input to a panel display drive block (not shown).

  In a panel display drive block (not shown), the image data is converted into a numerical value suitable for the display device by the gamma correction and response speed improvement block, and is output to the output processing unit 45. The output processing unit 45 converts the image data into a format suitable for the display device and outputs it to the display device via the output buffer 46.

  FIG. 11 shows the positional relationship of the panel display driving LSI 41 in the liquid crystal TV system. The image processing LSI 11 is arranged in the preceding stage and connected to the LCD panel 52 via the column driver 51 in the succeeding stage. The LCD panel 52 has the capability of enabling double frame frequency display (hereinafter, 120 Hz driving), and the frame frequency is increased from 60 Hz to 120 Hz by the panel display driving LSI 41 to improve display quality.

  Next, FIG. 12 shows an example of a configuration that realizes quadruple frame frequency display (hereinafter, 240 Hz driving) using the panel display driving LSI 41. In FIG. 12, image data with a frame frequency of 60 Hz output from the image processing LSI 11 is input to the distributor 60, and the image data is output to the two panel display drive LSIs 61 and 62. Since the general distributor 60 has no memory means, the output image data to the two panel display drive LSIs 61 and 62 is the same, the panel display drive LSI 61 processes the right screen, and the panel display drive LSI 62 processes the left screen. It will be. Here, the panel display drive LSI 61 and the panel display drive LSI 62 are the same LSI as the panel display drive LSI 41, but are given different numbers to process the left and right screens. That is, the panel display driving LSI 61 and the panel display driving LSI 62 that can realize a full screen of 120 Hz driving with one chip can realize a half-screen display of 240 Hz driving in terms of data rate. The right screen of the LCD panel 65 and the panel display driving LSI 62 are configured to process the left screen of the LCD panel 65 via the column driver 64.

  FIG. 13 shows a configuration of the panel display substrate 81 when a conventional panel display driving LSI is used and displays on a 240 Hz driving panel. Since the panel display driving LSI has the capability of displaying the FHD1 screen, two LSIs (61, 62) are required for display on the 240 Hz panel. Not only the distributor 60 but also the number of differential signals increases. Specifically, there are three types of differential signals of data for one FHD half screen driven by 60 Hz and two types of differential signals of data for FHD 1/2 screen driven by 240 Hz, leading to an increase in panel display board area. .

JP2007-328345

  However, as described above, when the 240 Hz drive is realized by using the panel display drive LSI 41, a distributor is required in the previous stage, which leads to a cost increase. Although it is not impossible to make a 240 Hz drive on a single chip, which eliminates the need for a distributor, due to the evolution of the semiconductor process, it becomes over-spec for 120 Hz drive and the cost is not suitable for use.

  In addition, for example, there is a demand for realizing a resolution display called 4K2K, and at least four panel display drive LSIs 41 are required for the display. Even in such a case, there is a problem that a function of distributing by some means is necessary, leading to an increase in cost.

  The present invention has been made in view of such a problem. By adding an image data dividing unit and an image data output unit to a semiconductor integrated circuit device such as a panel display driving LSI, a plurality of chips are connected. It is an object to enable connection, reduce the need for external distribution means, and reduce the amount of data transfer, thereby enabling power saving and low EMI.

In order to achieve the above object, a semiconductor integrated circuit device of the present invention includes an input unit, a dividing unit that divides image data input from the input unit into a desired size, and one output of the dividing unit externally. Output means newly provided in the semiconductor integrated circuit to output, and processing means for processing the other output of the dividing means in the semiconductor integrated circuit.
The semiconductor integrated circuit device according to the present invention includes an input unit, a dividing unit that divides the image data input from the input unit into a desired size, and a semiconductor integrated circuit that outputs one output of the dividing unit to the outside. Output means that also serves as the conventional output means, and processing means for processing the other output of the dividing means within the semiconductor integrated circuit.
Further, the semiconductor integrated circuit device of the present invention divides the data processed by the input processing means, the input processing means for performing certain processing on the image data inputted from the input means, and the input processing means into a desired size. A dividing unit; an output unit newly provided in a semiconductor integrated circuit that outputs one output of the dividing unit to the outside; and a processing unit that processes the other output of the dividing unit in the semiconductor integrated circuit. It is characterized by.

Furthermore, in the semiconductor integrated circuit device of the present invention, the total amount of image data output from the output means to the outside is reduced as compared with the total data amount of the semiconductor integrated circuit device input from the input means. It is characterized by that.
The image processing system according to the present invention includes a plurality of semiconductor integrated circuit devices, and the output means of one semiconductor integrated circuit device and the input means of another semiconductor integrated circuit device are connected in cascade. It is processed.

  According to the present invention, by adding an image data dividing unit and an image data output unit to a semiconductor integrated circuit device such as a panel display driving LSI, a daisy chain connection can be made in the case of using a plurality of chips and distributed to the outside. No means is required and the amount of data transfer can be reduced, thus enabling power saving and low EMI.

The block diagram explaining 1st Embodiment. The block diagram explaining the example of a connection of a 1st embodiment. The block diagram explaining the data division circuit of a 1st embodiment. The figure explaining FHD 1 screen. The figure explaining FHD 1 screen. FIG. 3 is a configuration diagram showing an example of a panel display substrate on which the display drive LSI of the first embodiment is mounted. The block diagram explaining 2nd Embodiment. The block diagram explaining the example of a connection of 2nd Embodiment. The block diagram explaining the example of a connection of 2nd Embodiment. The block diagram explaining a prior art example. The block diagram explaining the example of a connection of a prior art example. The block diagram explaining the example of a connection of a prior art example. The block diagram which shows the example of the panel display board | substrate which mounts the conventional panel display drive LSI.

  A mode for carrying out the present invention will be described.

  Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. In FIG. 1, reference numeral 1 denotes a panel display drive LSI, and image data from the previous-stage LSI is input to the input processing unit 3 via the input buffer 2. The input processing unit 3 performs data processing so as to be processed by the data division circuit 4 and the main signal processing circuit 6 in the subsequent stage and outputs the processed data. The data dividing circuit 4 divides or passes the input image data based on the control signal output from the main signal processing circuit 6 and outputs the divided data as data A and data B. For example, if the control signal output from the main signal processing circuit 6 to the data dividing circuit 4 is “through”, the image data is not divided and the input image data is output as the data A. If the control signal output from the main signal processing circuit 6 to the data division circuit 4 is “two divisions”, the left screen image data is output as the data A, and the right screen image data is output as the data B. In the main signal processing circuit 6, data A is input, the frame frequency is doubled by a double speed functional block (not shown), and is input to a panel display drive block (not shown). In a panel display drive block (not shown), the image data is converted into a numerical value suitable for the display device by the gamma correction and response speed improvement block, and is output to the output processing unit 7. The output processing unit 7 converts the image data into a format suitable for the display device, and outputs it to the display device via the output buffer 8.

  The detailed operation of the data dividing circuit 4 will be described with reference to FIGS. In FIG. 3, the image data input to the data dividing circuit 4 is input to the division processing unit 9, and is divided or passed through by the control signal input. Here, for example, if the value of the control signal input is “2 divisions”, the output data A0 of the division processing unit 9 includes the left screen data (1920 × 1080 Pixel (hereinafter referred to as FHD) 1 screen data in FIG. 4). 960 Pixel) is output, and the right screen data (960 Pixel) of the FHD1 screen data in FIG. 4 is output to the output data B 0 of the division processing unit 9.

  Next, the data A0 and the data B0 are input to the data selection unit 10, and an output destination is selected by inputting a control signal, and image data is sent to the subsequent stage as data A and data B.

  The operation in the case of performing 240 Hz drive display by connecting two panel display drive LSIs 1 (panel display drive LSIs 12 and 13) in a daisy chain will be described with reference to FIG. In FIG. 2, the image data output 17 of the image processing LSI 11 is input to the panel display driving LSI 12, and the image data is divided by the data dividing circuit in the panel display driving LSI 12. Of the divided image data, the data on the left screen side is input to the panel display driving LSI 13 as the image data output 18, and the panel display driving LSI 13 “throughs” the data dividing circuit and outputs the main signal of the panel display driving LSI 13. The image data output 20 is output through the processing circuit and the output processing unit. On the other hand, the data on the right screen side divided by the data dividing circuit in the panel display driving LSI 12 is output as the image data output 19 through the main signal processing circuit and the output processing unit in the panel display driving LSI 12.

  That is, the panel display driving LSI 12 and the panel display driving LSI 13 that can realize a full screen of 120 Hz driving with one chip can realize a half-screen display of 240 Hz driving in terms of data rate, and therefore the panel display driving LSI 12 passes through the column driver 15. The right screen of the LCD panel 16 and the panel display drive LSI 13 are configured to process the left screen of the LCD panel 16 via the column driver 14.

  Here, in the first embodiment, as shown in FIG. 4, the size of “two divisions” is 960 pixels on the left and right, but the case of “two divisions” is not limited to 960 pixels. As shown in FIG. 5, the data dividing circuit 4 in FIG. 3 is configured to be capable of, for example, 1000 pixels on the left and right. This is because the panel display drive LSI 12 and the panel display drive LSI 13 in FIG. 2 process the right screen and the left screen independently, and therefore, there is a problem in image quality at the boundary of each screen, that is, in the center. there is a possibility. Therefore, the above-described image quality defects can be avoided by performing processing including an overlap portion in advance and outputting the image with an appropriate number of pixels in the output processing unit 7 of FIG.

  FIG. 6 shows a panel display substrate 82 on which the panel display driving LSI of this embodiment is mounted. Since the panel display driving LSI is equipped with newly provided output means, LSIs (12, 13) can be connected in a daisy chain, the number of differential signals can be reduced, and the panel display substrate area can be reduced. More specifically, there are two types of differential signals of data for one FHD half screen driven by 60 Hz, and two types of differential signals of data for FHD 1/2 screen driven by 240 Hz.

  The difference between FIG. 6 and FIG. 13 described in the conventional example is “a differential signal of data for FHD1 screen driven at 60 Hz”. It becomes the signal. Since the LVDS signal is sensitive to signal quality, if possible, wiring on the surface layer on the panel display substrate, equal-length wiring, etc. are required. If the number increases, the substrate area increases. Further, in the panel display driving LSI, when the LVDS signal is increased by 12 pairs, there is a possibility that the area of the LSI is increased (that is, the LSI unit price is increased). It is not uncommon for the scale built-in memory to be mounted, and it can often be said that the increase in pins does not increase the LSI area.

  A second embodiment of the present invention will be described with reference to the drawings. In FIG. 7, data B, which is the output of the data dividing circuit 4, is input to the data selection unit 24 with respect to the panel display drive LSI 1 of FIG. 1. The data selection unit 24 receives the data B and data L, which is one output of the main signal processing circuit 26, selects an input signal based on the control signal 2 output from the main signal processing circuit 26, and outputs the output processing unit 23. Output to.

  Here, the operation when displaying on a panel having a resolution of 1920 × 1080 pixels will be described with reference to FIGS. The panel display driving LSI 25 divides the output buffer into two types, the output buffer 22 for right screen display and the output buffer 21 for left screen display. The panel display drive LSI 25 can display on a panel having a resolution of 1920 × 1080 pixels, and is indicated by the panel display drive LSI 27 in FIG. The output buffer 22 of the panel display drive LSI 27 is connected to the right screen column driver 31, and the output buffer 21 of the panel display drive LSI 27 is connected to the left screen column driver 32 to drive the LCD panel 33.

  The operation of the panel display driving LSI 25 in FIG. 7 at this time will be described. Image data from the preceding LSI is input to the input processing unit 3 via the input buffer 2. The input processing unit 3 performs data processing so that processing can be performed in the subsequent data division circuit 4 and the main signal processing circuit 26, and outputs the processed data. The data dividing circuit 4 divides or passes the input image data based on the control signal 1 output from the main signal processing circuit 26 and outputs it as data A and data B. Here, since the display is 1920 × 1080 Pixel, the control signal 1 output from the main signal processing circuit 26 to the data dividing circuit 4 is “through”, and the image data is not divided and is input to the data A. Image data is output. In the main signal processing circuit 26, the data A is input, the frame frequency is doubled by a double speed functional block (not shown), and is input to a panel display drive block (not shown). In a panel display drive block (not shown), the gamma correction and response speed improvement block converts the image data into a numerical value suitable for the display device, and outputs it to the output processing unit 23 and the data selection unit 24. Here, the data R output to the output processing unit 23 is for right screen display, and the data L output to the data selection unit 24 is for left screen display. The data selection unit 24 selects an input by the control signal 2, selects data L to display the left screen of the LCD panel 33, and outputs the output to the output processing unit 23. The output processing unit 23 converts the image data into a format suitable for the display device, and outputs the right screen display data via the output buffer 22 and the left screen display data via the output buffer 21 to the display device.

  Next, the operation when two panel display drive LSIs 25 (panel display drive LSIs 28 and 29) are connected in cascade and displayed on the panel 41 having a resolution of 2560 × 1080 pixels will be described with reference to FIG. In FIG. 9, the image data output 37 of the image processing LSI 11 is input to the panel display drive LSI 28, and the output buffer 22 of the panel display drive LSI 28 is connected to the right screen column driver 38 via the image data output 42, and panel display drive is performed. The output buffer 21 of the LSI 28 is input to the panel display drive LSI 29 as the image data output 43. The output buffer 22 of the panel display driving LSI 29 is connected to the middle screen column driver 39 via the image data output 44, and the output buffer 21 of the panel display driving LSI 29 is connected to the left screen column driver 40 via the image data output 45. Is done.

  The operation of the panel display driving LSI 28 and the panel display driving LSI 29 in FIG. 9 will be described using the panel display driving LSI 25 in FIG.

  Image data 37 having a resolution of 2560 × 1080 pixels output from the image processing LSI 11 that is the preceding LSI is input to the input processing unit 3 via the input buffer 2 in the panel display driving LSI 28. The input processing unit 3 performs data processing so that processing can be performed in the subsequent data division circuit 4 and the main signal processing circuit 26, and outputs the processed data. The data dividing circuit 4 divides or passes the input image data based on the control signal 1 output from the main signal processing circuit 26 and outputs it as data A and data B. Here, since the display is in 2560 × 1080 pixels, it is assumed that the panel display driving LSI 28 displays the right part of the panel and the panel display driving LSI 29 displays the remaining part. That is, the panel display driving LSI 28 processes data for 640 × 1080 pixels, and the panel display driving LSI 29 can process 2560 × 1080 pixels by processing data for 1920 × 1080 pixels.

  Therefore, in the panel display driving LSI 28, the control signal 1 output from the main signal processing circuit 26 to the data dividing circuit 4 is “3 divisions”, the image data is divided into 3 parts, and the data A contains the input image data. 1/3 on the right side is output, and 2/3 on the left side is output as data B. In the main signal processing circuit 26, the data A is input, the frame frequency is doubled by a double speed functional block (not shown), and is input to a panel display drive block (not shown). In a panel display drive block (not shown), the gamma correction and response speed improvement block converts the image data into a numerical value suitable for the display device, and outputs it to the output processing unit 23 and the data selection unit 24. Here, the data R output to the output processing unit 23 is for right screen display, and the data L output to the data selection unit 24 is meaningless data. In the data selection unit 24, the input is selected by the control signal 2, the data B is selected to display the left screen 2/3 of the LCD panel 41, and the output is output to the output processing unit 23. The output processing unit 23 converts the image data into a format suitable for the display device, and outputs the right screen display data via the output buffer 22 and the left screen display data via the output buffer 21 to the display device.

  Next, the panel display drive LSI 29 processes data for 1920 × 1080 pixels, and the image data output 43 is input to the input processing unit 3 via the input buffer 2. The input processing unit 3 performs data processing so that processing can be performed in the subsequent data division circuit 4 and the main signal processing circuit 26, and outputs the processed data. The data dividing circuit 4 divides or passes the input image data based on the control signal 1 output from the main signal processing circuit 26 and outputs it as data A and data B. Here, since the display is 1920 × 1080 Pixel, the control signal 1 output from the main signal processing circuit 26 to the data dividing circuit 4 is “through”, and the image data is not divided and is input to the data A. Image data is output. In the main signal processing circuit 26, the data A is input, the frame frequency is doubled by a double speed functional block (not shown), and is input to a panel display drive block (not shown). In a panel display drive block (not shown), the gamma correction and response speed improvement block converts the image data into a numerical value suitable for the display device, and outputs it to the output processing unit 23 and the data selection unit 24. Here, the data R output to the output processing unit 23 is for displaying the central screen of the LCD panel 41, and the data L output to the data selecting unit 24 is for displaying the left screen of the LCD panel 41. The data selection unit 24 selects an input by the control signal 2, selects data L to display the left screen of the LCD panel 41, and outputs the output to the output processing unit 23. The output processing unit 23 converts the image data into a format suitable for the display device, and outputs the central screen display data via the output buffer 22 and the left screen display data via the output buffer 21 to the display device.

  As a concept of the second embodiment, in a panel display driving LSI that originally has one output buffer that is driven on each of the left screen and the right screen, an output buffer that is not used when multiple LSIs are used is effective. In this case, it is not necessary to provide a new output buffer. The number of output buffers of the panel display driving LSI is not determined, but is determined by the panel size or the number of column drivers. In general, when the panel size is small, the number of column drivers is small, and the output buffer of the panel display driving LSI that drives them is small. On the other hand, the FHD panel requires a considerable number of column drivers and needs to be driven on each of the left screen and the right screen (for example, 14 column drivers are required, 7 for the left screen and 7 for the right screen). Drive the column driver separately.) For this reason, the number of output buffers also increases. In these cases, the output buffer of the second embodiment can also be used as a conventional output buffer.

1, 12, 13, 25, 27, 28, 29, 41, 61, 62 Panel display drive LSI
2, 42 Input buffer 3, 43 Input processing unit 4 Data division circuit 5, 8, 21, 22, 46 Output buffer 6, 26, 44 Main signal processing circuit 7, 23, 45 Output processing unit 9 Division processing unit 10, 24 Data selection unit 11 Image processing LSI
14, 15, 31, 32, 38, 39, 40, 63, 64 Column driver 16, 33, 41, 52, 65 LCD panel 60 Distributor 71 Connector 81, 82 Panel display board

Claims (5)

  An input means; a dividing means for dividing the image data input from the input means into a desired size; an output means newly provided in a semiconductor integrated circuit for outputting one output of the dividing means to the outside; and the dividing And a processing means for processing the other output of the means in the semiconductor integrated circuit.   An input unit, a dividing unit that divides image data input from the input unit into a desired size, and an output unit that is also used as a conventional output unit of a semiconductor integrated circuit that outputs one output of the dividing unit to the outside And a processing means for processing the other output of the dividing means within the semiconductor integrated circuit.   An input unit; an input processing unit that performs a certain process on the image data input from the input unit; a dividing unit that divides the data processed by the input processing unit into a desired size; and one output of the dividing unit A semiconductor integrated circuit device comprising: output means newly provided in a semiconductor integrated circuit for outputting the signal to the outside; and processing means for processing the other output of the dividing means within the semiconductor integrated circuit. In the semiconductor integrated circuit device according to any one of claims 1 to 3,
The total amount of image data output from the output means for outputting one output of the dividing means to the outside is reduced as compared with the total data amount of the semiconductor integrated circuit device input from the input means. A semiconductor integrated circuit device. In an image processing system provided with two or more semiconductor integrated circuit devices according to any one of claims 1 to 3,
An image processing system, wherein the output means of one semiconductor integrated circuit device and the input means of another semiconductor integrated circuit device are connected to each other and connected to be processed.

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