JP2011040766A - Epitaxial substrate for electronic device and manufacturing method therefor - Google Patents

Abstract

The present invention provides an epitaxial substrate for an electronic device that achieves both a reduction in lateral leakage current and a lateral breakdown voltage characteristic, and improves a vertical breakdown voltage.
A main laminate 4 having a channel layer 4a and an electron supply layer 4b, in which a group III nitride layer is epitaxially grown on a buffer 3 on a Si substrate 1, is provided, and the buffer is initially grown in contact with the Si substrate. has a superlattice laminate 6 comprising a superlattice multilayer structure on the layer 5 and the initial growth layer, the initial growth layer is made of AlN material, wherein the superlattice laminate from _{B a 1 Al b1 Ga c1 in} d1 N material It becomes the first layer 6a and the first layer formed by laminating a second layer 6b made of different _{B a 2 Al b 2 Ga c} 2 in d 2 N material band gap, the superlattice laminate, the main The portion on the buffer side of the channel layer constituting the laminate has a C concentration of 1 × 10 ¹⁸ / cm ³ or more, and the portion on the electron supply layer side of the channel layer has a C concentration of 4 × 10 ¹⁶ / cm ³ or less. It is characterized by being.
[Selection] Figure 2

Description

  The present invention relates to an epitaxial substrate for electronic devices and a method for manufacturing the same, and more particularly to an epitaxial substrate for HEMT and a method for manufacturing the same.

  In recent years, with the increase in speed of IC devices and the like, a high electron mobility transistor (HEMT) has been widely used as a high-speed field effect transistor (FET). In such a field effect transistor, for example, as schematically shown in FIG. 1, a channel layer 22 and an electron supply layer 23 are stacked on a substrate 21, and a source electrode 24, It is formed by disposing the drain electrode 25 and the gate electrode 26, and when the device operates, electrons move in the order of the source electrode 24, the electron supply layer 23, the channel layer 22, the electron supply layer 23, and the drain electrode 25, The lateral direction is the current conduction direction, and the movement of electrons in the lateral direction is controlled by the voltage applied to the gate electrode 26. In HEMT, electrons generated at the junction interface between the electron supply layer 23 and the channel layer 22 having different band gaps can move at a higher speed than in a normal semiconductor.

  As described above, the movement of electrons in the lateral direction, that is, the current is controlled by the gate voltage, but in general, the current does not become zero even when the gate voltage is turned off. The current that flows when the gate voltage is OFF is referred to as a leakage current. When the leakage current increases, power consumption increases, resulting in problems such as heat generation. This leakage current is generally divided into a lateral leakage current and a longitudinal leakage current. The lateral leakage current is between two electrodes (for example, a source electrode 24 and a drain electrode 25 arranged on the surface of the electron supply layer 23). The vertical leakage current refers to the leakage current flowing between the two electrodes disposed on the surface on the electron supply layer 23 side and on the surface on the substrate 21 side, respectively.

  In Patent Document 1, a HEMT including a buffer layer, a carbon concentration transition layer, a channel layer, and an electron supply layer is formed on a substrate so that the carbon concentration increases from the channel layer toward the buffer layer. A technique for reducing the lateral leakage current generated in the buffer layer and the carbon concentration transition layer and improving the lateral breakdown voltage is disclosed.

  Patent Document 2 discloses that in a semiconductor device having a superlattice buffer layer, a channel layer, and an electron supply layer on a substrate, the lateral leakage current of the semiconductor electronic device is reduced by adding carbon to the superlattice buffer layer. A technique for suppressing and improving the lateral withstand voltage is disclosed.

  Further, Patent Document 3 discloses a first group III nitride underlayer formed on a single crystal substrate and a second group III nitride formed on the first group III nitride underlayer. Including the acceptor impurity at the interface with the base layer, and reducing the concentration of the acceptor impurity in the thickness direction of the second group III nitride underlayer from the interface, the lateral leakage current of the semiconductor electronic device is suppressed. Techniques to do this are disclosed.

  By the way, when the HEMT is operated at a high frequency, it is necessary to reduce the leakage current and reduce the loss when applying a high frequency signal. This loss is caused by a capacitive or inductive interaction with the electrode placed on the surface of the substrate when the charge is present in the substrate or the epitaxial film on it and the depletion layer does not spread efficiently. is there.

  Therefore, Patent Document 4 discloses a technique for reducing the loss of the semiconductor electronic device in the high frequency region by increasing the specific resistance of the Si single crystal substrate to prevent the mixing of impurities, thereby reducing carriers. .

  However, in the invention described in Patent Document 1, when a group III nitride layer is grown on a substrate, a GaN-based low-temperature buffer layer is used. There was a problem that a through defect was generated and the vertical breakdown voltage was deteriorated. Moreover, although the invention described in Patent Document 2 can suppress leakage in the superlattice buffer layer, it cannot sufficiently suppress leakage at the interface between the channel layer and the superlattice buffer layer. It was a cause of deterioration of the breakdown voltage. Further, Patent Documents 3 and 4 do not consider the vertical breakdown voltage, and no consideration is given to the breakdown voltage of the buffer layer. Therefore, when applied to a semiconductor substrate such as a Si substrate, the vertical breakdown voltage is ensured. I could not.

JP 2007-251144 A JP-A-2005-85852 JP 2003-282598 A Special table 2008-522447

  An object of the present invention is to provide an epitaxial substrate for an electronic device and a method for manufacturing the same that can satisfactorily achieve a reduction in lateral leakage current and a lateral withstand voltage characteristic and can improve a longitudinal withstand voltage.

In order to achieve the above object, the gist of the present invention is as follows.
(1) Si single crystal substrate, a buffer as an insulating layer formed on the Si single crystal substrate, and a channel layer and an electron that are sequentially stacked by epitaxially growing a plurality of group III nitride layers on the buffer An epitaxial substrate for an electronic device comprising a main laminate having a supply layer and having a lateral direction as a current conduction direction, wherein the buffer includes an initial growth layer in contact with the Si single crystal substrate and a superstructure on the initial growth layer. At least a superlattice laminate having a lattice multilayer structure, the initial growth layer is made of an AlN material, and the superlattice laminate is B _a1 Al _b1 Ga _c1 In _d1 N (0 ≦ a ₁ ≦ 1, 0 ≦ b ₁ ≤ 1, 0 ≤ c ₁ ≤ 1, 0 ≤ d ₁ ≤ 1, a ₁ + b ₁ + c ₁ + d ₁ = 1, except when b ₁ and c ₁ are both 0 B _a2 Al _b2 Ga _c2 In _d2 N (0 ≦ a ₂ ≦ 1, 0 ≦ b ₂ ≦ 1, 0 ≦ c ₂ ≦ 1, 0 ≦ d ₂ ≤ 1, a ₂ + b ₂ + c ₂ + d ₂ = 1, except when both b ₂ and c ₂ are 0. ) The superlattice layer is formed by alternately laminating second layers made of materials . body and, buffer-side portion of the channel layer forming the main laminate, both C concentration Ri der 1 × 10 ¹⁸ / cm ³ or more, and the electron supply layer side of the channel layer forming the main laminate In the part, the C concentration is 4 × 10 ¹⁶ / cm ³ or less .

(2) The first layer is made of an AlN material, and the second layer is made of an Al _b2 Ga _c2 N (a ₂ = 0, 0 <b ₂ ≦ 0.5, 0.5 ≦ c ₂ <1, d ₂ = 0) material. The epitaxial substrate for electronic devices as described in said (1).

(3) The Si single crystal substrate has a specific resistance of 1000 Ω · cm or more, and a total maximum concentration of group III atoms from the initial growth layer to a depth of 0.1 μm is 1 × 10 ¹⁶ / cm ³ or less. And the epitaxial substrate for electronic devices as described in said (1) or (2) whose total density | concentration of the group III atom in the position of 0.3 micrometer depth from the said initial stage growth layer is 1 * 10 < ¹⁵ > / cm < ³ > or less.

(4) On the Si single crystal substrate, a buffer as an insulating layer and a plurality of group III nitride layers were epitaxially grown on the buffer to form a main laminate having a channel layer and an electron supply layer in order. A method of manufacturing an epitaxial substrate for an electronic device having a lateral direction as a current conduction direction, wherein the buffer includes an initial growth layer in contact with the Si single crystal substrate and a superlattice multilayer structure on the initial growth layer At least a stacked body, the initial growth layer is made of an AlN material, and the superlattice stacked body is B _a1 Al _b1 Ga _c1 In _d1 N (0 ≦ a ₁ ≦ 1, 0 ≦ b ₁ ≦ 1, 0 ≦ c ₁ ≦ 1, 0 ≦ d ₁ ≦ 1, a ₁ + b ₁ + c ₁ + d ₁ = 1, except when b ₁ and c ₁ are both 0. B _a2 Al _b2 Ga _c2 In _d2 N (0 ≦ a ₂ ≦ 1, 0 ≦ b ₂ ≦ 1, 0 ≦ c ₂ ≦ 1, 0 ≦ d ₂ ≦ 1, a ₂ + _{b 2 + c 2 + d 2} = 1, where b ₂ and c ₂ excluding both the case of zero.) becomes the second layer of material are laminated alternately, the superlattice laminate, buffer-side portion of the channel layer forming the main laminate Both of them are formed so that the C concentration is 10 ¹⁸ / cm ³ or more, and the portion of the channel layer constituting the main laminate on the electron supply layer side has a C concentration of 4 × 10 ¹⁶ / cm ³ or less. A method of manufacturing an epitaxial substrate for an electronic device, characterized by comprising:

(5) The Si single crystal substrate has a specific resistance of 1000 Ω · cm or more, and a total maximum concentration of group III atoms from the initial growth layer to a depth of 0.1 μm is 1 × 10 ¹⁶ / cm ³ or less. In addition, the epitaxial substrate for electronic devices according to (4), wherein the total concentration of group III atoms at a depth of 0.3 μm from the initial growth layer is 1 × 10 ¹⁵ / cm ³ or less. Method.

An epitaxial substrate for an electronic device according to the present invention includes an initial growth layer made of an AlN material, a buffer having a predetermined superlattice laminate, and a predetermined main laminate, and the superlattice laminate and a portion of the main laminate on the buffer side However, both of them have a C concentration of 1 × 10 ¹⁸ / cm ³ or more, so that not only the reduction of the lateral leakage current and the lateral withstand voltage characteristic can be made good, but also the longitudinal withstand voltage can be improved.

Further, the present invention comprises an initial growth layer made of an AlN material and a buffer having a predetermined superlattice laminate and a predetermined main laminate, and both the superlattice laminate and the buffer side portion of the main laminate are both provided. By having a C concentration of 1 × 10 ¹⁸ / cm ³ or more, the epitaxial substrate for electronic devices can not only achieve a good reduction in lateral leakage current and a good lateral breakdown voltage characteristic, but also improve the vertical breakdown voltage. Can be manufactured.

Furthermore, in the epitaxial substrate for electronic devices of the present invention, the Si single crystal substrate has a specific resistance of 1000 Ω · cm or more, and the total maximum concentration of group III atoms from the initial growth layer to a depth of 0.1 μm is 1 × 10. and ¹⁶ / cm ³ or less, and by the initial growth layer on the total concentration of the group III atoms at the position of depth 0.3μm and 1 × 10 ¹⁵ / cm ³ or less, in addition to the effects described above, during high-frequency operation Loss can be reduced.

Further, the present invention provides a Si single crystal substrate having a specific resistance of 1000 Ω · cm or more and a maximum total concentration of group III atoms from the initial growth layer to a depth of 0.1 μm of 1 × 10 ¹⁶ / cm ³ or less. In addition to the above-mentioned effects, the loss during high-frequency operation is achieved by forming the total concentration of group III atoms at a depth of 0.3 μm from the initial growth layer to be 1 × 10 ¹⁵ / cm ³ or less. It is possible to manufacture an epitaxial substrate for electronic devices that can reduce the above.

It is a typical sectional view showing a general field effect transistor. It is typical sectional drawing of the epitaxial substrate for electronic devices according to this invention. (a), (b), and (c) are graphs showing measurement results of lateral withstand voltage, lateral leak current, and longitudinal withstand voltage, respectively. (a), (b), and (c) are graphs showing measurement results of lateral withstand voltage, lateral leak current, and longitudinal withstand voltage, respectively. (a), (b) is the graph which showed the result of SIMS, and the result of CV measurement, respectively. (a), (b) is the graph which showed the result of SIMS, and the result of CV measurement, respectively. (a), (b) is the graph which showed the result of SIMS, and the result of CV measurement, respectively.

  Next, an embodiment of the epitaxial substrate for electronic devices of the present invention will be described with reference to the drawings. FIG. 2 schematically shows a cross-sectional structure of an epitaxial substrate for an electronic device according to the present invention. Note that FIG. 2 shows the thickness direction exaggerated for convenience of explanation.

As shown in FIG. 2, an electronic device epitaxial substrate 1 according to the present invention is an electronic device epitaxial substrate whose lateral direction is a current conduction direction, and is formed on a Si single crystal substrate 2 and a Si single crystal substrate 2. A buffer 3 as an insulating layer, and a main laminate 4 having a channel layer 4a and an electron supply layer 4b formed by sequentially stacking a plurality of group III nitride layers on the buffer 3 and epitaxially growing them. Has at least an initial growth layer 5 in contact with the Si single crystal substrate 2 and a superlattice laminate 6 having a superlattice multilayer structure on the initial growth layer 5, the initial growth layer 5 is made of an AlN material, and is a superlattice laminate. The field 6 is B _a1 Al _b1 Ga _c1 In _d1 N (0 ≦ a ₁ ≦ 1, 0 ≦ b ₁ ≦ 1, 0 ≦ c ₁ ≦ 1, 0 ≦ d ₁ ≦ 1, a ₁ + b ₁ + c ₁ + d ₁ = 1, except when b ₁ and c ₁ are both 0. ) A first layer 6a made of a material and the first layer 6a B _a2 Al _b2 Ga _c2 In _d2 N (0 ≦ a ₂ ≦ 1, 0 ≦ b ₂ ≦ 1, 0 ≦ c ₂ ≦ 1, 0 ≦ d ₂ ≦ 1, a ₂ + b ₂ + c ₂ + d ₂ = 1, except when b ₂ and c ₂ are both 0. ) Superlattice laminate 6 and main laminate 4 are formed by alternately laminating second layers 6b made of materials . buffer 3 side of the portion of the channel layer 4a constituting the the state, and are both C concentration 1 × 10 ¹⁸ / cm ³ or more, and part of the electron supply layer 4b side of the channel layer 4a constituting the main laminate 4 Is characterized in that the C concentration is 4 × 10 ¹⁶ / cm ³ or less, and by having such a configuration, not only the reduction of the lateral leakage current and the lateral withstand voltage characteristics can be achieved well, but also the longitudinal withstand voltage Can be improved.

  The plane orientation of the Si single crystal substrate 2 is not particularly specified, and (111), (100), (110) planes, etc. can be used, but the (0001) plane of group III nitride is grown with good surface flatness. For this purpose, it is desirable to use the (111) plane. Moreover, it may be p-type or n-type conductivity type. As for the conductivity of the Si single crystal substrate 2, a high resistivity substrate having a high insulation property of 10,000 Ω · cm or more and a low resistivity substrate having a resistivity of about 0.001 Ω · cm can be appropriately used depending on the application. As a method for producing the Si single crystal substrate 2, various methods such as CZ method and FZ method can be used, and Si, SiC and the like can be epitaxially grown on the substrate surface. Further, it is possible to use a substrate in which a thin film made of an oxide film, a nitride film, or a carbonized film is formed.

  In particular, when an epitaxial substrate for electronic devices having excellent high frequency characteristics is produced, it is preferable to use a substrate having a specific resistance of 1000 Ω · cm or more. Such a substrate is desirably manufactured by the FZ method, which can easily purify the Si crystal.

  In addition, by forming the initial growth layer 5 with an AlN material, the reaction with the Si single crystal substrate 2 is suppressed, and the vertical breakdown voltage can be improved. This is because when the initial growth layer 5 is formed of a group III nitride material containing Ga and In, Ga and In react with Si of the substrate to generate a defect and induce a through defect in the epitaxial film. The purpose is to suppress the decrease in the longitudinal breakdown voltage. However, the AlN material here may contain trace impurities of 1% or less regardless of intended or unintentional, for example, Ga, In, Si, H, O, C, Impurities such as B, Mg, As, and P can be included.

In particular, when fabricating an epitaxial substrate for electronic devices with excellent high frequency characteristics, the Si single crystal substrate has a specific resistance of 1000 Ω · cm or more, and the total of group III atoms from the initial growth layer to a depth of 0.1 μm It is preferable that the maximum concentration of the first group is 1 × 10 ¹⁶ / cm ³ or less, and the total concentration of group III atoms at a depth of 0.3 μm from the initial growth layer is 1 × 10 ¹⁵ / cm ³ or less. By using a substrate with a high specific resistance, the depletion layer can be effectively expanded, and when an electronic device operates at a high frequency due to capacitive or inductive coupling between carriers formed on the substrate surface and charges existing on the substrate. Loss can be suppressed. In particular, it is preferable that the specific resistance value of the Si single crystal substrate is 5000 Ω · cm or more, and the loss during high-frequency operation tends to be saturated. In addition, since the group III atom functions as a p-type impurity in the Si single crystal substrate, by setting the above concentration range, the electrode formed on the substrate surface and the capacitive or inductive property of the p-type impurity can be obtained. Loss during high frequency operation of the electronic device due to coupling can be suppressed. The impurity concentration is measured using SIMS analysis. In this case, the impurity concentration distribution in the depth direction is measured while etching from the back side (substrate side). At this time, it is desirable that the impurity concentration of Al is smaller than the impurity concentration of Ga. This is because Al has lower activation energy than Ga and is more likely to generate p-type carriers.

In this way, in order to produce an epitaxial substrate for electronic devices with excellent high frequency characteristics, in order to prevent contamination of impurities into the Si single crystal substrate during epitaxial growth,
It is important to 1) lower the deposition temperature, and 2) to suppress the island-like growth of the initial growth layer AlN and promote two-dimensional growth. In order to realize the above 2), it is desirable to suppress excessive nitridation of the surface of the Si polycrystalline substrate and to make the nitride film thickness smaller than 1 nm or not nitride. If the surface of the Si single crystal substrate is excessively nitrided, the raw material diffusion rate at the outermost surface of the substrate increases, and AlN grows in an island shape. This is because it is presumed that the group raw material will diffuse.

By setting the C concentration of the superlattice laminate 6 to 1 × 10 ¹⁸ / cm ³ or more, the vertical breakdown voltage is improved, and the C concentration of the portion 4 ′ on the buffer 5 side of the main laminate 4 is 1 × 10 ¹⁸ / By setting it to cm ³ or more, the lateral breakdown voltage can be improved and the lateral leakage current can be suppressed. In order to prevent generation of pits due to excessive increase of impurities, the C concentration is preferably less than 1 × 10 ²⁰ / cm ³ . The amount of other impurities is not particularly specified, but it is preferable to suppress the incorporation of donor impurities (Si, O, Ge) having relatively shallow impurity levels, but to the extent that such donor levels can be compensated. If C is contained, a certain amount of contamination is allowed. In addition, the impurity concentration measured the impurity concentration distribution of the depth direction, etching from the surface side using SIMS analysis.

  Here, “the lateral direction is the current conduction direction” means that a current flows from the source electrode 24 to the drain electrode 25 mainly in the width direction of the stacked body as shown in FIG. This means that the current flows mainly in the longitudinal direction, that is, in the thickness direction of the stacked body, as in a structure in which a semiconductor is sandwiched between a pair of electrodes.

  In addition, here, alternately laminating superlattice laminates means laminating so as to periodically include the first layer 6a and the second layer 6b. It is possible to include a layer (for example, a composition transition layer) other than the first layer 6a and the second layer 6b.

The C concentration of the portion 4 ′ on the buffer 3 side of the channel layer 4 a constituting the main laminate 4 is preferably higher than the C concentration of the superlattice laminate 6. In the portion 4 ′, a phenomenon in which dislocations bend horizontally or obliquely due to the difference in the lattice constant between the buffer 3 and the main laminate 4 is observed, and a path through which a leak current easily flows is formed. Therefore, the portion 4 'is more likely to have a leakage current than the buffer layer 3, and in order to suppress this leakage current, the C concentration as described above is desirable. Further, if the thickness of the portion 4 ′ on the buffer 3 side of the main laminate 4 is less than 0.1 μm, there is a possibility that dislocation bends may be prominent even in a portion with a low C concentration. It is preferable to set to. The upper limit of the thickness of the portion 4 ′ is not particularly specified from the viewpoint of improving the breakdown voltage and reducing the leakage current, and is appropriately set from the viewpoint of suppressing warpage and cracking of the substrate. At this time, when changing the composition of the group III element only in the portion 4 ', or changing the C concentration or the composition of the group III element in the portion on the opposite side of the buffer layer of the channel layer 4a from the portion 4'. Can be changed steeply or continuously.

The first layer 6a constituting the superlattice laminate 6 is made of an AlN material, and the second layer 6b is Al _b2 Ga _c2 N (a ₂ = 0, 0 <b ₂ ≦ 0.5, 0.5 ≦ c ₂ <1, d ₂ = 0) It is preferably made of a material. Since the band gap difference between the first layer 6a and the second layer 6b improves the longitudinal breakdown voltage, it is preferable to make the composition difference as large as possible and the band gap difference as large as possible. When a mixed crystal is formed from a group III nitride semiconductor material, the largest band gap difference is AlN (6.2 eV) and GaN (3.5 eV). Therefore, it is preferable to form a superlattice structure using an AlGaN material. If the lower limit of the compositional difference is less than 0.5, stress relaxation due to the difference in lattice constant between the Si single crystal and the group III nitride becomes insufficient and cracks are generated, so the compositional difference is preferably 0.5 or more. As for the upper limit of the composition difference, it is desirable that the composition difference is large. However, since the insulation of the AlGaN layer itself advances and the breakdown voltage is improved, the second layer having a small band gap should contain at least Al, and the composition of Al The difference is preferably smaller than 1. This is because when at least Al is contained, C can be taken in more efficiently. It is preferable that the number of superlattice pairs is at least 40 pairs or more because variations in breakdown voltage can be reduced.

  Regarding the thickness of each layer, from the viewpoint of improving the withstand voltage, the thickness of the first layer 6a having a large band gap should be not less than a thickness at which tunnel current can be suppressed and not more than a thickness at which cracks do not occur. preferable. For example, when AlN is used, it is preferably set to 2 to 10 nm. The thickness of the second layer 6b is appropriately set from the viewpoint of crack suppression and warpage control, but in order to effectively exhibit the strain buffering effect of the superlattice laminate structure and suppress the occurrence of cracks, The thickness of the small layer is preferably thicker than that of the layer having a large band gap and is 40 nm or less. Further, it is not always necessary to laminate the superlattice laminate with the same film thickness and the same composition.

The epitaxial substrate 1 for electronic devices is preferably used for HEMT. The main laminate 4 of the epitaxial substrate 1 shown in FIG. 2 is composed of B _a3 Al _b3 Ga _c3 In _d3 N (0 ≦ a3 ≦ 1, 0 ≦ b3 ≦ 1, 0 ≦ c3 ≦ 1, 0 ≦ d3 ≦ 1, a3 + b3 + c3 + d3 = 1) channel layer 4a made of material and B _a4 Al _b4 Ga _c4 In _d4 N (0 ≦ a4 ≦ 1, 0 ≦ b4 ≦ 1, 0 ≦ c4 ≦ 1) having a larger band gap than the channel layer 4a , 0 ≦ d4 ≦ 1, a4 + b4 + c4 + d4 = 1) The electron supply layer 4b made of a material can be provided. At this time, both layers can be composed of a single composition or a plurality of compositions. In particular, in order to avoid alloy scattering and to lower the specific resistance of the current conducting portion, it is preferable that at least a portion of the channel layer 4a in contact with the electron supply layer 4b is made of a GaN material.

The portion of the channel layer 4a opposite to the buffer layer preferably has a low C concentration, and is preferably set to 4 × 10 ¹⁶ / cm ³ or less. This is because this portion corresponds to a current conducting portion of the electronic device, and therefore it is desirable that the portion not contain impurities that impede conductivity or generate current collapse. Further, in order to suppress leakage due to residual carriers due to n-type impurities, it is desirable to exist at 1 × 10 ¹⁵ / cm ³ or more.

  Next, an embodiment of a method for producing an epitaxial substrate for an electronic device according to the present invention will be described with reference to the drawings.

As shown in FIG. 2, a HEMT structure having a channel layer and an electron supply layer obtained by epitaxially growing a buffer 3 as an insulating layer on a Si single crystal substrate 2 and a plurality of group III nitride layers on the buffer 3. In which the lateral direction is the current conduction direction, the buffer 3 includes an initial growth layer 5 in contact with the Si single crystal substrate 2 and an initial growth. The superlattice laminate 6 having a superlattice multilayer structure on the layer 5 is provided, the initial growth layer 5 is made of an AlN material, and the superlattice laminate 6 is B _a1 Al _b1 Ga _c1 In _d1 N (0 ≦ a ₁ ≤1, 0≤b ₁ ≤1, 0≤c ₁ ≤1, 0≤d ₁ ≤1, a ₁ + b ₁ + c ₁ + d ₁ = 1, provided that b ₁ and c ₁ are both 0 except.) the first layer 6a and the first layer 6a made of a material different band gaps _{B a2 Al b2 Ga c2 in d2} N (0 ≦ a 2 ≦ 1, 0 ≦ b 2 ≦ 1, 0 ≦ c 2 ≦ 1, 0 ≦ d ₂ ≦ 1 , a ₂ + b ₂ + c ₂ + d ₂ = 1, except when both b ₂ and c ₂ are 0. ) Superlattice layered product in which second layers 6b made of materials are alternately laminated. 6, the buffer 3 side of the portion of the channel layer 4a constituting the main laminate 4 are both C concentration Ri der 1 × 10 ¹⁸ / cm ³ or more and the channel layer 4a constituting the main laminate 4 The portion on the electron supply layer 4b side is characterized in that the C concentration is 4 × 10 ¹⁶ / cm ³ or less, and by having such a configuration, the longitudinal withstand voltage characteristic and the lateral withstand voltage characteristic are well balanced, And the epitaxial substrate for electronic devices which can reduce a horizontal direction leakage current can be manufactured.

When the C added to the portion 4 'on the buffer 3 side of the channel layer 4a constituting the superlattice laminate 6 and the main laminate 4 is grown using the CVD method, the following methods are used. Can be added. First method: A source gas containing C is added separately during group III nitride growth. Examples include methane, ethane, ethylene, acetylene, benzene, cyclopentane and the like. Second method: A methyl group, an ethyl group, or the like in the organic metal is mixed in the epitaxial growth layer according to the growth group III nitride growth conditions. The concentration of C added to the epitaxial growth layer can be adjusted by appropriately setting the growth temperature, growth pressure, growth rate, ammonia flow rate, hydrogen flow rate, nitrogen flow rate, etc. Is possible. In the present application, the C concentration of the superlattice laminate 6 is a measured value obtained by removing a half of the thickness of the superlattice laminate 6 by SIMS. The C concentration of the portion 4 ′ on the buffer 3 side of the main laminate 4 is a measured value obtained by removing a half of the thickness of the portion 4 ′ by SIMS.

  1 and 2 show examples of typical embodiments, and the present invention is not limited to these embodiments. For example, an intermediate layer that does not adversely affect the effects of the present invention can be inserted between the layers, another superlattice layer can be inserted, or the composition can be graded. In addition, a nitride film, a carbide film, an Al layer, or the like can be formed on the surface of the Si single crystal.

(Experimental example 1)
On a (111) 4 inch Si single crystal substrate with a specific resistance of 1 × 10 ^-1 Ω · cm, 1 × 10 Ω · cm, 2 × 10 ³ Ω · cm, 1 × 10 ⁴ Ω · cm and a thickness of 600 μm The initial growth layer (AlN material: thickness 100 nm) and superlattice stack (AlN: film thickness 4 nm and Al _0.15 Ga _0.85 N: film thickness 25 nm, total 85 layers) are grown to form a buffer, and this superlattice A channel layer (GaN material: thickness 1.5 μm) and an electron supply layer (Al _0.25 Ga _0.75 N material: thickness 20 nm) are epitaxially grown on the stack to form a main stack of HEMT structure, and samples 1 to 4 are formed. Obtained. The C concentration of the superlattice laminate was changed, and the C concentration in the buffer side portion of the channel layer constituting the main laminate was in the range of 1.5 to 2.0 × 10 ¹⁸ / cm ³ in all results. The portion of the channel layer on the electron supply layer side had a C concentration in the range of 0.8 to 3.5 × 10 ¹⁶ / cm ³ . Table 1 shows the growth temperature and pressure of each layer. Adjust the C concentration by adjusting the table in P _1, and increasing the C concentration by reducing the deposition pressure. As a growth method, MOCVD was used, TMA (trimethylaluminum) / TMG (trimethylgallium) was used as a group III material, ammonia was used as a group V material, and hydrogen and nitrogen gas were used as carrier gases. The film-forming temperature here means the temperature of the substrate itself measured using a radiation thermometer during growth. The C concentration SIMS measurement was performed by etching from the epitaxial layer side, using a Cameca measuring device, using Cs ⁻ as the ion source, and ion energy of 8 keV.

(Experimental example 2)
The same method as Sample 2 of Experimental Example 1 except that the initial growth layer was formed of a GaN material (thickness: 20 nm) grown at 700 ° C., and the growth temperature and pressure of each layer were performed under the conditions shown in Table 2. Sample 5 was prepared by the above.

3 (a), 3 (b) and 3 (c) show the measurement results of the lateral breakdown voltage, the lateral leakage current and the vertical breakdown voltage of Sample 2 and Sample 5. FIG. The measurement was performed as follows. Longitudinal direction: An ohmic electrode with a Ti / Al laminated structure of 80 μmφ is formed on the substrate surface, the outside of the ohmic electrode is etched to a thickness of 50 nm, the back surface of the substrate is grounded to a metal plate, and the current value flowing between both electrodes is measured Measured against voltage. Lateral direction: Ti / Al laminated structure ohmic electrodes consisting of 200μm square (squares) are formed with each side spaced apart by 10μm and etched around the ohmic electrode with a thickness of 150nm, then both electrodes The current value flowing between them was measured with respect to the voltage. At this time, in order to suppress discharge in the air, the two electrodes are insulated with insulating oil. Further, in order to eliminate the influence of leakage on the back surface of the substrate, an insulating plate is disposed under the substrate. In this experimental example, the vertical breakdown voltage is a voltage value in which the vertical current value converted to a value per unit area in the above electrode area reaches 10 ^-4 A / cm ² , and the horizontal breakdown voltage is the horizontal current. The value obtained by converting the value into a value per length of one side of the electrode reaches a voltage of 10 ⁻⁴ A / cm, and the lateral leakage current is defined as a current value at 100 V in the lateral direction. The C concentration of the superlattice laminate 6 was obtained by measuring a location where 1/2 of the thickness of the superlattice laminate 6 was removed by SIMS. The C concentration in the portion 4 ′ on the buffer 3 side of the main laminate 4 was obtained by measuring the location where 1/2 of the thickness of the portion 4 ′ was removed by SIMS.

As a result of changing the C concentration of the superlattice laminate, both the lateral breakdown voltage and the lateral leakage current hardly change, whereas the vertical breakdown voltage of sample 2 is the C concentration of the superlattice laminate. When it exceeds 1 × 10 ¹⁸ / cm ³ , it can be confirmed that it increases specifically and rapidly. Further, as can be seen with reference to the sample 5, it can be confirmed that such a phenomenon is a phenomenon inherent to the case where the initial growth layer is made of AlN. In addition, the same results as those of the sample 2 were obtained for the samples 1, 3 and 4.

(Experimental example 3)
The sample of Experimental Example 1 except that the growth pressure of the superlattice laminate was set to 10 kPa, the C concentration in the buffer side portion of the main laminate was changed, and the growth temperature and pressure of each layer were performed under the conditions shown in Table 3. Samples 6 to 9 were prepared in the same manner as in 1-4. Adjust the C concentration by adjusting the table in P _2, and increasing the C concentration by reducing the deposition pressure. The C concentration of the superlattice laminate was in the range of 1.5 to 2.5 × 10 ¹⁸ / cm ^{3 in} all results.

4A, 4B, and 4C show the measurement results of the lateral breakdown voltage, the lateral leakage current, and the vertical breakdown voltage of Sample 6. FIG. As a result of changing the C concentration of the main laminate, the lateral breakdown voltage and the lateral leakage current are hardly changed, whereas the vertical breakdown voltage of the sample 6 is the C concentration in the buffer side portion of the main laminate. It can be confirmed that when the value exceeds 1 × 10 ¹⁸ / cm ³ , it increases specifically and rapidly. Similarly to Experimental Example 1, the samples 7 to 9 having different specific resistances of the Si single crystal substrates to be used were not significantly different from the results shown in FIGS. 4 (a) to 4 (c). .

In Experimental Examples 1 to 3, in order to improve the vertical breakdown voltage, it was confirmed that the vertical breakdown voltage can be improved by setting the C concentration on the superlattice laminate and the channel layer buffer side to a predetermined value or more. In Experimental Example 4, the C concentration of the buffer layer was set to be equal to or higher than a predetermined value confirmed to be preferable in Experimental Examples 1 to 3, and an attempt was made to improve high-frequency characteristics.

(Experimental example 4)
An initial growth layer (AlN material: thickness 100 nm) and superlattice while suppressing the formation of an initial nitride layer on a (111) 4 inch Si single crystal substrate with a resistivity of 6 × 10 ³ Ω ・ cm and a thickness of 600 μm A stack (AlN: 4 nm thick and Al _0.15 Ga _0.85 N: 25 nm thick, total 85 layers) is grown to form a buffer, and a channel layer (GaN material: 1.5 μm thick) on this superlattice stack Then, an electron supply layer (Al _0.25 Ga _0.75 N material: thickness 20 nm) was epitaxially grown under the growth pressure and growth temperature conditions shown in Table 4 to form a main laminate having a HEMT structure, thereby obtaining a sample 10. The C concentration of the superlattice laminate was 2.0 × 10 ¹⁸ / cm ³ , and the C concentration of the 0.2 μm thick portion on the buffer side of the main laminate was 3.0 × 10 ¹⁸ / cm ³ . Further, the C concentration of the channel layer on the electron supply layer side is set to 1 × 10 ¹⁶ / cm ³ .

As a result of observing impurities in the Si single crystal substrate by SIMS, as shown in FIG. 5 (a), Group III element impurities other than Al and Ga are not recognized, and both Al and Ga are 1 × 10 ^The region of ¹⁶ / cm ³ or less and 1 × 10 ¹⁵ / cm ³ or more was a region within 0.2 μm from the interface between the Si single crystal and the initial growth layer. Although the interface between the Si single crystal substrate and the initial growth layer was confirmed by TEM, the presence of a SiN _x film having a thickness of 1 nm or more was not confirmed. It was also confirmed that the Al concentration was lower than the Ga concentration on average in the region within 0.2 μm from the interface between the Si single crystal substrate and the initial growth layer. In addition, SIMS measurement of Al and Ga was performed by etching from the Si single crystal side, using a measuring device made by Cameca, using O ²⁺ as an ion source, and ion energy at 3 keV.

  In addition, when this substrate was subjected to CV measurement using a mercury probe (manufactured by MSI electronics) and impedance analyzer (HP4284A), as shown in FIG. It was confirmed that it has spread. The frequency and amplitude of the AC component during CV measurement are 100 kHz and 10 mV, respectively. For convenience, the position of the interface between the Si single crystal and the initial growth layer is a position shifted from the position where the Si concentration is 1/5 or less to the 0.05 μm substrate side in SIMS measurement. This is to avoid an apparent increase in group III elements due to the mixed exposure of the Si single crystal and the epitaxial growth layer as a result of etching roughness during SIMS measurement.

In addition, the resistivity of the 4 inch Si single crystal substrate used was 2 × 10 ³ Ω · cm, 8 × 10 ³ Ω · cm, and 12 × 10 ³ Ω · cm. A similar test was performed on the fabricated samples 11, 12, and 13. In both of these tests, similarly to the above, when the impurities in the Si single crystal substrate were observed by SIMS, group III elements other than Al and Ga were not observed, and both Al and Ga were 1 × 10 ¹⁶ / cm ^{3 or} less, a region present 1 × 10 ¹⁵ / cm ³ or more, had the following regions 0.2μm from the interface of the Si single crystal and initial growth layer. The interface between the Si single crystal substrate and the initial growth layer was confirmed by TEM, but the presence of a SiN _x film having a thickness of 1 nm or more was not confirmed. It was also confirmed that the Al concentration was lower than that of Ga on average in the region of 0.2 μm or less from the interface between the Si single crystal substrate and the initial growth layer. In addition, it was confirmed that the depletion layer was converted to equivalent film thicknesses up to about 6 μm, 8 μm, and 8 μm, respectively.

(Experimental example 5)
On the (111) 4 inch Si single crystal substrate with a specific resistance of 5 × 10 ³ Ω · cm and a thickness of 600 μm, before starting the growth of the initial growth layer, 10% ammonia gas is contained in the carrier gas, hydrogen gas. A sample 14 was prepared in the same manner as the sample 2 except that the initial nitrided layer was intentionally formed by flowing only the prepared gas at 1050 ° C. for 5 minutes.

When the impurities in the Si single crystal substrate were observed by SIMS, as shown in FIG. 6A, both Al and Ga were 1 × 10 ¹⁶ / cm ³ or less, but Al or Ga was 1 × 10 ^{The area where 15} / cm ³ or more was present was 1 μm or more. When the interface between the Si single crystal substrate and the initial growth layer was confirmed by TEM, it was confirmed that the SiN _x film was present at about 1.5 nm. It was also confirmed that the concentration of Al was higher than that of Ga. Further, when CV measurement using a mercury probe was performed on this substrate, it was confirmed that the depletion layer spreads only to about 2 μm in terms of the equivalent film thickness as shown in FIG.

(Experimental example 6)
Sample 15 was fabricated in the same manner as Sample 10 except that the growth temperature of the channel layer was increased from the initial growth layer under the conditions shown in Table 5.

When the impurities in the Si single crystal substrate were observed by SIMS, as shown in FIG. 7 (a), there was a portion where the Ga concentration was 1 × 10 ¹⁶ / cm ³ or more, and 1 × 10 ¹⁵ / The area where cm ³ or more was present was 0.3 μm or less. The interface between the Si single crystal substrate and the initial growth layer was confirmed by TEM, but the presence of a SiN _x film having a thickness of 1 nm or more was not confirmed. It was also confirmed that the Al concentration was lower than that of Ga. Further, as shown in FIG. 7B, this substrate was subjected to CV measurement using a mercury probe. As a result, it was confirmed that the depletion layer spread only to about 2 μm in terms of the equivalent film thickness.

  Comparing Samples 1 to 13 with Samples 14 and 15 confirms that suppressing the mixing of Al and Ga into the Si single crystal leads to the effective expansion of the depletion layer. The ability to efficiently expand the depletion layer is synonymous with the reduction of carriers in the epitaxial layer and the Si single crystal substrate, and the electrode formed on the substrate surface and the capacitance of the p-type impurity. This means that the loss during high-frequency operation of the electronic device due to directional or inductive coupling can be suppressed. In particular, from the comparison between sample 2 and sample 14, it was inferred that the above effect could be brought out by reducing the nitride thickness and reducing the film formation temperature of the epitaxial layer from comparison between sample 2 and sample 15. Is done.

In addition, when the electrical characteristics of the channel layer portion were evaluated by the Hall effect measurement method in the epitaxial substrates manufactured in all the experimental examples, the sheet resistance value was 450Ω / □ or less (square), and the mobility was 1550 cm ² / Vs or more. It has been confirmed that it exhibits good characteristics.

According to the epitaxial substrate for an electronic device of the present invention, an initial growth layer made of an AlN material, a buffer having a predetermined superlattice stack, and a predetermined main stack, the superlattice stack and the buffer side of the main stack are provided. parts and is, by having both 1 × 10 ¹⁸ / cm ³ or more C concentration, reduction and lateral breakdown voltage of the lateral leakage current well is both, and it is possible to improve the vertical direction breakdown voltage. Furthermore, in addition to the above characteristics, the specific resistance of the Si single crystal substrate is 1000 Ω · cm or more, and the maximum total concentration of group III atoms on the initial growth layer side of the Si single crystal substrate is 1 × 10 ¹⁶ / cm ³ If the total concentration of group III atoms at a position of 0.3 μm depth is 1 × 10 ¹⁵ / cm ³ or less, the loss during high-frequency signal application can be reduced.

Further, according to the present invention, an initial growth layer made of an AlN material and a buffer having a predetermined superlattice laminate and a predetermined main laminate are provided, and the superlattice laminate and a buffer side portion of the main laminate are provided. Both of them have a C concentration of 1 × 10 ¹⁸ / cm ³ or more, so that both the reduction in the lateral leakage current and the lateral withstand voltage characteristic can be achieved and the longitudinal withstand voltage can be improved. In addition, it is possible to manufacture an epitaxial substrate for an electronic device that can reduce loss when a high-frequency signal is applied.

DESCRIPTION OF SYMBOLS 1 Epitaxial substrate for electronic devices 2 Si single crystal substrate 3 Buffer 4 Main laminated body 4a Channel layer 4b Electron supply layer 5 Initial growth layer 6 Superlattice laminated body 6a 1st layer 6b 2nd layer

Claims (5)

A channel layer and an electron supply layer formed by sequentially stacking a plurality of group III nitride layers epitaxially grown on the buffer as an insulating layer formed on the Si single crystal substrate, an insulating layer formed on the Si single crystal substrate, and An epitaxial substrate for an electronic device comprising a main laminate having a current conduction direction in a lateral direction,
The buffer has at least an initial growth layer in contact with the Si single crystal substrate and a superlattice laminate including a superlattice multilayer structure on the initial growth layer,
The initial growth layer is made of an AlN material, and the superlattice laminate is B _a1 Al _b1 Ga _c1 In _d1 N (0 ≦ a ₁ ≦ 1, 0 ≦ b ₁ ≦ 1, 0 ≦ c ₁ ≦ 1, 0 ≦ d ₁ ≦ 1, a ₁ + b ₁ + c ₁ + d ₁ = 1, except when both b ₁ and c ₁ are 0. ) The first layer made of material and the band gap B _a2 Al _b2 Ga _c2 In _d2 N (0 ≦ a ₂ ≦ 1, 0 ≦ b ₂ ≦ 1, 0 ≦ c ₂ ≦ 1, 0 ≦ d ₂ ≦ 1, a ₂ + b ₂ + c ₂ + d ₂ = 1, except when b ₂ and c ₂ are both 0. ) The second layer made of material is alternately laminated,
Wherein the superlattice laminate, buffer-side portion of the channel layer forming the main laminate, both C concentration Ri der 1 × 10 ¹⁸ / cm ³ or more, and
The electron substrate epitaxial substrate characterized in that the C concentration of the channel layer constituting the main laminate on the electron supply layer side is 4 × 10 ¹⁶ / cm ³ or less . The first layer is made of an AlN material, and the second layer is made of an Al _b2 Ga _c2 N (a ₂ = 0, 0 <b ₂ ≦ 0.5, 0.5 ≦ c ₂ <1, d ₂ = 0) material. 2. The epitaxial substrate for electronic devices according to 1. The Si single crystal substrate has a specific resistance of 1000 Ωcm or more, a maximum total concentration of group III atoms from the initial growth layer to a depth of 0.1 μm is 1 × 10 ¹⁶ / cm ³ or less, and the initial ^{3. The} epitaxial substrate for electronic devices according to claim 1, wherein the total concentration of group III atoms at a depth of 0.3 μm from the growth layer is 1 × 10 ¹⁵ / cm ³ or less. On the Si single crystal substrate, a buffer as an insulating layer, and a plurality of group III nitride layers are epitaxially grown on the buffer to form a main laminate having a channel layer and an electron supply layer in this order. Is a method for manufacturing an epitaxial substrate for an electronic device having a current conduction direction,
The buffer has at least an initial growth layer in contact with the Si single crystal substrate and a superlattice laminate including a superlattice multilayer structure on the initial growth layer,
The initial growth layer is made of an AlN material, and the superlattice laminate is B _a1 Al _b1 Ga _c1 In _d1 N (0 ≦ a ₁ ≦ 1, 0 ≦ b ₁ ≦ 1, 0 ≦ c ₁ ≦ 1, 0 ≦ d ₁ ≦ 1, a ₁ + b ₁ + c ₁ + d ₁ = 1, except when both b ₁ and c ₁ are 0. ) The first layer made of material and the band gap B _a2 Al _b2 Ga _c2 In _d2 N (0 ≦ a ₂ ≦ 1, 0 ≦ b ₂ ≦ 1, 0 ≦ c ₂ ≦ 1, 0 ≦ d ₂ ≦ 1, a ₂ + b ₂ + c ₂ + d ₂ = 1, except when b ₂ and c ₂ are both 0. ) The second layer made of material is alternately laminated,
The superlattice laminate and the buffer side portion of the channel layer constituting the main laminate are both formed to have a C concentration of 10 ¹⁸ / cm ³ or more , and
A method for manufacturing an epitaxial substrate for an electronic device , wherein a portion of the channel layer constituting the main laminate on the electron supply layer side is formed so that a C concentration is 4 × 10 ¹⁶ / cm ³ or less . The Si single crystal substrate has a specific resistance of 1000 Ωcm or more, a maximum total concentration of group III atoms from the initial growth layer to a depth of 0.1 μm is 1 × 10 ¹⁶ / cm ³ or less, and the initial The method for producing an epitaxial substrate for an electronic device according to claim 4, wherein the total concentration of group III atoms at a depth of 0.3 μm from the growth layer is 1 × 10 ¹⁵ / cm ³ or less.

Images