JP2010517345A - Clock signal generator - Google Patents

Abstract

A clock signal generator for generating a clock signal of an integrated circuit flexibly is realized.
A clock signal generator (1) for generating a clock signal of an integrated circuit. The clock signal generator comprises a delay locked loop (3) adapted to generate a plurality of mutually delayed clock phases based on a reference clock signal. The delay locked loop further selects one of a plurality of clock phases as an output signal of the delay locked loop (3) in response to the first control signal. Clock signal. The clock signal generator further includes an inverter (11) arranged to generate the inverse of the output signal and, in response to the clock inversion signal, either the output signal or the inverse of the output signal as the second clock signal. And a multiplexer unit (12) arranged so as to be transferred.
[Selection] Figure 1

Description

  The present invention relates to a clock signal generator.

  A mixed signal system, ie, a system that can include both analog and digital functions, may be implemented, for example, on a single integrated circuit (IC). An IC including a mixed signal system is referred to as a mixed signal IC in this application. The analog portion of the mixed signal IC may require a first clock signal for its operation. For example, the analog portion may include at least one data such as an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC), and / or a discrete-time analog filter such as a switched capacitor (SC) filter or a switched current (SI) filter. Converters may be included, which may require a first clock signal for operation, for example as a sampling clock. In addition, the digital portion of the mixed signal IC may require a second clock signal for its operation. For example, the digital portion may include a central processing unit (CPU), a digital signal processor (DSP), a finite state machine (FSM), etc., which require a second clock signal for operation. The first and second clock signals may have the same frequency.

  The second clock signal may need to be synchronized with the reference clock signal at the same frequency. For example, the second clock signal may need to be in phase with the reference clock signal. Alternatively, the second clock signal may need to have a given delay with respect to the reference clock signal. The reference clock signal may be generated by a reference clock generator, such as a crystal oscillator, which may be located at least partially outside the mixed signal IC.

  For reasons of flexibility, it may be desirable to be able to selectively invert the first clock signal relative to the second clock signal. For example, the analog input signal of the mixed signal IC may be generated by an external DAC. In the transition phase between two successive output values of the external DAC, unwanted transients in the form of ringing, overshoot and glitches may appear in the analog input signal of the mixed signal IC. The analog input signal of the mixed signal IC may be sampled by an ADC in the analog part of the mixed signal IC, for example. An option that allows the first clock signal to be selectively inverted with respect to the second clock signal may be used to avoid sampling the analog input signal of the mixed signal IC during the transition phase.

  An object of the present invention is to provide a clock signal generator for flexibly generating a clock signal of an integrated circuit.

  According to a first aspect, a clock signal generator for generating a clock signal of an integrated circuit includes a delay locked loop that generates a plurality of mutually delayed clock phases based on a reference clock signal. The delay locked loop is further configured to select one of a plurality of clock phases as an output signal of the delay locked loop in response to the first control signal, the output signal being the first clock signal. It is. The clock signal generator further transfers either the output signal or the inverse of the output signal as the second clock signal in response to the inverter arranged to generate the inverse of the output signal and the clock inversion signal. And a multiplexer unit arranged as described above.

  The delay locked loop is configured such that when the delay locked loop is in a synchronized state, the plurality of mutually synchronized clock phases with respect to the reference clock signal are evenly distributed within a range of 0 ° to 360 °. It is also possible to generate a delayed clock phase.

  The first control signal may be a first control word. The clock signal generator may further include a control unit arranged to generate the first control word based on the second control word and the clock inversion signal.

  The delay locked loop selects the output signal of the delay locked loop from the plurality of clock phases so that a 180 ° phase shift occurs in the output signal of the delayed locked loop as a result of the inversion of the MSB of the first control word. It may be.

  The control unit uses the MSB of the first control word as a copy of the MSB of the second control word when the clock inversion signal has a first value, and the second when the clock inversion signal has a second value. It may be generated as the reverse of the MSB of the control word.

  The control unit may include an XOR gate adapted to generate the MSB of the first control word based on the MSB of the second control word and the clock inversion signal.

  According to a second aspect, the integrated circuit comprises a clock signal generator.

  According to a third aspect, the electronic device comprises a clock signal generator. The electronic device may be, but is not limited to, a monitor, a projector, a television receiver, or a wireless transceiver.

  Further embodiments of the invention are set out in the dependent claims.

  The first clock signal may be used for clock control of an analog block in the mixed signal IC, for example. The second clock signal may be used, for example, to clock a digital block in the mixed signal IC. An advantage of some embodiments is that the first clock signal can be inverted with respect to the second clock signal while the first clock signal can be generated with a relatively low amount of jitter.

  The term “comprising” as used herein is used to define the presence of the mentioned feature, integer, step, or component, but one or more other features, integer, It should be emphasized that the existence or addition of steps, components or groups thereof is not excluded.

  Further objects, features and advantages of the present invention will become apparent from the following detailed description of the invention which refers to the accompanying drawings.

  FIG. 1 shows a circuit diagram of an embodiment of a clock signal generator 1 for flexibly generating an integrated circuit (IC) clock signal. The IC may be included in an electronic device such as, but not limited to, a monitor, a projector, a television receiver, or a wireless transceiver. In the following, a mixed signal IC comprising both analog and digital units will be considered. However, the clock signal generator 1 may be used in a pure digital or pure analog IC.

  The clock signal generator 1 includes, for example, a first clock signal that can be used as a sampling clock of an analog part of the mixed signal IC and a second clock signal that can be used to control the operation of the digital part of the mixed signal IC, for example. May be generated.

  Since the first clock signal is generated directly at the first clock terminal 2 by the delay locked loop (DLL) 3, the associated clock jitter can be relatively low, so that the operation of the analog part of the mixed signal IC can be performed. It may be used directly to control. Alternatively, a clock distribution circuit such as a single clock buffer or a network of clock buffers may be connected between the first clock terminal 2 and the analog portion of the mixed signal IC.

  The second clock signal is generated at the second clock terminal 4 of the clock signal generator 1 and the associated clock jitter can be relatively high compared to the first clock signal. This is acceptable because the tolerance for clock jitter in the digital part is relatively large. The second clock signal may be used directly to control the operation of the digital portion of the mixed signal IC. Alternatively, for example, if the capacitive load that needs to be driven by the second clock signal is too great for the clock signal generator 1 to be driven directly, a single clock buffer or a network of clock buffers may be used. A clock distribution circuit may be connected between the second clock terminal 4 and the digital portion of the mixed signal IC.

  The reference clock signal may be supplied to the DLL 3 via the terminal 5 of the clock signal generator 1. The reference clock signal may be generated by a crystal oscillator, for example. Alternatively, the reference clock signal may be generated by a phase locked loop (PLL). The PLL may be functionally connected to a crystal oscillator.

DLL 3 may generate a plurality of mutually delayed clock phases. The DLL 3 may further select one of a plurality of mutually delayed clock phases as an output signal of the DLL 3 based on the first control word. The output signal of DLL3 may be generated at the output terminal 6 of DLL3. The first control word may have, for example, N bits (N is an integer) such as 5 but not limited. The number of clock phases among the plurality of mutually delayed clock phases may be ^2N . Each of the plurality of clock phases may have the same frequency as the reference clock signal. For example, the phase shift of the plurality of mutually delayed clock phases with respect to the reference clock signal may be evenly distributed within a range of 0 ° to 360 ° under the DLL3 synchronization condition. The first control word may be supplied from the control unit 8 to the DLL 3 via the bus 7.

  The control unit 8 may be arranged to receive the second control word via the interface 9. The control unit 8 may be further arranged to receive a clock inversion signal from the control terminal 10 of the clock signal generator 1. The control unit 8 may generate the first control word based on the second control word and the clock inversion signal.

  The second control word may be supplied to the clock signal generator 1 by a synchronization unit (not shown). The synchronization unit may be arranged inside or outside the mixed signal IC. The synchronization unit generates a second control word such that the second clock signal is synchronized with the clock signal of the external unit that transmits and / or receives analog and / or digital information to and from the mixed signal IC. It may be. Alternatively or additionally, the synchronization unit may generate a clock inversion signal and supply it to the clock signal generator 1.

  The clock signal generator 1 may include an inverter 11. The inverter 11 may be connected to the output terminal 6 of the DLL 3 at the input terminal of the inverter 11. The inverter 11 may generate the reverse of the output signal from the DLL 3. The clock signal generator 1 may further include a multiplexer unit 12. The first input terminal of the multiplexer unit 12 may be connected to the output terminal 6 of the DLL 3. Further, the second input terminal of the multiplexer unit 12 may be connected to the output terminal of the inverter 11. The control terminal 10 of the clock signal generator may be connected to the select terminal of the multiplexer unit 12 in order to supply a clock inversion signal to the multiplexer unit 12. The multiplexer unit 12 selectively transfers either the output signal from the DLL or the reverse of the output signal from the DLL to the second clock terminal 4 of the clock signal generator 1 in response to the clock inversion signal. You may arrange as follows.

  Thereby, the first clock signal may be an output signal of DLL3. The first clock signal may be supplied to the first clock terminal 2 of the clock signal generator 1 via, for example, a short circuit between the first clock terminal 2 and the output terminal 6 of the DLL 3.

  The clock inversion signal may have one of two states or values, for example “0” or “1”. In some embodiments, the clock signal generator 1 may invert the first clock signal relative to the second clock signal when the clock inversion signal has the value “1”. The clock signal generator 1 may further generate a first clock signal that is in phase with the second clock signal when the clock inversion signal has a value “0”.

  The first control word and the second control word may have the same number of bits. The control unit 8 may generate the first control word as a copy of the second control word when the clock inversion signal has the value “0”. The control unit 8 further generates the first control word as a copy of the second control word, excluding the MSB of the first control word, which can be generated as the inverse of the most significant bit (MSB) of the second control word. It may be.

  When the value of the MSB of the first control word changes from “0” to “1” or vice versa when the DLL 3 is in a synchronized state, the value of the remaining bits of the first control word is held constant. Thus, the DLL 3 may be arranged so that a phase shift of 180 ° occurs in the output signal of the DLL 3.

  If the first clock signal and the second clock signal should be in phase with each other, the value of the clock inversion signal may be set to “0”. Then, the multiplexer unit 12 may be set so that the output signal from the DLL 3 is transferred as the second clock signal to the second clock terminal 4 of the clock signal generator. The control unit 8 may generate the first control word as a copy of the second control word. The second control word may be selected so that the second clock signal is in phase with the reference clock signal. Alternatively, the second control word may be selected such that the second clock signal has a given delay with respect to the reference clock signal.

  If the first clock signal is to be out of phase with the second clock signal, the value of the clock inversion signal may be changed from “0” to “1”. If the second control word is held at the same value as before, the MSB of the first control word is reversed compared to when the value of the clock inversion signal is set to “0”. The remaining bits of the first control word have the same value as before. Therefore, the output signal from DLL 3 is subject to a phase shift of 180 °, which is opposite to the case where the value of the clock inversion signal is set to “0”. Since the first clock signal is an output from DLL 3, the first clock signal is also reversed compared to the case where the value of the clock inversion signal is set to “0”. However, here, the multiplexer unit 12 is set so as to transfer the reverse of the output signal from the DLL 3 to the second clock terminal 4 of the clock signal generator 1 as the second clock signal. Therefore, the second clock signal is not affected by a change in the value of the clock inversion signal other than the delay introduced by the inverter 11.

  A circuit diagram of an embodiment of the control unit 8 is shown in FIG. The control unit 8 may include an exclusive OR (XOR) gate 13. The XOR gate 13 may generate the MSB of the first control word at the output terminal of the XOR gate. The MSB of the second control word and the clock inversion signal may be supplied to the first and second input terminals of the XOR gate 13, respectively. The remaining bits of the first control word may be generated as a copy of the corresponding bits of the second control word using a short circuit between the input interface 9 and the bus 7.

  Modern IC manufacturing processes can design and manufacture related low jitter DLLs. An advantage of the mechanism described above for generating the first and second clock signals is that the associated clock jitter is low because the first clock signal is generated directly by DLL3. Units such as inverters and / or multiplexers that are inserted into the signal path of the clock signal may introduce additional jitter. Thus, with the mechanism described above, the jitter associated with the second clock signal may be worse than that of the output signal from DLL3. However, digital circuits are usually more tolerant of clock jitter than analog circuits that use a clock signal as a sampling clock. Thus, the jitter introduced by inverter 11 and multiplexer unit 12 can be acceptable for mixed signal ICs. A further advantage of the mechanism described above for generating the first and second clock signals is that both the first and second clock signals are generated by a single clock signal generator, for example, the first and second A smaller circuit area and lower power consumption can be obtained than when a separate clock signal generator is used to generate the second clock signal.

  The present invention has been described above with reference to the individual embodiments. However, embodiments other than those described above are possible within the scope of the invention. Various features and steps of the invention may be combined in ways other than those described. The scope of the invention is limited only by the appended claims.

FIG. 2 is a circuit diagram of a clock signal generator according to an embodiment. FIG. 3 is a circuit diagram of a control unit according to an embodiment.

Claims (10)

A clock signal generator (1) for generating a clock signal of an integrated circuit, comprising:
A plurality of mutually delayed clock phases are generated based on the reference clock signal, and one of the plurality of clock phases is selected as an output signal of the delay locked loop (3) in response to the first control signal. A delay locked loop (3) in which the output signal is a first clock signal,
An inverter (11) arranged to generate the inverse of the output signal;
A multiplexer unit (12) arranged to transfer either the output signal or the inverse of the output signal as the second clock signal in response to the clock inversion signal; ).   When the delay locked loop (3) is in a synchronized state, the phase shift of the plurality of mutually delayed clock phases with respect to the reference clock signal is within a range of 0 ° to 360 ° when the delay locked loop (3) is in a synchronized state. The clock signal generator (1) according to claim 1, wherein the plurality of mutually delayed clock phases are generated so as to be evenly distributed.   The clock signal generator (1) according to claim 1 or 2, wherein the first control signal is a first control word.   The clock signal generator (1) further comprises a control unit (8) arranged to generate the first control word based on a second control word and the clock inversion signal. Clock signal generator (1).   Among the plurality of clock phases, the delay locked loop (3) causes a 180 ° phase shift in the output signal of the delay locked loop (3) as a result of the inversion of the MSB of the first control word. The clock signal generator (1) according to claim 3 or 4, wherein an output signal of the delay locked loop (3) is selected.   The control unit (8) uses the MSB of the first control word as a copy of the MSB of the second control word when the clock inverted signal has a first value, and the clock inverted signal is the second The clock signal generator (1) according to any one of claims 3 to 5, which occurs as the inverse of the MSB of the second control word when having the value of   The control unit (8) according to claim 6, comprising an XOR gate adapted to generate the MSB of the first control word based on the MSB of the second control word and the clock inversion signal. Clock signal generator (1).   An integrated circuit comprising the clock signal generator (1) according to any one of the preceding claims.   Electronic device comprising the clock signal generator (1) according to any one of the preceding claims.   The electronic device according to claim 9, wherein the electronic device is a monitor, a projector, a television receiver, or a wireless transceiver.

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