JP2010239180A - Method for manufacturing piezoelectric device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a piezoelectric device capable of securing proper quality with high productivity. <P>SOLUTION: In the same way as the formation of a cavity 22, a substrate is patterned by photolithography so that a resist may be left at a part other than a through hole 23 and a step 24. When the material of the substrate is silicon, etching is performed in the shape of a taper to form the through hole 23 and the step 24. The through hole 23 and the step 24 can be formed simultaneously in the same process. Moreover, the step 24 can be formed at the same time when the cavity 22 is formed. An alignment mark 32 is formed on the step 24 by an electrolytic plating method and the like. At this time, a piezoelectric vibrating element loading pad 29 and a through electrode 34 are also formed simultaneously. Then, the alignment mark 32 is utilized as a mounting positioning reference for the piezoelectric vibrating element 37, a joining positioning reference for a cover 36, and a dicing position reference at the time of dividing into each piezoelectric device. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a method of manufacturing a piezoelectric device that is incorporated in many portable communication devices and electronic devices.

  In recent years, piezoelectric devices such as piezoelectric vibrators have been used as timing devices incorporated into electronic devices such as portable communication devices.

  The piezoelectric device is completed by mounting a piezoelectric vibration element on which an excitation electrode is formed in a package for mounting on an electronic device, and then sealing the inside of the package with a lid on the package. . In the package, a conductive pattern (mounting terminal) for mounting the piezoelectric vibration element is formed inside the package, and a conductive pattern for mounting the piezoelectric device body on the circuit board on the electronic device side on the other surface. A configuration is adopted in which patterns (external terminals) are formed and they are electrically connected to each other by through electrodes penetrating the inside of the substrate. (For example, see Patent Documents 1 and 2.)

  Further, as means for hermetically sealing the piezoelectric vibration element mounted on the substrate, a closed space that is blocked from the outside is formed by joining a lid member separate from the substrate to the substrate. In this regard, examples of the bonding technique used at that time include anodic bonding and heat-melt bonding performed after a predetermined bonding film is interposed on the bonding surface. It has become possible to join different types of materials.

  FIG. 3 is a top view (a) showing the overall structure of the piezoelectric device, and a cross-sectional view taken along the line AA ′ of FIG. 3 (a), and the top view (a) is a perspective view of some members (a lid and a piezoelectric vibration element). FIG. Here, the case where the package material is silicon will be described. In the piezoelectric device 41, a piezoelectric vibration element 42 on which an excitation electrode (not shown) is formed is mounted on a piezoelectric vibration element mounting pad 43 and is electrically connected to the external terminal 45 through a through electrode 44. After the piezoelectric vibration element 42 is mounted in the piezoelectric device package 46 that houses the piezoelectric vibration element 42, a lid 47 is joined to the top of the piezoelectric device package 46 to hermetically seal the inside 48 of the piezoelectric device package. .

  The through electrode 44 is formed by forming a through hole 49 in the piezoelectric device package 46, forming an insulating film 50 on the inner surface of the through hole 49, performing insulation treatment, and filling the inner surface with a conductive member 53. It is what is done. Here, the piezoelectric vibration element mounting pad 43 and the conductive member 53 can be integrally formed of the same member.

  In order to prevent electrical connection between the external terminal 45 and the piezoelectric device package 46, an insulating film 51 and an organic insulating film 52 are formed therebetween. The purpose of forming the organic insulating film 52 is to reduce the package capacitance of the piezoelectric device package 46.

  Further, as a method for manufacturing the piezoelectric device, a large-diameter wafer having a plurality of piezoelectric device package forming regions is prepared, the piezoelectric device package is completed at a wafer level, and the piezoelectric device package at a wafer level is prepared. The upper part is covered with a bonding film 54 and hermetically sealed, and then separated into pieces by dicing to form a plurality of piezoelectric devices from a single substrate.

  FIGS. 4A and 4B are diagrams for explaining a method of manufacturing a piezoelectric device manufactured at a wafer level according to the prior art, and FIGS. 4A to 4J are cross-sectional views showing states of package formation in each process. FIGS. It is. Hereinafter, a conventional method for manufacturing a piezoelectric device will be described with reference to FIGS. 4A and 4B. Here, the case where the package material is silicon will be described.

  FIG. 4A shows a step of forming a cavity (concave portion) on the surface of the substrate. Here, a photoresist is applied to the surface of the substrate 61 made of a silicon wafer by spin coating, spray coating, or the like. After the coating, a photomask is placed on the substrate 61, UV exposure is performed, and the photoresist in the photosensitive region is removed with a developer to form a resist pattern. Subsequently, the substrate 61 is etched by a certain amount using the resist pattern as an etching mask to form a cavity 62. The used resist pattern is peeled off using an organic solvent such as acetone. The photoresist can be arbitrarily selected from a positive type and a negative type, and the same applies to the subsequent processes.

  FIG. 4B shows a step of forming a through hole for forming a through electrode on the bottom surface of the cavity. Here, the substrate is formed by photolithography following the method in which the cavity 62 is formed in the previous step. A resist pattern in which only the formation region of the through-hole 63 is opened is formed on the surface of 61, and the substrate 61 is etched through the resist pattern as an etching mask to form the through-hole 63. The through-hole 63 can be formed in a tapered shape as shown in the drawing by appropriately using dry etching and wet etching, and such a tapered through-hole 63 corresponds to the through-hole 63. Although there is an effect that stress is prevented from being concentrated and disconnected in the wiring straddling the outer edge portion (later connection wiring portion 69), the shape of the through hole 63 is not limited to this.

FIG. 4-1 (c) shows a step of forming an insulating film on the surface of the substrate. Here, the substrate 61 in which the cavity 62 and the through hole 63 are formed is placed in a quartz tube furnace or the like, By heating at a high temperature, the surface layer of the substrate 61 is transformed into a silicon oxide film (SiO ₂ ), and the insulating film 64 is formed.

  FIG. 4D shows a step of forming an organic insulating film on the insulating film on the surface facing the inner surface of the cavity. Here, a spin is formed on the insulating film 64 on the outer bottom surface side of the substrate 61. A polyamic acid which is a polyimide precursor is formed using a coating method or the like, and if it is photosensitive, it is patterned by photolithography so that only a region immediately below the through hole 63 is opened, An organic insulating film 65 is formed by heat treatment for imidization. When the organic insulating film 65 is non-photosensitive, a resist pattern is formed on the formed organic insulating film 65, and the organic insulating film 65 in the unnecessary region is removed by ashing using the resist pattern as a mask. The film 65 may be patterned.

  FIG. 4E shows a step of forming a common electrode film serving as a base of wiring on the insulating film formed on the surface of the substrate, and here, it is exposed to the outside at this point. A common electrode film 66 is formed by depositing a metal material such as gold (Au) or copper (Cu) over the entire surface of the insulating film 64 and the organic insulating film 65 by sputtering or vacuum evaporation.

  FIG. 4B shows a step of forming a mask pattern for electrolytic plating on the common electrode film. Here, a photoresist is applied to the entire surface of the common electrode film 66 using a spin coater or a spray coater. The photoresist is applied to the photomask and exposed to ultraviolet light, and then the photoresist in the photosensitive region is removed with a developing solution, and only a predetermined region where an electrolytic plating film is to be formed is opened. Form.

  FIG. 4-2 (g) shows a process of forming an electrolytic plating film on the common electrode film. Here, the entire substrate 61 is immersed in an electrolytic plating solution to perform electrolytic plating, and the mask pattern 67 is used. A conductive member 71 such as gold (Au) or copper (Cu) is deposited in an uncovered region (a region corresponding to the piezoelectric vibration element mounting pad 68, the through hole 63, the connection wiring 69, and the external terminal 70), Thereafter, the mask pattern 67 is peeled off.

  When it is desired to partially thicken the electrolytic plating film, electrolytic plating may be performed again after forming a mask pattern in which only the region to be thickened is opened after the above steps. As a situation where this is required, the piezoelectric vibration element mounting pad 68 is made thicker or penetrated for the purpose of sufficiently securing a vibration region of the piezoelectric vibration element mounted on the piezoelectric vibration element mounting pad 68 later. For example, the conductive member 71 in the through hole 63 may be increased in order to prevent leakage at the electrode portion.

  As a result, the inside of the through hole 63 is filled with the conductive member 71 to form the through electrode 72, while the piezoelectric vibration element mounting pad 68 is substantially thickened. When the common electrode film 66 is peeled off, a resist pattern is formed by photolithography, and the common electrode film 66 in an unnecessary region is removed using the resist pattern as an etching mask, or a conductive member (electrolytic plating film) 71. Utilizing the fact that the film thickness of the area where the film is formed is sufficiently thicker than the film thickness of the area without the electroplating film (area only with the common electrode film) An etching method or the like is employed.

FIG. 4-2 (h) shows a step of forming a bonding film on the upper end portion of the substrate. Here, a lid for hermetic sealing of the piezoelectric device is formed by anodic bonding or heat-melt bonding. On the premise of bonding to 61, first, a bonding film 73 is formed on the entire upper surface of the substrate 61 using a sputtering method, a vacuum evaporation method, a CVD method, or the like. Note that the material of the bonding film 73 is gold (Au) if the bonding method is a heat-melt bonding method, and silicon oxide film (SiO ₂ ) if the bonding method is an anodic bonding method. It depends on. However, in the case of room temperature bonding between silicon and silicon, since the insulating film 64 is formed on the upper end portion (bonding surface) of the substrate 61, the insulating film 64 at the bonding portion is removed by polishing or etching.

  FIG. 4-2 (i) shows a step of patterning the bonding film 73. Here, first, a photoresist is applied to the entire surface of the bonding film 73 using a spin coater or a spray coater, and then by photolithography. Patterning is performed to form a resist pattern that covers the upper end portion (bonding surface) of the substrate 61. Thereafter, the bonding film 73 in an unnecessary region is removed by etching using the resist pattern as an etching mask, and then the resist pattern is peeled off to leave the bonding film 73 only on the upper end portion of the substrate 61. Note that the patterning of the bonding film 73 is not necessarily performed by etching, and other means may be used as long as the same action can be obtained.

  FIG. 4B shows a step of hermetically sealing the piezoelectric vibration element. Here, the piezoelectric vibration element 75 is placed on the piezoelectric vibration element mounting pad 68 provided on the inner bottom surface of the cavity 62 of the substrate 61. , A flat lid 74 made of silicon or the like is placed on the bonding film 73 at the upper end of the substrate 61, and a bonding method (in a predetermined atmosphere such as a vacuum atmosphere) according to the material of the bonding film 73 ( The lid 74 is bonded to the substrate 61 using a heat-melt bonding method for Au and an anodic bonding method for a silicon oxide film. Finally, the wafer is divided into product units to complete one piezoelectric device.

  When the wafer is divided into product units, a dicing method is used. There are various methods for dicing, but because of the combination of the materials of the substrate and lid, and because it is a device that requires high productivity, division by blade dicing is desirable. As shown in FIG. 5, a plurality of piezoelectric devices are regularly arranged in the wafer, and in order to improve productivity, the producer aligns some cutting points, and from there, automatically at every product interval. Cutting with

  In the case of this device, a dicing line is simultaneously formed (not shown) when the organic insulating film 65 is formed, and alignment is performed using this line during dicing, and the product is divided into product units. ing. Even when it is difficult to form a dicing line with the organic insulating film 65, alignment is performed at the center of the external terminal of a certain piezoelectric device and the external terminal of the adjacent piezoelectric device, and then the product is automatically Divided into units.

  After dicing, expand, pick up the chip, invert the chip and place it on the jig with the lid facing up, and since the material on the surface and side of the chip is silicon, spray The chip is insulated by coating or the like to complete the product.

JP 2004-214787 A JP 2007-267101 A

  However, the above-described conventional method for manufacturing a piezoelectric device has the following problems in some steps.

  When dicing the device, if the substrate or lid is made of silicon, use a dicing line formed with an organic insulating film pattern to align the position and dice from the external terminal side of the substrate. Divided by product unit. At the stage after division, the lid of each chip is attached to the surface of the dicing tape, and in order to insulate the part where the silicon is exposed (the lid or the side of the substrate) in the subsequent process, each chip is inverted. Therefore, it must be replaced with a jig or the like so that the lid side is on the upper side, and the productivity is reduced by that amount.

  In the case of eliminating the step of inverting the chip, dicing may be performed from the lid side of the substrate. However, if an alignment mark for dicing is formed on the lid, the number of steps is increased accordingly. In addition, even if an alignment mark is to be formed, the alignment mark cannot be stably formed by a photolithography technique or the like because the lid is very thin and the mechanical strength is small.

  In general, when dicing is performed by blade dicing, the side of the chip on the side affixed to the dicing tape (on the lid side of the substrate in the conventional process) and a part of the substrate at the corner are chipped, resulting in deterioration in quality. End up.

  In addition, when bonding the lid to the substrate at the wafer level, the lid and the substrate are the same size and are installed in a jig, but the lid and the substrate have different thicknesses as well as different components. Therefore, the amount of warpage and the way of warping differ between the lid and the substrate, and the jig alone alone causes a shift due to expansion of the substrate due to heating or the like, and stable bonding cannot be performed.

  In addition, in order to mount the piezoelectric vibration element on the piezoelectric vibration element mounting pad, an alignment mark for alignment is required. In the case of the conventional process, since bonding is performed at the wafer level, the bonding surface is electrolyzed. An alignment mark for alignment cannot be formed by plating or the like, and an alignment mark for alignment may be separately formed on the bonding surface by etching or the like.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a piezoelectric device that ensures good quality and has high productivity.

  In order to achieve the above object, the piezoelectric device manufacturing method includes at least a step of forming a cavity for accommodating the piezoelectric vibration element in a flat wafer substrate, and a step portion on an outer peripheral portion of the wafer substrate. A step of forming an alignment mark serving as a positioning reference between members on the stepped portion, a step of mounting the piezoelectric vibration element in the cavity, and a flat lid member, Bonding a lid member to the wafer substrate so as to cover the cavity; and dividing the bonded lid member and the wafer substrate into individual piezoelectric vibration elements, and the piezoelectric vibration element and the lid member And a step of collectively forming a plurality of piezoelectric devices housed in a package constituted by a part of the wafer substrate.

  The alignment mark formed on the stepped portion includes a step of mounting the piezoelectric vibration element in the cavity, a step of bonding the lid member to the wafer substrate, and the bonding lid member and the wafer substrate. It is characterized in that it is used as a positioning reference for each member or a reference for a dividing position in at least one of the steps of dividing each piezoelectric vibration element individually.

  The step of forming a cavity for housing the piezoelectric vibration element in the wafer substrate and the step of forming a step portion on the outer periphery of the wafer substrate are performed simultaneously using an etching technique. .

  In the step of forming the alignment mark, the alignment mark is formed by an electrolytic plating method.

  In the step of forming the alignment mark, the alignment mark is formed by forming a concave portion in the stepped portion.

  In the step of bonding the lid member to the wafer substrate, the lid member is bonded to the wafer substrate so as not to overlap the alignment mark in a planar manner.

  According to the present invention, at the same time as forming the cavity or the like, a step is provided in a part of the outer peripheral portion of the wafer, and the dicing at the time of mounting the piezoelectric vibration element, joining with the lid, or dividing into pieces on the step Since the alignment mark used at the time of alignment is formed simultaneously with the piezoelectric vibration element mounting pad by electrolytic plating, the alignment mark can be easily formed without increasing the number of steps.

  Furthermore, according to the present invention, since it is possible to perform the dicing from the lid side by performing alignment with the alignment mark instead of from the external terminal side as in the conventional process, steps such as chip insulation processing performed after dicing Therefore, it is not necessary to invert the chip, and the production efficiency is improved accordingly.

  Further, since the depth of the step portion is deeper than the height of the electrolytic plating film, the alignment mark is never higher than the joint surface, and the lid size is at least smaller than the substrate size. Therefore, the alignment mark formed on the substrate can be seen without being covered with the lid, and the lid can be stably joined by performing fine adjustment while looking at the alignment mark. It is also possible to selectively perform bonding at the wafer level.

  Furthermore, according to the present invention, chip side surfaces and corners generated on the dicing tape surface side peculiar to the blade dicing are obtained by attaching the external terminal side (organic insulating film side) of the substrate to the dicing tape surface and performing dicing. (Chipping) reduces the impact of the blade applied to the chip during dicing by the organic insulating film, and can prevent deterioration of quality.

Explanatory drawing (Example 1) which shows the manufacturing process of the piezoelectric device of this invention. Explanatory drawing (Example 1) which shows the manufacturing process of the piezoelectric device of this invention. Explanatory drawing (Example 2) which shows the manufacturing process of the piezoelectric device of this invention. The top view and sectional drawing which show a piezoelectric device. Explanatory drawing which shows the manufacturing process of the conventional piezoelectric device. Explanatory drawing which shows the manufacturing process of the conventional piezoelectric device. Sectional drawing which shows the completed body of the wafer state of the conventional piezoelectric device. Explanatory drawing which shows the manufacturing process of the piezoelectric device of this invention. Explanatory drawing which shows the manufacturing process of the piezoelectric device of this invention.

[Example 1]
Hereinafter, a method for manufacturing a piezoelectric device of the present invention will be described in detail with reference to the drawings. FIGS. 1-1 and 1-2 are views for explaining a method of manufacturing a piezoelectric device according to the present invention, and FIGS. 1-1 (a) to (j) are cross-sectional views showing the state of the piezoelectric device in each step.

  FIG. 1-1A is a step of forming cavities 22 (concave portions) arranged at predetermined positions on the surface of the substrate 21. The material of the substrate is, for example, silicon or glass. Although not shown, after a resist is applied to the surface of the substrate 21 by a spin coat method or a spray coat method, a photomask is placed on the top of the substrate 21 and ultraviolet exposure is performed. Remove to form a pattern. Thereafter, when the substrate is made of silicon, a portion where the substrate surface is exposed is etched by an etching process, and the resist is peeled off using an organic solvent such as acetone to form the cavity 22. Note that the photoresist used in this step can be formed in the same manner whether it is a positive type or a negative type. When the substrate material is glass, a cavity may be formed by sandblasting after the pattern is formed.

  (B) is a through hole 23 for electrically connecting a piezoelectric vibration element mounted in the cavity 22 and an external terminal, and for positioning used at the time of mounting, joining and dicing of the piezoelectric vibration element. It is a figure which shows the process of forming the level | step-difference part 24 in the location in which the said cavity is not arranged in the process of forming this alignment mark. The purpose of forming the level difference is that when the alignment mark for alignment is formed on the level difference part by electroplating, the height of the alignment mark is higher than the bonding surface, and the lid is positioned at the time of bonding. This is to prevent the occurrence of poor bonding due to contact.

  Similar to the formation of the cavity 22, a pattern is formed by photolithography so that a resist is left in portions other than the through hole 23 and the stepped portion. When the substrate material is silicon, etching is performed in a tapered shape to form the through hole. A hole 23 and a stepped portion 24 are formed. The through hole 23 and the stepped portion 24 can be formed at the same time in the same process, and the stepped portion 24 can be formed at the same time when the cavity 22 is formed. The purpose of forming the through hole 23 in a tapered shape is to form a metal film when the piezoelectric vibration element mounting pad portion 27 to be formed later is electrically connected to the piezoelectric vibration element mounting pad portion 27 from the through hole 23. For example, a vertical shape may be used as long as an electrical short circuit does not occur by forming a conductive member on a thick film by electrolytic plating in a later step. In the case where the substrate material is glass, a through hole may be formed by sandblasting after the pattern is formed.

(C) shows a step of forming an insulating film on the surface of the substrate. Here, the substrate 21 in which the cavity 22, the through hole 23 and the stepped portion 24 are formed is placed in a quartz tube furnace or the like, By heating at a high temperature, the surface layer of the substrate 21 is transformed into a silicon oxide film (SiO ₂ ), and the insulating film 25 is formed collectively on each part. In the case where the substrate material is glass, the substrate material itself has an insulating property, so that the formation of the insulating film 25 is unnecessary.

  (D) shows a step of forming an organic insulating film on the insulating film on the surface facing the inner surface of the cavity. Here, a spin coat method or the like is formed on the insulating film 25 on the outer bottom surface side of the substrate 21. Is used to form a polyamic acid which is a polyimide precursor, and if it is photosensitive, patterning is performed by photolithography so that only the region immediately below the through hole 23 is opened, and then imidization is performed thereon. A heat treatment is performed to form the organic insulating film 26. In the case where the organic insulating film 26 is non-photosensitive, a resist pattern is formed on the formed organic insulating film 26, and the organic insulating film 26 in an unnecessary region is removed by ashing using the resist pattern as a mask. The film 26 may be patterned. In the case of this device, since dicing is performed from the lid side at the time of final singulation, it is not necessary to form a dicing line on the facing surface of the cavity of the substrate by an organic insulating film or the like.

  (E) shows a step of forming a common electrode film serving as a basis of wiring on the insulating film formed on the surface of the substrate. Here, the insulating film 25 exposed to the outside at this time and A common electrode film 27 is formed by depositing a metal material such as gold (Au) or copper (Cu) on the entire surface of the organic insulating film 26 by sputtering or vacuum deposition.

  FIG. 1-2 (f) shows a process of forming a mask pattern for electrolytic plating on the common electrode film. Here, a spin coater or a spray coater is used on the entire surface of the common electrode film 27. A photoresist is applied, a photomask is applied, UV exposure is performed, and then the photoresist in the photosensitive region is removed with a developing solution, and a predetermined region where an electroplating film is to be formed (piezoelectric vibration element mounting pad portion, connection wiring) The resist pattern 28 for electrolytic plating in which only the portion, the inside of the through hole, the external terminal portion, and the region corresponding to the alignment mark portion for alignment) are opened is formed.

  (G) shows a step of forming an electrolytic plating film on the common electrode film. Here, the entire substrate 21 is immersed in an electrolytic plating solution for electrolytic plating, and is covered with a mask pattern 28. Conductives such as gold (Au) and copper (Cu) in the non-existing region (piezoelectric vibration element mounting pad 29, inside of through hole 23 (through electrode 34), connection wiring portion 30, external terminal 31, alignment mark 32 for alignment) Next, the resist pattern 28 is peeled off.

  When it is desired to partially thicken the electrolytic plating film, electrolytic plating may be performed again after forming a mask pattern in which only the region to be thickened is opened after the above steps. The situation where this is required is that the piezoelectric vibration element mounting pad 29 is thickened for the purpose of sufficiently securing the vibration region of the piezoelectric vibration element 37 or the through hole 23 is used for the purpose of preventing leakage in the through electrode 34. For example, the amount of the internal conductive member 33 may be increased.

  As described above, the inside of the through hole 23 is filled with the conductive member 33 to become the through electrode 34, and on the other hand, a part of the common electrode film 27 is substantially thickened to form the piezoelectric vibration element mounting pad 29 and the connection wiring 30. The external terminal 31 is used. Then, the alignment mark 32 is used for positioning at the time of mounting, bonding, and dicing of the piezoelectric vibration element. In this way, the piezoelectric vibration element mounting pad 29, the through electrode 34, the connection wiring portion 30, the external terminal 31, and the alignment mark 32 are collectively formed of the same material. When the common electrode film 27 is peeled off, a resist pattern is formed by photolithography, and the resist pattern is used as an etching mask to remove only the common electrode film 27 in an unnecessary region, or a conductive member (electrolytic plating film). ) Utilizing the fact that the film thickness of the region where 33 is formed is sufficiently thicker than the film thickness of the region without the electrolytic plating film (the region having only the common electrode film), the electrolytic plating film and the entire common electrode film are kept constant as they are. A method of etching the amount is employed.

(H) shows the step of forming the bonding film 35 on the upper end portion of the substrate. Here, the substrate 21 is first assumed on the assumption that the lid 36 is bonded to the substrate 21 by the anodic bonding method or the heat-melt bonding method. A bonding film 35 is formed on the entire upper surface of the substrate using a sputtering method, a vacuum deposition method, a CVD method, or the like. The material of the bonding film 35 is gold (Au) if the bonding method is a heat-melt bonding method, or silicon oxide film (SiO ₂ ) if the bonding method is an anodic bonding method. In the case of using silicon-silicon activation bonding, the insulating film at the bonding portion of the substrate 21 may be removed by etching, polishing, or the like to expose the silicon of the substrate. A bonding film is not necessary.

  Next, although not shown, a resist pattern that covers only the upper end portion (bonding surface) of the substrate 21 is formed by applying a photoresist to the entire surface of the bonding film 35 using a spin coater or a spray coater and then patterning by photolithography. Form. Thereafter, the bonding film 35 in an unnecessary region is removed by etching using the resist pattern as an etching mask, and then the resist pattern is peeled off to leave the bonding film 35 only on the upper end portion of the substrate 21 as shown in the figure.

  (I) shows a step of hermetically sealing the piezoelectric vibration element. Although not shown, the mounting position of the piezoelectric vibration element 37 is recognized while the alignment mark 32 formed on the stepped portion is recognized on the piezoelectric vibration element mounting pad 29 provided on the bottom surface of the cavity 22 of the substrate 21 by a camera or the like. After mounting the piezoelectric vibration element 37, a flat lid 36 made of silicon is placed on the bonding film 35 at the upper end of the substrate 21, and the bonding film 35 is formed in a predetermined atmosphere such as a vacuum atmosphere. The lid 36 is bonded to the substrate 21 by aligning with the alignment mark using a bonding method according to the material (a heat-melt bonding method for Au and an anodic bonding method for a silicon oxide film).

  Here, FIG. 6 is a cross-sectional view when the substrate 21 and the lid 36 are joined, and FIG. 7 shows an example of a top view at that time. As shown in FIG. 21 is set on a stage 80, the lid 36 is placed on the substrate, a substrate 81 for adsorbing the lid 36 is further placed thereon, and the lid 36 and the lid 36 are passed through an exhaust pipe 82 by a pump 83. The adsorption substrate 81 is adsorbed and fixed so that the lid does not move, the stage 80 is moved, and the two alignment marks for alignment are attached to the two cameras 85 attached to the camera fixing jig 84. Fine adjustment of the stage is performed so that both 32 are shown, and the joining is performed.

  Here, since the alignment mark 32 is formed on the stepped portion 24, the height of the alignment mark 32 formed by electrolytic plating is lower than the joint portion. In addition, the contact between the alignment mark 32 and the lid can completely suppress defects such as cracks and cracks in the lid.

  Further, since the size of the lid 36 is made at least smaller than the substrate 21 and bonding is performed so that the alignment mark 32 for alignment can be seen, the alignment mark 32 can be used also in dicing in the next process. Also, the production efficiency of dicing is improved.

FIG. 1-2 (j) is a diagram showing a process of dividing into pieces by dicing by looking at the alignment mark 32 formed on the stepped portion 24 of the substrate 21.
The external terminal side of the substrate is mounted on a dicing tape, aligned with the alignment mark 32, and diced from the lid side to be singulated. Here, by performing the dicing from the lid side, it is possible to alleviate the chipping of the back surface that is generally generated during blade dicing by the organic insulating film, and it is possible to suppress deterioration in quality. Furthermore, since dicing is performed from the lid side of the substrate, it is possible to expand the dicing tape and expand the dicing tape to expand the gap between chips in the next process of chip insulation. Will improve.

  As described above, since the alignment mark 32 for alignment that can be used in each step is formed by electrolytic plating, the automatic recognition of the alignment mark by the camera becomes easier, and the mounting of the piezoelectric vibration element 37 and the lid 36 are facilitated. The joining and dicing steps can be performed stably and efficiently.

[Example 2]
In addition, the alignment mark for alignment is formed by electrolytic plating. However, a step portion may be formed on a silicon or glass substrate, and a step serving as the alignment mark may be provided on a part of the step portion by etching or the like again. FIG. 2 is a diagram showing a method of forming alignment marks for alignment without increasing the number of steps and without using electrolytic plating. FIGS. 2A and 2B are piezoelectric devices in each step. It is sectional drawing which shows this state.

  FIG. 2A shows a step of forming cavities 22 (concave portions) arranged at predetermined positions on the surface of the substrate 21. The material of the substrate is, for example, silicon or glass. Although not shown, after a resist is applied to the surface of the substrate 21 by spin coating or spray coating, a photomask is placed on the substrate 21 and ultraviolet exposure is performed. After the pattern is formed so that the resist remains other than the stepped portion 24, when the substrate is made of silicon, the portion where the substrate surface is exposed is etched by an etching process, and then the resist is organic solvent such as acetone. Is used to form the cavity 22 and the stepped portion 24. Note that the photoresist used in this step can be formed in the same manner whether it is a positive type or a negative type. When the substrate material is glass, the cavity and the stepped portion may be formed by sandblasting after the pattern is formed.

  (B) is a case where the piezoelectric vibration element is mounted or joined to a part of the through hole 23 and the step portion 24 for electrically connecting the piezoelectric vibration element mounted in the cavity 22 and an external terminal. FIG. 5 is a diagram showing a step of forming alignment marks for alignment used during dicing.

  Similar to the formation of the cavity 22, patterning is performed by photolithography so that a resist is left in portions other than the through holes 23 and the alignment marks for alignment, and when the substrate material is silicon, etching is performed in a tapered shape. The through hole 23 and the alignment mark 32 for alignment are formed.

  The subsequent steps are the same as the method shown in the first embodiment. In this method, since the alignment mark for alignment has already been formed at this stage, the alignment mark is formed by electrolytic plating. Is unnecessary.

21 Substrate 22 Cavity 23 Through-hole 24 Stepped part 25 Insulating film 26 Organic insulating film 27 Common electrode film 28 Electrolytic plating resist pattern 29 Piezoelectric vibration element mounting pad 30 Connection wiring part 31 External terminal 32 Alignment mark 33 Conductive member (electrolysis) Plating film)
34 Through electrode 35 Bonding film 36 Lid 37 Piezoelectric vibration element 41 Piezoelectric vibration element 42 Piezoelectric vibration element 43 Piezoelectric vibration element mounting pad 44 Through electrode 45 External terminal 46 Piezoelectric device package 47 Lid 48 Piezoelectric device package internal 49 Through hole 50 Insulating film 51 Insulation Film 52 Organic insulating film 53 Conductive member 54 Bonding film 61 Substrate 62 Cavity 63 Through-hole 64 Insulating film 65 Organic insulating film 66 Common electrode film 67 Resist pattern 68 for electroplating Piezoelectric vibration element mounting pad 69 Wiring connection part 70 External terminal 71 Conductive member 72 Through electrode 73 Bonding film 74 Lid 75 Piezoelectric vibration element 80 Bonding device stage 81 Lid adsorption substrate 82 Exhaust pipe 83 Pump 84 Camera fixing jig 85 Camera

Claims (6)

A method of manufacturing a piezoelectric device comprising a piezoelectric vibration element housed in a package,
At least forming a cavity for housing the piezoelectric vibration element in a flat wafer substrate;
Forming a stepped portion on the outer periphery of the wafer substrate;
Forming an alignment mark serving as a positioning reference between the members in the stepped portion;
Mounting the piezoelectric vibration element in the cavity;
Preparing a flat lid member and bonding the lid member to the wafer substrate so as to cover the cavity;
The bonded lid member and the wafer substrate are individually divided for each piezoelectric vibration element, and a plurality of piezoelectric devices in which the piezoelectric vibration element is housed in a package constituted by a part of the lid member and the wafer substrate. A process of forming individual pieces,
The method for manufacturing a piezoelectric device according to claim 1, comprising:   The alignment mark formed on the stepped portion includes a step of mounting the piezoelectric vibration element in the cavity, a step of bonding the lid member to the wafer substrate, and the bonding lid member and the wafer substrate. 2. The method of manufacturing a piezoelectric device according to claim 1, wherein the piezoelectric device is used as a positioning reference for each member or as a reference for a division position in at least one of the steps of dividing each piezoelectric vibration element individually.   The step of forming a cavity for housing the piezoelectric vibration element in the wafer substrate and the step of forming a stepped portion on the outer periphery of the wafer substrate are performed simultaneously using an etching technique. The manufacturing method of the piezoelectric device of Claim 1 or 2.   The method for manufacturing a piezoelectric device according to claim 1, wherein in the step of forming the alignment mark, the alignment mark is formed by an electrolytic plating method.   The method of manufacturing a piezoelectric device according to claim 1, wherein in the step of forming the alignment mark, the alignment mark is formed by forming a concave portion in the stepped portion. 6. The step of bonding the lid member to the wafer substrate, wherein the lid member is bonded to the wafer substrate so as not to overlap the alignment mark in a plan view. The manufacturing method of the piezoelectric device as described in one.

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