JP2010232568A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

By bonding substrates together via an insulating layer, a semiconductor layer formed on one substrate can be formed on the other substrate, and high quality can be maintained without damaging the crystal structure of the semiconductor layer. A semiconductor device and a manufacturing method thereof are proposed.
The oxide films 6a and 6b are formed on the III-V compound semiconductor layer 7 and the Si substrate 4 using ECR plasma, so that the III-V compound semiconductor layer 7 and the oxide film 6a are formed. , 6b is reduced, the oxide films 6a, 6b can be formed flat, and the crystal structure of the III-V compound semiconductor layer 7 can be maintained at a high quality without being damaged. Thereby, the III-V group compound semiconductor layer 7 formed on one InP substrate 12 can be formed on the other Si substrate 4 by bonding the Si substrate 4 and the InP substrate 12 to each other via the oxide films 6a and 6b. At the same time, it is possible to propose the semiconductor device 1 that can maintain high quality without damaging the crystal structure of the III-V compound semiconductor layer 7.
[Selection] Figure 5

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and is suitable for application in manufacturing a semiconductor device in which a III-V group compound semiconductor layer is provided on a Si substrate, for example.

  Conventionally, the III-V compound semiconductor layer has been a promising candidate to replace SiCMOS because of its high carrier mobility. In practice, a MOSFET using a III-V compound semiconductor layer on a Si substrate as a channel layer is a circuit element that further improves the characteristics of a miniaturized SiCMOS because of its high carrier mobility and low effective carrier mass. It has been expected (see, for example, Non-Patent Documents 1 to 13).

Ren, F. et al. Demonstration of enhancement-mode p- and n-channel GaAs MOSFETs with Ga2O3 (Gd2O3) As gate oxide.Solid State Electron. 41, 1751-1753 (1997). Ren, F. et al. Ga2O3 (Gd2O3) / InGaAs enhancement-mode n-channel MOSFET ’s. IEEE Electron Device Lett. 19, 309-311 (1998). Ye, P. D. et al. GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition.IEEE Electron Device Lett. 24, 209-211 (2003). Ye, P. D. et al. GaAs metal-oxide-semiconductor field-effect transistor with nanometer-thin dielectric grown by atomic layer deposition. Appl. Phys. Lett. 83, 180-182 (2003). Ye, P. D. et al. Depletion-mode InGaAs metal-oxide-semiconductor field-effect transistor with oxide gate dielectric grown by atomic-layer deposition.Appl.Phys. Lett. 84, 434-436 (2004) Rajagopalan, K., Abrokwah, J., Droopad, R., & Passlack, M. Enhancement-mode GaAs n-channel MOSFET. IEEE Electron. Device Lett. 27, 959-962 (2006). Oktyabrsky, S. et al. High-k gate stack on GaAs and InGaAs using in situ passivation with amorphous silicon. Mater. Sci. Eng. B 135, 272-274 (2006). Xuan, Y., Wu, YQ, Lin, HC, Shen, T., & Ye, PD Submicrometer inversion-type enhancement-mode InGaAs MOSFET with atomic-layer-deposited Al2O3 as gate dielectric.IEEE Electron. Device Lett. 28, 935-938 (2007). Wu, Y. Q. et al. Enhancement-mode InP n-channel metal-oxide-semiconductor field-effect transistors with atomic-layer-deposited Al2O3 dielectrics.Appl.Phys. Lett. 91, 022108 (2007). Zhu, F. et al. Depletion-mode GaAs metal-oxide-semiconductor field-effect transistor with amorphous silicon interface passivation layer HfO2 gate oxide.Appl.Phys. Lett. 91, 043507 (2007). Li, N. et al. Properties of InAs metal-oxide-semiconductor structures with atomic-layer-deposited Al2O3 Dielectric.Appl.Phys. Lett. 92, 143507 (2008). Lin, JQ et al. Inversion-mode self-aligned In0.53Ga0.47As n-channel metal-oxide-semiconductor field-effect transistor with HfAlO gate dielectric and TaN metal gate.IEEE Electron Device Lett. 29, 977-990 (2008 ). Chin, H. C. et al. Silane-ammonia surface passivation for gallium arsenide surface-channel n-MOSFETs.IEEE Electron Device Lett. 30, 110-112 (2009).

  However, when an attempt is made to manufacture a semiconductor device using such a III-V compound semiconductor layer, the III-V compound semiconductor layer remains high quality while maintaining crystallinity on the Si substrate or insulating film. Is difficult to form. By the way, in recent years, a direct wafer bonding (DWB) method is known as a technique for integration in an optical device, but even if this direct substrate bonding manufacturing method is used, a III-V group compound is used. Since the semiconductor layer is more sensitive to bonding damage, it is difficult compared to integration in an optical device. In particular, damage that occurs during bonding becomes a fatal problem in a semiconductor device using a III-V group compound semiconductor layer having an extremely thin film structure.

  The present invention has been made in consideration of the above points, and by bonding substrates together via an insulating film, a semiconductor layer formed on one substrate can be formed on the other substrate, and the semiconductor layer An object of the present invention is to propose a semiconductor device capable of maintaining high quality without damaging its crystal structure and a method for manufacturing the same.

  In order to solve this problem, claim 1 of the present invention is directed to at least one of a semiconductor layer formed by crystal growth on a surface of a first substrate and a second substrate, and one of the semiconductors. After the layer or the second substrate is irradiated with low-damage plasma, an oxide film is formed, and after the first substrate and the second substrate are bonded together by the oxide film, the semiconductor layer The first substrate is peeled off, and the semiconductor layer is formed on the second substrate.

  According to a second aspect of the present invention, the oxide film is irradiated with the plasma before the first substrate and the second substrate are bonded to each other by the oxide film. The surface of the film is activated.

  According to a third aspect of the present invention, contaminants on the surfaces of the semiconductor layer and the second substrate are removed by irradiating the semiconductor layer and the second substrate with the plasma. It is characterized by this.

  According to a fourth aspect of the present invention, the plasma is ECR (Electron Cyclotron Resonance) plasma.

  According to a fifth aspect of the present invention, the bonded surface is subjected to heat treatment before the first substrate and the second substrate are bonded by the oxide film. Is.

  According to a sixth aspect of the present invention, the semiconductor layer is a group III-V compound semiconductor layer.

Moreover, claim 7 of the present invention, the oxide _{film, SiO 2, Al 2 O 3} , AlN, Si, SiN, SiON, Ta 2 O 5, TaN, ZrO 2, ZrN, HfO 2, HfN, ITO, It is one of ZnO or an insulating film in which these are mixed.

  According to an eighth aspect of the present invention, the insulating film is formed at least on the surface of the semiconductor layer.

  According to a ninth aspect of the present invention, a source and a drain made of a metal member are provided, and the semiconductor layer is disposed as a channel layer between the sole and the drain.

  According to a tenth aspect of the present invention, at least one of the semiconductor layer formed by crystal growth on the surface of the first substrate and the second substrate, the one semiconductor layer or the first substrate. A film forming step in which an oxide film is formed by irradiating a low-damage plasma to the second substrate; a bonding step in which the first substrate and the second substrate are bonded together by the oxide film; and the semiconductor Forming a semiconductor layer on the second substrate by peeling the first substrate from the layer.

  The eleventh aspect of the present invention is characterized in that the surface of the oxide film is activated by irradiating the oxide film with the plasma before the bonding step. is there.

  According to a twelfth aspect of the present invention, the surface of the semiconductor layer and the second substrate is irradiated by irradiating the plasma to the semiconductor layer and the second substrate before the film forming step. It is characterized by comprising a removal step for removing contaminants.

  The thirteenth aspect of the present invention is characterized in that the plasma is ECR (Electron Cyclotron Resonance) plasma.

  According to a fourteenth aspect of the present invention, the bonded surface is subjected to heat treatment before the first substrate and the second substrate are bonded to each other by the oxide film.

  The fifteenth aspect of the present invention is characterized in that the semiconductor layer is a III-V group compound semiconductor layer.

Further, Claim 16 of the present invention, the oxide _{film, SiO 2, Al 2 O 3} , AlN, Si, SiN, SiON, Ta 2 O 5, TaN, ZrO 2, ZrN, HfO 2, HfN, ITO, It is one of ZnO or an insulating film in which these are mixed.

  According to a seventeenth aspect of the present invention, in the film forming step, the insulating film is formed at least on the surface of the semiconductor layer.

  According to an eighteenth aspect of the present invention, after the forming step, a predetermined region of the semiconductor layer is removed to provide a source and a drain made of a metal member, and the semiconductor layer is used as a channel layer between the source and the drain. It is characterized by arranging.

  According to the semiconductor device of claim 1 and the manufacturing method of claim 10 of the present invention, an insulating film is formed on the semiconductor layer or the second substrate by using low damage plasma on the semiconductor layer or the second substrate. By doing so, damage to the semiconductor layer or the insulating film is reduced, the insulating film can be formed flat, and the crystal structure of the semiconductor layer can be maintained at high quality without being damaged. Thus, by bonding substrates together via an insulating film, a semiconductor layer formed on one substrate can be formed on the other substrate, and high quality can be maintained without damaging the crystal structure of the semiconductor layer. A semiconductor device and a manufacturing method thereof can be proposed.

It is the schematic which shows the external appearance structure of the semiconductor device in this invention. It is the schematic which shows the cross-section of MOSFET. It is the schematic where it uses for description (1) of the manufacturing method of a semiconductor device. It is the schematic where it uses for description (2) of the manufacturing method of a semiconductor device. It is the schematic where it uses for description (3) of the manufacturing method of a semiconductor device. It is the schematic where it uses for description (4) of the manufacturing method of a semiconductor device. It is a photograph when the oxide film produced with the ECR plasma apparatus is observed with an atomic force microscope. It is a photograph of the verification result of the occurrence state of voids with and without heat treatment. It is a photograph which shows the IR analysis result of a bonding board | substrate, and shows an external appearance structure. It is a TEM photograph which shows the cross-sectional structure in a bonding board | substrate. It is a graph which shows the XRD spectrum of a bonding board | substrate. It is a graph which shows the relationship between the drain voltage and drain current of a semiconductor device. It is a graph which shows the relationship (1) of the gate voltage and drain current of a semiconductor device. It is a graph which shows the relationship (1) of the effective electron mobility of a semiconductor device, and a surface carrier concentration. It is a graph which shows the relationship (2) of the gate voltage and drain current of a semiconductor device. It is a graph which shows the relationship (2) of the effective electron mobility of a semiconductor device, and a surface carrier concentration. It is the schematic which shows the bonding board | substrate (1) by other embodiment. It is the schematic which shows the bonding board | substrate (2) by other embodiment. It is the schematic which shows the bonding board | substrate (3) by other embodiment. It is the schematic which shows the bonding board | substrate (4) by other embodiment. It is the schematic which shows the bonding board | substrate (5) by other embodiment. It is the schematic which shows the bonding board | substrate (6) by other embodiment. It is the schematic which shows the bonding board | substrate (7) by other embodiment. It is the schematic which shows the semiconductor device by other embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(1) Configuration of Semiconductor Device In FIG. 1, reference numeral 1 denotes a semiconductor device having a configuration in which a plurality of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) 2 are formed. As shown in FIGS. 1 and 2, the MOSFET 2 includes a back gate 3 made of Al (aluminum) and having a thickness of 280 μm on the back surface of the Si substrate 4 having a thickness of 280 μm. Thus, the gate 5 is formed. In this MOSFET _2, an oxide film 6 made of SiO ₂ (silicon oxide) having a thickness of 10 to 13 nm is disposed on a Si substrate 4. For example, InGaAs (indium gallium arsenide) that cannot grow crystals on this oxide film 6. The group III-V compound semiconductor layer 7 is provided on the oxide film 6.

  Further, a source 9 and a drain 10 made of an Au—Ge (gold-germanium) alloy are formed on the surface of the oxide film 6, and a III-V group compound semiconductor layer is formed in a region between the source 9 and the drain 10. 7 is arranged as a channel layer. Thus, the MOSFET 2 is configured such that a current flows from the source 9 to the drain 10 when a gate voltage is applied to the gate 5.

Incidentally, in the case of this embodiment, in the semiconductor device 1, the back gate structure is applied because it is easier to manufacture than the front gate structure and the operation of the MOSFET 2 can be easily verified. Further, in this semiconductor device 1, by using the back gate structure, the boundary surface between the oxide film 6 and the III-V group compound semiconductor layer 7 formed using the ECR plasma apparatus described later is good. It can show that the pasting method mentioned below is good.
(2) Manufacturing Method of Semiconductor Device Such a semiconductor device 1 is manufactured by the following manufacturing method. As shown in FIG. 3A, InP (indium phosphide) is obtained by metal organic vapor phase epitaxy (hereinafter also referred to as MOVPE (Metal-Organic Vapor Phase Epitaxy) method or MOCVD (Metal-Organic Chemical Vapor Deposition) method). The III-V compound semiconductor layer 7 is formed by epitaxially growing InGaAs crystals on the surface of the InP substrate 12 made of In this case, reaction gases TMGa (trimethylgallium) and TMIn (trimethylindium), which are raw materials for group III elements Ga (gallium) and In (indium), are placed in a reaction chamber (not shown) on which the InP substrate 12 is placed. ) And a reactive gas TBAs (tertiary butyl arsenide) which is a raw material for As (arsenic) which is a group V element, an InGaAs crystal can be epitaxially grown on the surface of the InP substrate 12 heated to a predetermined temperature.

Next, in the present invention, an ECR (Electron Cyclotron Resonance) plasma apparatus (not shown) is used, for example, at a temperature of 250 to 330 ° C. and a degree of vacuum of 10 ⁻⁵ (<1 × 10 ⁻⁴ ) Pa (which actually depends on the annealing state) However, by vacuum annealing the III-V compound semiconductor layer 7 for 15 min at 5 × 10 ⁻⁵ to 1 × 10 ⁻⁴ Pa), the surface of the III-V compound semiconductor layer 7 is exposed to the natural oxide film or the surface. Contaminants such as adhering hydrocarbons (contamination) are removed, and the surface of the III-V compound semiconductor layer 7 is cleaned. Although the case where the surface of the −V group compound semiconductor layer 7 is cleaned is described, the present invention is not limited to this, and the surface of the III-V group compound semiconductor layer 7 is cleaned by irradiating ECR plasma described later. May be.

In addition, in the present invention, as shown in FIG. 3B, an oxide film (SiO ₂ ) 6a is formed on the surface of the III-V compound semiconductor layer 7 using an ECR plasma apparatus. By applying the ECR sputtering method, an oxide film 6a having a flat surface can be formed while reducing damage to the surface of the III-V compound semiconductor layer 7 and the oxide film 6a as much as possible. It is made like that. Here, the ECR plasma in the ECR sputtering method can form an oxide film with a low energy ion flow of 10 to 30 eV. For example, other plasmas requiring irradiation energy of 50 to 1000 eV, 10 to 15 This is different from ion implantation with an irradiation energy of ke (˜500 keV).

In this case, the ECR plasma apparatus is under conditions of, for example, 250 to 330 ° C., vacuum degree 1.3 × 10 ⁻¹ Pa, 45 sec to ₂ min 30 sec, Ar / O ₂ mixed gas flow rate 15 / 6.6 to 15 / 8.1 sccm. Then, a Si target is sputtered in an Ar / O ₂ mixed gas to form an oxide film 6 a on the surface of the III-V compound semiconductor layer 7. At the same time, the oxide film 6a is irradiated with ECR plasma on its surface, thereby removing contaminants (contamination) such as a natural oxide film on the surface of the oxide film 6a and hydrocarbons attached to the surface. At the same time, the surface of the oxide film 6a can be activated. Next, as shown in FIG. 3C, for example, a degree of vacuum of 10 ⁻⁵ (<1 × 10 ⁻⁴ ) Pa (actually depending on the annealing state, 5 × 10 ⁻⁵ to 1 × 10 ^{− 4} Pa), the degassing treatment is performed by heat-treating the oxide film 6a at 250 to 330 ° C. for 15 minutes.

Separately, as shown in FIG. 4A, a Si substrate 4 having substantially the same diameter as that of the InP substrate 12 is prepared. For example, a temperature of 250 to 330 ° C. and a degree of vacuum of 10 ⁻⁵ (<1 × 10 ^{− 4} ) By vacuum annealing the surface of the Si substrate 4 for 15 minutes on the Pa base (5 × 10 ⁻⁵ to 1 × 10 ⁻⁴ Pa depending on the annealing state in practice), the surface of the Si substrate 4 is The natural oxide film and contaminants (contamination) such as hydrocarbons adhering to the surface are removed, and the surface of the Si substrate 4 is cleaned. Incidentally, in the case of the above-described embodiment, the case where the surface of the Si substrate 4 is cleaned by vacuum annealing has been described. However, the present invention is not limited to this, and the SiCR 4 is irradiated with ECR plasma. The surface of the substrate 4 may be cleaned.

  In addition, in the present invention, as shown in FIG. 4B, an ECR plasma apparatus is used to oxidize the surface of the Si substrate 4 to form an oxide film 6b. By using it, it is possible to form an oxide film 6b having a flat surface while reducing damage to the surface of the Si substrate 4 and the oxide film 6b as much as possible.

In this case, the ECR plasma apparatus is, for example, Ar / O under the conditions of 250 to 330 ° C., ¹ min at a vacuum degree of 1.1 to 1.3 × 10 ⁻¹ Pa, and Ar / O ₂ mixed gas flow rate of 15 / 6.6 to 15 / 8.1 sccm. _{2) The} Si substrate 4 is plasma oxidized in a mixed gas to form an oxide film (SiO ₂ film) 6b on the surface of the Si substrate 4. At the same time, the surface of the oxide film 6b is irradiated with ECR plasma, so that the natural oxide film on the surface of the oxide film 6b and contaminants such as hydrocarbons adhering to the surface are removed. The surface of the oxide film 6b can be activated. Next, as shown in FIG. 4C, for example, a degree of vacuum of 10 ⁻⁵ (<1 × 10 ⁻⁴ ) Pa (actually depending on the annealing state, 5 × 10 ⁻⁵ to 1 × 10 ^{− 4} Pa), the degassing process is performed by heat-treating the oxide film 6b at 250 to 330 ° C. for 1 min.

Next, as shown in FIG. 5A, the oxide film 6a of the InP substrate 12 and the oxide film 6b of the Si substrate 4 are opposed to each other, and as shown in FIG. 5B, the oxide film 6a of the InP substrate 12 Bonding is performed by pressing the Si substrate 4 while being in close contact with the oxide film 6b. Here, since the surfaces of the oxide film 6a of the InP substrate 12 and the oxide film 6b of the Si substrate 4 are activated, they can be easily joined by an external force applied by an operator's hand at room temperature. Next, in a state where the oxide film 6a of the InP substrate 12 and the oxide film 6b of the Si substrate 4 are joined, for example, a degree of vacuum of 10 ⁻⁵ (<1 × 10 ⁻⁴ ) Pa (actually in an annealed state) However, the bonding strength is improved by heating at 250 to 330 ° C. for 15 minutes at 5 × 10 ⁻⁵ to 1 × 10 ⁻⁴ Pa), and the oxidation of the InP substrate 12 is performed as shown in FIG. An oxide film 6 in which the film 6a and the oxide film 6b of the Si substrate 4 are integrated is formed.

Next, using a solution composed of HCl (hydrochloric acid) or a solution containing HCl: H ₃ PO ₄ (phosphoric acid) at a ratio of 1: 4 (˜1: 1 etc.), it is shown in FIG. Thus, the bonded substrate 15 can be formed by selectively removing the InP substrate 12 from the surface of the III-V compound semiconductor layer 7. Thereafter, as shown in FIG. 6A, a source 9 and a drain 10 made of an Au—Ge alloy (88-12 wt.%) Are formed in the exposed group III-V compound semiconductor layer 7. In the N-type MOSFET, the source and drain are formed of an Au—Ge alloy, whereas in the P-type MOSFET, the source and drain are formed of an Au—Zn alloy (95-5 wt.%).

  The source and drain made of such a metal member are formed by the following process. A resist is applied onto the III-V compound semiconductor layer 7, and the resist is exposed by using a predetermined mask, so that the resist is patterned so that only the source forming portion and the drain forming portion are removed. Subsequently, after forming an Au—Ge alloy (or Au—Zn alloy) at a low temperature (˜24 ° C.) using a resistance heating type vapor deposition apparatus, Au other than the source formation portion and the drain formation portion is formed for each resist. The -Ge alloy (or Au-Zn alloy) is lifted off, and the source 9 and the drain 10 are formed. Incidentally, the formation of the source and drain may be performed by a normal etching back process, or by various other deposition methods.

Next, a resist is applied on the group III-V compound semiconductor layer 7 on which the source 9 and the drain 10 are formed, and the resist is patterned by using a predetermined mask to pattern the resist, and H ₃ PO ₄ : H _2. The group III-V compound semiconductor layer is etched using a solution having a ratio of O ₂ : H ₂ O of 1: 1: 7, and the group III-V compound is formed into a predetermined shape as shown in FIG. A semiconductor layer 7 is formed. Finally, by depositing a back gate 3 made of Al on the back surface of the Si substrate 4 by using resistance heating, the semiconductor device 1 as shown in FIG. 1 can be manufactured.

(3) Operation and Effect In the above configuration, in the semiconductor device, the III-V compound semiconductor layer 7 is formed by epitaxially growing an InGaAs crystal on the surface of the InP substrate 12, and this III-V compound semiconductor layer is formed. An oxide film 6a is formed on the surface of 7 by sputtering using ECR plasma. At the same time, in the oxide film 6a, the surface natural oxide film and contaminants such as hydrocarbons are removed and cleaned by ECR plasma, and the surface is activated.

  Thus, since the oxide film 6a is formed on the InP substrate 12 by sputtering using low-damage ECR plasma on the III-V group compound semiconductor layer 7 and the oxide film 6a, the III-V group compound semiconductor layer 7 is formed. In addition, damage to the oxide film 6a can be reduced as compared with the prior art. Further, since the surface of the oxide film 6a is cleaned by irradiating with ECR plasma, it is possible to omit the solution processing for cleaning, which is necessary in the conventional bonding process, and simplify the manufacturing process. it can. Moreover, by not using a solution, generation | occurrence | production of the void resulting from the vaporization of the solution which osmose | permeated the film | membrane in the subsequent heat processing process can be suppressed.

  In addition, the oxide film 6a of the InP substrate 12 is separately degassed by heat treatment at a predetermined temperature, and voids are generated by the gas in the oxide film 6a during the heat treatment after bonding. This can be suppressed more reliably.

  In addition to this, the Si substrate 4 bonded to the InP substrate 12 is irradiated with ECR plasma, whereby an oxide film 6b is formed on its surface, and a natural oxide film on the surface of the oxide film 6b. And contaminants such as hydrocarbons are removed and cleaned, and the surface of the oxide film 6b is activated.

  Thus, even in the Si substrate 4, since the oxide film 6a is formed on the oxide film 6b using low-damage ECR plasma, damage to the oxide film 6b can be reduced as compared with the prior art, and the oxide film 6b is formed by the ECR plasma. Since the surface is cleaned, the solution processing that is necessary in the conventional bonding process can be omitted, the manufacturing process can be simplified, and generation of voids can be suppressed.

  Incidentally, in the case of this embodiment, vacuum annealing is performed on the surface of the III-V group compound semiconductor layer 7 and the surface of the Si substrate 4 in the InP substrate 12 before forming the oxide films 6a and 6b. By removing the natural oxide film on the surface of the III-V compound semiconductor layer 7 and the Si substrate 4 and contaminants (contamination) such as hydrocarbons adhering to the surface, voids are formed during the heat treatment after bonding. Occurrence can be more reliably suppressed.

  In addition, since the oxide film 6a of the InP substrate 12 and the oxide film 6b of the Si substrate 4 are activated by the ECR plasma, the bonding surface can be easily joined by the gripping force of the operator's hand. Can be positioned easily. Then, when the semiconductor device 1 is manufactured, the oxide films 6a and 6b are integrated by performing a heat treatment in a state where the oxide film 6a of the InP substrate 12 and the oxide film 6b of the Si substrate 4 are joined, and the InP The substrate 12 and the Si substrate 4 can be firmly bonded.

  In this embodiment, the annealing process before and after the formation of the oxide films 6a and 6b, the ECR plasma irradiation process when forming the oxide films 6a and 6b, the oxide film 6a of the InP substrate 12 and the Si substrate 4 are performed. By performing the annealing process in a state where the oxide film 6b is joined, it is possible to always remove contaminants (contamination) such as natural oxide films and hydrocarbons in a series of manufacturing processes. Generation of voids due to contaminants can be further reliably suppressed.

  In this method of manufacturing the semiconductor device 1, only the InP substrate 12 can be removed from the III-V compound semiconductor layer 7 by selective etching using a predetermined solution. Therefore, the III-V group compound semiconductor layer 7 is selectively etched. The III-V compound semiconductor layer 7 can be formed on the Si substrate 4 by peeling only the InP substrate 12 from the Si substrate 4.

  By the way, when, for example, ICP plasma, parallel plate plasma, or the like different from ECR plasma is used in the manufacturing process, the III-V group compound semiconductor layer 7 of the InP substrate 12, the oxide film to be formed, or the Si substrate 4 is formed. Since the damage to the oxide film is large, the characteristics deteriorate when the CMOS using the III-V compound semiconductor layer 7 as a channel is formed.

  On the other hand, in the semiconductor device 1 according to the present invention, the III-V compound semiconductor layer 7 and the oxide films 6a and 6b are used in the manufacturing process by using low-damage ECR plasma. When the CMOS using the III-V compound semiconductor layer 7 as a channel is formed with little influence of damage to the oxide films 6a and 6b, the characteristics are not deteriorated. As a result, the III-V compound semiconductor layer is obtained. 7 and the oxide film 6 can be formed to a film thickness of 100 nm or less, and the overall thickness can be reduced as compared with the prior art.

  Thus, in the semiconductor device 1, since the oxide film 6 can be thinned, even with a back gate structure in which the gate 5 is constituted by the back gate 3 and the Si substrate 4, good transistor characteristics can be obtained with a small gate voltage. Power consumption can be reduced.

  Incidentally, although it is difficult to reduce the resistance of the source and drain formed by ion implantation, the source 9 and the drain 10 used in the semiconductor device according to the present invention are formed by a simple metal member without using the formation method by ion implantation. Therefore, it can be formed by a low temperature process and the resistance can be reduced, and damage caused by ion implantation and damage caused by activation annealing after ion implantation can be avoided.

  In the case of this embodiment, the oxide film 6b is also formed on the surface of the III-V compound semiconductor layer 7, so that the oxide film 6a, The alignment boundary surface of 6b can be moved away, and the damage to the channel layer at the time of bonding can be further reduced.

  In the semiconductor device 1, the oxide film 6 a of the InP substrate 12 and the oxide film 6 b of the Si substrate 4 are annealed at a temperature of about 330 ° C. in a vacuum state during the manufacturing process. There is no gas generation and it can withstand heat treatment at about 400 ° C. That is, the semiconductor device 1 can obtain heat resistance applicable to a general semiconductor manufacturing process.

According to the above configuration, in the semiconductor device 1, the oxide films 6a and 6b are formed on the III-V group compound semiconductor layer 7 and the Si substrate 4 using ECR plasma, so that the III-V The damage to the group compound semiconductor layer 7 and the oxide films 6a and 6b is reduced, the surfaces of the oxide films 6a and 6b can be formed flat, and high without damaging the crystal structure of the group III-V compound semiconductor layer 7. Quality can be maintained. Thus, the Si substrate 4 and the InP substrate 12 are bonded to each other through the oxide films 6a and 6b, so that the III-V group compound semiconductor layer 7 formed on one InP substrate 12 is attached to the other Si substrate 4. The semiconductor device 1 that can be formed and maintained at high quality without damaging the crystal structure of the III-V compound semiconductor layer 7 and a method for manufacturing the semiconductor device 1 can be proposed.
(4) Example (4-1) Bonded substrate Next, a semiconductor device was manufactured according to the manufacturing method described above, and various verifications were performed on the semiconductor device. First, an InGaAs film made of In _0.53 Ga _0.47 As is formed on the surface of the InP substrate 12 as the III-V group compound semiconductor layer 7, and an ECR plasma apparatus (type The surface of the InGaAs film is cleaned by vacuum annealing the InGaAs film at 330 ° C. and a vacuum degree of 5 × 10 ⁻⁵ to 1 × 10 ⁻⁴ Pa for 15 min using a solid source ECR plasma deposition system) Processed.

Then, by using the ECR plasma apparatus, 330 ℃, 2 min 30 sec at a vacuum degree 1.3 × 10 ^-1 Pa, under the conditions of a flow rate 15 / 8.1 sccm of Ar / O ₂ mixed gas, with Ar / O ₂ mixed gas A Si target was sputtered to form an oxide film 6a on the surface of the InGaAs film. Next, degassing was performed by heat-treating the oxide film 6a at 330 ° C. for 15 min at a degree of vacuum of 5 × 10 ⁻⁵ to 1 × 10 ⁻⁴ Pa.

On the other hand, a Si substrate 4 having the same diameter as that of the InP substrate 12 is prepared separately, and using the above-described ECR plasma apparatus at 330 ° C. and a vacuum degree of 5 × 10 ⁻⁵ to 1 × 10 ⁻⁴ Pa. The surface of the Si substrate 4 was subjected to cleaning treatment by vacuum annealing the surface of the Si substrate 4 for 15 minutes.

Next, using an ECR plasma apparatus, the Si substrate 4 in an Ar / O ₂ mixed gas under conditions of 330 ° C., a vacuum of 1.1 × 10 ⁻¹ Pa for 1 min and an Ar / O ₂ mixed gas flow rate of 15 / 8.1 sccm. Then, an oxide film 6b was formed on the surface of the Si substrate 4. Next, degassing was performed by heat-treating the oxide film 6b at 330 ° C. for 1 min at a degree of vacuum of 5 × 10 ⁻⁵ to 1 × 10 ⁻⁴ Pa.

  The oxide film 6b on the Si substrate 4 manufactured as described above was observed with an atomic force microscope (AFM). As a result, a result as shown in FIG. 7 was obtained. As shown in FIG. 7, the oxide film 6b can be confirmed to have minute surface roughness (microroughness) to be a bonding surface, and has sufficient microroughness for bonding. It was confirmed that it was possible.

  Next, the manufactured InP substrate 12 and the Si substrate 4 are bonded together by the oxide films 6a and 6b, but before that, a void that may be generated at the time of the bonding was verified. Here, it was verified whether or not the state of void generation changes depending on the presence or absence of heat treatment on the oxide film before bonding. First, it can be confirmed that a plurality of voids B are generated as shown in FIG. 8A when the oxide films are bonded together without performing heat treatment on the formed oxide films. It was. On the other hand, when the oxide films are bonded together after heat treatment and degassing treatment on the formed oxide film, almost voids are generated as shown in FIG. It was confirmed that it was not. From this, it was confirmed that by performing a heat treatment on the oxide film before bonding, the generation of voids (also referred to as microvoids as distinguished from voids formed during bonding) can be suppressed.

Next, the oxide film 6a formed on the InP substrate 12 and the oxide film 6b formed on the Si substrate 4 were bonded together by the operator by hand. Next, in order to improve the bonding strength in a state where the InP substrate 12 and the Si substrate 4 are bonded to each other with the oxide films 6a and 6b, the vacuum degree is 5 × 10 ⁻⁵ to 1 × 10 ⁻⁴ Pa for 15 minutes at 330 ° C. And heated. Then, Yuki by removing the InP substrate 12 by using a solution of HCl, When the InP substrate 12 is thinned, then _HCl: H 3 PO ₄ is 1: with a solution containing at a ratio of 4, the remaining The InP substrate 12 was selectively removed.

  Thus, a bonded substrate 15 in which an InGaAs film was formed on the Si substrate 4 via the oxide film 6 was manufactured. With respect to the bonded substrate board 15 thus manufactured, an IR analysis result as shown in FIG. 9A was obtained. Here, a bonded substrate 15 having a diameter of about 50 mm was manufactured, but it was confirmed that the generation of voids was suppressed as compared to the conventional case, and the entire surface was bonded with good uniformity. Moreover, FIG. 9 (B) is a photograph of the produced bonded substrate 15, and it was confirmed that the entire mirror-like surface was formed flat.

FIG. 10 shows a TEM (Transmission Electron Microscope) photograph of the cross section of the bonded substrate 15. It was confirmed that each interface was flat and not seriously damaged by ECR plasma. Moreover, FIG. 11 shows the XRD spectrum of this bonding board | substrate 15, and the peak has appeared in 63.1o and 69.1o, respectively. Each peak of 63.1o and 69.1o indicates an In _0.53 Ga _0.47 As (004) plane and an Si (004) plane. From this result, after the InP substrate 12 and the Si substrate 4 are bonded together by the oxide films 6a and 6b formed by ECR plasma, the InP substrate 12 is removed, and the InGaAs film formed on the Si substrate 4 It was confirmed that excellent crystallinity and structural characteristics were maintained well.

(4-2) Semiconductor Device (4-2-1) First Example Next, an InGaAs film made of In _0.53 Ga _0.47 As is formed on the surface of the InP substrate 12 as the III-V group compound semiconductor layer 7. did. At this time, the carrier concentration of the InGaAs film was 1 × 10 ¹⁷ cm ⁻³ . Next, using an ECR plasma apparatus (model name EC-2300: solid source ECR plasma film-forming apparatus) manufactured by MSF Corporation, the vacuum degree is 5 × 10 ⁻⁵ to 1 × 10 ⁻⁴ Pa. The surface of the InGaAs film was subjected to cleaning treatment by vacuum annealing the surface of the InGaAs film for 15 minutes.

Next, using an ECR plasma apparatus, a Si target was placed in an Ar / O ₂ mixed gas under the conditions of 250 ° C., a vacuum of 1.3 × 10 ⁻¹ Pa for ₂ min 30 sec, and an Ar / O ₂ mixed gas flow rate of 15 / 8.1 sccm. Sputtering was performed to form an oxide film 6a on the surface of the InGaAs film. Next, degassing was performed by heat-treating the oxide film 6a at a degree of vacuum of 5 × 10 ⁻⁵ to 1 × 10 ⁻⁴ Pa and 250 ° C. for 15 minutes.

Subsequently, the Si substrate 4 prepared separately and the oxide film 6a formed on the InP substrate 12 were bonded together by the operator by hand. Next, in a state where the oxide film 6a of the InP substrate 12 and the Si substrate 4 are bonded, in order to improve the bonding strength, heating is performed at 250 ° C. for 15 minutes at a vacuum degree of 5 × 10 ⁻⁵ to 1 × 10 ⁻⁴ Pa. did. Next, the InP substrate 12 was selectively removed using a solution of HCl, whereby a bonded substrate 15 in which an InGaAs film was formed on the Si substrate 4 via the oxide film 6 was manufactured.

  A resist was applied onto the InGaAs film of the bonded substrate 15 and exposed to light using a predetermined mask, so that the resist was patterned so that only the source forming portion and the drain forming portion were removed. Subsequently, an Au—Ge alloy is formed at a low temperature (˜24 ° C.) using a resistance heating type vapor deposition apparatus, and then the Au—Ge alloy other than the source formation portion and the drain formation portion is lifted off for each resist. 9 and the drain 10 were formed.

Next, a resist is applied on the InGaAs film on which the source 9 and the drain 10 are formed, and the resist is patterned by exposing the resist using a predetermined mask, and H ₃ PO ₄ : H ₂ O ₂ : H ₂ O. The InGaAs film is etched using a solution having a ratio of 1: 1: 7, and finally, a back gate 3 made of Al is vapor-deposited on the back surface of the Si substrate 4 by using resistance heating to form the semiconductor device 1. Manufactured. The channel length L of the InGaAs film between the source 9 and the drain 10 was 500 μm.

  As a result of examining the relationship between the drain voltage and the drain current for the semiconductor device 1 manufactured as described above, a result as shown in FIG. 12 was obtained. From this result, as the drain current voltage characteristics, good saturation characteristics and pinch-off characteristics were shown. In addition, although the semiconductor device 1 has a leakage current, it exhibits a standard drain current-voltage characteristic after the leakage current is reduced.

FIG. 13 shows the relationship between the gate voltage and the drain current of the semiconductor device 1. From this result, the current on / off ratio Ion / Ioff during operation and when the operation is stopped is 10 ⁴ , and the slope value S is 120 mV / decade, the threshold value _{V T} is -0.22V, the interface state density was confirmed to be ^{1 × 10 12 cm -2 eV -1} .

Further, FIG. 14 shows the relationship between the effective electron mobility and the surface carrier concentration of the semiconductor device 1, and it is confirmed from this result that the effective electron mobility is 1,000 cm ² V ⁻¹ s ^−1. It was confirmed that a value 1.6 times higher than that obtained when a channel layer made of Si was used.

(4-2-2) Second Example Next, as a second example different from the first example described above, a group III-V compound semiconductor layer 7 is formed as In _0.53 Ga _{0.47 on} the surface of the InP substrate 12. An InGaAs film made of As was formed. At this time, the carrier concentration of the InGaAs film was 1 × 10 ¹⁵ cm ⁻³ . Next, using an ECR plasma apparatus (model name EC-2300: solid source ECR plasma film-forming apparatus) manufactured by MAS AFty Co., Ltd., 330 ° C., vacuum degree 5 × 10 ⁻⁵ to 1 × 10 ⁻⁴ Pa The surface of the InGaAs film was subjected to cleaning treatment by vacuum annealing the surface of the InGaAs film for 15 minutes.

Next, using an ECR plasma apparatus, a Si target was placed in an Ar / O ₂ mixed gas under conditions of 330 ° C., a vacuum of 1.3 × 10 ⁻¹ Pa for ₂ min 30 sec, and an Ar / O ₂ mixed gas flow rate of 15 / 8.1 sccm. Sputtering was performed to form an oxide film 6a on the surface of the InGaAs film. Next, degassing was performed by heat-treating the oxide film 6a at a vacuum degree of 5 × 10 ⁻⁵ to 1 × 10 ⁻⁴ Pa and 330 ° C. for 15 minutes.

Next, separately from this, a Si substrate 4 was prepared, and the surface of the Si substrate 4 was vacuum annealed at 330 ° C. and a vacuum degree of 5 × 10 ⁻⁵ to 1 × 10 ⁻⁴ Pa for 15 minutes using the above-described ECR plasma apparatus. As a result, the surface of the Si substrate 4 was cleaned.

Next, using an ECR plasma apparatus, the Si substrate 4 in an Ar / O ₂ mixed gas under conditions of 330 ° C., a vacuum of 1.3 × 10 ⁻¹ Pa for 1 min and an Ar / O ₂ mixed gas flow rate of 15 / 8.1 sccm. Was oxidized by plasma to form an oxide film 6 b on the surface of the Si substrate 4. Next, degassing was performed by heat-treating the oxide film 6b at a vacuum degree of 5 × 10 ⁻⁵ to 1 × 10 ⁻⁴ Pa and 330 ° C. for 15 minutes.

Next, the oxide film 6b of the Si substrate 4 and the oxide film 6a of the InP substrate 12 were bonded together by an operator by hand. Next, in a state where the oxide film 6a of the InP substrate 12 and the Si substrate 4 are bonded together, heating is performed at 330 ° C. for 15 minutes at a vacuum degree of 5 × 10 ⁻⁵ to 1 × 10 ⁻⁴ Pa in order to improve the bonding strength. did. Then, Yuki and selectively removing the InP substrate 12 by using a solution of HCl, After becoming thinner, then _HCl: H 3 PO ₄ is 1 - using a solution containing at a ratio of 4, the remaining InP The substrate 12 was selectively removed. Thus, a bonded substrate 15 in which an InGaAs film was formed on the Si substrate 4 via the oxide film 6 was manufactured.

  Next, the source 9 and the drain 10 made of an Au—Ge alloy are formed on the bonded substrate 15 manufactured as described above in the same manner as in the first embodiment, and finally, the back surface of the Si substrate 4 is made of Al. The back gate 3 to be formed was vapor-deposited using resistance heating to manufacture the semiconductor device 1. The channel length L of the InGaAs film between the source 9 and the drain 10 was 500 μm.

  In the semiconductor device 1 manufactured as described above, a standard current-voltage characteristic is shown for the n-MOSFET, and a leakage current exists for the p-MOSFET, but after the leakage current is reduced. Standard drain current voltage characteristics are shown. Thus, with respect to the semiconductor device 1 manufactured by the manufacturing method according to the present invention, the operation of the n-MOSFET and the p-MOSFET was confirmed, and it was proved that a CMOS could be manufactured using the semiconductor device 1.

FIG. 15 shows the relationship between the gate voltage and the drain current of the semiconductor device 1. From this result, the current on / off ratio Ion / Ioff during operation and when the operation is stopped is 10 ⁵ , and the slope value S is 98 mV / decade, the threshold value _{V T} is 0.10 V, the interface state density was confirmed to be ^{1 × 10 12 cm -2 eV -1} . That is, in the semiconductor device 1, it is confirmed that a relatively high current on / off ratio can be obtained and a relatively low S value and interface state density can be obtained among various MOSFETs using III-V group compound semiconductors. did it.

Further, FIG. 16 shows the relationship between the effective electron mobility and the surface carrier concentration of the semiconductor device 1, and it is confirmed from this result that the effective electron mobility is 1,200 cm ² V ⁻¹ s ^−1. It was confirmed that a value 1.9 times higher than that obtained when a channel layer made of Si was used.

(5) Other Embodiments The present invention is not limited to the present embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, in the above-described embodiment, the case where the oxide film made of SiO ₂ is formed on both the InP substrate and the Si substrate by the ECR plasma apparatus has been described. However, the present invention is not limited to this, and the ECR is not limited thereto. An oxide film may be formed only on either the InP substrate or the Si substrate by a plasma apparatus.

  In the above-described embodiment, the case where the III-V group compound semiconductor layer made of InGaAs is applied as the semiconductor layer has been described. However, the present invention is not limited to this, and various other III-V such as InP. A III-V compound semiconductor layer made of a group compound semiconductor may be applied. In the case where the III-V compound semiconductor layer is formed as a channel layer, an etching material is selected according to the III-V compound semiconductor layer. For example, in this case, as shown in FIG. 17A, for example, an InGaAs layer 42 is formed on the surface of the InP substrate 41 and an InP layer 43 is formed on the surface of the InGaAs layer 42.

Next, as shown in FIG. 17B, an oxide film formed on the surface of the Si substrate 44 manufactured separately and the surface of the InP layer 43 of the InP substrate 41 by using an ECR plasma apparatus, respectively. After the film 45 is bonded, the InP substrate 41 is removed with a solution of HCl or a solution containing HCl and H ₃ PO ₄ . Subsequently, a solution containing H ₃ PO ₄ , H ₂ O _2, and H ₂ O or a solution containing H ₂ SO ₄ , H ₂ O _2, and H ₂ O is shown in FIG. Thus, the bonded substrate 46 can be formed by removing the InGaAs layer 42.

  In another embodiment, a group III-V compound semiconductor layer in which an InP layer, an InGaAs layer, and an InP layer are stacked may be applied as the group III-V compound semiconductor layer. In this case, as shown in FIG. 18A, for example, an InGaAs layer 52, an InP layer 53, an InGaAs layer 54, and an InP layer 55 are formed in this order on the surface of the InP substrate 51. As a result, a channel layer can be formed by bonding laminated structures such as strain quantum wells.

Next, as shown in FIG. 18B, oxide films respectively formed on the surface of the Si substrate 56 manufactured separately and the surface of the InP layer 55 of the InP substrate 51 using an ECR plasma apparatus. After bonding 57, the InP substrate 51 is removed with a solution of HCl or a solution containing HCl and H ₃ PO ₄ . Subsequently, a solution containing H ₃ PO ₄ , H ₂ O ₂ and H ₂ O, or a solution containing H ₂ SO ₄ , H ₂ O ₂ and H ₂ O is shown in FIG. 18C. Thus, the bonded substrate 58 can be formed by removing the InGaAs layer 52.

  Furthermore, as another embodiment, a GaAs layer may be applied as the III-V compound semiconductor layer. In this case, as shown in FIG. 19A, for example, an AlAs layer 62 is formed on the surface of the GaAs substrate 61, and a GaAs layer 63 is sequentially formed on the surface of the AlAs layer 62.

Next, as shown in FIG. 19B, oxide films 65 respectively formed on the surface of the separately manufactured Si substrate 64 and the surface of the GaAs layer 63 of the GaAs substrate 61 using an ECR plasma apparatus. After the bonding, the GaAs substrate 61 is removed with a HCl solution or a solution containing HCl and H ₃ PO ₄ . Subsequently, a solution containing H ₃ PO ₄ , H ₂ O ₂ and H ₂ O or a solution containing H ₂ SO ₄ , H ₂ O ₂ and H ₂ O is shown in FIG. 19C. Thus, the bonded substrate 66 can be formed by removing the AlAs layer 62.

Furthermore, as another embodiment, a Si layer may be applied as the semiconductor layer. In this case, as shown in FIG. 20A, for example, an SOI (silicon on insulator) substrate composed of an Si substrate 71, a BOX (Buried Oxide) (SiO ₂ layer) layer 72, and an Si layer 73 is prepared. To do.

  Next, as shown in FIG. 20B, films were formed on the surface of the separately manufactured Si substrate 74 and the surface of the Si layer 73 of the SOI substrate using an ECR plasma apparatus. An oxide film 75 made of HfON (hafnium oxynitride) or the like is bonded. Subsequently, the bonded substrate 76 can be formed by removing the Si substrate 71 and the BOX (Buried Oxide) 72 using a predetermined solution, as shown in FIG.

Furthermore, as another embodiment, a Ge layer may be applied as the semiconductor layer. In this case, as shown in FIG. 21A, for example, a GOI (Ge on Insulator) substrate comprising a Si substrate 81, a BOX (Buried Oxide) (SiO ₂ layer) 82, and a Ge layer 83 is prepared. .

  Next, as shown in FIG. 21B, films were formed on the surface of the Si substrate 84 manufactured separately and the surface of the Ge layer 83 of the GOI substrate using an ECR plasma apparatus, respectively. An oxide film 85 made of HfON or the like is bonded. Subsequently, as shown in FIG. 21C, a bonded substrate 86 can be formed by removing the Si substrate 81 and the BOX 82 using a predetermined solution.

Furthermore, the semiconductor device 100 as shown in FIG. 24 can also be manufactured by the manufacturing method described above. In this case, as shown in FIG. 22A, for example, an InGeAs layer 92 is formed on the surface of the InP substrate 91. Separately, a GOI substrate comprising a BOX (Buried Oxide) (SiO ₂ layer) 94, a Ge layer 95, and a Si substrate 93 is prepared, and the surface of the Ge layer 95 of the GOI substrate and the InP substrate 91 are prepared. An oxide film is formed on the surface of the InGeAs layer 92 using an ECR plasma apparatus.

  Next, as shown in FIG. 22B, the oxide film on the Ge layer 95 of the GOI substrate and the oxide film on the InGeAs layer 92 of the InP substrate 91 are bonded together to form an integrated oxide film 96. The InGeAs layer 92 and the Ge layer 95 are joined via the oxide film 96. Subsequently, the InP substrate 91 is removed using a predetermined solution. Next, as shown in FIG. 22C, a bonded substrate 97 can be formed by removing predetermined regions of the InGeAs layer 92 and the oxide film 96. Incidentally, an n well 102 and a p well 103 (not shown) are provided at predetermined positions of the Si substrate 93.

Alternatively, as shown in FIGS. 23A and 23B, a GOI substrate including a BOX (Buried Oxide) (SiO ₂ layer) layer 94, a Ge layer 95, and a Si substrate 93 is used. The Ge layer 95 in the predetermined region is removed by etching the predetermined region. Next, the surface of the exposed BOX layer 94 of the GOI substrate is activated by irradiating ECR plasma using an ECR plasma apparatus, and as shown in FIG. 23C, the BOX (buried oxide film: A bonded substrate 99 is formed by bonding the Buried Oxide) layer 94 and the InGeAs layer 98 of the InP substrate 97.

  Thus, an InGeAs channel having a high electron mobility is obtained by forming a bonding substrate 97 and a bonding substrate 99 in predetermined regions with respect to the GOI substrate, and disposing the source 9 and the drain 10 made of metal members at predetermined positions. A high-performance CMOS semiconductor device in which a n-MOSFET and a Ge channel p-MOSFET having a high hole mobility are simultaneously formed on Si can be manufactured. This makes it possible to produce a device that surpasses Si CMOS. Furthermore, another semiconductor device can be integrated by re-growing another crystal on the bonding layer having high crystallinity.

Further, the present invention is not limited to the above-described embodiment, and a semiconductor layer serving as a channel layer and an oxide layer may be stacked in any number of layers. Further, in the above-described embodiment, the case where the oxide film (SiO ₂ film) formed by the ECR plasma apparatus is applied as the insulating film formed by the ECR plasma apparatus has been described, but the present invention is not limited to this. First, for example, SiO ₂ , Al ₂ O ₃ , AlN, Si, SiN, SiON, Ta ₂ O ₅ , TaN, ZrO ₂ , ZrN, HfO ₂ , HfN, ITO, ZnO, or a mixture of these by an ECR plasma apparatus. A film may be formed. In this case, when SiO ₂ , Al ₂ O ₃ , AlN, Si, SiN, SiON, Ta ₂ O ₅ , TaN, ZrO ₂ , ZrN, HfO ₂ , HfN, ITO, ZnO are formed by the ECR plasma apparatus. A solid source (target) and a gas source as shown in Table 1 below may be used.

1 Semiconductor device 4 Si substrate (second substrate)
6a, 6b Oxide film (insulating film)
7 III-V compound semiconductor layer (semiconductor layer)
9 Source
10 Drain
12 InP substrate (first substrate)

Claims (18)

At least one of the semiconductor layer formed by crystal growth on the surface of the first substrate and the second substrate is irradiated with low-damage plasma on the one semiconductor layer or the second substrate. As a result, an insulating film is formed, and after the first substrate and the second substrate are bonded together by the insulating film, the first substrate is peeled off from the semiconductor layer, and the second substrate A semiconductor device, wherein the semiconductor layer is formed on a substrate. The surface of the insulating film is activated by irradiating the insulating film with the plasma before the first substrate and the second substrate are bonded to each other by the insulating film. The semiconductor device according to claim 1. The contaminants on the surface of the semiconductor layer and the second substrate are removed by irradiating the plasma to the semiconductor layer and the second substrate. The semiconductor device described. The semiconductor device according to claim 1, wherein the plasma is ECR (Electron Cyclotron Resonance) plasma. 5. The heat treatment is performed on the bonding surface before the first substrate and the second substrate are bonded to each other by the insulating film. A semiconductor device according to item. The semiconductor device according to claim 1, wherein the semiconductor layer is a III-V group compound semiconductor layer. The insulating film is SiO ₂ , Al ₂ O ₃ , AlN, Si, SiN, SiON, Ta ₂ O ₅ , TaN, ZrO ₂ , ZrN, HfO ₂ , HfN, ITO, ZnO, or these The semiconductor device according to claim 1, wherein the semiconductor device is a mixed insulating film. The semiconductor device according to claim 1, wherein the insulating film is formed at least on a surface of the semiconductor layer. The semiconductor device according to claim 1, wherein a source and a drain made of a metal member are provided, and the semiconductor layer is disposed as a channel layer between the sole and the drain. At least one of the semiconductor layer formed by crystal growth on the surface of the first substrate and the second substrate is irradiated with low-damage plasma on the one semiconductor layer or the second substrate. A film forming step of forming an insulating film by
A bonding step of bonding the first substrate and the second substrate with the insulating film;
And a forming step of peeling the first substrate from the semiconductor layer to form the semiconductor layer on the second substrate. Before the pasting step,
The method of manufacturing a semiconductor device according to claim 10, wherein the surface of the insulating film is activated by irradiating the insulating film with the plasma. Before the film forming step,
The removal step of removing contaminants on the surface of the semiconductor layer and the second substrate by irradiating the plasma to the semiconductor layer and the second substrate is provided. 11. A method for producing a semiconductor device according to 11. The method of manufacturing a semiconductor device according to claim 10, wherein the plasma is ECR (Electron Cyclotron Resonance) plasma. In the pasting step,
14. The semiconductor according to claim 10, wherein a heat treatment is performed on a bonding surface before the first substrate and the second substrate are bonded to each other by the insulating film. Device manufacturing method. The said semiconductor layer is a III-V group compound semiconductor layer. The manufacturing method of the semiconductor device of any one of Claims 10-14 characterized by the above-mentioned. The insulating film is SiO ₂ , Al ₂ O ₃ , AlN, Si, SiN, SiON, Ta ₂ O ₅ , TaN, ZrO ₂ , ZrN, HfO ₂ , HfN, ITO, ZnO, or these The method for manufacturing a semiconductor device according to any one of claims 10 to 15, wherein the insulating film is a mixture of the above. The method of manufacturing a semiconductor device according to claim 10, wherein, in the film forming step, the insulating film is formed at least on a surface of the semiconductor layer. After the forming step,
The semiconductor layer is disposed as a channel layer between the source and the drain by removing a predetermined region of the semiconductor layer to provide a source and a drain made of a metal member. A method for manufacturing a semiconductor device according to claim 1.