JP2010225631A - Memory cell and method for manufacturing semiconductor diode - Google Patents

Abstract

A highly integrated cross-point type memory cell is provided at low cost.
In a semiconductor diode constituting a memory cell, an additional impurity in which a cathode and a reverse conductivity type are diffused at a low concentration between a cathode and an intrinsic semiconductor layer and / or between an anode and an intrinsic semiconductor layer. An additional semiconductor layer in which impurities having a conductivity type opposite to that of the semiconductor layer and / or the anode are diffused at a low concentration is provided.
[Selection] Figure 4

Description

  The present invention relates to a memory cell and a method for manufacturing a semiconductor diode.

A memory cell included in a cross-point type semiconductor memory device having a three-dimensional structure includes a rectifying element connected in series to the memory cell in addition to the memory element. As the rectifying element, a PIN / NIP diode is generally used (for example, Patent Document 1). This rectifying element will be described taking an NIP diode as an example. For example, an N-type and P-type impurity is diffused in both ends of a polycrystalline silicon film, and an intrinsic silicon film is formed as an intermediate layer in the central portion. N ⁺ layer / intrinsic layer (referred to as an intrinsic semiconductor layer or a high-resistance base layer, hereinafter referred to simply as “intrinsic semiconductor layer”) / P ⁺ layer of Si having a different concentration from the three dopant types It has a laminated structure of films. The rectifying element has a role of preventing stray current from flowing when a voltage is applied to the adjacent memory cell.

However, in order to improve the degree of integration, if the size of the diode is simply scaled to make the N ⁺ layer, the intrinsic semiconductor layer, and the P ⁺ layer smaller, the reverse becomes true as the intrinsic semiconductor layer becomes shorter. The breakdown voltage of the diode at the time of bias is lowered. In that case, stray current, which is the role of using such a diode for the cross-point type memory cell, cannot be prevented in the first place. The problem with scaling of NIP diodes formed on polycrystalline silicon is that phosphorus, boron, etc. implanted as donor-type or acceptor-type dopants into silicon due to the thermal process in the manufacturing process. Atoms diffuse in the silicon from the N ⁺ layer and the P ⁺ layer to the intrinsic semiconductor layer by a phenomenon such as thermal diffusion, so that the crystallization annealing of the silicon layer and the activation of the dopant can be performed. After finishing a manufacturing process including a thermal process such as annealing, the length of the intrinsic semiconductor layer becomes shorter than the initial film formation. The main steps as a thermal process for re-diffusion of the dopant after the polycrystalline silicon film is formed are the activation anneal for activating the dopant in the silicon crystal, and the next step. This is a LPCVD (Low Pressure Chemical Vapor Deposition) step, which is a step of forming a diode silicon film. In particular, when integrating the memory with a three-dimensional structure, the second and subsequent stages are formed after the first stage cell is formed and processed, so that each time the number of memory cell stages is increased, 1 Heat treatment is applied to the polycrystalline silicon diode of the cell in the stage.

  As described above, according to the conventional technique, when a small diode corresponding to scaling is to be manufactured, the donor-type and acceptor-type impurities that require formation of the diode are introduced into the intrinsic semiconductor layer. There was a problem that thermal diffusion could not be suppressed.

JP2007-165873A

  A first object of the present invention is to provide a highly integrated memory cell.

  A second object of the present invention is to provide a method for producing a fine semiconductor diode at a low cost.

  According to the first aspect of the present invention, the first and second wirings are arranged at the intersections of the first and second wirings arranged so as to be orthogonal to each other in plan view, and are electrically connected to the first and second wirings. A stack of a memory element and a rectifying element formed so as to be connected in series with each other, the rectifying element including an anode composed of a first semiconductor layer of a high-concentration first conductivity type, an intrinsic semiconductor layer, A semiconductor diode including a cathode, wherein the semiconductor diode is a low-concentration second conductivity type second semiconductor layer formed between the anode and the intrinsic semiconductor layer, and the cathode and the intrinsic semiconductor. There is provided a memory cell further including at least one of a low-concentration first-conductivity-type third semiconductor layer formed between the layers.

  According to the second aspect of the present invention, the step of forming the first semiconductor layer serving as the cathode doped with the first conductivity type impurity at the first concentration; Forming a second semiconductor layer doped at a second concentration lower than the first concentration on the first semiconductor layer; and a conductive layer serving as an anode on the second semiconductor layer. There is provided a method of manufacturing a semiconductor diode, comprising a step of forming and a step of activating the impurities of the first conductivity type and the second conductivity type by heat treatment.

  According to the present invention, a highly integrated memory cell is provided.

  Further, according to the present invention, a method for producing a fine semiconductor diode at a low cost is provided.

1 is a perspective view showing a schematic structure of a semiconductor memory device including a memory cell according to a first embodiment of the present invention. 1 is a perspective view showing a schematic structure of a memory cell according to a first embodiment of the present invention. FIG. 2 is a circuit diagram of the semiconductor memory device shown in FIG. 1. FIG. 3 is a schematic cross-sectional view showing a specific configuration of the memory cell shown in FIG. 2. The figure which shows dopant concentration distribution and band structure of a semiconductor diode with which the memory cell shown in FIG. 2 is provided. The figure which shows the dopant concentration distribution and band structure of the conventional semiconductor diode as a reference example. FIG. 3 is a schematic cross-sectional view showing a method for manufacturing the memory cell shown in FIG. 2. FIG. 3 is a schematic cross-sectional view showing a method for manufacturing the memory cell shown in FIG. 2. FIG. 3 is a schematic cross-sectional view showing a method for manufacturing the memory cell shown in FIG. 2. FIG. 3 is a schematic cross-sectional view showing a method for manufacturing the memory cell shown in FIG. 2. FIG. 3 is a schematic cross-sectional view showing a method for manufacturing the memory cell shown in FIG. 2. The figure which shows dopant concentration distribution in the polycrystalline-silicon part of a diode immediately after film-forming and after passing through all the heat processes. FIG. 6 is a schematic cross-sectional view showing a specific configuration of a memory cell according to a second embodiment of the present invention. FIG. 5 is a schematic cross-sectional view showing a specific configuration of a memory cell according to a third embodiment of the present invention. FIG. 10 is a schematic cross-sectional view showing a specific configuration of a memory cell according to a fourth embodiment of the present invention. FIG. 16 is a schematic cross-sectional view showing a method for manufacturing the memory cell shown in FIG. 15.

  Hereinafter, some embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same parts are denoted by the same reference numerals, and redundant description thereof is performed only when necessary.

(1) First Embodiment FIG. 1 is a perspective view showing a schematic structure of a semiconductor memory device including a memory cell according to a first embodiment of the present invention. The semiconductor memory device shown in the figure is a cross-point type three-dimensional memory device, and a memory driver circuit 10 on a silicon substrate (not shown) and a lattice on the memory driver circuit 10 in a top view. As shown, an MIM (Metal Insulator Metal) capacitor and a rectifier element, which are formed as memory elements, are formed at each point where the word lines WL and the bit lines BL intersect with each other and the word lines WL and the bit lines BL intersect. And a pillar-shaped memory cell MC1 including a stacked body with the diode.

  FIG. 2 is an enlarged perspective view of the memory cell MC1 of FIG. As shown in the figure, memory cell MC1 has a stacked structure including MIM capacitor 30 and PIN diode 20 connected in series.

  The MIM capacitor 30 includes an antifuse material or a variable resistance material thin film as an insulator serving as a memory portion, and an upper metal film and a lower metal film sandwiching the insulating film therebetween, and serves as a memory portion of the memory element. To play a role. For example, when an antifuse material is used as the insulating film, a sufficiently high voltage is applied to the insulating film, which is an arbitrary antifuse, through the word line WL and the bit line BL to cause dielectric breakdown. As a result, the resistance value of the MIM capacitor at that location can be lowered. When the cell in which the resistance value is lowered is (1) (high) and the resistance value is not lowered, that is, the state in which there is an insulating material that does not cause dielectric breakdown is (0) (low), At the time of reading, a desired low voltage is applied to an arbitrary memory cell MC1 in the forward direction of the diode 20 through the word line WL and the bit line BL, and if the current at that time is read by a sensor amplifier, an antifuse (Antifuse) is obtained. It can be determined whether the insulating film is in a state where it is not destroyed (0) or after the insulating film is destroyed (1).

  Therefore, when information is written in this memory (bit is set to “1”), the dielectric breakdown of the antifuse is an irreversible process, so that writing can be performed only once. In that case, the storage device is a storage device for one-time programming (hereinafter referred to simply as “OTP”). In addition, when a variable resistance material is used as the insulating film of the MIM capacitor, the forward direction of the diode depends on whether the resistance change state is a high resistance state such as an insulating film or a low resistance state. On the other hand, since the current under a predetermined voltage can be varied, the nonvolatile memory can be written any number of times.

  In order to apply a voltage only to an arbitrary memory cell, whether it is OTP or a nonvolatile memory using a resistance change material, a voltage is applied between a desired word line WL and a bit line BL. It is a diode provided in each memory cell that prevents stray current as shown in the circuit diagram of FIG. 3 from occurring in other adjacent memory cells. With this diode, stray current can be stopped by preventing reverse current when applied to reverse bias. When this diode element is formed of polycrystalline silicon or the like, it is necessary to ensure the breakdown voltage of the reverse current when the diode is scaled.

  FIG. 4 is a schematic cross-sectional view showing a specific configuration of memory cell MC1 shown in FIG. The memory cell MC1 of the present embodiment includes a PIN diode 20 formed on the word line WL through the barrier metal film BM2, and an MIM capacitor 30 formed on the PIN diode 20 through the barrier metal film BM4. Prepare. The MIM capacitor 30 includes a lower metal electrode film 310, an upper metal electrode film 330, and an insulating film 320 that is interposed between these metal electrode films and uses a resistance change material.

The feature of the memory cell MC1 of the present embodiment is the structure of the PIN diode 20, in addition to the P ⁺ silicon semiconductor layer 250 forming the anode, the intrinsic semiconductor layer 230, and the N ⁺ silicon semiconductor layer 210 forming the cathode, An N ⁻ silicon semiconductor layer 240 in which an impurity having a conductivity type opposite to that of the anode electrode is diffused between the P ⁺ silicon semiconductor layer 250 and the intrinsic semiconductor layer 230, the intrinsic semiconductor layer 230, the N ⁺ silicon semiconductor layer 210, And a P ⁻ type silicon semiconductor layer 220 in which impurities of a conductivity type opposite to that of the cathode electrode are diffused. By disposing the low-concentration reverse conductor layer between the anode / cathode and the intrinsic semiconductor layer, the dopant of the adjacent P ⁺ silicon semiconductor layer 250 and the N ⁺ silicon semiconductor layer in the annealing process at the time of manufacture. The dopants 210 cancel each other out and diffuse into the intrinsic semiconductor layer. 5A and 5B show a concentration distribution diagram and a band structure of the diode 20 according to the present embodiment, and FIGS. 6A and 6B show a concentration distribution of a PIN diode according to a conventional technique as a comparative example. Figure and band structure are shown. As is clear from these comparisons, in the PIN diode 20 of this embodiment, the dopant in each semiconductor layer of the anode electrode and the cathode electrode is suppressed from moving to the intrinsic semiconductor layer 230, and the band structure is also gentle. It can be seen that the region of the intrinsic semiconductor layer is sufficiently secured. In this embodiment, the P ⁺ silicon semiconductor layer 250 corresponds to, for example, a first semiconductor layer, the N ⁻ silicon semiconductor layer 240 corresponds to, for example, a second semiconductor layer, and the P ⁻ type silicon semiconductor layer 220 includes, for example, Corresponding to the third semiconductor layer, the N ⁺ silicon semiconductor 210 corresponds to, for example, the fourth semiconductor layer.

  Next, a method for manufacturing the memory cell MC1 shown in FIG. 4 will be described with reference to the schematic cross-sectional views of FIGS.

First, as shown in FIG. 7A, a trench TR is formed in an interlayer insulating film IF1 such as SiO ₂ formed on the surface of a substrate (not shown), and a word line (lower electrode) is formed with a metal such as tungsten (W). ) WL is formed.

  Next, as shown in FIG. 7B, a titanium nitride (TiN) film BM1 is formed as a barrier metal layer on the word line WL.

Next, amorphous silicon containing a large amount of phosphorus (P) is deposited on the entire surface to form an N ⁺ semiconductor layer 206 serving as a cathode of the diode as shown in FIG. 7C, and then a small amount of boron (B ) Is formed on the entire surface to form a P ⁻ semiconductor layer 216 as shown in FIG. Next, amorphous silicon containing a small amount of phosphorus (P) is formed on the entire surface to form an N ⁻ semiconductor layer 236 as shown in FIG. 7E, and further, amorphous containing a large amount of boron (B). Silicon is deposited on the entire surface to form a P ⁺ semiconductor layer 246 that becomes the anode of the diode as shown in FIG.

More specifically, for example, when using a vertical batch processing type LPCVD apparatus capable of processing a plurality of silicon wafers simultaneously, after setting the temperature of the reaction chamber of the LPCVD apparatus to around 500 ° C., In order to form the N ⁺ silicon semiconductor layer 206 to be the first layer, a monosilane gas (SiH ₄ ) gas, a phosphine (PH ₃ ) gas, and a carrier gas are supplied, and phosphorus having a concentration of 1 × 10 ²¹ atoms / cc or more is supplied. After the amorphous silicon film containing (P) is formed to 5 nm, the inside of the LPCVD apparatus is repeatedly purged with nitrogen gas or with the vacuum without releasing the vacuum state in the same LPCVD apparatus. After lowering the partial pressure of the phosphine gas and silane gas remaining in the chamber as necessary, the temperature of the LPCVD apparatus is also brought to around 500 ° C. And integer, 3 in an atmosphere chloride Borangasu mixed trace monosilane gas, boron (B) from about 1 × 10 by 18 it is 30nm about forming an amorphous silicon containing a small amount of ^{the atom /} cc second layer and A P ⁻ semiconductor layer 216 is formed. Similarly, after applying the necessary purge, the amount of phosphorus (P) of about 1E × 10 ¹⁸ atoms / cc is contained by flowing monosilane with a small amount of phosphine flow without releasing the vacuum state. In order to form the N ⁻ semiconductor layer 236 by depositing about 30 nm of amorphous silicon, and then forming the P ⁺ semiconductor layer 246 as the fourth layer without releasing the vacuum state. Then, an amorphous silicon film containing about 1 × 10 ²¹ atoms / cc of boron is formed by using borane trichloride gas and monosilane gas. Thereby, a laminated body of amorphous silicon films composed of four layers having different boron and phosphorus concentrations is formed. In the present embodiment, the N ⁺ semiconductor layer 206 corresponds to, for example, a first semiconductor layer, and the P ⁻ semiconductor layer 216 corresponds to, for example, a second semiconductor layer.

  In the above-described process, it is desirable not to interpose an insulating film such as a natural oxide film between the respective layers of the multilayer body in order to ensure a forward current of the diode. For this reason, it is desirable to perform the four layers at a time in a state where an oxidizing atmosphere such as air, oxygen, and water vapor is excluded, such as a vacuum state and a nitrogen atmosphere state. For this purpose, it is also effective to continuously form four layers in one reaction chamber without carrying out the silicon wafer to be processed from one LPCVD reaction chamber.

  In addition, in order to avoid cross-contamination between boron, which is an acceptor, phosphorus, which is a donor, and different types of impurities, two reaction chambers are provided, with a nitrogen atmosphere or vacuum between them. It is also effective to use a multi-chamber film forming apparatus arranged so that the wafer can be conveyed without being exposed to the atmosphere. In addition, the temperature control of the vertical LPCVD furnace during film formation of each layer is adjusted so that the film thickness to be formed is uniform on the batch-processed wafer under each film formation condition. Use. In addition, in the formation of the fourth layer containing a large amount of borane trichloride, the center temperature of the furnace is lowered to about 450 ° C., thereby preventing the crystallization of silicon during the film formation and maintaining the amorphous state. Can be maintained. Maintaining this amorphous state is effective for flattening the surface morphology of the silicon film. In particular, in the case where the three-dimensional structure is accumulated as in the present embodiment, the flatness is ensured, but it is effective in improving the processed shape of the next layer that is stacked.

Thereafter, in order to form the MIM capacitor 30, as shown in FIG. 8B, a barrier metal layer BM3 is formed on the P ⁺ semiconductor layer 246, and then a heat process at 600 ° C. for about 1 minute is performed. Add. As a result, the amorphous silicon layer formed of the four-layered stack described above is changed to a stack of polycrystalline silicon layers. In this method, since the surface morphology of the amorphous silicon during the initial film formation is maintained, it can be converted into polycrystalline silicon suitable for the current characteristics of the diode while ensuring flatness.

Next, a lower electrode metal film 308, a resistance variable material film 318, and an upper electrode metal film 328 are sequentially formed on the barrier metal layer BM3. Thereafter, in order to process into a pillar shape, as shown in FIG. 8C, a silicon oxide film HM1 is formed as a hard mask material by low-temperature PE (Plasma Enhanced) CVD. As shown in FIG. 10 (a), a hard mask HM2 is formed by patterning using a resist as shown in FIG. 10B, and a RIE (Reactive Ion Etching) process is performed. The pillar-shaped elements including the stacked body composed of the four semiconductor layers and the MIM capacitor 30 are arranged so as to form a matrix. By this step, the conventional N ⁺ semiconductor layer 206, P ⁻ semiconductor layer 216, N ⁻ semiconductor layer 236, and P ⁺ semiconductor layer 246 are converted into N ⁺ semiconductor layer 208, P ⁻ semiconductor layer 218, N ⁻ semiconductor layer 238, and It becomes P ⁺ semiconductor layer 248.

  After the pillar-shaped element is formed, as shown in FIG. 10B, the pillar-shaped element is covered with the insulating film IF3 by backfilling the space between the pillars with a silicon oxide film, and the upper surface is formed by CMP (Chemical Mechanical Polishing). After planarization, as shown in FIG. 11A, the upper part of the pillar and the upper part of the insulating film are aligned.

  After that, as shown in FIG. 11B, the bit line BL as the upper wiring is formed of tungsten (W).

  Through the above steps, a pillar including a silicon diode and an MIM capacitor can be formed between the upper and lower wirings BL and WL of tungsten (W).

Further, by repeating the above steps and further stacking memory cells having the same structure upward, a three-dimensional semiconductor memory device as shown in FIG. 1 can be formed. After forming the laminated body up to the desired number of stages, if phosphorus and boron doped in polycrystalline silicon are activated by RTA (Rapid Thermal Annealing) treatment at about 900 ° C. for about 5 seconds, N ^The polysilicon of the ⁺ and P ⁺ diffusion layers can be formed as a cathode electrode and an anode electrode of the diode, respectively. At this time, the N ⁺ semiconductor layer 208 and the P ⁺ semiconductor layer 248 are respectively formed as the N ⁺ semiconductor layer 210. (Cathode) and P ⁺ semiconductor layer 250 (anode), and P ⁻ semiconductor layer 218 and N ⁻ semiconductor layer 238 become P ⁻ semiconductor layer 220, intrinsic semiconductor layer 230, and N ⁻ semiconductor layer 240, and are shown in FIG. Cell MC1 can be obtained.

  FIG. 12 is a graph schematically showing the concentrations of phosphorus and boron forming donors and acceptors in the polycrystalline silicon portion of the diode 20 by the manufacturing method of this embodiment. The graph in the upper part of the drawing of the drawing shows the concentration distribution immediately after the film formation, and the graph in the lower portion of the drawing shows the concentration distribution after all the thermal processes are finished.

After the N ⁺ semiconductor layer 208, the P ⁻ semiconductor layer 218, the N ⁻ semiconductor layer 238, and the P ⁺ semiconductor layer 248 are formed, heat treatment is performed by performing the above-described crystallization annealing or RTA treatment for activation. Diffusion occurs. Then, disposed adjacent to the N ⁺ semiconductor layer 208, a thin density relatively P ^- de of the semiconductor layer 218 - punt de of N ⁺ semiconductor layer 208 - are intermingled with punt as cancel each other Therefore, the effective distance when the dopant of the N ⁺ semiconductor layer 208 moves to the intrinsic semiconductor layer by thermal diffusion can be maintained at a small value. Similarly, the P ⁺ semiconductor layer 248, thin relatively concentration disposed adjacent N ^- de of the semiconductor layer 238 - punt of P ⁺ semiconductor layer 248 de - diffusion to cancel and mingled in Punt and each other Thus, the fluctuation of the boundary position with the P ⁺ semiconductor layer 248 can be suppressed, and the movement distance due to the thermal diffusion of the dopant of the P ⁺ semiconductor layer 248 can be effectively reduced. As a result, N was placed near the center ^- the third semiconductor layer 238 and the P ^- junction between the second semiconductor layer 218 is sufficiently because the impurity concentration is lower part, function as an intrinsic semiconductor layer 230 after the thermal process is completed To do. On the contrary, it is important to set the initial N ⁻ first semiconductor layer 206 and P ⁻ fourth semiconductor layer 246 and the positions thereof so that such a concentration is obtained after the completion of all the thermal processes. is there.

  As described above, according to the manufacturing method of the present embodiment, the first semiconductor layer serving as the cathode is adjacent to the first semiconductor layer, and the impurity having the opposite conductivity type to the impurity of the first semiconductor layer is doped at a low concentration. Similarly, the third semiconductor layer is doped with an impurity of a conductivity type opposite to that of the fourth semiconductor layer adjacent to the fourth semiconductor layer to be an anode. Since all the semiconductor layers are formed in the state of amorphous silicon and are formed into a stacked body of polycrystalline silicon by the final thermal process, the first and second semiconductor layers and the third and fourth semiconductor layers are formed. The impurities cancel each other out, diffusion of impurities into the intrinsic semiconductor layer in the first and fourth semiconductor layers is suppressed, and the thickness of the intrinsic semiconductor layer can be reduced while maintaining the rectifying function of the diode. As a result, a fine diode is provided at a low cost, and a highly integrated memory cell is provided.

(2) Second Embodiment FIG. 13 is a schematic cross-sectional view showing a schematic structure of a memory cell according to a second embodiment of the present invention. As apparent from comparison with the memory cell MC1 shown in FIG. 4, the memory cell MC2 of this embodiment includes a semiconductor diode 40 instead of the semiconductor diode 20 of FIG. The semiconductor diode 40 is the same as the semiconductor diode 20 of FIG. 4 in that the semiconductor diode 40 includes a low-concentration N ^- semiconductor layer 240 formed immediately below the anodic P ⁺ semiconductor layer 250. A P ⁻ semiconductor layer is not provided between the N ⁺ semiconductor layer 210 and the intrinsic semiconductor layer 232 forming a negative electrode. With such an arrangement, the process of providing the P ⁻ semiconductor layer can be omitted, so that the cost of the product can be further reduced. On the other hand, since diffusion of boron (B) is dominant as thermal diffusion, it is important to take measures against thermal diffusion of the dopant of the P ⁺ semiconductor layer 250 forming the anodic. Depending on the specifications, it is not necessary to provide a P ⁻ semiconductor layer adjacent to the cathode N ⁺ semiconductor layer 210.

(3) Third Embodiment FIG. 14 is a schematic cross-sectional view showing a schematic structure of a memory cell according to a third embodiment of the present invention.

In the memory cell MC1 shown in FIG. 4, the diode 20 made of polycrystalline silicon is used, but the memory cell MC3 of this embodiment is characterized in that it includes a diode 50 formed using a SiGe film. The other structure of the diode 5 is substantially the same as the diode 20 of FIG. In the present embodiment, the P ⁺ SiGe semiconductor layer 550 corresponds to, for example, the first semiconductor layer, the N ⁻ SiGe semiconductor layer 540 corresponds to, for example, the second semiconductor layer, and the P ⁻ SiGe semiconductor layer 520 corresponds to the third semiconductor layer. In addition, the N ⁺ SiGe semiconductor layer 510 corresponds to, for example, a fourth semiconductor layer.

  Thus, by using SiGe having a band gap smaller than that of polycrystalline silicon, carrier mobility can be improved and a forward current can be increased. Similarly, a forward current can be increased even in a diode made of polycrystalline germanium.

(4) Fourth Embodiment FIG. 15 is a schematic cross-sectional view showing a schematic structure of a memory cell according to a fourth embodiment of the present invention. As is clear from comparison with the memory cell MC1 shown in FIG. 4, the feature of the memory cell MC4 of this embodiment is that a Schottky barrier diode 60 is provided instead of the PIN diode 20 of FIG. . The Schottky barrier diode 60 includes an N ⁺ silicon semiconductor layer 210 (anode), a P ⁻ silicon semiconductor layer 220, an intrinsic semiconductor layer 640, and a metal thin film 650 made of NiSi ₂ (nickel disilicide) (cathode). It is composed of a stacked body formed in order from the word line WL side to the MIM 30 side. In this embodiment, N ⁺ suppresses P diffusion silicon adjacent to the semiconductor layer 210 to the dopant of the intrinsic semiconductor layer 640 of the N ⁺ silicon semiconductor layer 210 that forms the anode ^- the silicon semiconductor layer 220 is provided The thickness of the intrinsic semiconductor layer 640 can be reduced while maintaining the rectifying function of the diode. As a result, a fine diode is provided at a low cost, and a highly integrated memory cell is provided.

As a method of manufacturing the Schottky barrier diode 60, the same steps are used in FIGS. 7A to 7D in the first embodiment described above, and thereafter, as shown in FIG. Thus, an undoped amorphous silicon layer 636 is formed. Thereafter, as shown in FIG. 16B, a nickel metal thin film 648 is formed on the undoped amorphous silicon layer 636 and silicided, so that the metal thin film 650 of nickel disilicide (NiSi ₂ ) What is necessary is just to form in upper part. As a result, a Schottky diode made of N ⁺ / Intrinsic (intrinsic semiconductor layer) / NiSi ₂ can be formed. The silicide constituting the metal thin film is not limited to NiSi ₂ but may be rhodium (Rh) silicide, platinum (Pt) silicide, tungsten (W) silicide, or titanium (Ti) silicide. As the barrier metal film interposed between the diode 60 and the MIM capacitor 30, conductive metal compounds such as titanium nitride (TiN) and tantalum nitride (TaN), cobalt silicide (CoSi), titanium silicide ( In addition to metal silicides such as TiSi), tungsten silicide (WSi) and nickel silicide (NiSi), refractory metals such as tungsten (W) are preferred.

(5) Others Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and it is needless to say that the present invention can be appropriately modified and applied within the technical scope. In the above embodiment, the PIN diode and the Schottky diode have been described as the rectifying elements. However, the present invention is not limited to these diodes. For example, the semiconductor layer is depleted such as a MIS (Metal Insulator Semiconductor) diode. Needless to say, the present invention can be applied to all rectifying elements that obtain rectifying characteristics by using. In the first to third embodiments, the PIN type semiconductor diode for flowing current from the bit line BL to the word line WL via the MIM 30 has been described. However, the present invention is not limited to this, and the fourth embodiment is not limited thereto. Needless to say, the present invention can also be applied to an NIP type diode that allows current to flow from the word line WL to the bit line, such as the Schottky barrier diode 60 in the embodiment. Furthermore, the pillar structure of the diode and the MIM need not be stacked in this order from the word line WL side, and may be stacked in the order of MIM → diode from the word line WL side according to product specifications.

20, 40, 50, 60: Semiconductor diode 30: MIM capacitor 206, 208: N ⁺ amorphous silicon semiconductor layer 210, 510: N ⁺ semiconductor layer 216, 218: P ^- amorphous silicon semiconductor layer 220, 520: P ^- semiconductor layer 230, 232, 530, 640: intrinsic semiconductor layer 240, 540: N ^- semiconductor layer 246, 248: B-doped high-concentration semiconductor layer 250, 550: P ⁺ semiconductor layer 648, 650: NiSi ₂ layer BL: bit line MC1 MC4: Memory cell WL: Word line

Claims (5)

A memory element that is arranged at the intersection of first and second wirings arranged so as to be orthogonal to each other in plan view, and is electrically connected to the first and second wirings and connected in series to each other And a laminate of rectifying elements,
The rectifying element is formed of a semiconductor diode including an anode composed of a high-concentration first conductive type first semiconductor layer, an intrinsic semiconductor layer, and a cathode;
The semiconductor diode includes a low-concentration second conductivity type second semiconductor layer formed between the anode and the intrinsic semiconductor layer, and a low concentration formed between the cathode and the intrinsic semiconductor layer. And further including at least one of the third semiconductor layer of the first conductivity type.
A memory cell characterized by the above.   2. The memory cell according to claim 1, wherein an impurity concentration of the second or third semiconductor layer is equal to or less than a concentration at which a rectifying function of the semiconductor diode works.   3. The memory cell according to claim 1, wherein the cathode is composed of a high-concentration second conductive type fourth semiconductor layer.   The memory cell according to claim 1, wherein the cathode is formed using a metal material. Forming a first semiconductor layer serving as a cathode doped with an impurity of a first conductivity type at a first concentration;
Forming a second semiconductor layer doped with an impurity of a second conductivity type at a second concentration lower than the first concentration on the first semiconductor layer;
Forming a conductive layer to be an anode on the second semiconductor layer;
Activating the impurities of the first conductivity type and the second conductivity type by heat treatment;
A method for manufacturing a semiconductor diode.

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