JP2010219745A - Data reproduction circuit - Google Patents

Abstract

A data recovery circuit for performing a lockup operation at a high speed when a burst optical signal is input is provided.
A data recovery circuit according to the present invention compares a clock generated by a VCO 4 with input data and adjusts an input voltage to the VCO 4 based on a comparison result (frequency / phase comparator 1, filter). Processing circuit 2, VCO 4), identification circuit 6 for identifying and reproducing input data using a clock generated by VCO 4, and reception timing generation for specifying a data input section based on a transmission schedule from each slave station device The PLL circuit includes an EOB section included in the first data input section in a period from the end of the first data input section to the start of the next second data input section. The voltage signal that has been input to the VCO 4 is continuously input to the VCO 4.
[Selection] Figure 1

Description

  The present invention relates to a data recovery circuit for extracting a clock from an input burst optical signal and retiming data.

  Due to the spread of the Internet to ordinary households and the rapid expansion of two-way data communication, high-definition video services, etc. Therefore, there is a demand for a significant increase in speed and bandwidth. To meet this demand, in recent years, FTTH (Fiber-to-the-home), which can significantly increase the speed and bandwidth compared to ADSL using electrical signals and coaxial cables by using broadband optical signals and optical fibers. With the full-scale market launch of services, the number of subscribers to optical access services targeting subscribers is increasing exponentially.

  As a communication system that accommodates this broadband optical access service, a master station device (OLT: Optical Line Terminal) and a subscriber device (ONU: Optical Network Unit) are used by using an optical fiber and a subscriber branching optical coupler. A PON (Passive Optical Networks) system that is bi-directionally connected via a many-to-many connection is the mainstream. Regarding the PON system, for example, the following non-patent document 1 discloses a system configuration as an international standard specification.

  In the PON system defined in Non-Patent Document 1, as a method of accommodating an upstream optical signal from each ONU to the OLT, the optical signal from the ONU is intermittently burst (on / off) and multiplexed in time. A TDMA (Time Division Multiplex Access) system is required. In the TDMA system using burst optical signals, the upstream signals from the respective ONUs are multiplexed so that the optical signals do not overlap with each other in time, so that the same transmitted light is transmitted by one OLT through a single optical fiber transmission line. A plurality of ONUs having a wavelength band can be accommodated. This makes it possible to share an OLT, which is an expensive master station device, among a plurality of subscribers (ONUs), and can efficiently reduce the cost of the system.

  The cost effective system configuration of the PON system is the most important factor for realizing a reduction in service cost per subscriber and further increasing the number of subscribers to the optical access service. .

  On the other hand, the multi-subscriber accommodation method based on the TDMA method using the burst optical signal has a great advantage of reducing the system cost, but there are many technical problems for receiving the burst light at high speed. In particular, as an important issue in burst light reception, there is a realization of high-speed clock extraction means in a burst data recovery circuit that extracts clock information from burst optical signal data and retimes the data. High-speed clock extraction is an indispensable technique for shortening the extra time required for burst data reproduction and improving system throughput, but the following Non-Patent Document 1 suggests a specific circuit system and circuit configuration. It has not been.

  By the way, as a specific method for extracting a clock from input data, a clock extraction method using a feedback control type PLL (Phase Locked Loop) is generally applied. This PLL system compares the input data signal with the phase and frequency information of the oscillator of the PLL loop, adjusts the oscillation frequency of the oscillator based on the comparison signal (comparison result), and synchronizes with the frequency component of the data signal, Output as extraction clock. Here, the comparison signal for controlling the oscillator is generally generated as an integral value of the data signal, the phase of the oscillator, and the frequency error detection information. When the time constant of this integration circuit is large, it is very The control signal has a slow low frequency response. Therefore, a clock extraction circuit using a general feedback control type PLL has advantages that the circuit scale can be simplified, integration is easy, and a highly accurate clock with excellent jitter characteristics can be extracted. On the other hand, it is difficult to obtain high-speed response characteristics unless special measures are taken.

  Even when the required high-speed response characteristic is obtained by adjusting the time constant of the integration circuit, a new problem occurs when a burst optical signal is input. That is, when the input signal is a burst optical signal, the PLL loop is out of synchronization in the interval where there is no signal input, and the oscillator output is in a free-running frequency oscillation state that is independent of the frequency and phase of the input data. When data (signal) is input in such an unlocked state where the PLL loop is out of synchronization, the phase / frequency information of the data signal and the phase / frequency information of the oscillator in which the PLL loop is free-running. Since the error in the data is very large, the time from when the burst data is input until the clock is stably extracted, that is, the lock-up time increases in proportion to the error, which significantly impedes the high-speed response characteristics. . In addition, in a process where a signal is input from such an unlocked state and stabilized to a predetermined phase and frequency, an operation that repeats a large transient vibration, usually called a cycle slip, is performed from a locked state to a locked state. Since it occurs continuously for a long time compared to the transition time to, response characteristics are further deteriorated.

  An example of means for solving such a problem is described in Patent Document 1 below. In the circuit described in Patent Document 1, a feedback control type PLL loop is synchronized with an input carrier when a carrier signal is detected based on a carrier detection circuit that detects an input signal and information from the carrier detection circuit. A PLL loop, and when a carrier signal is not detected, switching to a PLL loop that synchronizes with another clock signal having the same frequency information as the carrier signal, thereby switching the PLL loop to the carrier frequency even when there is no carrier signal Are synchronized to achieve high-speed lock-up operation when a carrier is input.

JP 2000-174616 A

IEEE 802.3-2005

  However, when the technique described in Patent Document 1 is applied to an actual PON system, the following problems occur.

  First, in the configuration shown in FIG. 1 of Patent Document 1, when the carrier signal and the external clock are switched, the comparison error can easily be maximized instantaneously at the input of the phase comparator. In a phase comparison circuit using an EX-OR that linearly outputs a phase error, the lock state cannot actually be maintained, and the lock-up operation from the unlock state may occur again. There are many. For this reason, there is a problem that the lock-up operation cannot be effectively performed at high speed.

  In the configuration shown in FIGS. 9 and 13 of Patent Document 1, it is usually difficult to accurately match the voltage level in the loop synchronization state with the voltage level based on another voltage source. In particular, when an integrated circuit (IC) that is often applied to realize a PLL circuit is created at a mass production level, this voltage level is individually controlled and adjusted in consideration of manufacturing variations. Increases costs. In addition, in order to realize a high-speed lockup operation, it is necessary to set a large loop gain, and this voltage level error eventually increases as a frequency error. Further, it is necessary to reduce the external voltage level error. In addition, there is a problem that the switching control means with the voltage source is not clear, and the lockup operation cannot be effectively speeded up due to transient chattering or the like.

  As a configuration for avoiding this problem, FIG. 10 and FIG. 14 of the document disclose a configuration for maintaining a synchronization voltage level according to a carrier detection signal. However, in the carrier detection method shown in this method, the carrier is disconnected. Therefore, it is impossible to maintain the synchronized state that preserves the time when the carrier was input. Also, the holding method is not clear. For example, when a holding capacitor is inserted, the time constant of the loop filter becomes large, and as a result, the lock-up operation cannot be speeded up, and the holding time is also the lock-up time. Therefore, it is impossible to provide a holding time for continuing the synchronization state when the lock-up time is long, and particularly when the no-signal section where the burst optical signal is not input is long as in the PON system.

  In addition, the carrier detection method described in Patent Document 1 requires the number of clocks up to the amount recognized as an error. For example, a carrier input of 10E + 4 clocks or more is required to determine an error of 100 ppm or less, which is determined as a normal synchronization state. Actually, it takes a long carrier input detection time / disconnection detection time. The lockup time, which is the time until the clock is extracted, cannot be effectively increased. In addition, a high-gain limiting amplifier is input in front of the burst data reproduction circuit to obtain a predetermined signal amplitude, and a differential drive method is generally applied to high-speed data input. Even in the state, the differential state is not completely balanced, and noise data having the same amplitude as the carrier signal is often output. In this case, there is a problem that it is necessary to tighten the input determination standard in order to distinguish it from the carrier signal, and the longer the carrier detection time, the longer the lockup time.

  The present invention has been made in view of the above, and even when a burst optical signal is input, the lock-up operation is performed at a high speed by avoiding the unlock state in the no-signal section (lock-up operation). An object is to obtain a data reproduction circuit).

  In order to solve the above-described problems and achieve the object, the present invention provides a data recovery circuit for identifying and reproducing input burst data in a master station apparatus of an optical communication system for transmitting and receiving burst data, A PLL circuit that compares a clock generated by the VCO with input data and adjusts an input voltage to the VCO based on the comparison result, and an input using the clock generated by the VCO of the PLL circuit An identification reproduction circuit that identifies and reproduces data; and a data input section identification unit that identifies a section in which data is input (data input section) based on a transmission schedule from each slave station device, and the PLL circuit includes: After a certain data input interval (first data input interval) ends, the interval (decode) until the next data input interval (second data input interval) starts In data non-input section), a voltage signal which has been input and at EOB section included in the first data input section to the VCO, characterized in that to continuously input to the VCO.

  According to the present invention, since the voltage signal input to the VCO in the data input section is continuously input to the VCO in the data non-input section, the data input section becomes a data input section and burst data input is resumed. By reducing the initial frequency / phase synchronization error and not creating an unlocked state, it is possible to shorten the lock-up time, which is a transient process until a stable synchronized state is achieved. The effect is that a high-speed lockup operation can be realized.

FIG. 1 is a diagram illustrating a configuration example of a data reproduction circuit according to a first embodiment of the present invention. FIG. 2 is a diagram showing a timing chart of the recovery clock extraction operation in the data recovery circuit of the first embodiment. FIG. 3 is a diagram illustrating a configuration example of the filter processing circuit. FIG. 4 is a diagram illustrating a configuration example of the data reproduction circuit according to the second embodiment. FIG. 5 is a diagram illustrating a configuration example of a frequency / phase comparator. FIG. 6 is a diagram showing a timing chart (simulation result) of the frequency / phase comparator. FIG. 7 is a timing chart of the recovery clock extraction operation in the data recovery circuit of the second embodiment. FIG. 8 is a diagram illustrating a configuration example of the data reproduction circuit according to the third embodiment. FIG. 9 is a timing chart of the reproduction clock extraction operation in the data reproduction circuit according to the third embodiment.

  Embodiments of a data reproduction circuit according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram illustrating a configuration example of a data reproduction circuit according to a first embodiment of the present invention. The data recovery circuit includes a frequency / phase comparator 1, a filter processing circuit 2, a pass / hold signal generation circuit 3, a voltage controlled oscillator (VCO) 4, a 1 / N frequency divider 5, and an identification circuit 6. , Including a delay adjustment circuit 7 and a reception timing generation circuit 8 (corresponding to a data input section specifying means), and an optical communication system to which a TDMA system is applied, a master station receiving apparatus for receiving an optical signal transmitted in time division multiplexing Constitute.

  In FIG. 1, a frequency / phase comparator 1 compares the frequency and phase of two input signals. The filter processing circuit 2 includes a loop filter 21 that filters the input signal from the frequency / phase comparator 1 and other signal processing circuits, and according to the input signal (pass / hold switching signal) from the pass / hold signal generation circuit 3. The filtering result of the loop filter 21 or the alternative filtering result that holds the filtering result in a state where the burst data is input is output. The pass / hold signal generation circuit 3 generates a pass / hold switching signal, which is an operation control signal of the filter processing circuit 2, based on the signal (valid data interval signal) output from the reception timing generation circuit 8. The VCO 4 generates a clock having a frequency corresponding to the voltage level of the input signal. The 1 / N frequency divider 5 divides the input signal and generates a signal having a frequency of 1 / N with respect to the input signal. The identification circuit 6 identifies and reproduces input data. The delay adjustment circuit 7 gives a predetermined amount of delay to the input. The reception timing generation circuit 8 generates a valid data section signal (details will be described later).

  The operation of the data reproduction circuit having the above configuration will be described below. In the description of the operation, for simplification, it is assumed that the frequency division ratio of the 1 / N frequency divider 5 is N = 1 and the 1 / N frequency divider 5 outputs the input signal as it is. That is, the description will be made assuming that the clock output from the VCO 4 is input to the frequency / phase comparator 1 as it is.

  Input data that is intermittent in time (burst input data) is input to the frequency / phase comparator 1 and the delay adjustment circuit 7. The frequency / phase comparator 1 determines the frequency and phase of the input data and the clock input from the VCO 4. Compare phases. The error information obtained as a result is input to the filter processing circuit 2, and the filter processing circuit 2 that has received the error information integrates the error information according to the time constant in which the loop filter 21 is set. The integration result is output as a comparison result between the input data and the VCO4 output clock. Here, the configuration of the frequency / phase comparison 1 and the loop filter 21 is not limited, and in these components, the frequency of the input data is high according to the frequency / phase comparison result between the input data and the clock, or When the phase is advanced, the voltage level increases according to the time constant of the loop filter 21, while when the frequency is low or the phase is delayed, the voltage level generally decreases according to the time constant of the loop filter 21. An operation equivalent to that of a simple PLL circuit is performed.

  In the filter processing circuit 2, the voltage level output from the loop filter 21 is a signal generated by the passing / holding signal generating circuit (passing / holding switching signal) based on the valid data section signal given from the reception timing generation circuit 8. ) Is handled as follows according to the state of That is, when the pass / hold switching signal indicates the pass state, the output of the loop filter 21 is output from the filter processing circuit 2 as it is. On the other hand, when it indicates the hold state, the time when the hold signal is input (pass / hold) While the output (output voltage level) of the loop filter 21 at the time when the switching signal changes from the passing state to the holding state), the voltage is applied until the next passing signal is given (until the change from the holding state to the passing state). Continue to output level.

  The voltage level output from the filter processing circuit 2 is input to the VCO 4, and the VCO 4 changes the oscillation frequency according to the input voltage level. The frequency-changed clock output by the VCO 4 is input to the frequency / phase comparator 1 again. When the output of the pass / hold signal generation circuit 3 is in the pass state, a feedback control loop with the input data is formed. After repeating the operation, the VCO 4 converges to a state in which a recovered clock synchronized with the input data is output. When the output of the pass / hold signal generation circuit 3 is in the hold state, the feedback control loop with the input data is in an open state, and the VCO 4 is at the voltage level held by the filter processing circuit 2 regardless of the presence or absence of the input data. Continues oscillation. The clock output from the VCO 4 is input to the frequency / phase comparator 1 and also input to the identification circuit 6 as a reproduction clock. The identification circuit 6 uses the reproduction clock to identify and reproduce the input data. And output as playback data. The delay adjustment circuit 7 is inserted for the purpose of optimizing the identification timing between the input data and the recovered clock, and compensates for circuit delay and the like.

  FIG. 2 is a diagram showing a timing chart of the recovery clock extraction operation in the data recovery circuit of the first embodiment. (A) Burst input data, (b) Valid data section signal (output of the reception timing generation circuit 8) , (C) The operation timing of the pass / hold switching signal (output of the pass / hold signal generation circuit 3) and (d) the reproduction clock (output of the VCO 4).

  (a) Burst input data is composed of burst packets (..., burst packet # n-1, burst packet #n, burst packet # n + 1, ...) that are intermittent in time, and each burst packet is an overhead period. And an EOB (End of Burst) pattern section indicating the end of the burst packet. In the PON system, the overhead period is given as a spare time necessary for burst data reproduction, and EOB is given as a spare period for determining the end of a burst packet.

  (b) The valid data section signal indicates a section in which a burst packet is input, and outputs a Hi level when valid data is input, and outputs a Low level as a section without valid data when a burst packet is not input. Here, the valid data section signal is determined based on the reception timing (scheduling result) generated by the scheduler (not shown) that manages the transmission / reception timing of the entire PON system in the reception timing generation circuit 8. This valid data section signal can accurately set the start position and end position of the valid data section according to the scheduling result (data transmission permission section for each ONU) for each ONU in the system. This eliminates the influence of noise output that occurs spontaneously at the limiting amplifier (not shown) in the previous stage of the data generation circuit, which may occur in the no-signal input section, and corrects only the data section. Can be distinguished. Further, by adjusting the start and end positions of the valid data section between the overhead section and the EOB section, respectively, it is possible to designate the area where the input data exists as the valid data section. As a result, the holding start point can be set as an area where data exists, and the synchronization information can be held accurately.

  (c) The input passing / holding switching signal is generated by the passing / holding signal generation circuit 3 based on the valid data section signal. In the valid data input section, the Hi level indicating the passing state is output and there is no valid data. In the section, the Low level indicating the holding state is output.

  (d) The recovered clock operates as follows according to the pass / hold switching signal. That is, when burst packet # n-1 is input and the passing / holding switching signal is in a passing state (Hi level), a feedback control loop of input data and VCO4 output (clock) is configured, and after the lockup operation is completed, The VCO 4 outputs a stable extraction clock. After that, when the pass / hold switching signal becomes the holding state (Low level), the holding state is instantaneously entered. Here, as shown in the figure, since the timing of changing to the holding state is before the end of burst packet # n-1 (within the EOB section), the voltage level synchronized with the data can be held. Therefore, if there is no error between the holding voltage level and the output level of the loop filter 21 in the extracted clock output state, the VCO 4 sends a reproduction clock synchronized with the burst packet # n-1 (burst packet # n-1 shown in the figure). (Synchronous clock) continues to be output. The reproduction clock output is continued over the entire no signal input interval between burst packets, and the VCO 4 is in a state in which frequency synchronization with the input data is maintained. In this state, when the next burst packet #n is input and a passing signal (passing / holding switching signal indicating the passing state) is output, the PLL circuit (frequency / phase comparator 1, filter processing circuit 2, VCO 4 and Since the frequency synchronization with the 1 / N frequency divider 5) is already established with the burst packet #n, it becomes a feedback control loop only for phase comparison and can realize a high-speed lockup operation. Thereafter, the same operation is repeated according to the burst packet input and the intermittent state.

  Next, the detailed operation of the filter processing circuit 2 will be described. FIG. 3 is a diagram illustrating a configuration example of the filter processing circuit 2. As illustrated, the filter processing circuit 2 includes a loop filter 21 composed of resistors R1 and R2 and a capacitor C1, a switch 22 controlled by a pass / hold switching signal, and a plurality of (two in this example) transistors. And the output circuit 23 configured by Darlington connection. As a feature, the capacitor C1 constituting the loop filter 21 operates as a capacitor for maintaining the voltage level.

  In this filter processing circuit 2, when the pass / hold switching signal indicates a pass state, the switch 22 is closed and the input signal (frequency / phase comparator output) from the frequency / phase comparator 1 (see FIG. 1) is looped as it is. The signal is integrated by the filter 21 and output from the output circuit 23 to the VCO 4 at the next stage. That is, a passing operation is performed. On the other hand, when the passing / holding switching signal indicates the holding state, the switch 21 is opened, and the charge amount charged in the capacitor C1, that is, the voltage level at the moment when the switch 22 is opened is output to the VCO 4 in the next stage. Thus, a holding operation for holding and outputting a constant voltage level is performed regardless of the output of the phase comparator 1. The voltage level (holding voltage level) gradually decreases as the electric charge charged in the capacitor C1 is discharged through the output circuit 23. The output circuit 23 has a circuit configuration with a large current gain, for example, as shown in FIG. By using such a Darlington connection, the amount of electric charge discharged in the non-signal period (time) can be set to a negligible level.

  With this circuit configuration, the voltage level at the time of passing / holding switching can be held as a continuous analog amount, and the error can be suppressed to a negligible level, and in the no-signal section (time) A stable voltage level can be maintained. Further, by appropriately selecting the value of the capacitor C1, it is possible to speed up the time constant of the loop filter 21 necessary for speeding up the lockup and to output a sufficiently stable voltage level over the entire non-signal section. Furthermore, the loop filter 21 has a lag / lead filter configuration, so that the damping characteristics, vibration characteristics and holding characteristics of the PLL feedback control loop necessary for shortening the lock-up time of the PLL loop can be adjusted to some extent independently. It becomes possible to optimize the PLL loop.

  As described above, in the data recovery circuit of this embodiment, when there is data input, the filter processing circuit outputs the filtering result by the loop filter to the subsequent VCO, and based on the uplink transmission scheduling result. Identify the section where the data is input (valid data input section), hold the filtering result (voltage level) before this section ends, and then until the next valid data input section (no signal section) ), Feedback control is performed using the retained signal instead of the filtering result by the loop filter. As a result, for example, even when a data recovery circuit is applied to a PON system and intermittent burst data is input in time, it is always synchronized with the frequency when burst data is input in the no-signal section. It is possible to provide a VCO clock stably, and reduce the initial error of frequency / phase synchronization when burst data input is resumed. In addition, an unlocked state is not created, thereby achieving a stable synchronized state. It is possible to shorten the lock-up time, which is a transient process up to, and realize a high-speed lock-up operation when a burst optical signal is input.

Embodiment 2. FIG.
FIG. 4 is a diagram illustrating a configuration example of the data reproduction circuit according to the second embodiment. In the data recovery circuit of this embodiment, the frequency / phase comparator 1 of the data recovery circuit (see FIG. 1) described in the first embodiment is replaced with a frequency / phase comparator 1a, and a variable gain amplifier 9 is added. This is the configuration. Therefore, in the present embodiment, description will be made mainly on the operations of the frequency / phase comparator 1a and the variable gain amplifier 9, and the same components as those in the data reproduction circuit of the first embodiment are denoted by the same reference numerals. A description thereof will be omitted. In the present embodiment, similarly to the first embodiment, the frequency division ratio of the 1 / N frequency divider 5 is assumed to be N = 1.

  In the data recovery circuit according to the present embodiment, the frequency / phase comparator 1a determines the frequency and phase of the input data and the clock input from the VCO 4 in the same manner as the frequency / phase comparator 1 described in the first embodiment. It has a function of comparing and outputting error information. In addition, when frequency synchronization between the input data and the input clock is detected, it has a function of notifying the outside using a frequency synchronization signal. The error information output from the frequency / phase comparator 1a is input to the filter processing circuit 2, and the filter processing circuit 2 executes the processing described in the first embodiment. On the other hand, the frequency synchronization signal is input to the variable gain amplifier 9.

  The variable gain amplifier 9 is arranged between the filter processing circuit 2 and the VCO 4, and receives an input signal (frequency synchronization signal) from the frequency / phase comparator 1 a and an input signal (pass / hold) from the pass / hold signal generation circuit 3. The switching signal is received, the input signal from the filter processing circuit 2 is amplified with a gain according to the state, and is output to the VCO 4 at the subsequent stage. To describe the operation in more detail, the variable gain amplifier 9 amplifies the input signal with a small gain when the frequency synchronization signal indicates that the frequency is in a synchronous state, otherwise (the frequency is in an asynchronous state). Amplify with a large gain). However, this amplification operation is performed only when the pass / hold switching signal indicates the pass state, and when the signal indicates the hold state, the gain setting at the time when the signal is changed to the hold state is held (with a small gain). Amplification process).

  FIG. 5 is a diagram illustrating a configuration example of the frequency / phase comparator 1a. As shown, the frequency / phase comparator 1a includes two sample-and-hold type phase detection circuits 11 and 12 (corresponding to first and second sampling means) and a frequency detection circuit 13 (corresponding to third sampling means). ) And the selector 14, as described above, the input data (burst input data) and the input clock (VCO output clock) are compared, and the error information (comparison result) and the frequency synchronization signal are output. The overall operation of the frequency / phase comparator 1a will be described below.

  In the frequency / phase comparator 1a, data (burst input data) and a clock (VCO output clock) are input to the sample and hold type phase detection circuits 11 and 12, and the sample and hold type phase detection circuits 11 and 12 have a burst input. The VCO output clock is sampled at the rising and falling edges of the data, and the hold level is output. However, among the clocks input to these circuits, the clock input to the sample-and-hold type phase detection circuit 12 is input with a delay of about π / 2 with respect to the other. The circuit gains of the sample-and-hold type phase detection circuits 11 and 12 are different. The former has a low circuit gain and the latter has a high circuit gain. In the following description, the sample and hold type phase detection circuit 11 will be referred to as the S / HI circuit 11 and the sample and hold type phase detection circuit 12 will be referred to as the S / H-Q circuit 12 as necessary. Distinguish.

  The frequency detection circuit 13 samples the output signal from the S / HI circuit 11 at the rising edge of the output signal from the S / H-Q circuit 12, and outputs a hold value. The selector 14 selects an input signal from the S / H-I circuit 11 or an input signal from the frequency detection circuit 13 according to the output signal from the S / H-Q circuit 12, and outputs it as a comparison result. The frequency / phase comparator 1a inverts the output signal from the S / H-Q circuit 12 and outputs it as a frequency synchronization signal.

  Next, the operation of the frequency / phase comparator 1a will be described with reference to the block diagram and timing chart of FIG. FIG. 6 is a diagram showing a timing chart (simulation result) of the frequency / phase comparator 1a. Note that the simulation conditions when the result of FIG. 6 is obtained set an example that makes the explanation simple, and does not limit the circuit operation.

  6 shows (1) VCO output, (2) VCO π / 2 shift output, (3) input data, (4) S / HI output, (5) S / HQ output, and (6) frequency detection. (1) VCO output is a clock input to the S / HI circuit 11, (2) VCOπ / 2 shift output is S / H-Q. This is an input to the circuit 12 and (1) a clock whose phase is shifted by approximately π / 2 from the VCO output.

  In the frequency / phase comparator 1a, the S / HI circuit 11 outputs (1) the VCO output (clock), the S / H-Q circuit 12 outputs (2) the VCOπ / 2 shift output, and (3) the input data. Sampling is performed at both edges. At this time, the sampling result at the rising edge is output as the hold value as it is until the next sampling (falling sampling edge) is executed, while the sampling result at the falling edge is inverted and the next sampling is performed as the hold value. Output until (rising sampling edge) is executed.

  As a result, the outputs from the S / HI circuit 11 and the S / HQ circuit 12 are as shown in (4) S / HI output and (5) S / HQ output in FIG. The signal of the beat frequency component according to the frequency / phase shift. Here, (5) the low level region of the S / H-Q output indicates that (1) the phase of the VCO output (clock) and the phase of the input data are within about ± π / 2. In this case ((5) S / H-Q output is at low level), the selector 14 selects (4) S / HI output and outputs it as a comparison result (error information), assuming that the frequency is synchronized. To do. On the other hand, when the (5) S / HQ output is at the Hi level, the selector 14 selects (6) the frequency detection circuit output and outputs it as the comparison result (error information), assuming that the frequency is asynchronous.

  As described above, (6) the frequency detection circuit output is the result of sampling and holding (4) S / HI output at the rising edge of (5) S / H-Q output. When the VCO frequency is (3) higher than the input data frequency, it becomes Hi level. (1) When the VCO frequency is lower than the input data frequency, it becomes Low level.

  As described above, in the frequency / phase comparison process, when the VCO phase and the input data phase do not have a phase difference within about ± π / 2 in the frequency / phase comparison process, that is, (5) S / HQ output is In the high level section, it is determined that the frequency is asynchronous, and (6) the output of the frequency detection circuit is output as (7) the comparison result. On the other hand, when the VCO phase and the input data phase have a phase difference within about ± π / 2, that is, (5) when the S / H-Q output is at the low level, it is determined that the frequency is in a synchronized state. A certain (4) S / HI output is output as a (7) comparison result.

  As a result, it is possible to generate a frequency synchronization signal in response to detection of the frequency synchronization state of the input data and the input clock and to output a comparison result. In addition, since the frequency / phase comparator 1a itself can easily and quickly realize the frequency comparison operation with a large detection gain and the phase comparison operation with a small detection gain, it contributes to high-speed lockup characteristics. Can do.

  FIG. 7 is a timing chart of the recovery clock extraction operation in the data recovery circuit of the second embodiment. Note that the data reproduction circuit of the present embodiment is a modification of the data reproduction circuit of the first embodiment, and therefore only the parts different from the timing chart (see FIG. 2) described in the first embodiment will be described. FIG. 7 is a timing chart of FIG. 2 in which operation timings of (e) frequency synchronization signal and (f) variable gain amplifier gain setting value are added.

  (e) As already described, the frequency synchronization signal is a signal output from the frequency / phase comparator 1a to the variable gain amplifier 9, and is controlled at high speed in accordance with the data input state to the frequency / phase comparator 1a. When the frequency is synchronized, it becomes Hi level, and when it becomes asynchronous, it becomes Low level. (c) In the initial operation state in which the pass / hold switching signal is in the pass state and the feedback control loop is formed, the synchronization and the asynchronous state are repeated, and then the stable synchronous state is obtained, and in the no-signal input section, the asynchronous state is obtained.

  (f) The variable gain amplifier gain setting value (e) follows the frequency synchronization signal and increases the gain when this signal indicates an asynchronous state, and decreases the gain when this signal indicates a synchronous state.

  In general, in a PLL loop, increasing the loop gain improves the transient response characteristics and enables fast lockup, while decreasing the loop gain improves the jitter characteristics, and there is a trade-off relationship between them. is there. Therefore, by increasing the loop gain when asynchronous in the lockup process, the lockup time can be further shortened, and further, by reducing the loop gain during synchronization, a stable feedback control loop with improved jitter characteristics. Can be configured. The variable gain amplifier 9 is also controlled by (c) a pass / hold switching signal, and performs an operation of holding a low gain state in the hold state. As a result, the holding voltage level (output voltage from the filter processing circuit 2 in the holding section) can be stabilized and input to the no-signal section as compared with the data reproduction circuit described in the first embodiment. A constant gain state can be maintained even when an erroneous frequency synchronization signal is output due to erroneous synchronization with noise from a limiting amplifier or the like.

  As described above, in addition to the function of the data recovery circuit of the first embodiment, the data recovery circuit of the present embodiment changes the gain of the amplifier used in the feedback control loop according to the frequency synchronization state ( If it is synchronized, it will be reduced, otherwise it will be increased). Thereby, in addition to the effects shown in the first embodiment, the lock-up time can be further shortened, and a stable feedback control loop with improved jitter characteristics can be realized in a state where the frequencies are synchronized. Further, in the no-signal input section, the holding voltage level can be stabilized as compared with the data reproduction circuit of the first embodiment, and the erroneous frequency synchronization signal is erroneously synchronized with noise from the limiting amplifier or the like. Even when it is output, a constant gain state can be maintained.

Embodiment 3 FIG.
FIG. 8 is a diagram illustrating a configuration example of the data reproduction circuit according to the third embodiment. The data reproduction circuit of this embodiment is different from the data reproduction circuit described in the second embodiment (see FIG. 4) in the selector 31, the 1 / N frequency divider 32, and the frequency / phase comparator 33 (corresponding to comparison means). ), A frequency error detection circuit 34 and a reference clock generation unit 35 are added, and the pass / hold signal generation circuit 3 is replaced with a pass / hold signal generation circuit 3b. For this reason, in the present embodiment, description will be made centering on the operation of these added or replaced components, and the same components as those in the data reproduction circuit of the second embodiment will be denoted by the same reference numerals. Is omitted. In the present embodiment, similarly to Embodiments 1 and 2, the frequency division ratio of 1 / N frequency divider 5 will be described as N = 1.

  In the data reproduction circuit of the present embodiment, the selector 31 receives either one of the input signal from the frequency / phase comparator 1 a and the input signal from the frequency / phase comparator 33 from the frequency error detection circuit 34. The signal is selected according to the state of the input signal (frequency error detection signal) and the input signal (pass / hold switching signal) from the pass / hold signal generation circuit 3 b and is output to the filter processing circuit 2. The 1 / N frequency divider 32 divides the clock output from the VCO 4 by N and outputs it to the frequency / phase comparator 33. The frequency / phase comparator 33 compares the input signal from the 1 / N frequency divider 32 with the input signal from the reference clock generator 35 and outputs the comparison result to the selector 31. The frequency error detection circuit 34 monitors the input signal from the 1 / N frequency divider 32 and the input signal from the reference clock generation unit 35. If there is an error exceeding a certain amount in these frequencies, the frequency error detection circuit 34 indicates that. The selector 31 is notified by the detection signal. The reference clock generator 35 generates a reference clock synchronized with the system frequency. The pass / hold signal generation circuit 3b performs the above-described pass / hold switching based on the input signal (valid data interval signal) from the reception timing generation circuit 8 and the input signal (frequency error detection signal) from the frequency error detection circuit 34. A signal and an operation instruction signal instructing operation start / stop of the frequency error detection circuit 34 are generated.

  Of the control operation in the data generation circuit of the present embodiment, a portion different from the data generation circuit of the second embodiment will be described. In the data generation circuit of the present embodiment, the clock output from the VCO 4 is input to the frequency / phase comparator 1 a and also input to the frequency / phase comparator 33 via the 1 / N divider 32. The The comparison method in the frequency / phase comparator 33 is not particularly limited. The frequency / phase comparator 33 compares the frequency and phase of the divided clock input from the VCO 4 via the 1 / N divider 32 and the reference clock received from the reference clock generator 35. The comparison result obtained is output. The comparison result is input to the selector 31. In the PON system, since the entire system is frequency-synchronized with the reference clock, the input data to the data recovery circuit and the reference clock are frequency-synchronized.

  Based on a control signal, which will be described later, the selector 31 provides a feedback control loop for the burst input data and the VCO 4 (path for the burst input data from the VCO 4 to the selector 31 via the frequency / phase comparator 1a. And a feedback control loop of the reference clock and the VCO 4 (a feedback control loop in a path from the VCO 4 as an input to the selector 31 via the frequency / phase comparator 33).

  The frequency error detection circuit 34 detects the frequency error between the frequency-divided clock received from the 1 / N frequency divider 32 and the reference clock, and when the detected frequency error reaches a predetermined value set arbitrarily, the frequency error is detected. The selector 31 and the pass / hold signal generation circuit 3b are notified that an error has been detected. The frequency error detection operation is started and stopped in accordance with instructions from the pass / hold signal generation circuit 3b. Here, the frequency error detection circuit 34 may be realized by using a general clock pulse number counting method or the like. That is, while counting a fixed time (pulse) using the reference clock, the number of pulses of the clock (VCO clock) input from the 1 / N frequency divider 32 is also counted, and the count value of the VCO clock is less than the target range. If it is shifted, it is determined that there is a frequency error. At this time, a frequency error signal is output (updated). The frequency error signal is a latch signal, and then the transmission information signal is input. As a result, the logic level is fixed until an operation stop instruction is issued from the pass / hold signal generation circuit 3b. When the frequency error detection signal is latched (when the frequency error is detected), the selector 31 selects the feedback control loop (input from the frequency / phase comparator 33) of the VCO 4 and the reference clock, and performs subsequent filter processing. Output to circuit 2. Thereafter, when a passage information signal (burst data) is input and, as a result, the latched state is released, the selector 31 switches to the feedback control loop (input from the frequency / phase comparator 1a) for the VCO 4 and the input burst data. .

  Further, the pass / hold signal generation circuit 3b sets the pass / hold switch signal state to the pass state even when the frequency error detection signal is latched. That is, the passing / holding signal generation circuit 3b has a case where the valid data section signal from the reception timing generation circuit 8 is Hi (when valid data is input) and a frequency error is detected by the frequency error detection circuit 34. The state of the pass / hold switching signal is set to the pass state. When the valid data section signal changes to Hi, the pass / hold signal generation circuit 3b sets the pass / hold switch signal to the pass state and performs a frequency error detection operation on the frequency error detection circuit 34. Instruct to stop. On the other hand, when the frequency error detection signal is latched, no stop instruction is given. Further, when the valid data section signal changes to Low, the pass / hold signal generation circuit 3b instructs the frequency error detection circuit 34 to start the frequency error detection operation.

  FIG. 9 is a timing chart of the reproduction clock extraction operation in the data reproduction circuit according to the third embodiment. Note that the data reproduction circuit according to the present embodiment is a modification of the data reproduction circuit according to the second embodiment, and therefore only different portions from the timing chart (see FIG. 7) described in the second embodiment will be described. FIG. 9 is a timing chart of FIG. 7 in which (g) the operation timing of the frequency error detection signal is added.

  The frequency error detection circuit 34 is initialized and reset in accordance with an operation start instruction signal issued from the pass / hold signal generation circuit 3b in response to an edge (falling edge) in which the valid data section signal becomes a section without valid data (b). The frequency error detection is started. When the no-signal section lasts for a very long time, the holding voltage level (the output voltage from the filter processing circuit 2 in the holding section) gradually changes as the charge charges are discharged, so that the VCO4 output clock is frequency-synchronized with the input data. You will be out of the state you were doing. In this case, the frequency error detection circuit 34 detects this loss of synchronization as a predetermined frequency error, and (g) latches the frequency error detection signal at the Hi level. The selector 31 switches to output the input signal from the frequency / phase comparator 33 when (g) the frequency error detection signal becomes Hi. At this time, the pass / hold signal generation circuit 3b switches the pass / hold switch signal to the pass state. As a result, the VCO 4 becomes a feedback control loop with the reference clock, and a clock synchronized with the reference clock is output from the VCO 4. After that, when (a) burst input data is input again and (b) the valid data section signal changes to the valid data input section, an operation stop instruction signal is issued from the pass / hold signal generation circuit 3b, and (g) frequency error detection The signal is reset. As a result, the selector 31 switches to output the input signal from the frequency / phase comparator 1a, becomes a feedback control loop between the VCO 4 and the burst input data, and repeats the above-described clock extraction process.

  Thus, in addition to the function of the data recovery circuit of the second embodiment, the data recovery circuit of the present embodiment further uses the reference clock that is frequency-synchronized with the input data to When the frequency synchronization state is monitored and it is detected that the frequency error has reached a certain level, the feedback control loop operation is continued using the reference clock. As a result, in addition to the effects shown in the first and second embodiments, the initial error of frequency / phase synchronization is reduced even when a burst packet is next input from a state where there is no data input for a long time, and the unlock state It is possible to reduce the lock-up time, which is a transient process until a stable synchronization state is achieved. That is, a high-speed lockup operation when a burst optical signal is input can be realized.

  In this embodiment, the operation when the data reproduction circuit of the second embodiment is modified has been described. However, the data reproduction circuit of the first embodiment (see FIG. 1) can be similarly modified. is there. In this case, the frequency / phase comparator 1a of the data recovery circuit (see FIG. 8) of this embodiment is replaced with the frequency / phase comparator 1, and the variable gain amplifier 9 is deleted.

  As described above, the data recovery circuit according to the present invention is useful for clock recovery in a burst optical signal receiver, and in particular, a master station side that receives burst optical signals transmitted by TDMA from a plurality of subscriber side devices. It is suitable for receiving devices.

1, 1a, 33 Frequency / phase comparator 2 Filter processing circuit 3, 3b Pass / hold signal generation circuit 4 Voltage controlled oscillator (VCO)
5, 32 1 / N frequency divider 6 Discriminating circuit 7 Delay adjustment circuit 8 Reception timing generation circuit 9 Gain variable amplifier 11, 12 Sample hold type phase detection circuit 13 Frequency detection circuit 14 Selector 21 Loop filter 22 Switch 23 Output circuit 31 Selector 34 Frequency error detection circuit 35 Reference clock generator

Claims (6)

In a master station device of an optical communication system that performs transmission / reception of burst data, a data recovery circuit for identifying and reproducing input burst data,
A PLL circuit that includes a VCO, compares a clock generated by the VCO with input data, and adjusts an input voltage to the VCO based on a comparison result;
An identification reproduction circuit for identifying and reproducing input data using a clock generated by the VCO of the PLL circuit;
A data input section specifying means for specifying a section (data input section) in which data is input based on a transmission schedule from each slave station device;
With
The PLL circuit has a period (data non-input period) from the end of a certain data input section (first data input section) to the start of the next data input section (second data input section). A data reproduction circuit characterized in that a voltage signal input to the VCO in an EOB section included in the first data input section is continuously input to the VCO. The PLL circuit includes:
As a configuration for continuously inputting the voltage signal input to the VCO in the EOB section to the VCO,
A switch that is in a closed state in the data input section and outputs a comparison result between the clock generated by the VCO and the input data, which is an input from the previous stage;
A loop filter for integrating the output from the switch;
When the switch is open, the electric charge accumulated in the capacitor constituting the time constant of the loop filter is output as a VCO in the subsequent stage, and the output has a current gain that is high enough to ignore the time variation of the discharge current from the capacitor. Circuit,
The data reproduction circuit according to claim 1, further comprising: The PLL circuit includes:
For the operation in the data input section, according to the frequency comparison result obtained by comparing the clock generated by the VCO and the input data and indicating whether these clock and input data are in a frequency synchronization state, A variable gain amplifier that amplifies the input signal to the VCO with a different gain for each state;
The data reproduction circuit according to claim 1, further comprising: The PLL circuit includes:
As a configuration for comparing the clock generated by the VCO and the input data,
The input data is sampled at both edges of the clock generated by the VCO, and the sampling result at the rising edge is kept as it is, while the sampling result at the falling edge is inverted and output until the next sampling timing is reached. Sampling means,
A signal obtained by delaying the phase of the input data by π / 2 is sampled at both edges of the clock generated by the VCO, and the sampling result at the rising edge remains as it is, while the sampling result at the falling edge is inverted, Second sampling means for outputting until the next sampling timing;
A third sampling means for sampling the output signal of the first sampling means at the rising edge of the output signal of the second sampling means, and outputting until the next sampling timing;
When the output of the second sampling means is at a low level, the output signal from the first sampling means is output as a comparison result, while when the output of the second sampling means is at a high level, the third signal is output. A selector that outputs an output signal from the sampling means as a comparison result;
With
4. The data reproduction circuit according to claim 3, wherein when the output of the second sampling means is at a low level, it is determined that the clock generated by the VCO and the input data are in a frequency synchronization state.   5. The data reproduction circuit according to claim 4, wherein the circuit gain in the second sampling means is higher than the circuit gain in the first sampling means. A reference clock generating means for generating a reference clock synchronized with the system frequency;
Comparing means for comparing the frequency and phase of the clock generated by the VCO and the reference clock;
A frequency error detecting means for determining whether or not a frequency error between the clock generated by the VCO and the reference clock is equal to or less than a certain amount in a data non-input period;
Further comprising
When the frequency error is determined by the frequency error detection means to exceed a certain amount, the PLL circuit uses the comparison result by the comparison means instead of the comparison result between the clock generated by the VCO and the input data. 6. The data reproduction circuit according to claim 1, wherein an input voltage to the VCO is adjusted.

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