JP2010218196A - Data transfer controller, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer control device, an electronic device and the like capable of switching a port connection target.
In a first mode, a data transfer control device transfers data from a first upstream / downstream port circuit 20-1 for upstream port operation via a hub logic circuit 40 and a routing logic circuit 50. Transfer to the second upstream port circuit 20-2 for downstream port operation, and in the second mode, data from the second upstream port circuit 20-2 for upstream port operation is transferred to the hub logic circuit 40. Transfer via the routing logic circuit 50 to the first upstream port circuit 20-1 for downstream port operation.
[Selection] Figure 2

Description

  The present invention relates to a data transfer control device, an electronic device, and the like.

  In recent years, USB serial interfaces standardized by USB 2.0 (Universal Serial Bus 2.0) and the like have become widespread. For example, it is widely used as an interface for connecting electronic devices such as a connection between a personal computer and peripheral devices, a connection between a printer and a digital camera, and a connection between a car navigation system and portable audio.

  In general, a hub is used to connect a USB host controller to a plurality of devices. That is, a host controller is connected to the upstream port circuit of the hub via the USB, and a plurality of devices are connected to the downstream port circuit of the hub via the USB.

  However, in such a configuration, there is a problem that the connection target of the upstream port circuit is fixed to the host controller, and the connection target of the downstream port circuit is fixed to the device. For example, when the electronic device has a built-in hub and a USB port connected to the downstream port circuit of the hub is provided, the external device connected to the USB port can only perform device operations.

  Patent Document 1 discloses a technique that includes two or more upstream port circuits and switches between using any one of the upstream port circuits for data transfer.

Special table 2008-53885 gazette

  According to some aspects of the present invention, it is possible to provide a data transfer control device, an electronic device, and the like that can switch a port connection target.

  One aspect of the present invention provides at least one downstream port circuit, a first upstream port circuit that performs upstream port operation in a first mode and performs downstream port operation in a second mode, A second upstream port circuit that performs downstream port operation in the first mode and performs upstream port operation in the second mode, a routing logic circuit, and a hub logic circuit that performs hub logic operation; In the first mode, data from the first upstream port circuit in upstream port operation is transferred to the second up / down port in downstream port operation via the hub logic circuit and the routing logic circuit. Stri The data from the second upstream port circuit of the upstream port operation in the second mode, the data of the downstream port operation through the hub logic circuit and the routing logic circuit. It relates to a data transfer control device for transferring to the first upstream / downstream port circuit.

  According to an aspect of the present invention, in the first mode, data from the first upstream port circuit of the upstream port operation is transmitted through the hub logic circuit and the routing logic circuit. 2 upstream and downstream port circuits. Also, in the second mode, data from the second upstream / downstream port circuit in the upstream port operation passes through the hub logic circuit and the routing logic circuit, and the first upstream / downstream port circuit in the downstream port operation. Forwarded to

  Thereby, in the first mode, a device performing a host operation can be connected to the first upstream port circuit, and a device performing a device operation can be connected to the second upstream port circuit. In the second mode, a device that performs device operation can be connected to the first upstream port circuit, and a device that performs host operation can be connected to the second upstream port circuit. Thus, according to one aspect of the present invention, it is possible to connect a device that performs a host operation to the first and second upstream port circuits, and connect a device that performs a device operation. It becomes possible.

  In one aspect of the present invention, in the first mode, data from the first upstream port circuit in upstream port operation is transferred to the at least one via the hub logic circuit and the routing logic circuit. And in the second mode, data from the second upstream port circuit for upstream port operation is transferred to the at least one via the hub logic circuit and the routing logic circuit. May be forwarded to one downstream port circuit.

  In this way, in the first mode, the first upstream port circuit in the upstream port operation transfers data to and from the second upstream port circuit in the downstream port operation. Data can be transferred to and from the stream port circuit. In the second mode, the second upstream port circuit for upstream port operation transfers data to and from the first upstream port circuit for downstream port operation, and Can transfer data between.

  In one embodiment of the present invention, a first bus provided between the first upstream / downstream port circuit and the hub logic circuit, the first upstream / downstream port circuit, and the routing logic circuit, A second bus provided between the second upstream port circuit and the hub logic circuit, a second upstream port circuit and the routing logic. And a fourth bus provided between the first bus, the hub logic circuit, and the routing in the first mode for transferring data from the first upstream port circuit in the first mode. A logic circuit, transferred to the second upstream / downstream port circuit via the fourth bus; In this mode, data from the second upstream port circuit is transferred to the first upstream port via the third bus, the hub logic circuit, the routing logic circuit, and the second bus. It may be transferred to a circuit.

  According to one aspect of the present invention, in the first mode, data is transferred via the first bus of the first and second buses, and the fourth bus of the third and fourth buses is transferred. Data is transferred via Thereby, data from the first upstream port circuit can be transferred to the second upstream port circuit via the hub logic circuit and the routing logic circuit. According to one embodiment of the present invention, in the second mode, data is transferred via the second bus of the first and second buses, and the third of the third and fourth buses. Data is transferred via the bus. Thereby, in the second mode, data from the second upstream port circuit can be transferred to the first upstream port circuit via the hub logic circuit and the routing logic circuit.

  In one aspect of the present invention, the hub logic circuit may include a hub controller, a hub repeater logic circuit, a transaction translator, a hub state machine, and a frame timer.

  Thus, in one embodiment of the present invention, the hub logic circuit may include these components to perform hub logic operation. However, in one embodiment of the present invention, the hub logic circuit may be configured without including some of these components.

  In one aspect of the present invention, a host / device controller capable of switching between host operation and device operation is connected to the first upstream / downstream port circuit, and the first upstream port circuit is connected in the first mode. The downstream port circuit performs an interface process between the host / device controller that performs a host operation and the hub logic circuit. In the second mode, the first upstream port circuit performs a device operation. Interface processing between the host / device controller to be performed and the routing logic circuit may be performed.

  In this way, a host / device controller capable of switching between host operation and device operation can be connected to the first upstream port circuit. Specifically, in the first mode, the host / device controller that performs the host operation can be connected to the first upstream port circuit. In the second mode, the host / device controller that performs device operation can be connected to the first upstream port circuit. For example, after switching between host operation and device operation of the host / device controller, the host / device can be connected to the first upstream port circuit, or connected to the first upstream / downstream port circuit. It is also possible to switch between the controller host operation and device operation.

  In the aspect of the invention, the first upstream port circuit may perform an interface process with the host / device controller via a USB (Universal Serial Bus).

  In this way, the host / device controller compliant with the USB standard can be connected to the first upstream / downstream port circuit by performing the interface process with the host / device controller via the USB.

  In one aspect of the present invention, the host / device controller is compliant with an OTG (On-The-Go) standard, and the first upstream port circuit is compliant with the OTG standard with the host / device controller. Compliant interface processing may be performed.

  According to this embodiment, a host / device controller compliant with the OTG standard can be connected to the first upstream / downstream port circuit. Data transfer between the host / device controller compliant with the OTG standard and a device connected to another port can be performed.

  In the aspect of the invention, the first upstream port circuit may perform an interface process with a link layer circuit of the host / device controller.

  In this way, the first upstream port circuit can perform interface processing with the link layer circuit of the host / device controller without going through the physical layer circuit (transceiver). This eliminates the need for the first upstream port circuit to include a transceiver, thereby reducing the circuit scale of the data transfer control device.

  In one aspect of the present invention, the first upstream port circuit is connected to the host / device controller via a bus of ULPI standard (UTMI + Low Pin Interface), and the link layer circuit of the host / device controller. The ULPI interface processing between the two may be performed.

  According to one aspect of the present invention, the first upstream / downstream port circuit performs the ULPI interface process with the link layer circuit of the host / device controller, so that the link layer circuit of the host / device controller Interface processing can be realized.

  In the aspect of the invention, the first upstream port circuit may include a first interface circuit that performs an interface process with the link layer circuit of the host / device controller, and the first mode. A second interface circuit that performs an interface process with the hub logic circuit and performs an interface process with the routing logic circuit in the second mode; an interface signal of the first interface circuit; A conversion circuit that performs conversion processing with an interface signal of the interface circuit.

  By doing so, it is possible to convert the interface signal for the interface processing with the link layer circuit of the host / device controller and the interface signal for the interface processing with the hub logic circuit or the routing logic circuit. Thereby, interface processing with the link layer circuit of the host / device controller can be realized. For example, the first interface circuit may perform ULPI interface processing, and the second interface circuit may perform UTMI (USB 2.0 Transceiver Macrocell Interface) interface processing. The conversion circuit may perform a conversion process between the ULPI interface signal and the UTMI interface signal.

  In the aspect of the present invention, in the first mode, a host controller is connected to the first upstream port circuit, and the first upstream port circuit includes the host controller and the Interface with a hub logic circuit, and in the second mode, a device is connected to the first upstream port circuit, and the first upstream port circuit is connected to the device and the routing Interface processing with a logic circuit may be performed.

  In this way, a host controller or device can be connected to the first upstream port circuit. Specifically, in the first mode, the host controller can be connected to the first upstream port circuit, and in the second mode, the device can be connected to the first upstream port circuit. For example, the device connected to the first upstream / downstream port circuit can be replaced from the host controller to the device, or the device can be replaced to the host controller.

  In the aspect of the invention, the first upstream port circuit may perform an interface process with the host controller or the device via a USB (Universal Serial Bus).

  In this way, the host controller or device compliant with the USB standard can be connected to the first upstream / downstream port circuit by performing interface processing with the host controller or device via the USB.

  Another aspect of the invention relates to an electronic apparatus including the data transfer control device described above.

1A is a first comparative example of the present embodiment, and FIG. 1B is a second comparative example of the present embodiment. 1 is a configuration example of a data transfer control device according to the present embodiment. The 1st connection structural example of this embodiment in a 1st mode. The 1st connection structural example of this embodiment in a 2nd mode. The 2nd connection structural example of this embodiment in a 1st mode. The 2nd connection structural example of this embodiment in a 2nd mode. The 1st detailed structural example of an upstream / downstream port circuit. The 2nd detailed structural example of an upstream / downstream port circuit. The 1st signal waveform example of a conversion process. The 2nd signal waveform example of a conversion process. The 3rd example of a signal waveform of conversion processing. 3 shows a detailed configuration example of a data transfer control device. Example of host / device controller configuration. FIGS. 14A and 14B are configuration examples of a transceiver of an upstream port circuit. Configuration example of an electronic device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Comparative Example First and second comparative examples of this embodiment will be described with reference to FIGS. 1 (A) and 1 (B). FIGS. 1A and 1B show connection configuration examples in which a host controller and a plurality of devices transfer data via a USB hub as first and second comparative examples.

  The first comparative example shown in FIG. 1A is a connection configuration example when the transceiver PHY_HCA (physical layer circuit) is built in the host controller HCA. Specifically, the hub HB includes an upstream port circuit PHY_HUB (transceiver), a hub logic circuit HL, a routing logic circuit RL, and downstream port circuits DP1 to DPn (n is a natural number). PHY_HCA is connected to PHY_HUB via USB. The PHY_HUB and the hub logic circuit HL are connected by a UTMI standard bus. The hub logic circuit HL controls data transfer between the host controller HCA and the devices DEV1 to DEVn. The routing logic circuit RL transfers data from the hub logic circuit HL to the downstream port circuits DP1 to DPn. Devices DEV1 to DEVn are connected to the downstream port circuits DP1 to DPn via USB. The upstream port circuit PHY_HUB performs interface processing with the host controller HCA, and the downstream port circuits DP1 to DPn perform interface processing with the devices DEV1 to DEVn.

  A second comparative example shown in FIG. 1B is a connection configuration example in the case where the host controller HCB and the transceiver PHY_HCB are configured in separate chips. In the second comparative example, the HCB and PHY_HCB configured by different chips are connected by a ULPI standard bus. At this time, the HCB accesses the ULPI standard bus via the link controller LK_HCB (link layer circuit) and the ULPI interface circuit. The transceiver PHY_HCB is connected to the transceiver PHY_HUB of the hub HB via USB. Similarly to the first comparative example, PHY_HUB and HUB_LC are connected by a UTMI standard bus, data from HL is transferred to DP1 to DPn by RL, and DEV1 to DEVn are transferred to DP1 to DPn via USB. Is connected. The upstream port circuit PHY_HUB performs interface processing with the transceiver PHY_HCB, and the downstream port circuits DP1 to DPn perform interface processing with the devices DEV1 to DEVn.

  As described above, in the first and second comparative examples, the upstream port circuit of the hub performs the upstream port operation with the host controller as a connection target, and the downstream port circuit has the downstream with the device as a connection target. Perform port operation. Therefore, there is a problem that the connection target of the upstream port circuit is fixed to the host controller, and the connection target of the downstream port circuit is fixed to the device. For example, in the first and second comparative examples, a device capable of switching between host operation and device operation is connected to a port, and data transfer cannot be performed by switching the host operation and device operation of the device. Alternatively, it is not possible to transfer data by replacing the host controller and device for the port.

  In the first comparative example, the hub and the host controller incorporate transceivers (PHY_HUB, PHY_HCB). Therefore, the first comparative example also has a problem that the circuit scale of the hub and the host controller increases due to the built-in transceiver. In the second comparative example, the host controller and the transceiver are configured as separate chips. Therefore, in the second comparative example, there is a problem that the mounting area on the wiring board is increased by the transceiver of another chip.

2. Data transfer control device 2.1. Configuration Example FIG. 2 shows a configuration example of a data transfer control device of the present embodiment that solves the above-described problems. FIG. 2 shows a configuration example of a hub as a configuration example of the data transfer control device. The hub 10 (data transfer control device in a broad sense) shown in FIG. 2 includes first and second upstream and downstream port circuits 20-1 and 20-2, a hub logic circuit 40, a routing logic circuit 50, The k-th downstream port circuits 60-1 to 60-k (k is a natural number) are included. The hub 10 connects a device that performs a host operation to one of the upstream / downstream port circuits 20-1 and 20-2, and connects a device that performs a device operation to the other. This circuit controls data transfer (data transmission / reception).

  Specifically, one of the upstream / downstream port circuits 20-1 and 20-2 performs an upstream port operation, and the other performs a downstream port operation. That is, a device (for example, a host controller) that performs a host operation is connected to the upstream port circuit that performs the upstream port operation. The upstream / downstream port circuit performs interface processing between the device that performs the host operation and the hub logic circuit 40. On the other hand, a device (for example, a device) that performs a device operation is connected to an upstream port circuit that performs a downstream port operation. The upstream / downstream port circuit performs interface processing between the device that performs the device operation and the routing logic circuit 50. For example, the upstream / downstream port circuits 20-1 and 20-2 may perform interface processing of a serial interface in conformity with a USB (Universal Serial Bus) standard (for example, USB 2.0, USB 1.1) or the like. Parallel interface processing conforming to the (UTMI + Low Pin Interface) standard or the like may be performed.

  The hub logic circuit 40 and the routing logic circuit 50 control data transfer between ports. Specifically, the hub logic circuit 40 and the routing logic circuit 50 control data transfer between an upstream port circuit that performs an upstream port operation and an upstream port circuit that performs a downstream port operation. The hub logic circuit 40 and the routing logic circuit 50 control data transfer between the upstream port circuit that performs the upstream port operation and the downstream port circuits 60-1 to 60-k.

  More specifically, the hub logic circuit 40 performs hub logic operations other than the processing performed by the routing logic circuit 50. That is, the hub logic circuit 40 controls the interface processing of the upstream / downstream port circuit that performs the upstream port operation, and transfers data to / from the upstream / downstream port circuit. The hub logic circuit 40 controls the interface processing of the upstream port circuit that performs the downstream port operation via the routing logic circuit 50, and transfers data to and from the upstream port circuit. Further, the hub logic circuit 40 controls interface processing of the downstream port circuits 60-1 to 60-k via the routing logic circuit 50, and data is transmitted to and from the downstream port circuits 60-1 to 60-k. Forward. For example, the hub logic circuit 40 controls a data transfer between ports by performing a hub logic operation conforming to the USB standard. Specifically, the hub logic circuit 40 detects a connection / disconnection with a device that performs a host operation or a device that performs a device operation, or performs a connection process or a disconnection process with these devices. The interface processing of each port is controlled by controlling the timing of data transfer to the bus and detecting the bus error (fault). Alternatively, the hub logic circuit 40 controls the data transfer between ports by performing a translation process (conversion process) on a transaction from a port or a transfer process on a transaction from a port as it is.

  The routing logic circuit 50 performs data routing processing. That is, the routing logic circuit 50 performs interface processing between the hub logic circuit 40 and the upstream port circuit that performs the downstream port operation. The routing logic circuit 50 performs interface processing between the hub logic circuit 40 and the downstream port circuits 60-1 to 60-k. Specifically, the routing logic circuit 50 distributes the data from the hub logic circuit 40 to the corresponding downstream port circuit (or upstream port circuit) and performs interface processing. For example, the routing logic circuit 50 distributes data by interface processing compliant with the USB standard. In other words, the routing logic circuit 50 distributes data by transferring the transaction processed by the hub logic circuit 40 to an appropriate downstream port circuit (or an upstream port circuit that performs a downstream port operation). .

  Devices (for example, devices) that perform device operations are connected to the downstream port circuits 60-1 to 60-k. For example, the downstream port circuits 60-1 to 60-k are connected to a device or a host / device controller that performs the device operation as a device that performs the device operation. The downstream port circuits 60-1 to 60-k perform interface processing between the connected device and the routing logic circuit 50. For example, the downstream port circuits 60-1 to 60-k perform interface processing with the routing logic circuit 50 by performing interface processing of a serial interface compliant with the USB standard. In the present invention, the data transfer control device may include one downstream port circuit 60-1 (k = 1) as at least one downstream port circuit, and a plurality of downstream port circuits 60-1 to 60-60. -K (k ≧ 2) may be included. For example, when a plurality of downstream port circuits are included as at least one downstream port circuit, data from the routing logic circuit 50 is transferred to all of the plurality of downstream port circuits. However, in the present invention, the data from the routing logic circuit 50 may not be transferred to some of the plurality of downstream port circuits (for example, the downstream port circuit to which no device is connected).

  Note that the data transfer control device of the present invention is not limited to the configuration shown in FIG. 2, and some of the components (eg, downstream port circuit, routing logic circuit) may be omitted, or other components may be added. Various modifications such as this are possible.

2.2. First Connection Configuration Example FIGS. 3 and 4 show a first connection configuration example of the present embodiment. In the following description, a host / device controller HDCA capable of switching between host operation and device operation is connected to the upstream port circuit 20-1, and the host controller HCA or device is connected to the upstream port circuit 20-2. A case will be described as an example where the DVA is connected and the devices DV1 to DVk are connected to the downstream port circuits 60-1 to 60-k. However, in the present invention, a host controller or a device may be connected to the upstream port circuit 20-1, and a host / device controller may be connected to the upstream port circuit 20-2. A host / device controller that performs device operations may be connected to the downstream port circuits 60-1 to 60-k.

  In the following description, the host / device controller HDCA, the host controller HCA, the device DVA, and the devices DV1 to DVk conform to the USB standard, and the upstream port circuits 20-1 and 20-2 and the downstream port circuit 60-1 A case where ˜60-k performs interface processing conforming to the USB standard will be described as an example. However, in the present invention, HDCA, HCA, DVA, DV1 to DVk comply with other serial interface standards, and upstream port circuits 20-1 and 20-2 and downstream port circuits 60-1 to 60-k. However, interface processing conforming to the serial interface standard may be performed.

  FIG. 3 shows a first connection configuration example of the present embodiment in the first mode. In the first connection configuration example, in the first mode, a host / device controller HDCA that performs a host operation is connected to the upstream port circuit 20-1 via a USB (serial bus in a broad sense). The A device DVA is connected to the upstream / downstream port circuit 20-2 via USB. In the first mode, the upstream / downstream port circuit 20-1 performs an upstream port operation, and the upstream / downstream port circuit 20-2 performs a downstream port operation.

  Specifically, the upstream / downstream port circuit 20-1 and the hub logic circuit 40 are connected via the first bus BUS1, and the upstream / downstream port circuit 20-1 and the routing logic circuit 50 are connected to the second bus. Connected via BUS2. The upstream / downstream port circuit 20-2 and the hub logic circuit 40 are connected via a third bus BUS3, and the upstream / downstream port circuit 20-2 and the routing logic circuit 50 are connected via a fourth bus BUS4. Connected. These buses BUS1 to BUS4 are configured by, for example, parallel buses conforming to the UTMI (USB 2.0 Transceiver Macrocell Interface) standard. In the first mode, data is transferred between the upstream / downstream port circuit 20-1 and the hub logic circuit 40 via the BUS1 and routed with the upstream / downstream port circuit 20-2 via the BUS4. Data is transferred to and from the logic circuit 50. For example, data from the host / device controller HDCA is transferred to the upstream / downstream port circuit 20-1, transferred from the upstream / downstream port circuit 20-1 to the hub logic circuit 40 via the BUS 1, and from the hub logic circuit 40. It is transferred to the routing logic circuit 50. The data is transferred from the routing logic circuit 50 to the upstream / downstream port circuit 20-2 via the BUS4, and transferred from the upstream / downstream port circuit 20-2 to the device DVA.

  Note that the hub (data transfer control device) of the present embodiment can also transfer data between the HDCA and the devices DV1 to DVk in the first mode. For example, data from the HDCA is transferred to the routing logic circuit 50 via the upstream / downstream port circuit 20-1, the BUS1, and the hub logic circuit 40 in the same manner as described above. Then, the data may be transferred from the routing logic circuit 50 to the downstream port circuits 60-1 to 60-k, and may be transferred from the downstream port circuits 60-1 to 60-k to DV1 to DVk.

  FIG. 4 shows a first connection configuration example of the present embodiment in the second mode. As shown in FIG. 4, in the second mode, the upstream / downstream port circuit 20-1 is connected to a host / device controller HDCA that performs device operation via a USB bus. A host controller HCA is connected to the upstream / downstream port circuit 20-2 via a USB bus. The upstream / downstream port circuit 20-1 performs a downstream port operation, and the upstream / downstream port circuit 20-2 performs an upstream port operation.

  Specifically, in the second mode, data is transferred between the upstream / downstream port circuit 20-1 and the routing logic circuit 50 through the BUS2, and the upstream / downstream port circuit 20- through the BUS3. 2 and the hub logic circuit 40 transfer data. For example, data from the host controller HCA is transferred to the upstream / downstream port circuit 20-2, transferred from the upstream / downstream port circuit 20-2 to the hub logic circuit 40 via the BUS3, and the routing logic from the hub logic circuit 40. It is transferred to the circuit 50. Then, the data is transferred from the routing logic circuit 50 to the upstream / downstream port circuit 20-1 via the BUS2, and is transferred from the upstream / downstream port circuit 20-1 to the host / device controller HDCA.

  Note that the hub of the present embodiment can also perform data transfer between the HCA and the devices DV1 to DVk in the second mode. For example, data from the HCA is transferred to the routing logic circuit 50 through the upstream / downstream port circuit 20-2, BUS3, and the hub logic circuit 40 in the same manner as described above. Then, the data may be transferred from the routing logic circuit 50 to the downstream port circuits 60-1 to 60-k, and may be transferred from the downstream port circuits 60-1 to 60-k to DV1 to DVk.

  Here, in the first and second comparative examples described above, there is a problem that the connection target of the port is fixed. That is, the connection target of the upstream port circuit is fixed to the host controller, and the connection target of the downstream port circuit is fixed to the device.

  In this regard, according to the present embodiment, at least one downstream port circuit 60-1 to 60-k, first and second upstream port circuits 20-1, 20-2, and routing logic circuit 50 are provided. And a hub logic circuit 40 that performs a hub logic operation. Then, in the first mode, the data from the upstream / downstream port circuit 20-1 is transferred to the second upstream / downstream port circuit 20-2 via the hub logic circuit 40 and the routing logic circuit 50. Specifically, in the first mode, data from the upstream / downstream port circuit 20-1 in the upstream port operation is transferred to the hub logic circuit 40, transferred from the hub logic circuit 40 to the routing logic circuit 50, It is transferred from the routing logic circuit 50 to the upstream / downstream port circuit 20-2 for downstream port operation. Thereby, in the first mode, a device that performs a host operation can be connected to the upstream port circuit 20-1, and a device that performs a device operation can be connected to the upstream port circuit 20-2.

  Further, according to the present embodiment, in the second mode, data from the upstream / downstream port circuit 20-2 is transferred to the upstream / downstream port circuit 20-1 via the hub logic circuit 40 and the routing logic circuit 50. To do. Specifically, data from the upstream port circuit 20-2 in the upstream port operation is transferred to the hub logic circuit 40, transferred from the hub logic circuit 40 to the routing logic circuit 50, and down from the routing logic circuit 50. The data is transferred to the upstream / downstream port circuit 20-1 in the stream port operation. Thereby, in the second mode, a device that performs a device operation can be connected to the upstream port circuit 20-1, and a device that performs a host operation can be connected to the upstream port circuit 20-2. In this way, the connection target of the upstream / downstream port circuit can be changed in the first mode and the second mode.

  Here, as shown in FIG. 12 described later, the hub may include a switching control circuit 460, and the switching control circuit 460 outputs a switching control signal HostEn for switching between the first mode and the second mode. May be. In this way, the switching control circuit 460 outputs HostEn, so that the first mode and the second mode can be switched.

  In the present embodiment, in the first mode, data from the upstream port circuit 20-1 is sent to the downstream port circuits 60-1 to 60-k via the hub logic circuit 40 and the routing logic circuit 50. In the second mode, data from the upstream port circuit 20-2 is transferred to the downstream port circuits 60-1 to 60-k via the hub logic circuit 40 and the routing logic circuit 50. May be.

  In this manner, in the first mode, data is transferred between the upstream / downstream port circuit 20-1 and the upstream / downstream port circuit 20-2, and the upstream / downstream port circuit 20-1 and the downstream port are transferred. Data can be transferred to and from the circuits 60-1 to 60-k. In the second mode, data is transferred between the upstream / downstream port circuit 20-2 and the upstream / downstream port circuit 20-1, and the upstream / downstream port circuit 20-2 and the downstream port circuit 60-1 are also transferred. Data can be transferred between ˜60-k.

  In the present embodiment, the first to fourth buses BUS1 to BUS4 are included, and in the first mode, data from the upstream / downstream port circuit 20-1 is transferred to BUS1, the hub logic circuit 40, and the routing logic circuit 50. , And transfer the data from the upstream / downstream port circuit 20-2 to the upstream / downstream port circuit 20-2 via the BUS4, in the second mode, through the BUS3, the hub logic circuit 40, the routing logic circuit 50, and the BUS2. Via the upstream port circuit 20-1.

  Thus, in the first mode, the BUS1 is selected from BUS1 and BUS2 connected to the upstream / downstream port circuit 20-1, so that the data from the upstream / downstream port circuit 20-1 is transferred to the hub logic circuit. 40 can be transferred. Further, by selecting BUS4 from among BUS3 and BUS4 connected to the upstream / downstream port circuit 20-2, data from the routing logic circuit 50 can be transferred to the upstream / downstream port circuit 20-2. On the other hand, in the second mode, data from the upstream / downstream port circuit 20-2 can be transferred to the hub logic circuit 40 by selecting BUS3 from among BUS3 and BUS4. Further, when BUS2 is selected from BUS1 and BUS2, data from the routing logic circuit 50 can be transferred to the upstream / downstream port circuit 20-1.

  In the present embodiment, the upstream / downstream port circuit 20-1 may be connected to a host / device controller capable of switching between host operation and device operation. In the first mode, the upstream / downstream port circuit 20-1 performs an interface process between the host / device controller that performs the host operation and the hub logic circuit 40. In the second mode, the upstream / downstream port circuit 20-1 The circuit 20-1 may perform interface processing between the host / device controller that performs device operation and the routing logic circuit 50.

  According to this embodiment, a host / device controller can be connected to the upstream / downstream port circuit 20-1, and interface processing with the host / device controller can be performed. Then, the host operation and device operation of the host / device controller can be switched between the first mode and the second mode. In this way, switching of the connection target of the upstream / downstream port circuit 20-1 can be realized. Specifically, the host operation and the device operation of the host / device controller can be switched with the host / device controller connected to the upstream / downstream port circuit 20-1.

  In the present invention, the upstream / downstream port circuit 20-2 may be connected to a host / device controller capable of switching between host operation and device operation. In the first mode, the upstream / downstream port circuit 20-2 performs interface processing between the host / device controller that performs the device operation and the routing logic circuit 50. In the second mode, the upstream / downstream port circuit 20-2 The circuit 20-2 may perform an interface process between the host / device controller performing the host operation and the hub logic circuit 40.

  In this way, the host / device controller can be connected to the upstream port circuit 20-2 to switch the connection target of the upstream port circuit 20-2.

  In this embodiment, in the first mode, a host controller is connected to the upstream port circuit 20-1, and the upstream port circuit 20-1 is an interface between the host controller and the hub logic circuit 40. Processing may be performed. In the second mode, a device is connected to the upstream port circuit 20-1, and the upstream port circuit 20-1 may perform an interface process between the device and the routing logic circuit 50.

  According to the present embodiment, in the first mode, the upstream port circuit 20-1 performs an interface process between the host controller and the hub logic circuit 40. On the other hand, in the second mode, the upstream port circuit 20-1 performs interface processing between the device and the routing logic circuit 50. Thus, the host controller can be connected to the upstream port circuit 20-1 in the first mode, and the device can be connected to the upstream port circuit 20-1 in the second mode. In this way, switching of the connection target of the upstream / downstream port circuit 20-1 can be realized. Specifically, the host controller and the device can be replaced for the upstream / downstream port circuit 20-1.

  In the present invention, in the first mode, a device is connected to the upstream port circuit 20-2, and the upstream port circuit 20-2 performs interface processing between the device and the routing logic circuit 50. May be. In the second mode, a host controller is connected to the upstream port circuit 20-2, and the upstream port circuit 20-2 may perform interface processing between the host controller and the hub logic circuit 40. Good.

  In this way, the device can be connected to the upstream port circuit 20-2 in the first mode, and the host controller can be connected to the upstream port circuit 20-2 in the second mode. In this way, switching of the connection target of the upstream / downstream port circuit 20-2 can be realized.

  In the present embodiment, the upstream / downstream port circuit 20-1 may perform an interface process with the host / device controller via the USB.

  Alternatively, in the present embodiment, the upstream port circuit 20-1 may perform an interface process with a host controller or a device via a USB.

  In this way, a host / device controller compliant with the USB standard, a host controller compliant with the USB standard, or a device compliant with the USB standard can be connected to the upstream / downstream port circuit 20-1. Then, interface processing of a serial interface compliant with the USB standard can be performed between these devices.

  In this embodiment, as will be described later with reference to FIG. 13 and the like, the host / device controller may conform to the OTG (On-The-Go) standard. Then, the upstream / downstream port circuit 20-1 may perform interface processing in accordance with the OTG standard with the host / device controller.

  According to the present embodiment, a host / device controller compliant with the OTG standard can be connected to the upstream / downstream port circuit 20-1. Data transfer between the host / device controller compliant with the OTG standard and other connected devices can be performed.

  In the present invention, the upstream / downstream port circuit 20-2 may perform an interface process with the host / device controller via the USB. Alternatively, the upstream / downstream port circuit 20-2 may perform an interface process with the host controller or the device via the USB. Further, in the present invention, the upstream port circuit 20-2 may perform interface processing conforming to the OTG standard with a host / device controller conforming to the OTG standard.

2.3. Second Connection Configuration Example FIGS. 5 and 6 show a second connection configuration example of the present embodiment. In the following, a host / device controller HDCB capable of switching between host operation and device operation is connected to the upstream port circuit 20-1, and the host controller HCB or device is connected to the upstream port circuit 20-2. A case where DVB is connected will be described as an example. In the following, a case where the host / device controller HDCB conforms to the ULPI standard and the upstream port circuit 20-1 performs interface processing conforming to the ULPI standard will be described as an example. However, in the present invention, HDCB may conform to another parallel interface standard (for example, UTMI), and the upstream / downstream port circuit 20-1 may perform interface processing conforming to the parallel interface standard.

  FIG. 5 shows a second connection configuration example of the present embodiment in the first mode. As shown in FIG. 5, in the first mode, the upstream / downstream port circuit 20-1 is connected to the host / device controller HDCB that performs the host operation via the ULPI bus (parallel bus in a broad sense). The The device DVB is connected to the upstream / downstream port circuit 20-2 via a USB bus. In the first mode, the upstream / downstream port circuit 20-1 performs an upstream port operation, and the upstream / downstream port circuit 20-2 performs a downstream port operation.

  Specifically, the host / device controller HDCB includes a link controller LK_HB (link layer circuit) and an ULPI interface circuit IF_HB. The link controller LK_HB is a circuit that performs a link process with the hub 10, and the interface circuit IF_HB is a circuit that performs an ULPI interface process. Then, the upstream / downstream port circuit 20-1 performs interface processing with the link controller LK_HB via the interface circuit IF_HB. More specifically, data is transferred between the upstream / downstream port circuit 20-1 and LK_HB by the upstream port circuit 20-1 performing interface processing with LK_HB. For example, data from the HDCB is transferred to the upstream / downstream port circuit 20-1 via the LK_HB, IF_HB, and ULPI buses. Then, as described with reference to FIG. 3 above, data from the upstream / downstream port circuit 20-1 is transmitted to the BUS1, the hub logic circuit 40, the routing logic circuit 50, BUS4, and the upstream / downstream port circuit 20-2. To the device DVB. Alternatively, data from the upstream / downstream port circuit 20-1 is transferred to the devices DV1 to DVk via the BUS1, the hub logic circuit 40, the routing logic circuit 50, and the downstream port circuits 60-1 to 60-k. .

  FIG. 6 shows a second connection configuration example of the present embodiment in the second mode. As shown in FIG. 6, in the second mode, a host / device controller HDCB that performs device operation is connected to the upstream / downstream port circuit 20-1 via the ULPI bus. The host controller HCB is connected to the upstream / downstream port circuit 20-2 via a USB bus. In the second mode, the upstream / downstream port circuit 20-1 performs a downstream port operation, and the upstream / downstream port circuit 20-2 performs an upstream port operation.

  For example, the data from the host controller HCB is up / down via the upstream / downstream port circuit 20-2, BUS3, the hub logic circuit 40, the routing logic circuit 50, and BUS2, as described in FIG. It is transferred to the stream port circuit 20-1. Alternatively, data from the devices DV1 to DVk is transferred to the upstream / downstream port circuit 20-1 via the downstream port circuits 60-1 to 60-k, the routing logic circuit 50, and the BUS2. Data from the upstream / downstream port circuit 20-1 is transferred to the host / device controller HDCB via the ULPI bus, the interface circuit IF_HB, and the link controller LK_HB.

  Here, in the first and second comparative examples described above, the upstream port circuit of the hub incorporates the transceiver PHY_HCB (physical layer circuit). Therefore, in the first and second comparative examples, there is a problem that the circuit scale of the hub increases due to the built-in transceiver. In the second comparative example, the host controller and the transceiver are configured as separate chips. Therefore, in the second comparative example, there is a problem that the mounting area on the wiring board is increased by the transceiver of another chip.

  In this regard, according to the present embodiment, the upstream / downstream port circuit 20-1 may perform an interface process with the link controller LK_HB of the host / device controller HDCB.

  According to the present embodiment, by performing an interface process with the link controller LK_HB, data can be transferred between the hub 10 and the host / device controller HDCB without using a transceiver. Thereby, the transceiver of the upstream port circuit 20-1 (for example, PHY_HUB in FIG. 1A) can be omitted, and the circuit scale of the hub 10 can be reduced. Further, the circuit scale of the host / device controller can be reduced by omitting the transceiver of the host / device controller (for example, PHY_HCA in FIG. 1A). Alternatively, the transceiver on a separate chip from the host / device controller (for example, PHY_HCB in FIG. 1B) can be omitted to reduce the mounting area on the wiring board.

  As described above with reference to FIG. 5 and the like, in the present embodiment, the upstream / downstream port circuit 20-1 is connected to the host / device controller HDCB via a ULPI standard bus, and the link controller LK_HB of the host / device controller HDCB is connected to the host / device controller HDCB. The ULPI interface processing between the two may be performed.

  In this way, the host / device controller HDCB having the ULPI interface can be connected to the upstream / downstream port circuit 20-1. An ULPI interface between the upstream / downstream port circuit 20-1 and the link controller LK_HB can be performed. Thereby, the transceiver of the upstream / downstream port circuit 20-1 and the transceiver of the host / device controller HDCB can be omitted.

  As will be described later with reference to FIG. 8 and the like, in this embodiment, the upstream / downstream port circuit 20-1 may include first and second interface circuits 150 and 160 and a conversion circuit 100. Then, the first interface circuit 150 performs interface processing with the link layer circuit LK_HB of the host / device controller HDCB, and the second interface circuit 160 performs interface processing with the hub logic circuit 40 in the first mode. In the second mode, interface processing with the routing logic circuit 50 is performed, and the conversion circuit 100 performs conversion processing between the interface signal of the first interface circuit 150 and the interface signal of the second interface circuit 160. May be.

  In this way, the upstream / downstream port circuit 20-1 can perform an interface process with the link controller LK_HB of the host / device controller HDCB. Specifically, in the present embodiment, the conversion circuit 100 performs a conversion process between the interface signal of the first interface circuit 150 and the interface signal of the second interface circuit 160. Thereby, the interface process between the hub logic circuit 40 and the link controller LK_HB or the interface process between the routing logic circuit 50 and the link controller LK_HB can be performed without going through the transceiver.

  For example, in the present embodiment, a host / device controller may be connected to the first interface circuit 150 via a ULPI bus, and the first interface circuit 150 is connected to the link layer circuit of the host / device controller. The ULPI interface processing may be performed. In this way, ULPI interface processing with the link controller of the host / device controller can be realized.

  In the present embodiment, the second interface circuit 160 may perform a UTMI interface process with the hub logic circuit 40 or the routing logic circuit 50 via a UTMI (USB 2.0 Transceiver Macrocell Interface) bus. . In this way, data can be transferred between the upstream / downstream port circuit 20-1 and the hub logic circuit 40 or the routing logic circuit 50 via the UTMI bus.

  In this embodiment, the conversion circuit 100 may perform a conversion process between the ULPI interface signal of the first interface circuit 150 and the UTMI interface signal of the second interface circuit 160. In this way, interface processing with the link controller of the host / device controller can be realized by performing conversion processing between the ULPI interface signal and the UTMI interface signal.

  In the present invention, the upstream / downstream port circuit 20-2 may perform interface processing with the link controller of the host / device controller. For example, the upstream / downstream port circuit 20-2 may be connected to the host / device controller via a bus of the ULPI standard, and may perform ULPI interface processing between the link controller of the host / device controller. In the present invention, the upstream / downstream port circuit 20-2 may include first and second interface circuits and a conversion circuit.

3. Upstream / downstream port circuit 3.1. First Detailed Configuration Example FIG. 7 shows a first detailed configuration example of the upstream / downstream port circuit. FIG. 7 shows an upstream port circuit 300 as a first detailed configuration example. The upstream / downstream port circuit 300 includes a transceiver 310 (physical layer circuit, analog front-end circuit), a serial / parallel conversion circuit 320, a parallel / serial conversion circuit 330, and a selector 340. The upstream / downstream port circuit 300 is connected to, for example, a host / device controller (or host controller or device) via USB, and performs interface processing based on the USB standard with the host / device controller.

  The transceiver 310 inputs and outputs interface signals. Specifically, the transceiver 310 receives a serial signal from the parallel-serial conversion circuit 330 and outputs a USB differential signal based on the serial signal. On the other hand, the transceiver 310 receives a USB differential signal, generates a serial signal, and outputs the serial signal to the serial-parallel conversion circuit 320. The transceiver 310 inputs and outputs a USB power supply voltage. Alternatively, an interface signal (for example, an UTMI interface signal) from the hub logic circuit 40 or the routing logic circuit 50 is input to the transceiver 310 via the selector 340. Based on the interface signal, the mode of the transceiver 310 is set (for example, HS mode, LS mode). The transceiver 310 generates an interface signal (for example, HS_Disconect, squelch signal) based on the state of the bus, and outputs the interface signal to the hub logic circuit 40 or the routing logic circuit 50 via the selector 340. For example, the transceiver 310 can be configured by a transceiver shown in FIGS. 14A and 14B described later.

  The serial / parallel conversion circuit 320 receives the serial signal from the transceiver 310, converts the serial signal into a parallel signal (for example, an UTMI interface signal), and outputs the parallel signal after the conversion processing to the selector 340. Specifically, the serial / parallel conversion circuit 320 outputs a parallel signal to the hub logic circuit 40 or the routing logic circuit 50 via the selector 340.

  The parallel-serial conversion circuit 330 receives a parallel signal (for example, an UTMI interface signal) from the selector 340, converts the parallel signal into a serial signal, and outputs the serial signal after the conversion process to the transceiver 310. Specifically, the parallel signal from the hub logic circuit 40 or the routing logic circuit 50 is input to the parallel-serial conversion circuit 330 via the selector 340. Note that the serial-parallel conversion circuit 320 and the parallel-serial conversion circuit 330 can be configured by, for example, a shift register using a flip-flop circuit.

  The selector 340 inputs and outputs interface signals to and from the hub logic circuit 40 or the routing logic circuit 50. Specifically, the selector 340 outputs the parallel signal from the serial / parallel conversion circuit 320 to the hub logic circuit 40 or the routing logic circuit 50. The selector 340 outputs the parallel signal from the hub logic circuit 40 or the routing logic circuit 50 to the parallel-serial conversion circuit 330. More specifically, the selector 340 selects a first parallel bus with the hub logic circuit 40 or a second parallel bus with the routing logic circuit 50 (for example, a UTMI bus). The selector 340 inputs / outputs interface signals via the selected parallel bus. For example, the selector 340 may be configured by a switching circuit using a transfer gate, and the first parallel bus or the second parallel bus may be selected by the switching circuit. Alternatively, the selector 340 may be configured by a selection circuit having first and second input / output buffers that input and output interface signals to and from the first and second parallel buses. Then, the first parallel bus may be selected by enabling the first input / output buffer, and the second parallel bus is selected by enabling the second input / output buffer. May be.

  Here, the upstream / downstream port circuit 300 receives the switching signal HostEn (for example, HostEn from the switching control circuit 460 shown in FIG. 12 described later). HostEn is a signal for switching between the first mode and the second mode of the hub. The upstream port circuit 300 switches between upstream port operation and downstream port operation based on HostEn. Specifically, HostEn is input to the transceiver 310 and the selector 340, and the transceiver 310 and the selector 340 switch operations based on the HostEn.

  For example, it is assumed that the upstream / downstream port circuit 300 is applied to the upstream / downstream port circuit 20-1 shown in FIGS. Then, in the first mode, HostEn is activated (or inactive, first logic level in a broad sense), and the upstream port circuit 300 performs an upstream port operation. Specifically, the transceiver 310 performs an upstream port operation (for example, an upstream port operation shown in FIG. 14A described later). The selector 340 selects the first parallel bus with the hub logic circuit 40 and inputs / outputs interface signals with the hub logic circuit 40 via the first parallel bus. On the other hand, in the second mode, HostEn is deactivated (or active, the second logic level in a broad sense), and the upstream port circuit 300 performs a downstream port operation. Specifically, the transceiver 310 performs a downstream port operation (for example, a downstream port operation illustrated in FIG. 14B described later). The selector 340 selects the second parallel bus with the routing logic circuit 50, and inputs / outputs interface signals with the routing logic circuit 50 via the second parallel bus.

  In the above description, the case where the upstream port circuit 300 performs the upstream port operation in the first mode and performs the downstream port operation in the second mode has been described as an example. However, in the present invention, the upstream port circuit 300 may perform a downstream port operation in the first mode and perform an upstream port operation in the second mode. That is, in the first mode, the transceiver 310 may perform a downstream port operation, and the selector 340 may input / output an interface signal with the routing logic circuit 50. On the other hand, in the second mode, the transceiver 310 may perform an upstream port operation, and the selector 340 may input / output an interface signal with the hub logic circuit 40.

3.2. Second Detailed Configuration Example FIG. 8 shows a second detailed configuration example of the upstream / downstream port circuit. FIG. 8 shows an upstream / downstream port circuit 350 as a second detailed configuration example. The upstream / downstream port circuit 350 includes an ULPI interface circuit 150 (first interface circuit), a conversion circuit 100, and a UTMI interface circuit 160 (second interface circuit). For example, a host / device controller (or host controller or device) is connected to the upstream / downstream port circuit 350 via an ULPI bus. The upstream port circuit 350 performs an interface process with the host / device controller without using the USB by performing a conversion process between the ULPI interface signal and the UTMI interface signal.

  The interface circuit 150 inputs and outputs ULPI interface signals data [7: 0], dir, stp, and nxt (first interface signal in a broad sense). Specifically, the interface circuit 150 receives the signals data [7: 0] and stp from the host / device controller and outputs the signals to the conversion circuit 100. The interface circuit 150 receives the signal data [7: 0] from the conversion circuit 100 and outputs the signal to the host / device controller. The interface circuit 150 receives the control signal from the conversion circuit 100 and outputs the signals dir and nxt to the host / device controller based on the control signal. For example, the interface circuit 150 outputs signals data [7: 0], nxt, and dir to drive a ULPI bus, and a receiver that receives signals data [7: 0] and stp from the ULPI bus. Can be configured.

  The interface circuit 160 inputs and outputs a UTMI interface signal (second interface signal in a broad sense). Specifically, the interface circuit 160 communicates with the hub logic circuit (for example, the hub logic circuit 40 in FIG. 2 described above) with the interface signals DataIn1 [7: 0], DataOut1 [7: 0], TXValid1 of the UTMI. , TXReady1 and the like (first parallel bus signal in a broad sense) are input / output. Further, the interface circuit 160 is connected to a routing logic circuit (for example, the routing logic circuit 50 of FIG. 2 described above), interface signals DataIn2 [7: 0], DataOut2 [7: 0], TXValid2, TXReady2, etc. (In a broad sense, the second parallel bus signal) is input / output. More specifically, the interface circuit 160 receives signals DataIn1 [7: 0], TXValid1 and the like from the hub logic circuit and outputs the signals to the conversion circuit 100. Further, the interface circuit 160 receives the signal DataOut1 [7: 0] from the conversion circuit 100 and outputs the signal to the hub logic circuit. The interface circuit 160 receives the control signal from the conversion circuit 100 and outputs the signal TXReady1 and the like to the hub logic circuit based on the control signal. Similarly, the interface circuit 160 receives the signals DataIn2 [7: 0], TXValid2 and the like from the routing logic circuit and outputs the signals to the conversion circuit 100. Further, the interface circuit 160 receives the signal DataOut2 [7: 0] from the conversion circuit 100 and outputs the signal to the routing logic circuit. The interface circuit 160 receives the control signal from the conversion circuit 100 and outputs the signal TXReady2 and the like to the routing logic circuit based on the control signal.

  Here, the upstream / downstream port circuit 350 receives a switching signal HostEn (for example, HostEn from the switching control circuit 460 shown in FIG. 12 described later). Specifically, HostEn is input to the interface circuit 160. The interface circuit 160 inputs / outputs interface signals with the hub logic circuit or the routing logic circuit based on HostEn. More specifically, the interface circuit 160 includes a selector 162. Based on HostEn, the selector 162 selects a first UTMI bus (first parallel bus in a broad sense) with a hub logic circuit or a second UTMI bus (in a broad sense) with a routing logic circuit. , Second parallel bus).

  For example, it is assumed that the upstream / downstream port circuit 350 is applied to the upstream / downstream port circuit 20-1 shown in FIGS. Then, in the first mode, the upstream port circuit 350 performs an upstream port operation. Specifically, in the first mode, the selector 162 selects the first UTMI bus. The selector 162 inputs / outputs interface signals to / from the hub logic circuit via the first UTMI bus. On the other hand, in the second mode, the upstream / downstream port circuit 350 performs a downstream port operation. Specifically, the selector 162 selects the second UTMI bus. The selector 162 inputs / outputs an interface signal to / from the routing logic circuit via the second UTMI bus. Note that the selector 162 can be configured by, for example, a switching circuit using a transfer gate or a selection circuit using an input / output buffer, similarly to the selector 340 shown in FIG.

  Here, in the above description, the case where the upstream port circuit 350 performs the upstream port operation in the first mode and performs the downstream port operation in the second mode has been described as an example. However, in the present invention, the upstream port circuit 350 may perform a downstream port operation in the first mode and perform an upstream port operation in the second mode. That is, in the first mode, the selector 162 may input / output an interface signal to / from the routing logic circuit 50, and in the second mode, the selector 162 inputs / outputs an interface signal to / from the hub logic circuit 40. May be.

  The conversion circuit 100 performs conversion processing between the ULPI interface signal of the interface circuit 150 and the UTMI interface signal of the interface circuit 160. Specifically, the conversion circuit 100 performs an emulation process on data transfer via a USB (in the broad sense, a serial bus). That is, the conversion circuit 100 performs an emulation process on an interface process of a transceiver (for example, PHY_HCB, PHY_HUB shown in FIG. 1B described above) that performs data transfer via USB. More specifically, the conversion circuit 100 includes a reception circuit 110, a transmission circuit 120, a control circuit 130 (bus state controller), and a register 140.

  The reception circuit 110 receives ULPI reception data data [7: 0] (in a broad sense, reception data of the first interface signal) from the host / device controller via the interface circuit 150. The reception circuit 110 converts data [7: 0] into reception data DataOut1 [7: 0] or DataOut2 [7: 0] (in a broad sense, reception data of the second interface signal). Then, the receiving circuit 110 outputs DataOut1 [7: 0] to the hub logic circuit via the interface circuit 160. Alternatively, the reception circuit 110 outputs DataOut2 [7: 0] to the routing logic circuit via the interface circuit 160. Specifically, the reception circuit 110 includes a reception buffer 112 that buffers received data. Then, the receiving circuit 110 captures received data into the receiving buffer 112 based on a control signal from the control circuit 130, transfers received data from the receiving buffer 112 to the hub logic circuit, and receives the receiving buffer. The received data is transferred from 112 to the routing logic circuit.

  The transmission circuit 120 receives transmission data DataIn1 [7: 0] or DataIn2 [7: 0] (transmission data of the second interface signal in a broad sense) of UTMI via the interface circuit 160. Here, DataIn1 [7: 0] is transmission data from the hub logic circuit, and DataIn2 [7: 0] is transmission data from the routing logic circuit. The transmission circuit 120 converts DataIn1 [7: 0] or DataIn2 [7: 0] into ULPI transmission data data [7: 0] (transmission data of the first interface signal in a broad sense). Then, the transmission circuit 120 outputs data [7: 0] to the host / device controller via the interface circuit 150. Specifically, the transmission circuit 120 includes a transmission buffer 122 that buffers transmission data. Based on the control signal from the control circuit 130, the transmission circuit 120 fetches transmission data into the transmission buffer 122 and transfers transmission data from the transmission buffer 122 to the host / device controller.

  The control circuit 130 controls the conversion process between the ULPI interface signal and the UTMI interface signal. Specifically, the control circuit 130 monitors the bus state based on the ULPI interface signal and the UTMI interface signal. The control circuit 130 controls the interface circuits 150 and 160 based on the monitoring result, and outputs an ULPI interface signal and a UTMI interface signal. More specifically, the control circuit 130 receives signals stp, data [7: 0], signals TXValid1, DataIn1 [7: 0], TXValid2, DataIn2 [7: 0], and the like. In addition, a signal indicating the buffering state of the reception buffer 112 and a signal indicating the buffering state of the transmission buffer 122 are input to the control circuit 130. Based on these signals, the control circuit 130 detects the data reception state of the bus and the data transmission state of the bus, and monitors the bus state. In addition, the control circuit 130 includes, as signals for controlling data transfer, interface signals OpMode1 [1: 0], TermSelect1 [1: 0], TermMode1 [1: 0], TermSelect2 [1: 0], and TermSelect2 [1: 0, not shown. ] Etc. are entered. The control circuit 130 monitors the bus state by detecting these signals. Then, the control circuit 130 controls the interface circuit 150 based on these monitoring results and outputs signals nxt, dir, and data [7: 0]. The control circuit 130 also controls the interface circuit 160 to output signals TXReady1, DataOut1 [7: 0], TXReady2, DataOut2 [7: 0], and the like.

  The register 140 sets a register value for conversion processing between the ULPI interface signal and the UTMI interface signal. Specifically, the register 140 sets a register value for emulating the control of the transceiver on the host / device controller side (for example, PHY_HOST in FIG. 1B) by the host / device controller. More specifically, the register 140 sets a UTMI interface signal as a register value in order to compensate for a shortage of ULPI bus signals. For example, in the register 140, control signals OpMode [1: 0], XcvrSelect [1: 0], TermSelect, etc. of the transceiver on the host / device controller side are set as set values. In the register, a signal LineState [1: 0] generated by the transceiver on the host / device controller side is set as a set value. The host / device controller accesses (writes and reads) the register 140 in which these setting values are set, so that the host / device controller is as if there is a transceiver on the host / device controller side. To recognize. The control circuit 130 controls the ULPI interface signal of the interface circuit 150 by referring to the setting value of the register 140.

3.3. Example of Signal Waveform of Conversion Process An example of a signal waveform of the conversion process will be described with reference to FIGS. In the following, examples of signal waveforms of interface signals of the interface circuit 160, such as interface signals RXActive1 and RXValid1 between the interface circuit 160 and the hub logic circuit, are shown. However, similar signal waveform examples can be applied to interface signals RXActive2, RXValid2, etc. between the interface circuit 160 and the routing logic circuit. In the following, a case where the host / device controller is connected to the upstream / downstream port circuit will be described as an example. However, in the present invention, a host controller or a device may be connected to the upstream port circuit.

  FIG. 9 shows a first signal waveform example of the conversion process. FIG. 9 shows a signal waveform example when reception data is received from the host / device controller to the hub as a first signal waveform example.

  As shown in A1 of FIG. 9, when reception data is output from the host / device controller to the bus data [7: 0], the output reception data is detected. Then, as shown at A2, the signal nxt is activated (asserted and set to the first logic level), and buffering of received data is started. When the reception data output to data [7: 0] is detected, the signal RXActive1 is activated as indicated by A3. When it is detected that the received data has been buffered, the signal RXValid1 is activated as indicated by A4. Then, during the period in which RXActive1 and RXValid1 are active, the received data is transferred to the hub logic circuit as indicated by A5.

  As shown in A6, when the output of the received data from the host / device controller is completed, the signal stp is activated and then deactivated (negated, negated as shown in A7). To the logic level). When it is detected that the signal stp is active, the signal nxt is deactivated as shown at A8. As shown in A9, when it is detected that transfer of received data has been completed, the signal RXActive1 is deactivated as shown in A10, and the signal RXValid1 is deactivated as shown in A11.

  Here, as indicated by A12, during the data transfer, the J state is output as the signal LineState1 [1: 0]. For example, when data is transferred in the HS mode (High Speed Mode, 480 Mbps), the signal XcvrSelect1 [1: 0] = (0,0) is output as shown in A13, and as shown in A14, TermSelect1 = 0 (0 is L level or second logic level) is output. For example, when the normal operation mode of the transceiver is emulated, the signal OpMode1 [1: 0] = (0,0) is output as shown at A15.

  FIG. 10 shows a second signal waveform example of the conversion process. FIG. 10 shows a signal waveform example when transmission data is transmitted from the hub to the host / device controller as a second signal waveform example.

  The signal TXValid1 is activated as indicated by B2 in FIG. 10, and the transmission data is output from the hub logic circuit as indicated by B1. When it is detected that the signal TXValid1 is activated, TXReady1 is activated and buffering of transmission data is started, as indicated by B3. When it is detected that the signal TXValid1 is activated, the signal dir is activated, as indicated by B4. When it is detected that the transmission data is buffered, the signal nxt is activated as shown in B5, and the transmission data is transferred to the host / device controller as shown in B6. At this time, as shown in B6, turn around is secured in the transmission data, and an RX command (RX CMD) is added. This turnaround is secured at the active and inactive change points of the signal dir. Further, as the RX command, for example, data including the register value VbusState, LineState, etc. of the register 140 is added. As indicated by B7, nxt is deactivated during the period in which the RX command is output.

  As shown in B8, when the output of the transmission data from the hub logic circuit is completed, the signal TXValid1 is deactivated as shown in B9. When it is detected that the signal TXValid1 has been deactivated, the signal TXReady1 is deactivated, as indicated by B10. When it is detected that the transmission of the transmission data has been completed, the signal dir is deactivated as indicated by B11. As shown in B12, when it is detected that the transmission of the transmission data has been completed, the signal nxt is deactivated as shown in B13.

  Here, as indicated by B14, during the data transfer, the J state is output as the signal LineState1 [1: 0]. Similarly to FIG. 9 described above, as signals XcvrSelect1 [1: 0], TermSelect1, OpMode1 [1: 0], XcvrSelect1 [1: 0] = (0,0), TermSelect1 = 0, OpMode1 [1: 0] ] = (0,0) is output.

  FIG. 11 shows a third signal waveform example of the conversion process. FIG. 11 shows a signal waveform example when the transceiver reset operation is emulated as a third signal waveform example. FIG. 11 shows an example of a signal waveform when the upstream port circuit 350 performs the upstream port operation.

  As shown at C1 in FIG. 11, a register write command TX CMD (RegWr) is transmitted from the host / device controller (host operation) of the upstream port circuit. In response to the command TX CMD, a register value (for example, OpMode1 [1: 0] = (1,0)) corresponding to the operation mode for reset is set in the register 140. As shown in C2, SE0 (Single Ended Zero) is output to LineState1 [1: 0] for a fixed time. When it is detected that SOF (Start-of-Frame) is not output to LineState1 [1: 0], TermSelect1 = 1 (1 is H level or 1st) corresponding to termination of FS mode as shown in C3. 1 logic level) is output. Then, as indicated by C4, OpMode1 [1: 0] = (1,0) is output. The device chirp K is transmitted from the hub logic circuit, and LineState1 [1: 0] is set to the device chirp K as indicated by C5. As shown in C6, a command RX CMD for notifying the host / device controller that LineState1 [1: 0] has changed is transmitted.

  As shown in C7, after the transmission of the device chirp K is completed, LineState1 [1: 0] is set to SE0. As shown in C8, a command RX CMD for notifying the host / device controller that LineState1 [1: 0] has changed is transmitted. As shown in C9, the command TX CMD (NOPID) and the host chirp K / J are transmitted from the host / device controller. As shown in C10, the host chirp K / J is transmitted to the hub logic circuit. If it is determined that the data transfer rate is, for example, the HS mode, TermSelect1 = 0 corresponding to the termination of the HS mode is output as shown in C11. As shown in C12, in response to TermSelect1 = 0, LineState1 [1: 0] is set to the J state. As shown in C13, after the transmission of the host chirp K / J is finished, LineState1 [1: 0] is set to SE0. As shown in C14, a register write command TX CMD (RegWr) is transmitted from the host / device controller. In response to the command TX CMD, a register value (for example, OpMode1 [1: 0] = (0,0)) corresponding to the normal operation mode is set in the register 140.

4). Hub Logic Circuit FIG. 12 shows a detailed configuration example of a hub (data transfer control device). The hub of the detailed configuration example shown in FIG. 12 includes upstream and downstream port circuits 20-1 and 20-2, a hub logic circuit 40, a routing logic circuit 50, downstream port circuits 60-1 to 60-k, and a switching control circuit. 460. In the following, the same components as those described in FIG. 2 and the like described above are denoted by the same reference numerals, and description thereof will be omitted as appropriate. Here, in the following description, an example will be described in which the upstream port circuit 20-1 performs an upstream port operation and the upstream / downstream port circuit 20-2 performs a downstream port operation in the first mode. In the following, an example will be described in which a host controller is connected to the upstream port circuit 20-1, and a device is connected to the upstream port circuit 20-2.

  The hub logic circuit 40 includes a hub controller 410, a hub repeater logic circuit 420, a transaction translator 430, a hub state machine 440, and a frame timer 450. The hub logic circuit of the present invention is not limited to the configuration shown in FIG. 12, and various modifications such as omitting a part of the configuration or adding other components are possible.

  The transaction translator 430 performs transaction conversion processing. Specifically, the upstream / downstream port circuit 20-1 is connected to the host controller in the HS mode (High Speed Mode, 480 Mbps), and the upstream / downstream port circuit 20-2 or the downstream port circuits 60-1 to 60-. When k is connected to the device in the FS mode and LS mode, the transaction translator 430 performs conversion processing between the HS mode transaction on the upstream port side and the FS mode and LS mode transactions on the downstream port side.

  The hub repeater logic circuit 420 includes a mode of data transfer rate of the host controller connected to the upstream / downstream port circuit 20-1 and data transfer of a device connected to the upstream / downstream port circuit 20-2 or the downstream port circuit. Data transfer is performed when the speed mode is the same.

  Hub state machine 440 controls the state of the hub. For example, connection / disconnection between the upstream / downstream port circuit 20-1 and the host controller is detected. The hub state machine 440 detects connection / disconnection between the upstream / downstream port circuit 20-2 and the downstream port circuits 60-1 to 60-k and the device. Alternatively, the hub state machine 440 controls reset / stop / return of the upstream / downstream port circuits 20-1 and 20-2 and the downstream port circuits 60-1 to 60-k.

  The hub controller 410 controls communication between the hub and the host controller. For example, the hub controller 410 performs enumeration and exchanges hub resource information and settings with the host controller. The hub controller 410 also processes requests from the host controller.

  The frame timer 450 synchronizes the frame on the upstream port side and the frame on the downstream port side, and controls the frame interval.

  The routing logic circuit 50 connects the transaction translator 430 and the upstream / downstream port circuit 20-2 or each downstream port circuit. Alternatively, the routing logic circuit 50 connects the hub repeater logic circuit 420 and the upstream / downstream port circuit 20-2 or each downstream port circuit.

  The switching control circuit 460 outputs a switching control signal HostEn for switching between the first mode and the second mode. Specifically, the switching control circuit 460 outputs a signal HostEn to the upstream / downstream port circuits 20-1 and 20-2 and the hub logic circuit 40. For example, in the first mode, the switching control circuit 460 activates the signal HostEn (first logic level). In response, the upstream port circuits 20-1 and 20-2 perform upstream port operation and downstream port operation, respectively. The hub controller 410, the hub repeater logic circuit 420, and the transaction translator 430 perform interface processing with the upstream / downstream port circuit 20-1. On the other hand, in the second mode, the switching control circuit 460 makes the signal HostEn inactive (second logic level). In response, the upstream port circuits 20-1 and 20-2 perform a downstream port operation and an upstream port operation, respectively. The hub controller 410, the hub repeater logic circuit 420, and the transaction translator 430 perform interface processing with the upstream / downstream port circuit 20-2.

  For example, the hub may be provided with an external terminal to which a mode switching signal is supplied, and the switching control circuit 460 may be input with a mode switching signal from the external terminal. Then, the switching control circuit 460 may switch between the first mode and the second mode based on the mode switching signal from the external terminal. For example, a mode switching switch may be provided in the electronic device, and a mode switching signal may be supplied from the switch to an external terminal. Alternatively, the mode switching signal may be supplied from the host controller to the external terminal. The interface signal between the upstream / downstream port circuits 20-1 and 20-2 and the hub logic circuit 40 may include a mode switching signal. Then, the switching control circuit 460 may switch between the first mode and the second mode based on the mode switching signal included in the interface signal. For example, the mode switching signal included in the interface signal may be controlled by the host controller.

  In the above description, the case where the hub of this embodiment conforms to the USB 2.0 standard has been described as an example. However, in the present invention, the hub may conform to other standards such as USB 1.1.

5). OTG
FIG. 13 shows a configuration example of a host / device controller that can realize an OTG (On-The-Go) dual-role device. The host / device controller of this configuration example includes a transceiver 200, a transfer controller 210, a buffer controller 220, a data buffer 230, and an OTG controller 250 (state controller).

  The transfer controller 210 is a controller for controlling data transfer via the USB, and realizes a so-called SIE (Serial Interface Engine) function and the like. Specifically, the transfer controller 210 includes a switching circuit 212, a host controller 214, a peripheral controller 216, and a register unit 218. The switching circuit 212 controls switching of the connection between the transceiver 200 and the host controller 214 or the peripheral controller 216. Based on the transfer condition information set in the register unit 218, the host controller 214 performs data transfer control as a host role during host operation. The peripheral controller 216 performs data transfer control as a role of the peripheral during the peripheral operation (device operation) based on the transfer condition information set in the register unit 218.

  The OTG controller 250 is a circuit for realizing the SRP function and the HNP function of the OTG. That is, the OTG controller 250 controls a plurality of states including a host operation state operating as a host role and a peripheral operation state operating as a peripheral role.

  The transceiver 200 is a circuit for transmitting and receiving data using differential signals DP and DM (differential data signals). The buffer controller 220 secures a storage area (such as an endpoint area) in the data buffer 230 and performs access control on the storage area of the data buffer 230. The data buffer 230 (packet buffer) is a buffer (FIFO) for temporarily storing (buffering) data (transmission data or reception data) transferred via the USB.

  According to the present embodiment, even when such an OTG host / device controller is connected to a hub, data transfer can be performed. In the present invention, the hub may perform OTG interface processing, and the mode may be switched by OTG. That is, the hub may include an OTG controller and a transfer controller similar to the OTG controller 250 and the transfer controller 210 shown in FIG. Then, host operation and peripheral operation of the host / device controller connected to the hub may be switched by OTG interface processing, and the first mode and second mode of the hub may be switched.

6). Transceiver of Upstream Port Circuit FIG. 14A and FIG. 14B show a detailed configuration example of the transceiver of the upstream port circuit. The transceiver in this detailed configuration includes pull-up resistor Rpu, switch SW_Rpu, pull-down resistors Rpd1, Rpd2, switch SW_Rpd1, SW_Rpd2, switch SW_VBUS, HS (High Speed) current driver HSD, LS / FS (Low Speed / Full Speed) Includes driver LSD, resistors Rs1, Rs2, HS differential data receiver HSR, transmission envelope detector SQL, LS / FS differential data receiver LSR, disconnection envelope detector DIS, single-ended receiver DP_SER, DM_SER.

  FIG. 14A shows an example of a connection configuration when the transceiver performs a downstream port operation. As shown in FIG. 14A, the switches SW_Rpd1 and SW_Rpd2 are turned on and the switch SW_Rpu is turned off based on the signal HD_Select (for example, the switching control signal HostEn from the switching control circuit 460 in FIG. 12). Further, based on the signal HD_Select, the DP line and DM line are pulled down via the resistors Rpd1 and Rpd2, the switch SW_VBUS is switched to the VBUS supply state, and the bus power VBUS is supplied from the transceiver to the USB. The disconnection envelope detector DIS is switched to an enable state based on the signal HD_Select and detects the HS disconnect state.

  FIG. 14B shows a connection configuration example when the transceiver performs an upstream port operation. As shown in FIG. 14B, the switches SW_Rpd1 and SW_Rpd2 are turned off and the switch SW_Rpu is turned on based on the signal HD_Select. Based on the signal HD_Select, the DP line is pulled up through the resistor Rpu, the switch SW_VBUS is switched to the VBUS detection state, and the bus power VBUS is supplied from the USB bus to the transceiver. The disconnection envelope detector DIS is switched to a disabled state based on the signal HD_Select.

  14A and 14B, a connection configuration example in which the DP line is pulled up in the downstream port operation when the hub of the present embodiment operates in the HS / FS mode has been described. However, in the present invention, when the hub operates in the LS mode, the DM line may be pulled up via the resistor Rpu and the switch SW_Rpu in the downstream port operation.

7). Electronic Device FIG. 15 shows a configuration example of an electronic device to which the hub (data transfer control device) of this embodiment is applied. For example, the hub of this embodiment can be applied to electronic devices such as a personal computer (PC), a home game machine, a car navigation system, a printer, a television, a digital photo frame, and an AV recorder / player.

  An electronic device 500 illustrated in FIG. 15 includes a hub 570, a CPU 510 (for example, a host / device controller capable of switching between host operation and device operation), devices 520-1, 520-2, a port 580, a ROM 530 (Read Only Memory), A RAM 540 (Random Access Memory), a display unit 550, and an operation unit 560 are included.

  The CPU 510 communicates with the ROM 530, the RAM 540, the display unit 550, and the operation unit 560 via the CPU bus. The display unit 550 is configured by, for example, a liquid crystal panel, an EL (Electro Luminescence) panel, or the like. The operation unit 560 includes, for example, a mouse, a keyboard, a touch panel, a game controller, an infrared receiving unit, and the like.

  A CPU 510 is connected to the first upstream port circuit of the hub 570, and the hub 570 communicates with the CPU 510 via a ULPI bus. Further, the port 580 is connected to the second upstream port circuit of the hub 570. The external device 600 is connected to the port 580 by a USB cable. The hub 570 communicates with the external device 600 via the USB. Devices 520-1 and 520-2 are connected to the downstream port circuit of the hub 570, and the hub 570 communicates with the devices 520-1 and 520-2 via the USB.

  For example, an external device such as a USB memory, a portable audio player, or a digital camera may be connected to the hub 570 as the external device 600. These devices may be capable of switching between host operation and device operation. That is, when the external device 600 that performs the host operation is connected to the port 580, the CPU 510 may perform the device operation. On the other hand, when the external device 600 that performs the device operation is connected to the port 580, the CPU 510 may perform the host operation. In addition, a built-in device such as an HDD (Hard Disk Drive), a DVD drive, and a CD drive, a display unit, and an operation unit may be connected to the hub 570 as the devices 520-1 and 520-2.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, terms (USB, ULPI interface) described at least once together with different terms (serial bus, first interface circuit, second interface circuit, data transfer control device, etc.) having a broader meaning or the same meaning Circuit, UTMI interface circuit, hub, etc.) may be replaced by their different terms anywhere in the specification or drawings. Further, the configurations and operations of the upstream / downstream port circuit, the downstream port circuit, the hub logic circuit, the routing logic circuit, the data transfer control device, the electronic device, etc. are not limited to those described in this embodiment, and various modifications are possible. Implementation is possible.

10 data transfer control device,
20-1, 20-2 first and second upstream port circuits,
40 Hub logic circuit, 50 Routing logic circuit,
60-1 to 60-k downstream port circuit, 100 conversion circuit,
110 receiving circuit, 112 receiving buffer, 120 transmitting circuit,
122 transmission buffer, 130 control circuit, 140 registers,
150 first interface circuit, 160 second interface circuit,
162 selector, 310 transceiver, 320 serial parallel conversion circuit,
330 parallel-serial conversion circuit, 340 selector,
410 Hub controller, 420 Hubbell Peter logic circuit,
430 Transaction Translator, 440 Hub State Machine,
450 frame timer, 460 switching control circuit, 500 electronic equipment,
510 CPU, 520-1, 520-2 device, 530 ROM,
540 RAM, 550 display unit, 560 operation unit, 570 hub, 580 port,
600 External equipment,
HDCA host / device controller, HCA host controller,
DVA device, BUS1 to BUS4 first to fourth buses,
HostEn switching control signal

Claims (13)

At least one downstream port circuit;
A first upstream port circuit that performs upstream port operation in a first mode and performs downstream port operation in a second mode;
A second upstream port circuit that performs a downstream port operation in the first mode and performs an upstream port operation in the second mode;
A routing logic circuit;
Hub logic circuit that performs hub logic operation,
Including
In the first mode,
Transferring data from the first upstream port circuit in upstream port operation to the second upstream port circuit in downstream port operation via the hub logic circuit and the routing logic circuit;
In the second mode,
Transferring data from the second upstream port circuit in upstream port operation to the first upstream port circuit in downstream port operation via the hub logic circuit and the routing logic circuit; A data transfer control device. In claim 1,
In the first mode,
Transferring data from the first upstream port circuit in upstream port operation to the at least one downstream port circuit via the hub logic circuit and the routing logic circuit;
In the second mode,
Data transfer control, wherein data from the second upstream port circuit in upstream port operation is transferred to the at least one downstream port circuit via the hub logic circuit and the routing logic circuit apparatus. In claim 1 or 2,
A first bus provided between the first upstream port circuit and the hub logic circuit;
A second bus provided between the first upstream / downstream port circuit and the routing logic circuit;
A third bus provided between the second upstream port circuit and the hub logic circuit;
A fourth bus provided between the second upstream / downstream port circuit and the routing logic circuit;
Including
In the first mode,
Data from the first upstream / downstream port circuit is transferred to the second upstream / downstream port circuit via the first bus, the hub logic circuit, the routing logic circuit, and the fourth bus. ,
In the second mode,
Data from the second upstream / downstream port circuit is transferred to the first upstream / downstream port circuit via the third bus, the hub logic circuit, the routing logic circuit, and the second bus. A data transfer control device. In any one of Claims 1 thru | or 3,
The hub logic circuit is:
A hub controller,
Have a repeater logic circuit,
A transaction translator,
Hub state machine,
Frame timer,
A data transfer control device comprising: In any one of Claims 1 thru | or 4,
A host / device controller capable of switching between host operation and device operation is connected to the first upstream port circuit,
In the first mode,
The first upstream port circuit performs an interface process between the host / device controller that performs a host operation and the hub logic circuit,
In the second mode,
The data transfer control apparatus, wherein the first upstream port circuit performs an interface process between the host / device controller that performs a device operation and the routing logic circuit. In claim 5,
The first upstream port circuit includes:
A data transfer control device that performs interface processing with the host / device controller via a USB (Universal Serial Bus). In claim 6,
The host / device controller conforms to the OTG (On-The-Go) standard,
The first upstream port circuit includes:
A data transfer control device that performs interface processing in conformity with the OTG standard with the host / device controller. In claim 5,
The first upstream port circuit includes:
A data transfer control device for performing interface processing with a link layer circuit of the host / device controller. In claim 8,
The first upstream port circuit includes:
A data transfer control device connected to the host / device controller via a bus of ULPI standard (UTMI + Low Pin Interface) and performing an ULPI interface process with the link layer circuit of the host / device controller. In claim 8 or 9,
The first upstream port circuit includes:
A first interface circuit that performs an interface process with the link layer circuit of the host / device controller;
A second interface circuit that performs interface processing with the hub logic circuit in the first mode, and performs interface processing with the routing logic circuit in the second mode;
A conversion circuit that performs conversion processing between an interface signal of the first interface circuit and an interface signal of the second interface circuit;
A data transfer control device comprising: In any one of Claims 1 thru | or 4,
In the first mode,
A host controller is connected to the first upstream port circuit, and the first upstream port circuit performs an interface process between the host controller and the hub logic circuit,
In the second mode,
A device is connected to the first upstream port circuit, and the first upstream port circuit performs interface processing between the device and the routing logic circuit. . In claim 11,
The first upstream port circuit includes:
A data transfer control device that performs interface processing with the host controller or the device via a USB (Universal Serial Bus).   An electronic apparatus comprising the data transfer control device according to claim 1.

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