JP2010217344A - Display device and driving method thereof - Google Patents

Abstract

Provided is a display device capable of maintaining a display function even when a malfunction occurs in a drive circuit.
A gate line is composed of a plurality of adjacent gate lines and a gate line, and includes a gate driver that drives the gate line and a gate driver that drives the gate line. The gate output determination unit 71 determines whether one of the gate drivers 30a and 30b has failed based on the output timing of the gate signals Gout_A and Gout_B output from the gate drivers 30a and 30b. When the gate output determination unit 71 determines that the gate driver 30a is out of order, the gate line 12b is driven by the gate driver 30b.
[Selection] Figure 12

Description

  The present invention provides a scanning signal line, a switching element that is turned on / off by the scanning signal line, a pixel electrode connected to one end of the switching element, and a switching element, such as an active matrix liquid crystal display panel. The present invention relates to a display device for driving a display panel having a data signal line connected to the other end and a driving method thereof.

  In recent years, a monolithic circuit in which a scanning signal line driving circuit and a data signal line driving circuit are formed on the same TFT substrate in an active matrix liquid crystal display device has been proposed. This monolithic circuit has the advantage that the device can be reduced in size and the manufacturing process can be simplified. However, if a problem occurs in the drive circuit, the entire display panel is judged as a defective product, resulting in a decrease in yield. It was a factor.

  In view of this, Japanese Patent Application Laid-Open No. H10-133707 discloses a technique that can prevent a decrease in yield even when such a malfunction of the drive circuit occurs. FIG. 33 is a diagram showing a schematic configuration of the liquid crystal display device of Patent Document 1. In FIG. The liquid crystal display device includes two systems of scanning signal line driving circuits 13 and 15 and two systems of data signal line driving circuits 17 and 19. Therefore, when one scanning signal line drive circuit fails, it can be switched to the other normal scanning signal line drive circuit (hereinafter also referred to as a redundant circuit), and one data signal line drive circuit fails. In this case, it is possible to switch to the other normal data signal line driving circuit (redundant circuit). Therefore, the defect rate of the display panel can be reduced and the yield can be improved.

JP-A-6-67200 (published March 11, 1994)

  However, the technique of Patent Document 1 has the following problems. That is, since the liquid crystal display device is configured to improve the yield, the inspection of defects of each drive circuit and the switching process to the redundant circuit are performed before product shipment, particularly in the final inspection process. For this reason, it is difficult to perform the switching process to the redundant circuit for those that are determined to be normal in the final inspection process and are distributed to general users.

  Therefore, if the drive circuit fails during long-term use by the user, even if it has a redundant circuit, the switching process to the redundant circuit is not automatically performed. It is determined that there is a failure, and nothing is displayed on the display screen.

  In addition, even a display panel mounted with a normal LSI may cause a problem although it is relatively small when used for a long period of time. In the case where the display panel is used for an application requiring reliability, even such a problem may not be allowed. In addition, when the driver circuit is built in the display panel as in recent years, the probability of occurrence of the failure is greatly increased, especially when the driver circuit is built with an amorphous panel or the like, the risk of occurrence of the failure is extremely high. To be high.

  Here, the specific example is demonstrated using FIGS. FIG. 34 is a block diagram showing the overall configuration when a gate driver is built in the panel, and shows one configuration example of the gate driver. FIG. 35 is an internal circuit diagram of each shift register constituting the gate driver of FIG. Here, a configuration example of a shift register in a case where only an N-channel TFT is used and the panel is formed of amorphous silicon or the like is shown. FIG. 36 is a timing chart showing an operation example of the shift register shown in FIG.

  GSPOI output from the controller unit is input to Qn−1 of the uppermost shift register shown in FIG. In the other shift registers, the output of the previous stage is input to Qn−1 (set). Further, the output of each stage is configured to be input (reset) to Qn + 1 of the previous stage. In addition, GCK is input to cka and GCKB is input to ckb to the odd-numbered shift register, and GCKB is input to cka and GCK is input to ckb to the even-numbered shift register. As an example, the operation principle of an odd-numbered (2n + 1) shift register will be described. First, when Gout (2n) in the previous stage is output, the output is input to the 2n + 1-th shift register (Gn-1 (previous stage in FIG. 34)). )), The transistor TrB is turned on, and netA (2n + 1) is set to the Hi level. Next, when GCK rises (GCK is connected to cka in FIG. 34), netA is further boosted by the bootstrap effect of the TrI section, and TrI is turned on. When TrI is turned on, the output of GCK is output as it is for Gout (2n + 1). Similarly, Gout (2n + 1) sets the shift register of the next stage (2n + 2 stage), and Gout (2n + 2) is output at the next rising edge of GCKB. Since Gout (2n + 2) is connected to Gn + 1 (next stage) in FIG. 34, TrL and TrN of the 2n + 1 stage shift register are turned on by Gout (2n + 2), and Gout (2n + 1) and netA (2n + 1) Is dropped to Lo level. In the cycle as described above, the output is shifted from the first stage to the last stage. The CLR signal is used for forcibly stopping the output or resetting.

  In such a circuit, as is well known, when the transistor is operated for a long time, the threshold voltage (Vth) of the transistor tends to shift (shift to the positive side), thereby reducing the current driving capability of the transistor, A problem that shift operation cannot be performed occurs. This defect also depends on temperature, and tends to occur more easily when used under severe conditions.

  Therefore, when a liquid crystal display device having such a drive circuit is applied to an in-vehicle instrument panel exposed to a high temperature environment, a particularly serious problem occurs. Specifically, when the above-mentioned problem occurs in the in-vehicle instrument panel to which the liquid crystal display device is applied, the instrument panel display (for example, speedometer, tachometer, engine thermometer, remaining fuel amount) (Summary, turn signals, various warning lights such as seat belt warning lights, navigation to display a map, website information, information on the surroundings of the vehicle including the own vehicle and conditions in the vehicle, etc.) are hidden. May cause a serious accident.

  As described above, since the conventional drive circuit may cause problems due to long-term use, the conventional liquid crystal display device including such a drive circuit is particularly reliable (high temperature range) such as an in-vehicle instrument panel. And it is very difficult to apply to the field where long life is required.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a display device capable of maintaining a display function even when a malfunction occurs in a drive circuit, and a driving method thereof. .

  In order to solve the above problems, a display device according to the present invention includes a scanning signal line, a transistor that is turned on / off by a scanning signal supplied to the scanning signal line, and a pixel electrode connected to one end of the transistor. And a display panel including a data signal line connected to the other end of the transistor, wherein at least one of the scanning signal line and the data signal line is a plurality of adjacent signal lines. At least two sets are provided, and each set includes at least one signal line drive circuit that drives the signal lines of the set, and at least one of the plurality of signal line drive circuits fails. Determining means based on the output timing of the signal output from each signal line driving circuit, and the determining means determines that one signal line driving circuit has failed. Is the case was at least, the other normal signal line driver circuit, and drives the pair of signal lines corresponding to the normal signal line driving circuit.

  According to the above configuration, for example, a plurality of scanning signal lines can be divided into two sets, and one scanning signal line driving circuit can be provided for each set. When one scanning signal line driving circuit fails, the other scanning signal line driving circuit can drive the scanning signal line of its own set. As a result, the display function can be maintained in a normal display area in which the scanning signal lines driven by the other scanning signal line driving circuit are arranged. Therefore, for example, an operation such as displaying a message (warning) indicating that an abnormality has occurred in the display device can be performed in the normal display area.

  As described above, in the above configuration, even if a certain signal line driver circuit fails, the display function can be maintained, and thus a problem that the entire display screen is suddenly not displayed can be avoided.

  Note that the signal line driver circuit may be either a scanning signal line driver circuit or a signal line driver circuit, or both.

  In the present display device, two signal line drive circuits for driving the signal lines of the set are provided for each of the groups, and one of the signal line drive circuits corresponding to one set has failed due to the determination unit. If it is determined that the switching unit is switched to the other normal signal line driver circuit corresponding to the same group, the switching unit may be provided.

  According to the above configuration, two signal line drive circuits are provided for one set, and when one signal line drive circuit fails, the other signal line drive circuit drives the signal line of the set. The

  For this reason, even if one of the signal line drive circuits fails, the normal signal line drive circuit is automatically switched to the other, so that a normal display operation can be maintained. Therefore, the lifetime of the display device can be extended. In addition, the manufacturing yield can be improved.

  In the present display device, the determination means determines whether the signal output from each signal line driving circuit is output at a predetermined timing or not at a timing other than the predetermined timing. When the signal output from the signal line driver circuit is output at a predetermined timing and not at a timing other than the predetermined timing, it is determined that the signal line driver circuit has not failed. The signal output from one signal line driver circuit is not output at a predetermined timing, or is output at a timing that is not a predetermined timing, or is not a predetermined timing and a predetermined timing. If the signal is output at both timings, the signal is determined to be abnormal, and the signal line driver circuit is determined to be faulty. It can also be a.

  According to the above configuration, there are various cases of abnormalities, such as when no signal is output from the signal line drive circuit or when it is output at other timings although it is output normally at a predetermined timing. Therefore, the accuracy of detecting a failure of the signal line driver circuit can be improved.

  In the present display device, the predetermined timing may be set in advance according to the number of signal lines included in each set.

  In the above configuration, for example, in an 800 RGB × 480 (WVGA) liquid crystal display device, when the 480 scanning signal lines are divided into two sets (240 each), the predetermined timing is set to the gate start pulse. Can be set to the end of 240-line scanning (240 horizontal scanning period). Thus, according to the number of signal lines, the predetermined timing can be easily set.

  In this display device, the signal line driving circuit is a scanning signal line driving circuit, and the determination means is a scanning signal line located at an end portion on the scanning end side of the plurality of scanning signal lines in each set. It is also possible to determine whether the scanning signal output from is output at the predetermined timing and whether it is output at a timing other than the predetermined timing.

  According to the above example, when the signal line driving circuit is normally driven, the scanning signal output from the scanning signal line located at the end portion on the scanning end side is 240 lines from the output of the gate start pulse. Are output at the end of scanning (240 horizontal scanning periods). Therefore, it is possible to easily determine whether or not the signal line driving circuit is normally driven by monitoring the scanning signal.

  In this display device, the signal line driving circuit is a scanning signal line driving circuit, and each scanning signal line driving circuit is connected to the scanning signal line via a switching element corresponding to the scanning signal line driving circuit. An off signal is input to a switching element connected to a scanning signal line drive circuit determined to have failed by the determination means, while an on signal is input to a switching element connected to another normal scanning signal line drive circuit. Thus, the scanning signal line driver circuit can be switched.

  According to the above configuration, since the failed scanning signal line drive circuit can be electrically disconnected from the scanning signal line, there is a risk of malfunction caused by the failed scanning signal line drive circuit after switching the drive circuit. Can be suppressed.

  In the display device, the switching unit further stops the output of the gate start pulse to the scanning signal line driving circuit determined to have failed by the determining unit, while the other switching signal line driving circuit is not operated. The gate start pulse can be output.

  According to the above configuration, no gate start pulse is input to the failed scanning signal line driving circuit, and the operation of the scanning signal line driving circuit can be stopped, so that useless power consumption can be reduced. . In the case of a monolithic circuit, useless shift of the threshold can be stopped, which contributes to improving the total life.

  In the present display device, the signal line drive circuit is a data signal line drive circuit, and the determining means is located at an end of a plurality of data signal lines on the end side in the data sampling direction in each set. It is also possible to determine whether a data signal output from the data signal line to be output is output at the predetermined timing and whether it is not output at a timing other than the predetermined timing.

  Thereby, the failure of the data signal line driving circuit can be determined by a simple method. The data signal is specifically a signal applied from the data signal line driving circuit to each data signal line, or a source start pulse input from the data signal line driving circuit to the control circuit (control unit). A signal corresponding to.

  In the present display device, the switching means stops the output of the source start pulse to the data signal line drive circuit determined to have failed by the determination means, while the source of the other normal data signal line drive circuit is stopped. It can also be configured to output a start pulse.

  According to the above configuration, the source start pulse is not input to the failed data signal line driving circuit, and the operation of the data signal line driving circuit can be stopped, so that useless power consumption can be reduced. .

  The display device further includes measurement means for measuring the number of times the determination means determines that the output timing of the signal output from each signal line drive circuit is abnormal, and the determination means includes the signal from the measurement means. When the number of times of abnormality determination reaches a predetermined number, it can be determined that the signal line driver circuit that outputs the signal has failed.

  According to said structure, the said abnormality determination frequency can be set to multiple times, for example. Thereby, when an abnormality (for example, noise) that does not affect the display quality is detected once, it is possible to prevent the drive circuit from being switched unnecessarily, and the reliability can be improved.

  The display device further includes notifying means for notifying the operation state of the signal line driving circuit to the outside, and the notifying means determines whether each signal line driving circuit has failed according to the determination result of the determining means. Can also be configured to notify the outside.

  Thereby, it is possible to make the user recognize the failure of each signal line driving circuit. As a specific notification method, a known method such as turning on an LED lamp, displaying a message, or generating an error sound can be applied.

  Here, for example, when it is applied to a vehicle (instrument panel or the like), it is a very big problem for a driver who is on board that the instrument panel displaying a speedometer or the like is not displayed. In this regard, according to the above configuration, even if one signal line driving circuit fails, it can be displayed normally by another signal line driving circuit, and the driver can detect that one signal line driving circuit has failed. Can be recognized. That is, since it is possible to perform appropriate measures such as component replacement and repair while the instrument panel is operating normally, it is possible to avoid the worst situation in which the instrument panel is not displayed at all.

  In this display device, when all the signal line drive circuits corresponding to one set fail, and at least one signal line drive circuit corresponding to the other set is normal, the normal signal line drive is performed. A message for informing the outside of the abnormality of the display device may be displayed in a display area where a signal line driven by a circuit is arranged.

  Thereby, it is possible to make the user recognize the abnormality of the display device.

  A driving method of a display device according to the present invention includes a scanning signal line, a transistor that is turned on / off by a scanning signal supplied to the scanning signal line, a pixel electrode connected to one end of the transistor, A data signal line connected to the other end, and at least two signal lines of the scanning signal line and the data signal line are provided with at least two sets composed of a plurality of adjacent signal lines. A driving method of a display device having a display panel, wherein at least one signal line driving circuit for driving the signal lines of the set is provided, wherein at least one of the plurality of signal line driving circuits fails. A determination step for determining whether or not there is a signal output from each signal line drive circuit, and one of the signal line drive circuits has failed due to the determination step. And when it is determined at least by other normal signal line driver circuit, and drives the pair of signal lines corresponding to the normal signal line driving circuit.

  In the above method, the display function can be maintained even when a problem occurs in the drive circuit, similarly to the effect described for the display device.

  In the display device and the driving method thereof according to the present invention, as described above, whether or not at least one of the plurality of signal line driving circuits has failed is determined based on the output timing of the signal output from each signal line driving circuit. If it is determined that one of the signal line driver circuits is out of order, another normal signal line driver circuit drives a pair of signal lines corresponding to the normal signal line driver circuit. Is.

  According to the above configuration and method, the display function can be maintained even when a problem occurs in the drive circuit.

It is a block diagram which shows the structure of the liquid crystal display device which concerns on Embodiment 1 of this invention. FIG. 2 is an equivalent circuit diagram illustrating an electrical configuration of each pixel in the liquid crystal display device of FIG. 1. FIG. 2 is a block diagram illustrating a configuration of a gate driver in the liquid crystal display device of FIG. 1. 3 is a timing chart showing various signals when a first gate driver in the liquid crystal display device of FIG. 1 is operating normally. 3 is a timing chart showing various signals when the first gate driver in the liquid crystal display device of FIG. 1 fails. 3 is a timing chart showing various signals when a second gate driver in the liquid crystal display device of FIG. 1 fails. 4 is a timing chart showing various signals when a third gate driver in the liquid crystal display device of FIG. 1 fails. 7 is a timing chart showing various signals when a fourth gate driver in the liquid crystal display device of FIG. 1 fails. 6 is a timing chart showing another example when the first gate driver in the liquid crystal display device of FIG. 1 fails. 3 is a flowchart illustrating an operation example of detecting an abnormality in a first gate driver and a third gate driver of the liquid crystal display device in FIG. 1. 6 is a flowchart illustrating an operation example of detecting an abnormality in a second gate driver and a fourth gate driver of the liquid crystal display device in FIG. 1. It is a block diagram which shows the other structure of the liquid crystal display device of this invention. It is a block diagram which shows the other structure of the liquid crystal display device of this invention. It is a block diagram which shows the structure of the gate driver in the liquid crystal display device of FIG. It is a circuit diagram which shows the internal structure of the shift register which comprises the gate driver of FIG. 14 is a timing chart showing various signals when the first gate driver in the liquid crystal display device of FIG. 13 fails. 14 is a timing chart showing various signals when the fourth gate driver in the liquid crystal display device of FIG. 13 fails. 14 is a flowchart illustrating an operation example of detecting an abnormality in the first gate driver and the third gate driver of the liquid crystal display device in FIG. 13. 14 is a flowchart illustrating an operation example of detecting an abnormality in the second gate driver and the fourth gate driver of the liquid crystal display device in FIG. 13. It is a block diagram which shows the structure of the liquid crystal display device which concerns on Embodiment 2 of this invention. FIG. 21 is a block diagram illustrating a schematic configuration of a source driver in the liquid crystal display device of FIG. 20. 21 is a timing chart showing various signals when the first source driver in the liquid crystal display device of FIG. 20 is operating normally. FIG. 21 is a block diagram illustrating a state in which a first source chip driver of a first source driver in the liquid crystal display device of FIG. 20 is out of order. 21 is a timing chart showing various signals when the first source driver in the liquid crystal display device of FIG. 20 fails. 21 is a timing chart showing various signals when a third source driver in the liquid crystal display device of FIG. 20 fails. 21 is a flowchart illustrating an operation example (source driver) of the liquid crystal display device of FIG. It is a block diagram which shows the other structure of the liquid crystal display device of this invention. 21 is a timing chart showing various signals when the first gate driver in the liquid crystal display device of FIG. 20 is operating normally. FIG. 21 is a timing chart showing various signals when the first gate driver in the liquid crystal display device of FIG. 20 fails. FIG. 21 is a timing chart showing various signals when a third gate driver in the liquid crystal display device of FIG. 20 fails. 21 is a flowchart showing an operation example (gate driver) of the liquid crystal display device of FIG. FIG. 21 is a block diagram illustrating another configuration of the liquid crystal display device of FIG. 20. It is a block diagram which shows the structure of the conventional liquid crystal display device. FIG. 34 is a block diagram showing a configuration of a gate driver in the liquid crystal display device of FIG. 33. FIG. 35 is an internal circuit diagram of each shift register constituting the gate driver of FIG. 34. 36 is a timing chart illustrating an operation example of the shift register illustrated in FIG. 35.

[Embodiment 1]
An embodiment of the present invention will be described below with reference to FIGS.

  First, the configuration of the liquid crystal display device 1 corresponding to the display device of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing the overall configuration of the liquid crystal display device 1, and shows a case where a gate driver (scanning signal line driving circuit) is integrally formed in the panel. FIG. 2 is an equivalent circuit diagram showing an electrical configuration of a pixel of the liquid crystal display device 1.

  The liquid crystal display device 1 includes an active matrix liquid crystal display panel 10, a source driver (data signal line driving circuit) 20, a first gate driver (scanning signal line driving circuit) 30a, a second gate driver 30b, and a third gate driver 40a. , Fourth gate driver 40b, first changeover switch part (switching means) 50a, second changeover switch part 50b, third changeover switch part 60a, fourth changeover switch part 60b, control part (switching means) 70, notification part ( Notification means) 80 is provided.

  The liquid crystal display panel 10 is configured by sandwiching a liquid crystal between an active matrix substrate (not shown) and a counter substrate, and has a large number of pixels P (see FIG. 2) arranged in a matrix.

  As shown in FIG. 2, the liquid crystal display panel 10 includes a source bus line (data signal line) 11, a gate line (scanning signal line) 12 (12a and 12b), a thin film transistor (Thin Film Transistor) on an active matrix substrate. Hereinafter referred to as “TFT”) 13 and a pixel electrode 14, and a counter electrode 18 is provided on the counter substrate.

  One source bus line 11 is formed in each column so as to be parallel to each other in the column direction (vertical direction), and one gate line 12 is provided in each row so as to be parallel to each other in the row direction (lateral direction). Each book is formed. A dummy gate line (dummy line, dummy scanning signal line) 12x (see FIG. 1) that does not contribute to the display is arranged in parallel with the gate line 12 at the extreme end located on the scanning end side of the gate signal (scanning signal). Is provided. The TFT 13 and the pixel electrode 14 are formed corresponding to the intersections of the source bus line 11 and the gate line 12, respectively. The source electrode s of the TFT 13 is the source bus line 11, the gate electrode g is the gate line 12. Drain electrodes d are connected to the pixel electrodes 14 respectively. In addition, a liquid crystal capacitor 17 is formed between the pixel electrode 14 and the counter electrode 18 via a liquid crystal.

  Thereby, the gate of the TFT 13 is turned on by the gate signal (scanning signal) supplied to the gate line 12, the data signal from the source bus line 11 is written into the pixel electrode 14, and the potential corresponding to the source signal is applied to the pixel electrode 14. And applying a voltage according to the source signal to the liquid crystal interposed between the counter electrode 18 and the gray scale display according to the source signal can be realized.

  The liquid crystal display device 1 may include a CS bus line (retention capacitor line) 15 as shown in FIG. One CS bus line 15 is formed in each row so as to be parallel to each other in the row direction (lateral direction), and is arranged to make a pair with the gate line 12. Each CS bus line 15 is capacitively coupled to the pixel electrode 14 disposed in each row, and forms a storage capacitor (also referred to as “auxiliary capacitor”) 16 with each pixel electrode 14.

  The first gate driver 30a and the third gate driver 40a are configured as a pair via the same gate line, and the second gate driver 30b and the fourth gate driver 40b are configured as a pair via the same gate line. Each gate line (12) is configured as a set of a plurality of adjacent adjacent lines. That is, the first gate driver 30a is connected to one end of the set of gate lines 12a, and the third gate driver 40a is connected to the other end, and the second gate driver 30b is connected to one end of the set of gate lines 12b. And the fourth gate driver 40b is connected to the other end.

  The first changeover switch unit 50a includes a plurality of first switches (switching elements) 51a corresponding to the gate lines 12a. Specifically, each of the first switches 51a has one conduction electrode connected to the first gate driver 30a, the other conduction electrode connected to each gate line 12a, and each control electrode connected to each other. Yes. Accordingly, by inputting an ON signal to the control electrode, all the first switches 51a are turned ON, the first gate driver 30a and the gate line 12a are electrically connected, and an OFF signal is input to the control electrode. Thus, all the first switches 51a are turned off, and the first gate driver 30a and the gate line 12a are electrically disconnected.

  The second changeover switch unit 50b includes a plurality of second switches (switching elements) 51b corresponding to the gate lines 12b. Specifically, each of the second switches 51b has one conductive electrode connected to the second gate driver 30b, the other conductive electrode connected to each gate line 12b, and each control electrode connected to each other. Yes. Thus, by inputting an ON signal to the control electrode, all the second switches 51b are turned ON, the second gate driver 30b and the gate line 12b are electrically connected, and an OFF signal is input to the control electrode. As a result, all the second switches 51b are turned off, and the second gate driver 30b and the gate line 12b are electrically disconnected.

  The third changeover switch unit 60a includes a plurality of third switches (switching elements) 61a corresponding to the gate lines 12a. Specifically, each of the third switches 61a has one conductive electrode connected to the third gate driver 40a, the other conductive electrode connected to each gate line 12a, and each control electrode connected to each other. Yes. Accordingly, by inputting an ON signal to the control electrode, all the third switches 61a are turned ON, the third gate driver 40a and the gate line 12a are electrically connected, and an OFF signal is input to the control electrode. As a result, all the third switches 61a are turned off, and the third gate driver 40a and the gate line 12a are electrically disconnected.

  The fourth changeover switch unit 60b includes a plurality of fourth switches (switching elements) 61b corresponding to the gate lines 12b. Specifically, each of the fourth switches 61b has one conduction electrode connected to the fourth gate driver 40b, the other conduction electrode connected to each gate line 12b, and each control electrode connected to each other. Yes. Thus, by inputting an ON signal to the control electrode, all the fourth switches 61b are turned ON, the fourth gate driver 40b and the gate line 12b are electrically connected, and an OFF signal is input to the control electrode. As a result, all the fourth switches 61b are turned off, and the fourth gate driver 40b and the gate line 12b are electrically disconnected.

  As described above, the first gate driver 30a and the third gate driver 40a have the same function, and the first gate driver 30a is connected to the gate line 12a via the first changeover switch unit 50a. 40a is connected to the gate line 12a via the third changeover switch 60a. That is, the first gate driver 30a and the third gate driver 40a are arranged in pairs via the same signal line (gate line 12a), and are configured to have redundancy. Similarly, the second gate driver 30b and the fourth gate driver 40b have the same function, and the second gate driver 30b is connected to the gate line 12b via the second changeover switch unit 50b, and the fourth gate driver 40b Is connected to the gate line 12b via the fourth changeover switch 60b. That is, the second gate driver 30b and the fourth gate driver 40b are arranged in pairs via the same signal line (gate line 12b), and are configured to have redundancy. Hereinafter, the first gate driver 30a and the second gate driver 30b are replaced by the main gate driver 30a and the main gate driver 30b, respectively, and the third gate driver 40a and the fourth gate driver 40b are respectively replaced by the sub-gate driver 40a (redundant circuit). ) Also referred to as sub-gate driver 40b (redundant circuit).

  In addition to a general function (not shown) for controlling each drive circuit (gate driver and source driver), the control unit 70 includes gate signals (30a, 30b, 40a, 40b) output from each gate driver ( Gout) is monitored, and a gate output determination unit 71 that determines whether or not the output timing is normal is provided. When the gate output determination unit 71 determines that the output timing of the gate signal is abnormal, normal display is not performed, and thus it is determined that the gate driver that has output the gate signal has failed. A specific determination method will be described later.

  Further, the control unit 70 switches the gate driver for driving the gate line 12a between the first gate driver 30a and the third gate driver 40a according to the determination result of the gate output determination unit 71. A gate driver switching signal SW (SW_C · SW_D) for switching between the second gate driver 30b and the fourth gate driver 40b for the driver for outputting the switching signal SW (SW_A · SW_B) and driving the gate line 12b. ) Is output. That is, the control unit 70 also has a function as switching means for switching the main gate driver to the sub gate driver.

  The control unit 70 also includes a memory unit 76 that stores message data to be displayed on the liquid crystal display panel 10 when an abnormality occurs in the gate driver. When this message is displayed, a potential corresponding to the data is supplied to the source driver 20.

  Furthermore, the control unit 70 outputs an error flag for notifying the outside of the abnormal state of the gate driver to the notification unit 80. The notification unit 80 has a function of notifying the user of a failure of the gate driver. For example, a known method such as turning on an LED lamp, displaying a message, or generating an error sound can be applied. A more detailed configuration of the control unit 70 will be described later.

  As shown in FIG. 1, a level shifter 72 for shifting the logic level and the gate drive level is provided between the control unit 70 and each gate driver. It may be provided in the control unit 70. Further, the level shifter 72 and the control unit 70 may be provided in the source driver 20.

  In this embodiment, in the active period (effective scanning period) in the vertical scanning period that is periodically repeated, the horizontal scanning period of each row is sequentially assigned, and each row is sequentially scanned. Therefore, each gate driver (30a, 30b, 40a, 40b) sequentially outputs a gate signal for turning on the TFT 13 to the gate line 12 of the row in synchronization with the horizontal scanning period of each row.

  The source driver 20 outputs a source signal to each source bus line 11. This source signal is a signal obtained by assigning a video signal supplied from the outside of the liquid crystal display device 1 to the source driver 20 via the control unit 70 to each column in the source driver 20 and performing boosting or the like.

(Operation example 1 of the liquid crystal display device 1)
Next, an operation example of the liquid crystal display device 1 will be described together with a specific configuration of the control unit 70. Here, as an example, the liquid crystal display device 1 of 800 RGB × 480 (WVGA) will be described as an example.

  FIG. 3 is a block diagram showing the configuration of the gate driver of the present liquid crystal display device. As shown in the figure, each shift register (A1, A2,...) Constituting the first gate driver 30a and each shift register (C1, C2,...) Constituting the third gate driver 40a are the same gate line 12a. The shift registers (B1, B2,...) Constituting the second gate driver 30b and the shift registers (D1, D2,...) Constituting the fourth gate driver 40b are connected to each other via the same gate line 12b. Are connected to each other. A gate start pulse GSP is input to the first-stage shift register of each gate driver, and a gate output Gout is output from the last-stage shift register.

  FIG. 4 is a timing chart showing various signals in the control unit 70 and the first and second gate drivers 30a and 30b when the first (main) gate driver 30a is operating normally. FIG. 6 is a timing chart showing various signals in the control unit 70, the first, second, and third gate drivers (30a, 30b, 40a) when the first (main) gate driver 30a fails. 3 is a timing chart showing various signals in the control unit 70, first, second, and fourth gate drivers (30a, 30b, 40b) when a 2 (main) gate driver 30b fails.

  In each figure, GCK and GCKB indicate clock signals, GSP indicates a gate start pulse, G1, G2,..., G239, G240, G241, ..., G480, G481 (Gout_A) are the first and second lines, respectively. ,..., 239th line, 240th line, 241st line, 480th stage (final stage), 481st stage (outer area of active area 10a, corresponding to dummy line 12x) Yes. The detection pulse (detection pulse) is a signal that serves as a trigger for periodically detecting the high level (Hi level) / low level (Lo level) of the gate signal of each row. Here, the detection pulse is detected every horizontal scanning period. It is the composition to do. SW_A, SW_B, SW_C, and SW_D indicate gate driver switching signals input to the first changeover switch unit 50a, the second changeover switch unit 50b, the third changeover switch unit 60a, and the fourth changeover switch unit 60b, respectively. When the SW is at the Hi level (Hi), the changeover switch unit is turned on and the corresponding gate driver is in the active state, and when the SW is at the Lo level (Lo), the changeover switch unit is turned off to correspond. The gate driver becomes inactive. The error flags A to D are signals that are output in synchronization with the timing at which the gate driver switching signals SW_A to SW_D are switched from the Hi level to the Lo level.

  First, a case where the first (main) gate driver 30a and the second (main) gate driver 30b are operating normally will be described.

  In the initial state, SW_A and SW_B are set to the Hi level, and SW_C and SW_D are set to the Lo level. Thereby, the first changeover switch unit 50a and the second changeover switch unit 50b are turned on, the first gate driver 30a and the second gate driver 30b are activated, and the third changeover switch unit 60a and the fourth changeover switch unit. 60b is turned off, and the third gate driver 40a and the fourth gate driver 40b are inactivated.

  When GSP_A is input from the control unit 70 to the first gate driver 30a, the first stage (first stage) shift register A1 (FIG. 3) is set. In this state, when a Hi pulse is input to the terminal cka of the first-stage shift register A1 (that is, GCK becomes Hi level), the gate signal G1 is output. The gate signal G1 sets the shift register A2 at the next stage (second stage), and a Hi pulse is input to the terminal cka of the shift register A2 (that is, GCKB becomes Hi level), whereby the gate signal G2 Is output. Similarly, output pulses (gate signals) are sequentially shifted and input to the final stage (240th stage) shift register A240. The gate signal G240 (Gout_A) output from the shift register A240 is input to the gate line 12a at the final stage and input to the control unit 70.

  Here, the gate output determination unit 71 of the control unit 70 determines whether or not the gate signal is output at regular (predetermined) timing. Specifically, the gate output determination unit 71 determines whether the gate signal Gout_A in the 240th row is output 240 lines (240 horizontal scanning periods) after GSP_A is output, and whether the gate signal Gout_A is GSP_A Whether the signal is output at a timing not later than 240 lines after output is determined by monitoring the gate line 12a in the 240th row for each horizontal scanning period using a detection pulse as a trigger. When the gate output determination unit 71 determines that the gate signal Gout_A on the 240th row is not output at the normal timing, it determines that the first gate driver 30a has failed, and the control unit 70 determines the gate driver switching signal SW_A. Is switched from the Hi level to the Lo level (description of FIG. 5 described later).

  In FIG. 4, since the gate signal Gout_A on the 240th row is output at a regular timing (after 240 lines (240 horizontal scanning periods)) (circled portion in FIG. 4), the first gate driver 30a is normal. The gate driver switching signal SW_A is maintained at the Hi level, and the error flag A is maintained at the Lo level.

  Thereby, in the next frame, GSP_A is input again from the control unit 70 to the first gate driver 30a, and the same processing as described above is repeated. That is, in FIG. 4, since the first gate driver 30a has no malfunction, the first gate driver 30a is not switched to the third gate driver 40a, and the gate lines G1 to G240 are driven by the first gate driver 30a. Is repeated. At this time, in the third gate driver 40a, all the various signals that are input and output are maintained at the Lo level (not shown). Since the error flags A and C input to the notification unit 80 are both at the Lo level, for example, an LED lamp (first Main) and an LED lamp that display the operating states of the first and third gate drivers 30a and 40a. (First Sub) is in a “green lighting” state indicating a normal state.

  Here, the control unit 70 performs the determination process by the gate output determination unit 71 and gives an operation instruction to the second gate driver 30b. Specifically, the control unit 70 outputs GSP_B to the second gate driver 30b 240 lines (240 horizontal scanning periods) after outputting GSP_A to the first gate driver 30a. Thereby, the driving (scanning) of the second gate driver 30b is started regardless of whether or not the first gate driver 30a is broken. That is, when GSP_B is input from the control unit 70 to the second gate driver 30b, the first-stage (first stage) shift register B1 (FIG. 3) is set. In this state, when a Hi pulse is input to the terminal cka of the first-stage shift register B1 (that is, GCK becomes Hi level), the gate signal G241 is output. The gate signal G241 sets the shift register B2 at the next stage (second stage), and a Hi pulse is input to the terminal cka of the shift register B2 (that is, GCKB becomes Hi level), whereby the gate signal G242 is set. Is output. Thereafter, the output pulse (gate signal) is sequentially shifted, and the pulse is output up to the final stage (480th stage). The gate signal G480 of the 480th stage is output to the gate line 12a of the last row and also input to the shift register B241 corresponding to the dummy line 12x. From the shift register B241, the gate signal G481 (Gout_B ) Is output and input to the control unit 70.

  Here, the gate output determination unit 71 of the control unit 70 similarly determines whether or not the gate signal is output at regular (predetermined) timing. Specifically, the gate output determination unit 71 determines whether the gate signal G481 in the 481st row is output 241 lines (241 horizontal scanning periods) after the GSP_B is output, and whether the gate signal G481 is the GSP_B Whether the signal is output at a timing not later than 241 lines after output is determined by monitoring the dummy line 12x in the 481st row for each horizontal scanning period using a detection pulse as a trigger. When the gate output determination unit 71 determines that the gate signal Gout_B of the 481st row is not output at the normal timing, it determines that the second gate driver 30b is out of order, and the control unit 70 determines the gate driver switching signal SW_B. Is switched from the Hi level to the Lo level (description of FIG. 6 described later).

  In FIG. 4, since the gate signal G481 in the 481st row is output at regular timing (after 241 lines (241 horizontal scanning period)) (circled portion in FIG. 4), the second gate driver 30b is normal. The gate driver switching signal SW_B is maintained at the Hi level, and the error flag B is maintained at the Lo level.

  Thereby, in the next frame, GSP_B is input again from the control unit 70 to the second gate driver 30b, and the same processing as described above is repeated. That is, in FIG. 4, since the second gate driver 30 b is not defective, the second gate driver 30 b is not switched to the fourth gate driver 40 b, and the gate lines G241 to G480 are driven by the second gate driver 30 b. Is repeated. At this time, in the fourth gate driver 40b, all the various signals that are input and output are maintained at the Lo level (not shown). Since the error flags B and D input to the notification unit 80 are both at the Lo level, for example, an LED lamp (second Main) and an LED lamp that display the operating states of the second and fourth gate drivers 30b and 40b. (Second Sub) is in a “green lighting” state indicating a normal state.

(Operation example 2 of the liquid crystal display device 1)
Next, a case where the first (main) gate driver 30a fails while using the liquid crystal display device 1 will be described. In FIG. 5, the shift register A239 (FIG. 3) fails (for example, the shift operation is not performed normally), the 239th stage gate signal G239 is not output, and the 240th stage gate signal G240 is at the normal timing. Is not output (circled dotted line portion in FIG. 5). For convenience of explanation, it is assumed that the failure has occurred in the first frame.

  In this case, since the gate signal G240 (Gout_A) of the 240th row is not input to the gate output determination unit 71 at a regular timing (240 lines (240 horizontal scanning periods) after the GSP_A is output), The gate output determination unit 71 determines that the first gate driver 30a has failed. Upon receiving this determination result, the control unit 70 switches the gate driver switching signal SW_A from the Hi level to the Lo level, and switches the gate driver switching signal SW_C from the Lo level to the Hi level. Thereby, the first changeover switch unit 50a is turned off, the first gate driver 30a is switched from the active state to the inactive state, the operation of the first gate driver 30a is stopped, and the third changeover switch unit 60a is turned on. Thus, the third gate driver 40a is switched from the inactive state to the active state. As a result, in the next frame (second frame), the third gate driver 40a drives the gate lines G1 to G240.

  Further, the error flag A is switched from the Lo level to the Hi level in synchronization with the timing at which the gate driver switching signal SW_A is switched from the Hi level to the Lo level. Thereby, the notification unit 80 notifies the outside of the message notifying that the first gate driver 30a has failed. For example, the LED lamp (first Main) that displays the state of the first gate driver 30a is switched from “green lighting” indicating a normal state to “red lighting” indicating an abnormal state. Thereby, the user can recognize that the first gate driver 30a has failed.

  On the other hand, the control unit 70 performs the determination process and the switching process, and outputs GSP_B to the second gate driver 30b. In FIG. 5, since the second gate driver 30b has not failed, the normal operation shown in FIG. 4 is performed.

  Subsequently, the control unit 70 outputs GSP_C to the third gate driver 40a in synchronization with the start timing of the second frame. When GSP_C is input from the control unit 70 to the third gate driver 40a, the first-stage (first stage) shift register C1 (FIG. 3) is set. In this state, when a Hi pulse is input to the terminal cka of the first-stage shift register C1 (that is, GCK becomes Hi level), the gate signal G1 is output. The gate signal G1 sets the shift register C2 in the next stage (second stage), and a Hi pulse is input to the terminal cka of the shift register C2 (that is, GCKB becomes Hi level), whereby the gate signal G2 Is output. Similarly, output pulses (gate signals) are sequentially shifted and input to the final stage (240th stage) shift register C240. The gate signal G240 output from the shift register C240 is input to the gate line 12a at the final stage and input to the control unit 70.

  The gate output determination unit 71 of the control unit 70 determines whether or not the gate signal is output at regular (predetermined) timing. Specifically, the gate output determination unit 71 determines whether the gate signal G240 of the 240th row is output 240 lines (240 horizontal scanning periods) after the GSP_C is output, and the gate signal G240 indicates that the GSP_C is Whether the signal is output at a timing not later than 240 lines after output is determined by monitoring the gate line 12a in the 240th row for each horizontal scanning period using a detection pulse as a trigger. When the gate output determination unit 71 determines that the gate signal Gout_C on the 240th row is not output at the regular timing, it is determined that the third gate driver 40a has failed, and the control unit 70 determines the gate driver switching signal SW_C. Is switched from the Hi level to the Lo level (description of FIG. 7 described later).

  In FIG. 5, since the gate signal Gout_C in the 240th row is output at a normal timing (after 240 lines (240 horizontal scanning periods)), the third gate driver 40a is determined to be normal, and the gate driver switching signal SW_C Is maintained at the Hi level, and the error flag C is maintained at the Lo level.

  As a result, in the next frame (third frame), GSP_C is again input from the control unit 70 to the third gate driver 40a, and the same processing as described above is repeated. At this time, in the first gate driver 30a, various signals (GSP_A, SW_A) to be input and output are maintained at the Lo level. Note that the error flag A input to the notification unit 80 is at the Hi level, and the error flags B and C are at the Lo level. For example, the LED lamp (first Main) indicating the state of the first gate driver 30a is abnormal. The LED lamps (second main, first sub) indicating the operating state of the second and third gate drivers 30b and 40a are in a "green lighting" state indicating a normal state.

  On the other hand, the control unit 70 performs the determination process and the switching process, and gives an operation instruction to the second gate driver 30b. Specifically, the control unit 70 outputs GSP_B to the second gate driver 30b 240 lines (240 horizontal scanning periods) after outputting GSP_C to the third gate driver 40a. Thus, in the second frame, the gate lines G241 to 480 are driven (scanned) by the second gate driver 30b following the previous frame (first frame) regardless of whether or not the third gate driver 40a has failed. )

  Thus, in the configuration of FIG. 5, when the first gate driver 30a fails in the first frame, the gate lines G1 to G240 are driven by the third gate driver 40a in the second and subsequent frames, while the gate lines G241 to G480 are driven by the second gate driver 30b. When the second gate driver 30b fails in the first frame, the gate lines G1 to G240 are driven by the first gate driver 30a, while the gate lines G241 to G480 are driven after the second frame. It is driven by the fourth gate driver 40b. This state is shown in FIG. The operation content of FIG. 6 is the same as that of FIG.

(Operation example 3 of the liquid crystal display device 1)
Next, while using the liquid crystal display device 1 in FIG. 5 (that is, the first (main) gate driver 30a is stopped and the third (sub) gate driver 40a is driven), the third (sub) The case where the gate driver 40a fails will be described. In FIG. 7, a certain shift register A239 (FIG. 3) fails (for example, the shift operation is not performed normally), the 239th stage gate signal G239 is not output, and the 240th stage gate signal G240 is normal. The state where it is not output at the timing is shown (circled dotted line portion in FIG. 7). For convenience of explanation, it is assumed that the above failure has occurred in the second frame.

  In this case, the 240th stage gate signal G240 (Gout_C) is not input to the gate output determination unit 71 at a regular timing (240 lines (240 horizontal scanning periods) after the GSP_C is output). The gate output determination unit 71 determines that the third gate driver 40a has failed. Upon receiving this determination result, the control unit 70 switches the gate driver switching signal SW_C from the Hi level to the Lo level. As a result, the third changeover switch portion 60a is turned off, the third gate driver 40a is switched from the active state to the inactive state, and the operation of the third gate driver 40a is stopped. As a result, in the next frame (third frame), both the first and third gate drivers 30a and 40a are stopped, and the gate lines G1 to G240 are in an indefinite state.

  Further, the error flag C switches from the Lo level to the Hi level in synchronization with the timing at which the gate driver switching signal SW_C switches from the Hi level to the Lo level. Thereby, the notification unit 80 notifies the outside of the message notifying that the third gate driver 40a has failed. For example, the LED lamp (first sub) that displays the state of the third gate driver 40a switches from “green light” indicating a normal state to “red light” indicating an abnormal state. Thereby, the user can recognize that the third gate driver 40a has failed.

  On the other hand, the control unit 70 performs the determination process and the switching process, and outputs GSP_B to the second gate driver 30b. In FIG. 7, since no failure has occurred in the second gate driver 30b, the normal operation shown in FIG. 4 is performed.

  Subsequently, in the third frame, the control unit 70 does not output GSP_C at the start timing of the third frame, and outputs GSP_B after 240 lines (240 horizontal scanning periods). At this time, the control unit 70 supplies the message data stored in the memory unit 76 to the source driver 20. The content of the message is a content that warns the user that a failure has occurred in the liquid crystal display device 1 and may further include a contact information of the service center. These messages are registered in advance in the memory unit 76, and can be added or modified as necessary.

  Thus, in the third frame, nothing is displayed on the upper half of the display screen corresponding to the gate lines G1 to G240, and a desired message (warning) is displayed on the lower half of the display screen corresponding to the gate lines G241 to G480. ) Is displayed.

(Operation example 4 of the liquid crystal display device 1)
Next, the liquid crystal display device 1 performing the driving of FIG. 7 (that is, the first (main) gate driver 30a and the second (main) gate driver 30b are stopped and the third (sub) gate driver 40a is driven)). The case where the third (sub) gate driver 40a and the fourth (sub) gate driver 40b fail will be described. In FIG. 8, a certain shift register Dn (not shown) breaks down (for example, the shift operation is not normally performed), the n-th stage gate signal Gn is not output, and the 481-th stage gate signal G481 (Gout_D ) Indicates a state in which it is not output at regular timing (circled dotted line portion in FIG. 8).

  In this case, since the gate signal Gout_D at the 481st stage is not input to the gate output determination unit 71 at a regular timing (after 241 lines (241 horizontal scanning periods) after the GSP_D is output), the gate output determination The unit 71 determines that the fourth gate driver 40b has failed. In response to this determination result, the control unit 70 switches the gate driver switching signal SW_D from the Hi level to the Lo level. As a result, the fourth changeover switch unit 60b is turned off, the fourth gate driver 40b is switched from the active state to the inactive state, and the operation of the fourth gate driver 40b is stopped. As a result, in the next frame, all the gate drivers are stopped, so that the gate lines G1 to G480 are in an indefinite state.

  Further, the error flag D is switched from the Lo level to the Hi level in synchronization with the timing when the gate driver switching signal SW_D is switched from the Hi level to the Lo level. Thereby, the notification unit 80 notifies the outside of the message notifying that the fourth gate driver 40b has failed. For example, the LED lamp (second Sub) indicating the state of the fourth gate driver 40b is switched from “green lighting” indicating a normal state to “red lighting” indicating an abnormal state. As a result, all the LED lamps are “lit red” and the user can recognize that all the gate drivers have failed.

  By the way, in each of the above-described configurations, the case where the gate signal Gout of the final stage (240 stage or 481 stage) is not output due to an abnormality in the shift operation of the shift register is shown. However, as another problem example, the gate signal is incorrect. There are a case where the signal is output at a timing and a case where the gate signal is output at both a normal timing and an incorrect timing. For example, FIG. 9 shows a case where the gate signal G240 (Gout_A) is output at an incorrect timing (circled portion in FIG. 9). In this regard, according to the gate output determination unit 71 of the present liquid crystal display device 1, whether the gate signal Gout_A is output 240 lines (240 horizontal scanning periods) after the GSP_A is output, and the gate signal Gout_A is: It is possible to reliably detect a failure of the gate driver because it is determined whether the signal is not output at a timing not later than 240 lines after the output of GSP_A.

  Further, in order to increase the detection accuracy, the period of the detection pulse may be shortened. Specifically, one pulse (rise) (such as FIG. 4) may be performed twice or more in one horizontal scanning period. Thereby, for example, an abnormal pulse with a short pulse width can be detected.

  In addition, the gate output determination unit 71 may determine that each gate driver is faulty when the number of times that it is determined that the gate signal is abnormal reaches a plurality of times continuously. Specifically, the control unit 70 measures the number of times that the gate output determination unit 71 determines that the output timing of the gate signal output from the gate driver is abnormal (measurement means) 73 (FIG. 1). And the gate output determination unit 71 can determine that the gate driver has failed when the number of abnormal determinations of the gate signal by the counter unit 73 reaches a predetermined number (multiple times). .

  Further, in the above embodiment, for the second gate driver 30b and the fourth gate driver 40b, the gate signals Gout_B · Gout_D that are input to (return to) the gate output determination unit 71 from the gate driver and are subjected to abnormality detection are as follows: Although the gate signal G481 of the next stage (481st stage, dummy line 12x) of the final stage gate line 12a contributing to display is used, the present invention is not limited to this and may be the final stage gate signal G480. Alternatively, the gate signal Gout at each stage may be sequentially input to the gate output determination unit 71 to determine whether the gate signal Gout is abnormal for each stage.

  Further, in the above embodiment, for the second gate driver 30b and the fourth gate driver 40b, the gate output determination unit 71 determines that the gate signal G481 is 281 lines (281 horizontal scanning period) after the GSP_B (GSP_D) is output. Although it is determined whether it is output later and whether the gate signal G481 is not output after 281 lines after GSP_B (GSP_D) is output, it is not limited to this. For example, when the period from when GSP_B (GSP_D) is output to when the gate signal G241 is output is not one horizontal scanning period, the gate output determination unit 71 outputs the gate signal G481 and the gate signal G1. Output after 240 lines (240 horizontal scanning period) from the start of scanning, and the gate signal G481 is output at a timing not 280 lines after the gate signal G1 is output (from the start of scanning). It is preferable to adopt a configuration for determining whether or not it is performed.

(Operation flow 1 of the liquid crystal display device 1)
Here, a flowchart corresponding to the above operation example of the liquid crystal display device 1 is shown in FIG. FIG. 10 shows an operation flow for detecting an abnormality in the first gate driver 30a and the third gate driver 40a, and FIG. 11 shows an operation flow for detecting a failure in the second gate driver 30b and the fourth gate driver 40b. Yes.

  As shown in FIG. 10, first, in step S1, the control unit 70 outputs a gate start pulse GSP_A and clocks GCK, GCKB, and CLR. The output waveform is as shown in FIG. In step S1, the Hi level of the gate driver switching signal SW_A and the Lo level of the gate driver switching signal SW_C are output. At this time, the Lo level is output for the gate start pulse GSP_C and the error flags A and C.

  Next, in step S2, the gate output determination unit 71 determines whether the gate signal Gout_A is output at a normal position (timing) and whether the gate signal Gout_A is not output at a position other than the normal position. (Judgment step).

  If YES in step S2, that is, if the gate signal Gout_A is output at a normal position (timing) and not output at a position other than the normal position, the first gate driver 30a is normal. It returns to step S1 and normal operation is repeated in the first gate driver 30a.

  On the other hand, if NO in step S2, that is, if the gate signal Gout_A is not output at the normal position (timing), or is output at a position that is not the normal position, or at the normal position. If it is output at another position even though it is output, it is determined that the first gate driver 30a has failed, and the process proceeds to the next step S3.

  In step S3, based on the determination result of the gate output determination unit 71 (failure of the first gate driver 30a), the control unit 70 switches the gate driver switching signal SW_A to Lo level and sets the gate driver switching signal SW_C to Hi level. Switch. Further, the gate start pulse GSP_A is switched to the Lo level, and the gate start pulse GSP_C is switched to the output mode (see FIG. 5).

  Further, the error flag A is switched to the Hi level. For the error flag C, the Lo level is maintained. As a result, the first gate driver 30a stops and the third gate driver 40a starts driving. At the same time, the failure of the first gate driver 30a is notified to the outside.

  Next, in step S4, as in the process of step S2, in the third gate driver 40a, the gate output determination unit 71 monitors the output timing of the gate signal Gout_C and determines the state of the third gate driver 40a.

  If YES in step S4, that is, if the gate signal Gout_C is output at a normal position (timing) and not output at a position other than the normal position, the third gate driver 40a is normal. It returns to step S3 and the normal operation | movement by the 3rd gate driver 40a is repeated.

  On the other hand, in the case of NO in step S4, that is, when the gate signal Gout_C is not output at the regular position (timing), or is output at a position that is not the regular position, or at the regular position. If it is output at another position even though it is output, it is determined that the third gate driver 40a has failed, and the process proceeds to the next step S5.

  In step S5, the control unit 70 switches the gate driver switching signal SW_C to the Lo level based on the determination result of the gate output determination unit 71 (failure of the third gate driver 40a). Further, the gate start pulse GSP_C is switched to the Lo level. Further, the error flag C is switched to the Hi level. As a result, in addition to the first gate driver 30a, the operation of the third gate driver 40a is also stopped. Then, the failure of the first and third gate drivers 30a and 40a is notified to the outside. In this case, a warning display (see FIG. 7) is displayed on the upper half of the display screen.

  Next, in step S6, it is determined whether both error flags B and D are ON (Hi level). If YES in step S6, that is, if both of the error flags B and D are at the Hi level, it is determined that all of the first to fourth gate drivers 30a, 30b, 40a, and 40b have failed. Then, the function of the liquid crystal display device 1 is stopped (step S7) (see FIG. 8).

  On the other hand, if NO in step S6, that is, if at least one of the error flags B and D is at the Lo level, at least one of the second and fourth gate drivers 30b and 40b is normal. Determination is made, the process returns to step S5, and the warning display is repeated (see FIG. 7).

(Operation flow 2 of the liquid crystal display device 1)
The contents of each process in the above-described operation example are the same for the operation example (FIG. 11) for detecting a failure of the second gate driver 30b and the fourth gate driver 40b.

  As shown in FIG. 11, first, in step S11, the control unit 70 outputs a gate start pulse GSP_B and clocks GCK, GCKB, and CLR. The output waveform is as shown in FIG. In step S11, the Hi level of the gate driver switching signal SW_B and the Lo level of the gate driver switching signal SW_D are output. At this time, the Lo level is output for the gate start pulse GSP_D and the error flags B and D.

  Next, in step S12, the gate output determination unit 71 determines whether the gate signal Gout_B is output at a normal position (timing) and whether the gate signal Gout_B is not output at a position other than the normal position. To do.

  If YES in step S12, that is, if the gate signal Gout_B is output at a normal position (timing) and not output at a position other than the normal position, the second gate driver 30b is normal. It returns to step S11 and normal operation is repeated in the second gate driver 30b.

  On the other hand, if NO in step S12, that is, if the gate signal Gout_B is not output at the normal position (timing), or is output at a position that is not the normal position, or at the normal position. If it is output at another position even though it is output, it is determined that the second gate driver 30b is out of order, and the process proceeds to the next step S13.

  In step S13, based on the determination result of the gate output determination unit 71 (failure of the second gate driver 30b), the control unit 70 switches the gate driver switching signal SW_B to Lo level and sets the gate driver switching signal SW_D to Hi level. Switch. Further, the gate start pulse GSP_B is switched to the Lo level, and the gate start pulse GSP_D is switched to the output mode (see FIG. 6).

  Further, the error flag B is switched to the Hi level. For the error flag D, the Lo level is maintained. As a result, the second gate driver 30b stops and the fourth gate driver 40b starts driving. At the same time, the failure of the second gate driver 30b is notified to the outside.

  Next, in step S14, as in the process of step S12, in the fourth gate driver 40b, the gate output determination unit 71 monitors the output timing of the gate signal Gout_D and determines the state of the fourth gate driver 40b.

  If YES in step S14, that is, if the gate signal Gout_D is output at a normal position (timing) and not output at a position other than the normal position, the fourth gate driver 40b is normal. It returns to step S13 and the normal operation | movement by the 4th gate driver 40b is repeated.

  On the other hand, in the case of NO in step S14, that is, when the gate signal Gout_D is not output at the regular position (timing), or is output at a position that is not the regular position, or at the regular position. If it is output at another position even though it is output, it is determined that the fourth gate driver 40b is out of order, and the process proceeds to the next step S15.

  In step S15, based on the determination result of the gate output determination unit 71 (failure of the fourth gate driver 40b), the control unit 70 switches the gate driver switching signal SW_D to the Lo level. Further, the gate start pulse GSP_D is switched to the Lo level. Further, the error flag D is switched to the Hi level. As a result, in addition to the second gate driver 30b, the operation of the fourth gate driver 40b is also stopped. Then, the failure of the second and fourth gate drivers 30b and 40b is notified to the outside. In this case, a warning is displayed on the lower half of the display screen.

  Next, in step S16, it is determined whether both error flags A and C are ON (Hi level). If YES in step S16, that is, if both error flags A and C are at the Hi level, it is determined that all of the first to fourth gate drivers 30a, 30b, 40a, and 40b have failed. Then, the function of the liquid crystal display device 1 is stopped (step S17) (see FIG. 8).

  On the other hand, if NO in step S16, that is, if at least one of the error flags A and C is at the Lo level, at least one of the second and fourth gate drivers 30b and 40b is normal. Determination is made, the process returns to step S15, and the warning display is repeated.

  As described above, in the liquid crystal display device 1 according to the present embodiment, all the gate lines have a plurality of groups (two groups in FIGS. 1 and 3: gate lines 12a (G1 to G240) and gate lines 12b (G241 to G241). G480)), and gate drivers (gate drivers 30a and 30b) are individually provided corresponding to each set. As a result, even if any of the gate drivers (for example, the gate driver 30a) fails, the corresponding gate line (for example, the gate line 12b (G241 to G480)) is set by the normal gate driver (for example, the gate driver 30b). The display function does not stop suddenly. Therefore, it is possible to avoid the problem that nothing is displayed on the display screen during use by the user. In addition, when one gate driver fails, a message indicating the failure is displayed on a part of the display screen due to the operation of the other gate driver, so the user recognizes the cause of the failure (display failure), etc. can do.

  In order to obtain such an effect, the present liquid crystal display device only needs to include at least one gate driver for each of the divided sets as shown in FIG.

  In addition, since the liquid crystal display device shown in FIG. 1 includes two gate drivers for each of the divided groups, for example, when the first (main) gate driver 30a fails, Since switching to the 3 (sub) gate driver 40a (redundant circuit), the operation can be continued without stopping the display function. Therefore, it is possible to save the trouble of switching to the redundant circuit at the time of manufacture, and it is possible to extend the product life when used by the user.

  Further, by setting the signal related to the other driver to the Lo level while one driver is operating, it is possible to obtain an effect that the shift of Vth in the other driver can be suppressed.

  Incidentally, in the configuration of the liquid crystal display device 1, as described above, when either the upper half or the lower half of the display screen cannot be displayed, that is, for example, the first gate driver 30a and the third gate driver 40a. Is broken and the upper half of the display screen cannot be displayed (see FIG. 7), a warning is displayed in the lower half of the display screen, which is the displayable area. However, in this case, in the non-displayable area (here, the upper half of the display screen), there is a problem that noise is generated because the state is indefinite. Therefore, in order to avoid the generation of this noise, the liquid crystal display device may be configured as shown in FIG.

  In the liquid crystal display device 1 ′ shown in FIG. 13, the fixed signal ERR is input from the control unit 70 to each gate driver in the liquid crystal display device 1 of FIG. 1. Below, it demonstrates centering on difference with the liquid crystal display device 1 of FIG.

  FIG. 14 is a block diagram showing the configuration of the gate driver in the liquid crystal display device 1 ′ of FIG. The fixed signals ERR_H1, ERR_L1 are simultaneously input from the control circuit 70 to the shift registers A1, A2,... Constituting the gate driver 30a, and from the control circuit 70 to the shift registers B1, B2,. The fixed signals ERR_H2 and ERR_L2 are simultaneously input, and the shift signals C1, C2,... Constituting the gate driver 40a are simultaneously input with the fixed signals ERR_H1 and ERR_L1 from the control circuit 70. ... The fixed signals ERR_H2 and ERR_L2 are simultaneously input from the control circuit 70 to D2.

  FIG. 15 is a circuit diagram showing a configuration of the shift register. The shift register is further provided with a transistor O and a transistor P in the configuration of the shift register of FIG. In the transistor O, one end of the conduction electrode is connected to the output Gout, the other end is connected to the input of the fixed signal ERR_H, and the input is connected to the control electrode. In the transistor P, one end of the conduction electrode is connected to the output Gout, the other end is connected to VSS, and the control electrode is connected to the input of the fixed signal ERR_L. Thus, when a fixed signal ERR_H (Hi level) is input to the shift register, a Hi level signal is output from the shift register, and when a fixed signal ERR_L (Hi level) is input to the shift register, VSS is output from the shift register. A level signal is output.

  In the liquid crystal display device 1 ′, when the first (main) gate driver 30a and the second (main) gate driver 30b are operating normally, the operation is the same as that shown in FIG. Description is omitted. In this case, the fixed signals ERR_H and ERR_L are both at the Lo level. FIG. 16 shows that the first (main) gate driver 30a is stopped and the third (sub) gate driver 40a fails while the liquid crystal display device 1 'driven by the third (sub) gate driver 40a is in use. It is a timing chart which shows the various signals at the time of doing.

  In FIG. 16, a certain shift register C239 (FIG. 14) fails (for example, the shift operation is not performed normally), the 239th stage gate signal G239 is not output, and the 240th stage gate signal G240 is normal. The state where it is not output at the timing is shown (circled dotted line portion in FIG. 16). For convenience of explanation, it is assumed that the above failure has occurred in the second frame.

  In this case, since the gate signal G240 (Gout_C) of the 240th row is not input to the gate output determination unit 71 at a normal timing (240 lines (240 horizontal scanning periods) after the GSP_C is output), The gate output determination unit 71 determines that the third gate driver 40a has failed. Upon receiving this determination result, the control unit 70 switches the gate driver switching signal SW_C from the Hi level to the Lo level. As a result, the third changeover switch portion 60a is turned off, the third gate driver 40a is switched from the active state to the inactive state, and the operation of the third gate driver 40a is stopped. As a result, in the next frame (third frame), both the first and third gate drivers 30a and 40a are stopped, and the gate lines G1 to G240 are in an indefinite state.

  Further, the error flag C is switched from the Lo level to the Hi level in synchronization with the timing at which the gate driver switching signal SW_C is switched from the Hi level to the Lo level. Thereby, the notification unit 80 notifies the outside of the message notifying that the third gate driver 40a has failed. For example, the LED lamp (first sub) that displays the state of the third gate driver 40a switches from “green light” indicating a normal state to “red light” indicating an abnormal state. Thereby, the user can recognize that the third gate driver 40a has failed.

  On the other hand, the control unit 70 performs the determination process and the switching process, and outputs GSP_B to the second gate driver 30b. In FIG. 16, since the second gate driver 30b has not failed, a normal operation is performed.

  Subsequently, in the third frame, the control unit 70 switches the gate driver switching signal SW_A (or the gate driver switching signal SW_C) from the Lo level to the Hi level at the start timing of the third frame, and outputs the fixed signal ERR_H1 ( (Switch from Lo level to Hi level). As a result, Hi level signals are output from the shift registers A1 to A240 (or C1 to C240), and the gate lines G1 to G240 are activated. Thereafter, based on the gate start pulse GSP_B, the fixed signal ERR_H1 is switched to the Lo level, and the fixed signal ERR_L1 is switched to the Hi level. Here, while each of the gate lines G1 to G240 is in the active state, the control unit 70 supplies the black display data stored in the memory unit 76 to the source driver 20, so that the upper half of the display screen in the frame is displayed. Black display.

  In the lower half of the display screen, as shown in FIG. 7, the control unit 70 supplies the message data stored in the memory unit 76 to the source driver 20, thereby displaying a desired message (warning). Done.

  Here, the first (main) gate driver 30a, the second (main) gate driver 30b, and the third (sub) gate driver 40a are stopped, and only the fourth (sub) gate driver 40b is driven. A case where the fourth (sub) gate driver 40b fails in 1 ′ will be described. In FIG. 17, a certain shift register Dn (not shown) breaks down (for example, the shift operation is not normally performed), the n-th stage gate signal Gn is not output, and the 481-th stage gate signal G481 (Gout_D ) Indicates a state in which it is not output at regular timing (circled dotted line portion in FIG. 17).

  In this case, since the gate signal G481 (Gout_D) in the 481st row is not input to the gate output determination unit 71 at a regular timing (after 241 lines (241 horizontal scanning periods) after the GSP_D is output), The gate output determination unit 71 determines that the fourth gate driver 40b is out of order. In response to this determination result, the control unit 70 switches the gate driver switching signal SW_D from the Hi level to the Lo level. As a result, the fourth changeover switch unit 60b is turned off, the fourth gate driver 40b is switched from the active state to the inactive state, and the operation of the fourth gate driver 40b is stopped. As a result, in the next frame (third frame), the second and fourth gate drivers 30b and 40b are both stopped, and the gate lines G241 to G481 are in an indefinite state.

  Further, the error flag D is switched from the Lo level to the Hi level in synchronization with the timing at which the gate driver switching signal SW_D is switched from the Hi level to the Lo level. Thereby, the notification unit 80 notifies the outside of the message notifying that the fourth gate driver 40b has failed. For example, the LED lamp (second Sub) indicating the state of the fourth gate driver 40b is switched from “green lighting” indicating a normal state to “red lighting” indicating an abnormal state. Thereby, the user can recognize that the fourth gate driver 40b has failed.

  Subsequently, in the third frame, the control unit 70 switches the gate driver switching signal SW_B (or the gate driver switching signal SW_D) from the Lo level to the Hi level at the start timing of the third frame, and outputs the fixed signal ERR_H2 ( (Switch from Lo level to Hi level). As a result, Hi level signals are output from the shift registers B1 to B241 (or D1 to D241), and the gate lines G241 to G481 are activated. Note that the gate lines G1 to G240 are already in an active state. As a result, in the subsequent frames, the control unit 70 supplies the black display data stored in the memory unit 76 to the source driver 20 so that the entire display screen is displayed in black.

(Operation flow 1 of the liquid crystal display device 1 ')
Next, a flowchart corresponding to the above operation example of the liquid crystal display device 1 'is shown in FIG. 18 shows an operation flow for detecting an abnormality in the first gate driver 30a and the third gate driver 40a, and FIG. 19 shows an operation flow for detecting a failure in the second gate driver 30b and the fourth gate driver 40b. Yes.

  As shown in FIG. 18, first, in step S21, the control unit 70 outputs a gate start pulse GSP_A and clocks GCK, GCKB, and CLR. The output waveform is as shown in FIG. In step S21, the Hi level of the gate driver switching signal SW_A and the Lo level of the gate driver switching signal SW_C are output. At this time, the Lo level is output for the gate start pulse GSP_C, the error flags A and C, and the fixed signals ERR_H1 and ERR_L. Since the processing up to step S24 is the same as the processing of steps S1 to S4 shown in FIG.

  In step S24, in the third gate driver 40a, the gate output determination unit 71 monitors the output timing of the gate signal Gout_C and determines the state of the third gate driver 40a.

  If YES in step S24, that is, if the gate signal Gout_C is output at a normal position (timing) and not output at a position that is not a normal position, the third gate driver 40a is normal. It returns to step S23, and the normal operation | movement by the 3rd gate driver 40a is repeated.

  On the other hand, in the case of NO in step S24, that is, when the gate signal Gout_C is not output at the regular position (timing), or is output at a position that is not the regular position, or at the regular position. If it is output at another position even though it is output, it is determined that the third gate driver 40a is out of order, and the process proceeds to the next step S25.

  In step S25, based on the determination result of the gate output determination unit 71 (failure of the third gate driver 40a), the control unit 70 switches the gate driver switching signal SW_C to the Lo level. Further, the gate start pulse GSP_C is switched to the Lo level. Further, the error flag C is switched to the Hi level. As a result, in addition to the first gate driver 30a, the operation of the third gate driver 40a is also stopped. Then, the failure of the first and third gate drivers 30a and 40a is notified to the outside. Thereafter, the gate driver switching signal SW_A (or SW_C) is switched to the Hi level again at the start timing of the next frame, and the ERR_H1 is switched from the Lo level to the Hi level. Accordingly, a warning is displayed on the upper half of the display screen, while black is displayed on the lower half of the display screen (see FIG. 16). In the selection period of the gate lines G241 to G481, it is preferable to perform AC control of the corresponding shift register by switching ERR_H1 to Lo level and switching ERR_L1 to Hi level.

  Next, in step S26, it is determined whether both error flags B and D are at the Hi level. If YES in step S26, that is, if both error flags B and D are at the Hi level, it is determined that all of the first to fourth gate drivers 30a, 30b, 40a, and 40b have failed. Then, the function of the liquid crystal display device is stopped (step S27). Further, the gate driver switching signals SW_A (or SW_C) and SW_B (or SW_D) are switched to the Hi level, the Hi levels of the fixed signals ERR_H1 and ERR_H2 are output, and all the gate outputs are set to the Hi level. Alternatively, the Hi level of the fixed signals ERR_L1 and ERR_L2 is output, and all the gate outputs are set to the Lo level.

  On the other hand, if NO in step S26, that is, if at least one of the error flags B and D is at the Lo level, at least one of the second and fourth gate drivers 30b and 40b is normal. The determination is made, the process returns to step S25, and the warning display is repeated.

(Operation flow 2 of the liquid crystal display device 1 ')
The contents of each process in the above-described operation example are the same for the operation example (FIG. 19) for detecting a failure of the second gate driver 30b and the fourth gate driver 40b. The processing from step S31 to S34 in FIG. 19 is the same as the processing from step S11 to S14 shown in FIG.

  In step S34, in the fourth gate driver 40b, the gate output determination unit 71 monitors the output timing of the gate signal Gout_D to determine the state of the fourth gate driver 40b.

  If YES in step S34, that is, if the gate signal Gout_D is output at a normal position (timing) and not output at a position other than the normal position, the fourth gate driver 40b is normal. It returns to step S33 and the normal operation | movement by the 4th gate driver 40b is repeated.

  On the other hand, in the case of NO in step S34, that is, when the gate signal Gout_D is not output at the regular position (timing), or is output at a position that is not the regular position, or at the regular position. If it is output at another position even though it is output, it is determined that the fourth gate driver 40b is out of order, and the process proceeds to the next step S35.

  In step S35, based on the determination result of the gate output determination unit 71 (failure of the fourth gate driver 40b), the control unit 70 switches the gate driver switching signal SW_D to the Lo level. Further, the gate start pulse GSP_D is switched to the Lo level. Further, the error flag D is switched to the Hi level. As a result, in addition to the second gate driver 30b, the operation of the fourth gate driver 40b is also stopped. Then, the failure of the second and fourth gate drivers 30b and 40b is notified to the outside. Thereafter, the gate driver switching signal SW_B (or SW_D) is switched to the Hi level again at the start timing of the next frame, and the ERR_H2 is switched from the Lo level to the Hi level. As a result, a warning is displayed in the lower half of the display screen, while black is displayed in the upper half of the display screen. In the selection period of the gate lines G1 to G240, it is preferable to perform AC control of the corresponding shift register by switching ERR_H2 to Lo level and switching ERR_L2 to Hi level.

  Next, in step S36, it is determined whether both of the error flags A and C are at the Hi level. If YES in step S36, that is, if both error flags A and C are at the Hi level, it is determined that all of the first to fourth gate drivers 30a, 30b, 40a, and 40b have failed. Then, the function of the liquid crystal display device is stopped (step S37). Further, the gate driver switching signals SW_A (or SW_C) and SW_B (or SW_D) are switched to the Hi level, the Hi levels of the fixed signals ERR_H1 and ERR_H2 are output, and all the gate outputs are set to the Hi level. Alternatively, the Hi level of the fixed signals ERR_L1 and ERR_L2 is output, and all the gate outputs are set to the Lo level.

  On the other hand, if NO in step S36, that is, if at least one of the error flags A and C is at the Lo level, at least one of the first and third gate drivers 30a and 40a is normal. Determination is made, the process returns to step S35, and the warning display is repeated.

  As described above, according to the liquid crystal display device 1 ′ of FIG. 13, when the first and third gate drivers 30a and 40a fail or when the second and fourth gate drivers 30b and 40b fail, Since the gate lines G1 to G240 or the gate lines G241 to G481 are not in an indefinite state, generation of noise on the display screen can be suppressed. In the present liquid crystal display device 1 ', since the same fixed signal ERR_H1 / L1 is input to the first and third gate drivers 30a and 40a, the first changeover switch section 50a is used when both drivers fail. Any of the third changeover switch 60a may be turned on. Similarly, since the same fixed signal ERR_H2 / L2 is input to the second and fourth gate drivers 30b and 40b, when both drivers fail, the second changeover switch unit 50b and the fourth changeover switch unit 60b. Any of these may be turned on.

  By the way, in this embodiment, although the form which switches a gate driver was demonstrated, this invention is not limited to this, The structure which provides a source driver for every group comprised by a several source line is also provided. Can be applied. In Embodiment 2 described below, a liquid crystal display device including a plurality of gate drivers and a plurality of source drivers will be described.

[Embodiment 2]
The liquid crystal display device of the present invention is not limited to the monolithic circuit shown in the first embodiment, and may be a liquid crystal display device including a gate chip driver and a source chip driver. In the second embodiment, the liquid crystal display device will be described with reference to FIGS. For convenience of explanation, members having the same functions as those shown in Embodiment 1 are given the same reference numerals, and explanation thereof is omitted. The terms defined in Embodiment 1 are used in accordance with the definitions in this embodiment unless otherwise specified.

  FIG. 20 is a block diagram showing the overall configuration of the liquid crystal display device 2. The liquid crystal display device 2 includes an active matrix liquid crystal display panel 10, a first source driver 21, a second source driver 22, a third source driver 23, a fourth source driver 24, a first gate driver 31, and a second gate driver 32. , A third gate driver 33, a fourth gate driver 34, a control unit 70, and a notification unit 80.

  The first source driver 21 and the third source driver 23 are configured as a pair via the same source line, and the second source driver 22 and the fourth source driver 24 are paired via the same source line. Each source line (11) is configured as a set of a plurality of adjacent adjacent lines. That is, the first source driver 21 is connected to one end of the set of source lines 11a and the third source driver 23 is connected to the other end, and the second source driver 22 is connected to one end of the set of source lines 11b. And the fourth source driver 24 is connected to the other end.

  The first gate driver 31 and the third gate driver 33 are configured as a pair via the same gate line, and the second gate driver 32 and the fourth gate driver 34 are paired via the same gate line. Each gate line (12) is configured as a set of a plurality of adjacent adjacent lines. That is, the first gate driver 31 is connected to one end of the set of gate lines 12a, and the third gate driver 33 is connected to the other end, and the second gate driver 32 is connected to one end of the set of gate lines 12b. And the fourth gate driver 34 is connected to the other end.

  As described above, the first source driver 21 and the third source driver 23 have the same function, and are connected to the same source line 11a, and the second source driver 22 and the fourth source driver 24 are mutually connected. Each has the same function and is connected to the same source line 11b. That is, the first source driver 21 and the third source driver 23 are arranged in pairs via the same signal line (source line 11a), and are configured to have redundancy. Similarly, the second source driver 22 and the fourth source driver 24 are arranged in pairs via the same signal line (source line 11b), and are configured to have redundancy.

  The first gate driver 31 and the third gate driver 33 have the same function, and are connected to the same gate line 12a. The second gate driver 32 and the fourth gate driver 34 are the same. Each of them has a function and is connected to the same gate line 12b. That is, the first gate driver 31 and the third gate driver 33b are arranged in pairs via the same signal line (gate line 12a) and are configured to have redundancy. Similarly, the second gate driver 32 and the fourth gate driver 34 are arranged in pairs via the same signal line (gate line 12b), and are configured to have redundancy.

  In the following description, the first source driver 21 and the second source driver 22, respectively, the main source driver 21 and the main source driver 22, the third source driver 23 and the fourth source driver 24, respectively, as the sub source driver 23 (redundant) as necessary. Circuit) Also referred to as sub-source driver 24 (redundancy circuit). The first gate driver 31 and the second gate driver 32 are respectively the main gate driver 31 and the main gate driver 32, and the third gate driver 33 and the fourth gate driver 34 are respectively the sub gate driver 33 (redundant circuit) and the sub gate driver 34 (redundant circuit). Circuit).

  The first source driver 21 is configured to include a plurality of first source chip drivers. In the present embodiment, the first source driver 21 includes three first source chip drivers 21a, 21b, and 21c. The second source driver 22 includes a plurality of second source chip drivers. In the present embodiment, the second source driver 22 includes three second source chip drivers 22a, 22b, and 22c. The third source driver 23 includes a plurality of third source chip drivers. In the present embodiment, the third source driver 23 includes three third source chip drivers 23a, 23b, and 23c. The fourth source driver 24 includes a plurality of fourth source chip drivers. In the present embodiment, the fourth source driver 24 includes three fourth source chip drivers 24a, 24b, and 24c. Each source chip driver drives a plurality of source lines individually connected thereto.

  The first gate driver 31 includes a plurality of first gate chip drivers, and in the present embodiment, includes two first gate chip drivers 31a and 31b. The second gate driver 32 includes a plurality of second gate chip drivers. In the present embodiment, the second gate driver 32 includes two second gate chip drivers 32a and 32b. The third gate driver 33 includes a plurality of third gate chip drivers. In the present embodiment, the third gate driver 33 includes two third gate chip drivers 33a and 33b. The fourth gate driver 34 includes a plurality of fourth gate chip drivers. In the present embodiment, the fourth gate driver 34 includes two fourth gate chip drivers 34a and 34b. Each gate chip driver drives a plurality of gate lines individually connected thereto.

  The control unit 70 monitors a source signal output from each source driver (first to fourth source drivers 21 to 24) in addition to a general function (not shown) for controlling the gate driver and the source driver. The source output determination unit 74 that determines whether or not the output timing is normal and the gate signals output from the gate drivers (first to fourth gate drivers 31 to 34) are monitored, and the output timing is determined. And a gate output determination unit 75 for determining whether or not it is normal. When the source output determination unit 74 determines that the output timing of the source signal is abnormal, normal display is not performed, so that it is determined that the source driver that has output the source signal has failed. When the gate output determination unit 75 determines that the output timing of the gate signal is abnormal, normal display is not performed, and thus it is determined that the gate driver that has output the gate signal is faulty.

  Further, the control unit 70 switches between the first source driver 21 and the third source driver 23 for the driver for driving the source line 11a according to the determination result of the source output determination unit 74, and switches the source line 11b. Regarding the driver for driving, the second source driver 22 and the fourth source driver 24 are switched to each other. Also, a driver for driving the gate line 12b by switching between the first gate driver 31 and the second gate driver 32 for the driver for driving the gate line 12a according to the determination result of the gate output determination unit 75. , The second gate driver 32 and the fourth gate driver 34 are switched to each other. That is, the control unit 70 also has a function as switching means for switching the main gate driver to the sub gate driver.

  In addition, the control unit 70 includes a memory unit 76 that stores message data to be displayed on the liquid crystal display panel 10 when an abnormality occurs in the source driver or the gate driver. When this message is displayed, a potential corresponding to the data is supplied to the source driver.

  Further, the control unit 70 outputs an error flag (source error flag, gate error flag) for notifying the abnormal state of each driver to the outside to the notification unit 80. The notification unit 80 has a function of notifying the user of a failure of the source driver and the gate driver, and for example, a known method such as turning on an LED lamp, displaying a message, or generating an error sound can be applied. A more detailed configuration of the control unit 70 will be described later.

(Operation example of the liquid crystal display device 2)
Next, an operation example of the liquid crystal display device 2 will be described together with a specific configuration of the control unit 70. Here, as an example, the liquid crystal display device 2 of 800 RGB × 480 (WVGA) will be described as an example.

<Switching source driver>
First, the source driver switching operation process will be described together with the specific configuration of the source output determination unit 74. FIG. 21 is a block diagram showing a schematic configuration of the first and second source drivers 21 and 22.

  As shown in FIG. 21, the first source driver 21 is configured by cascading first source chip drivers 21a, 21b, and 21c, and a source start pulse SPOI_A is sent from the control unit 70 to the first source chip driver 21a. By inputting, data sampling of the first source chip driver 21a is started. The first source chip driver 21a samples a data signal (Digital Data) corresponding to the video signal to each corresponding source line 11a and outputs the source signal SPIO to the adjacent first source chip driver 21b. When the source signal SPIO is input, the first source chip driver 21b starts data sampling, samples the data signal corresponding to the video signal to each corresponding source line 11a, and to the adjacent first source chip driver 21c. The source signal SPIO is output. When the source signal SPIO is input, the first source chip driver 21c starts data sampling, samples the data signal corresponding to the video signal to each corresponding source line 11a, and outputs the source signal SPIO_A to the control unit 70. To do. The source signal SPIO_A is input to the source output determination unit 74 of the control unit 70. The second source driver 22 is configured by cascading second source chip drivers 22 a and 22 b and has the same function as the first source driver 21.

  The control unit 70 outputs a source start pulse SPOI_B to the second source chip driver 22a at a predetermined timing. Thereby, data sampling of the second source chip driver 22a is started. Then, after the same processing as described above is performed in the second source chip drivers 22b and 22c, the second source chip driver 22c samples the data signal corresponding to the video signal to each corresponding source line 11b, The source signal SPIO_B is output to the control unit 70. The source signal SPIO_B is input to the source output determination unit 74 of the control unit 70. Here, the predetermined timing is a timing at which the data sampling process in the first source driver 21 that drives one set of source lines 11a ends.

  In FIG. 21, the sampling is performed from the left direction to the right direction in the drawing. However, the output signals SPIO and SPOI may be switched to perform sampling from the right direction to the left direction.

  Here, a case where the first (main) source driver 21 is operating normally will be described with reference to FIGS. 21 and 22. FIG. 22 is a timing chart showing various signals in the control unit 70 and the first and second source drivers 21 and 22 when the first source driver 21 is operating normally.

  First, the control unit 70 sets the source start pulse SPOI_A to the first source chip driver 21a in the output state (Hi), and sets the Lo level of the source start pulse SPOI to the second to fourth source chip drivers 22a, 23a, and 24a. Output. As a result, the first source driver 21 is activated, and the second to fourth source drivers 22, 23, and 24 are deactivated. When SPOI_A is input from the control unit 70 to the first source chip driver 21a, sampling is started based on the clock CLK. The clock CLK is determined according to the panel resolution. In the form of FIG. 20, for example, a liquid crystal display device of 800 RGB × 480 (WVGA), the source driver performs sampling for 800 clocks. That is, the first source driver 21 and the third source driver 23 perform sampling for 400 clocks to drive the 400 RGB line (source line 11a), and the second source driver 22 and the fourth source driver 24 In order to drive the line (source line 11b), sampling is performed for 400 clocks.

  The first source chip drivers 21 a, 21 b, and 21 c are sequentially driven by the source start pulse SPOI_A, and the source signal SPIO_A is output from the first source chip driver 21 c and input to the control unit 70.

  Here, the source output determination unit 74 of the control unit 70 determines whether or not the source signal is output at regular timing. Specifically, the source output determination unit 74 determines whether the source signal SPIO_A is output 400 clocks after the source start pulse SPOI_A is output, or after the source signal SPIO_A is output from the source start pulse SPOI_A. It is determined by monitoring the source signal SPIO_A for each clock whether or not it is output at a timing not after 400 clocks (FIG. 22 shows a state of monitoring at every rising edge of CLK). When the source output determination unit 74 determines that the source signal SPIO_A is not output at the normal timing, it determines that the first source driver 21 is out of order, and the control unit 70 outputs the source start pulse SPOI_A from the output state to Lo. Switching to the level (description of FIG. 24 described later).

  In FIG. 22, since the source signal SPIO_A is output at regular timing (circled portion in FIG. 22), the first source driver 21 is determined to be normal, and the source error flag A is maintained at the Lo level.

  Thereby, in the next horizontal scanning period, the source start pulse SPOI_A is input again from the control unit 70 to the first source chip driver 21a, and the same processing as described above is repeated. That is, in FIG. 22, since the first source driver 21 is not defective, the process is repeated only by the first source driver 21 without switching to the third source driver 23. At this time, in the third source driver 23, all the various signals that are input and output are maintained at the Lo level. Since the source error flags A and C input to the notification unit 80 are both at the Lo level, for example, an LED lamp (first Main) and an LED lamp for displaying the states of the first and third source drivers 21 and 23 are used. (First Sub) is in a “green lighting” state indicating a normal state.

  Here, the control unit 70 performs the determination process by the source output determination unit 74 and gives an operation instruction to the second source driver 22. Specifically, the control unit 70 outputs the source start pulse SPOI_B to the second source driver 22 400 clocks after outputting the source start pulse SPOI_A to the first source driver 21. Thereby, driving (data sampling) of the second source driver 22 is started regardless of whether or not the first source driver 21 is out of order. That is, when the source start pulse SPOI_B is input from the control unit 70 to the second source driver 22, the first source (first stage) second source chip driver 22a (FIG. 21) is set.

  Accordingly, the second source chip drivers 22a, 22b, and 22c are sequentially driven, and the source signal SPIO_B is output from the second source chip driver 22c and input to the control unit 70.

  Here, the gate output determination unit 71 of the control unit 70 similarly determines whether or not the source signal SPIO_B is output at regular (predetermined) timing. Specifically, the source output determination unit 74 determines whether the source signal SPIO_B is output 400 clocks after the source start pulse SPOI_B is output, and the source signal SPIO_B is output after the source start pulse SPOI_B is output. It is determined by monitoring the source signal SPIO_B for each clock whether or not it is output at a timing not after 400 clocks (FIG. 22 shows a state where monitoring is performed at every rising edge of CLK). When the source output determination unit 74 determines that the source signal SPIO_B is not output at the normal timing, it determines that the second source driver 22 is out of order, and the control unit 70 outputs the source start pulse SPOI_B from the output state to Lo. Switch to level.

  In FIG. 22, since the source signal SPIO_B is output at regular timing (circled portion in FIG. 22), the second source driver 22 is determined to be normal, and the source error flag B is maintained at the Lo level.

  Thereby, in the next horizontal scanning period, the source start pulse SPOI_B is input again from the control unit 70 to the second source chip driver 22a, and the same processing as described above is repeated. That is, in FIG. 22, since the second source driver 22 has no malfunction, the process is repeated only by the second source driver 22 without switching to the fourth source driver 24. At this time, in the fourth source driver 24, all the various signals inputted and outputted are maintained at the Lo level. Since the source error flags B and D input to the notification unit 80 are both at the Lo level, for example, an LED lamp (second Main) and an LED lamp for displaying the states of the second and fourth source drivers 22 and 24 are used. (Second Sub) is in a “green lighting” state indicating a normal state.

  Next, a case where the first (main) source driver 21 fails while using the liquid crystal display device 2 will be described with reference to FIGS. Here, the first source chip driver 21b fails (shaded area in FIG. 23), the source signal SPIO is not input to the first source chip driver 21c, and the source signal SPIO_A is received from the first source chip driver 21c at the final stage. It shows a state in which it is not output at regular timing (circled dotted line portion in FIG. 24).

  In this case, since the source signal SPIO_A is not input to the source output determination unit 74 at a regular timing (400 clocks after the source start pulse SPOI_A is output), the source output determination unit 74 includes the first source driver 21. It is determined that there is a failure. Then, the control unit 70 fixes the source start pulse SPOI_A at the Lo level and switches the source error flag A from the Lo level to the Hi level. As a result, the first source driver 21 is switched from the active state to the inactive state, the operation of the first source driver 21 is stopped, and a message informing that the first source driver 21 has failed is notified from the notification unit 80 to the outside. Informed. For example, the LED lamp (first Main) that displays the state of the first source driver 21 switches from “green light” indicating a normal state to “red light” indicating an abnormal state. As a result, the user can recognize that the first source driver 21 has failed.

  In addition, the control unit 70 performs the above determination process and outputs a source start pulse SPOI_B to the second source driver 22 at a predetermined timing (400 clocks after the source start pulse SPOI_A is output). In FIG. 24, no failure has occurred in the second source driver 22, and therefore the normal operation shown in FIG. 22 is performed.

  Subsequently, in synchronization with the start timing of the next horizontal scanning period, the control unit 70 switches the source start pulse SPOI_C from the Lo level to the output state, and switches the third source driver 23 from the inactive state to the active state. Thereby, in the next horizontal scanning period, the third source driver 23 drives the source line 11a. The third source chip drivers 23 a, 23 b, and 23 c of the third source driver 23 are sequentially driven, and the source signal SPIO_C is output from the third source chip driver 23 c and input to the control unit 70.

  In the source output determination unit 74 of the control unit 70, the source signal SPIO_C is output 400 clocks after the source start pulse SPOI_C is output, or the source signal SPIO_C is output after the source start pulse SPOI_C is output. It is determined by monitoring the source signal SPIO_C for each clock whether the signal is not output at a timing not after 400 clocks. In FIG. 24, since the source signal SPIO_C is output at regular timing (circled portion in FIG. 24), the third source driver 23 is determined to be normal, and the source error flag C is maintained at the Lo level.

  Accordingly, in the next horizontal scanning period, the source start pulse SPOI_C is input again from the control unit 70 to the third source driver 23, and the same processing as described above is repeated. That is, in FIG. 24, since no defect has occurred in the third source driver 23, the processing is repeated by the third source driver 23. At this time, in the first source driver 21 determined to be out of order, the source start pulse SPOI_A is maintained at the Lo level.

  Thus, in the configuration of FIG. 24, when the first source driver 21 fails in the first horizontal scanning period, the source line 11a is driven by the third source driver 23 after the second horizontal scanning period, The source line 11b is driven by the second source driver 22. When the second source driver 22 fails in the first horizontal scanning period, the source line 11a is driven by the first source driver 21, while the source line 11b is driven after the second horizontal scanning period. It is driven by the fourth source driver 24.

  Next, while using the liquid crystal display device 2 in FIG. 24 (that is, the first (main) source driver 21 is stopped and the third (sub) source driver 23 is driven), the third (sub) ) A case where the source driver 23 fails will be described with reference to FIG. In FIG. 25, a certain third source chip driver 23b (not shown) breaks down, the source signal SPIO is not input to the third source chip driver 23c, and the source signal SPIO_C is received from the third source chip driver 23c at the final stage. It shows a state where it is not output at regular timing (circled dotted line portion in FIG. 25). For convenience of explanation, it is assumed that the failure has occurred in the second horizontal scanning period.

  In this case, since the source signal SPIO_C is not input to the source output determination unit 74 at a regular timing (400 clocks after the source start pulse SPOI_C is output), the source output determination unit 74 includes the third source driver 23. It is determined that there is a failure. In response to this determination result, the control unit 70 fixes the source start pulse SPOI_C to the Lo level. Thereby, the third source driver 23 is switched from the active state to the inactive state, and the operation of the third source driver 23 is stopped.

  In addition, the control unit 70 switches the source error flag C from the Lo level to the Hi level, so that the notification unit 80 notifies the outside of the message notifying that the third source driver 23 has failed. For example, the LED lamp (first sub) that displays the state of the third source driver 23 switches from “green light” indicating a normal state to “red light” indicating an abnormal state. As a result, both the LED lamp (first main) and the LED lamp (first sub) are “lit red”, and the user can recognize that the first and third source drivers 21 and 23 have failed.

  On the other hand, the control unit 70 performs the determination process and the switching process, and outputs a source start pulse SPOI_B to the second source driver 22. In FIG. 25, since the second source driver 22 has not failed, the normal operation shown in FIG. 22 is performed.

  Subsequently, in the third horizontal scanning period, the control unit 70 does not output the source start pulse SPOI_C at the start timing of the third horizontal scanning period, and outputs the source start pulse SPOI_B after 400 clocks. At this time, the control unit 70 supplies the message data stored in the memory unit 76 to the second source driver 22. The content of the message is a content that warns the user that a failure has occurred in the liquid crystal display device 2, and may further include a contact information of a service center. These messages are registered in advance in the memory unit 76, and can be added or modified as necessary.

  Thus, in the third horizontal scanning period, nothing is displayed on the left half of the display screen corresponding to the source line 11a, and a desired message (warning) is displayed on the right half of the display screen corresponding to the source line 11b. Is done.

  Here, the liquid crystal display device in which the first (main) source driver 21, the second (main) source driver 22, and the third (sub) source driver 23 are stopped and only the fourth (sub) source driver 24 is driven. 2, the case where the fourth (sub) source driver 24 fails will be described.

  In this case, since the source signal SPIO_D is not input to the source output determination unit 74 at regular timing (400 clocks after the source start pulse SPOI_D is output), the source output determination unit 74 includes the fourth source driver 24. It is determined that there is a failure. Receiving this determination result, the control unit 70 fixes the source start pulse SPOI_D to the Lo level. As a result, the fourth source driver 24 is switched from the active state to the inactive state, and the operation of the fourth source driver 24 is stopped. As a result, in the next horizontal scanning period, all source drivers are stopped.

  In addition, the control unit 70 switches the source error flag D from the Lo level to the Hi level, so that the notification unit 80 notifies the outside of the message notifying that the fourth source driver 24 has failed. For example, the LED lamp (second Sub) that displays the state of the fourth source driver 24 switches from “green light” indicating a normal state to “red light” indicating an abnormal state. Thereby, all the LED lamps are turned “red”, and the user can recognize that all the source drivers have failed.

  In FIG. 23, the case where the source signal SPIO_A is not output due to the failure of the first source chip driver 21b is shown. However, as another example of malfunction, the source signal SPIO_A is output at an incorrect timing, There is a case where the source signal SPIO_A is output at both timing and incorrect timing. In this regard, according to the source output determination unit 74 of the present liquid crystal display device 2, the source signal SPIO_A is output 400 clocks after the source start pulse SPOI_A is output, and the source signal SPIO_A is the source start pulse. Since it is determined whether the SPOI_A is output at a timing not more than 400 clocks after the SPOI_A is output, it is determined whether the source driver is normal or abnormal, so that a failure of the source driver can be reliably detected.

  In addition, the source output determination unit 74 may determine that each source driver is faulty when the number of times determined that the source signal SPIO is abnormal reaches a plurality of times continuously. This configuration can be realized by providing the counter unit 73 as in the first embodiment.

  In the above embodiment, the source signal SPIO that is the target of abnormality detection input (returned) to the source output determination unit 74 from the source driver is the source signal SPIO of the final 400th clock, but this is not limitative. For example, the source signal SPIO output from the first source chip driver 21a or 21b may be used. Alternatively, the source signals SPIO of the first source chip drivers 21a, 21b, and 21c are sequentially input to the source output determination unit 74 to determine whether the source signal SPIO is abnormal for each source chip driver. It is good. Furthermore, it is good also as a structure which determines whether the output timing of the data signal output to each source line 11a, 11b is abnormal.

  Here, a flowchart corresponding to the above operation example of the liquid crystal display device 2 is shown in FIG. As shown in FIG. 26, first, in step S41, the control unit 70 sets the source start pulse SPOI_A to the output state. At this time, the Lo level is output for the source start pulse SPOI_C, the source error flag A, and the source error flag C.

  Next, in step S42, the source output determination unit 74 determines whether the source signal SPIO_A is output at a regular position (timing) and whether the source signal SPIO_A is not output at a position other than the regular position. (Judgment step).

  If YES in step S42, that is, if the source signal SPIO_A is output at a normal position (timing) and not output at a position that is not a normal position, the first source driver 21 is normal. It returns to step S41, and the first source driver 21 repeats the normal operation.

  On the other hand, in the case of NO in step S42, that is, when the source signal SPIO_A is not output at the regular position (timing), or is output at a position that is not the regular position, or at the regular position. If it is output at another position even though it is output, it is determined that the first source driver 21 has failed, and the process proceeds to the next step S43.

  In step S43, based on the determination result of the source output determination unit 74 (failure of the first source driver 21), the control unit 70 fixes the source start pulse SPOI_A to Lo level and switches the source start pulse SPOI_C to the output state. . Further, the source error flag A is switched to the Hi level. For the source error flag C, the Lo level is maintained. As a result, the first source driver 21 stops and the third source driver 23 starts driving. At the same time, the failure of the first source driver 21 is notified to the outside.

  Next, in step S44, in the third source driver 23, the source output determination unit 74 monitors the output timing of the source signal SPIO_C to determine the state of the third source driver 23.

  If YES in step S44, that is, if the source signal SPIO_C is output at a normal position (timing) and not output at a position that is not a normal position, the third source driver 23 is normal. It returns to step S43, and the normal operation | movement by the 3rd source driver 23 is repeated.

  On the other hand, in the case of NO in step S44, that is, when the source signal SPIO_C is not output at the regular position (timing), or is output at a position that is not the regular position, or at the regular position. If it is output at another position even though it is output, it is determined that the third source driver 23 has failed, and the process proceeds to the next step S45.

  In step S45, based on the determination result of the source output determination unit 74 (failure of the third source driver 23), the control unit 70 fixes the source start pulse SPOI_C at the Lo level. Further, the source error flag C is switched to the Hi level. As a result, the operation of the third source driver 23 in addition to the first source driver 21 is also stopped. Then, the failure of the first and third source drivers 21 and 23 is notified to the outside. In this case, a warning display (see FIG. 25) is displayed on the right half of the display screen.

  Next, in step S46, it is determined whether or not both of the source error flags B and D are ON (Hi level). If YES in step S46, that is, if both of the source error flags B and D are at the Hi level, it is determined that all of the first to fourth source drivers 21 to 24 have failed, and the liquid crystal display The function of the device 2 is stopped (step S47).

  On the other hand, if NO in step S46, that is, if at least one of the source error flags B and D is at the Lo level, at least one of the second and fourth source drivers 22 and 24 is normal. It returns to step S45 and the said warning display is repeated (refer FIG. 25).

  Note that the processing contents in the above-described operation example are the same as those in the operation example for detecting the failure of the second source driver 22 and the fourth source driver 24, and thus the description thereof is omitted.

  As described above, in the liquid crystal display device 2 according to the present embodiment, all the source lines are divided into a plurality of sets (in FIG. 20, two sets: source line 11a and source line 11b), corresponding to each set. Source drivers (source drivers 21 and 22) are individually provided. Thus, even when any source driver (for example, the source driver 21) fails, the corresponding source line (for example, the source line 11b) can be driven by a normal source driver (for example, the source driver 22). The display function will not stop suddenly. Therefore, it is possible to avoid the problem that nothing is displayed on the display screen during use by the user. In addition, when one source driver fails, a message indicating the failure is displayed on a part of the display screen due to the operation of the other source driver, so the user recognizes the cause of the failure (display failure). can do.

  In order to obtain such an effect, the present liquid crystal display device only needs to include at least one source driver for each of the divided sets as shown in FIG.

  In addition, since the liquid crystal display device 2 shown in FIG. 20 includes two source drivers for each of the divided groups, for example, when the first (main) source driver 21 fails, the liquid crystal display device 2 automatically Since switching to the third (sub) source driver 22 (redundant circuit), the operation can be continued without stopping the display function. Therefore, it is possible to save the trouble of switching to the redundant circuit at the time of manufacture, and to extend the product life at the time of use by the user.

<Switching gate driver>
Subsequently, switching of the gate driver will be described together with the configuration of the gate output determination unit 75. As shown in FIG. 20, the first gate driver 31 is configured by cascading first gate chip drivers 31a and 31b, and a gate start pulse GSPOI_A is input from the control unit 70 to the first gate chip driver 31a. Thus, driving of the first gate chip driver 31a is started. The first gate chip driver 31a outputs a gate signal Gout to each corresponding gate line 12a, and outputs a gate signal GSPIO to the adjacent first gate chip driver 31b. Thus, driving of the first gate chip driver 31b is started, and the first gate chip driver 31b outputs the gate signal Gout and the gate signal GSPIO_A to each corresponding gate line 12a. The gate signal GSPIO_A is input to the gate output determination unit 75 of the control unit 70. The second gate driver 32 is configured by cascading second gate chip drivers 32 a and 32 b and has the same function as the first gate driver 31.

  Further, the control unit 70 outputs the gate start pulse GSPOI_B to the second gate chip driver 32a at a predetermined timing. Thereby, data sampling of the second gate chip driver 32a is started. Then, after the same processing as described above is performed in the second gate chip drivers 32b and 32c, the second gate chip driver 32c outputs the gate signal Gout to the corresponding gate lines 12b and also to the control unit 70. The gate signal GSPIO_B is output. The gate signal GSPIO_B is input to the gate output determination unit 75 of the control unit 70. Here, the predetermined timing refers to the end of 240 lines (240 horizontal scanning periods) after the gate signal GSPIO_A is output and the gate start pulse GSPOI_A is output.

  Here, a case where the first (main) gate driver 31 operates normally will be described with reference to FIG. FIG. 28 is a timing chart showing various signals in the control unit 70 and the first gate driver 31 when the first gate driver 31 is operating normally.

  First, the control unit 70 sets the gate start pulse GSPOI_A to the output state (Hi) to the first gate chip driver 31a, and sets the Lo level of the gate start pulse GSPOI to the second to fourth gate chip drivers 32a, 33a, and 34a. Output. As a result, the first gate driver 31 is activated, and the second to fourth gate drivers 32, 33, and 34 are deactivated. When GSPOI_A is input from the control unit 70 to the first gate chip driver 31a, scanning is started based on the clock GCK. The clock GCK is determined according to the panel resolution. In the form of FIG. 20, for example, a liquid crystal display device of 800 RGB × 480 (WVGA), the gate driver performs scanning for 480 lines (480 horizontal scanning periods). That is, the first gate driver 31 and the third gate driver 33 drive 240 lines (gate lines 12a: G1 to G240), and the second gate driver 32 and the fourth gate driver 34 have 240 lines (gate line 12b: G241 to G480) are driven.

  The first gate chip drivers 31 a and 31 b are sequentially driven by the gate start pulse GSPOI_A, and the gate signal GSPIO_A is output from the first gate chip driver 31 b and input to the control unit 70.

  Here, the gate output determination unit 75 of the control unit 70 determines whether or not the gate signal is output at regular timing. Specifically, the gate output determination unit 75 determines whether the gate signal GSPIO_A is output 240 lines after the gate start pulse GSPOI_A is output and the gate signal GSPIO_A is output after the gate start pulse GSPOI_A is output. Whether the signal is not output at a timing after 240 lines is determined by monitoring the gate signal GSPIO_A using a detection pulse as a trigger. When the gate output determination unit 75 determines that the gate signal GSPIO_A is not output at the normal timing, it determines that the first gate driver 31 is out of order, and the control unit 70 fixes the gate start pulse GSPOI_A at the Lo level. (Description of FIG. 29 described later).

  In FIG. 28, since the gate signal GSPIO_A is output at regular timing (the circled portion in FIG. 28), the first gate driver 31 is determined to be normal, and the gate error flag A is maintained at the Lo level.

  Accordingly, in the next frame, the gate start pulse GSPOI_A is input again from the control unit 70 to the first gate chip driver 31a, and the same processing as described above is repeated. That is, in FIG. 28, since the first gate driver 31 is not defective, the process is repeated only by the first gate driver 31 without switching to the second gate driver 32. At this time, in the second gate driver 32, all the various signals that are input and output are maintained at the Lo level. Since the gate error flags A and C input to the notification unit 80 are both at the Lo level, for example, an LED lamp (first Main) and an LED lamp for displaying the states of the first and third gate drivers 31 and 33 are displayed. (First Sub) is in a “green lighting” state indicating a normal state.

  Here, the control unit 70 performs the determination process by the gate output determination unit 75 and gives an operation instruction to the second gate driver 32. Specifically, the control unit 70 outputs the gate start pulse GSPOI_B to the second gate driver 32 240 lines after the gate start pulse GSPOI_A is output to the first gate driver 31 (240 horizontal scanning period). Thereby, the driving (scanning) of the second gate driver 32 is started regardless of whether or not the first gate driver 31 is out of order.

  Accordingly, the second gate chip drivers 32 a and 32 b are sequentially driven, and the gate signal GSPIO_B is output from the second gate chip driver 32 b and input to the control unit 70.

  Here, the gate output determination unit 71 of the control unit 70 similarly determines whether or not the gate signal GSPIO_B is output at regular (predetermined) timing. Specifically, the gate output determination unit 75 determines whether the gate signal GSPIO_B is output 240 lines after the gate start pulse GSPOI_B is output and the gate signal GSPIO_B is output after the gate start pulse GSPOI_B is output. Whether the signal is output at a timing not later than 240 lines is determined by monitoring the gate signal GSPIO_B using a detection pulse as a trigger. When the gate output determination unit 75 determines that the gate signal GSPIO_B is not output at the normal timing, it determines that the second gate driver 32 is out of order, and the control unit 70 outputs the gate start pulse GSPOI_B from the output state to Lo. Switch to level.

  In FIG. 28, since the gate signal GSPIO_B is output at a normal timing (circled portion in FIG. 28), the second gate driver 32 is determined to be normal, and the gate error flag B is maintained at the Lo level.

  Thereby, in the next frame, the gate start pulse GSPOI_B is input again from the control unit 70 to the second gate chip driver 32a, and the same processing as described above is repeated. That is, in FIG. 28, since the second gate driver 32 is not defective, the process is repeated only by the second gate driver 32 without switching to the fourth gate driver 34. At this time, in the fourth gate driver 34, all the various signals that are input and output are maintained at the Lo level. Since the gate error flags B and D input to the notification unit 80 are both at the Lo level, for example, an LED lamp (second Main) and an LED lamp for displaying the states of the second and fourth gate drivers 32 and 34 are displayed. (Second Sub) is in a “green lighting” state indicating a normal state.

  Next, a case where the first (main) gate driver 31 breaks down while using the liquid crystal display device 2 will be described with reference to FIG. Here, the first gate chip driver 31a has failed (not shown), the gate signal GSPIO is not input to the first gate chip driver 31b, and the gate signal GSPIO_A from the first gate chip driver 31b at the final stage is normal. The state where it is not output at the timing is shown (circled dotted line portion in FIG. 29).

  In this case, since the gate signal GSPIO_A is not input to the gate output determination unit 75 at regular timing (240 lines after the gate start pulse GSPOI_A is output), the gate output determination unit 75 includes the first gate driver 31. It is determined that there is a failure. Then, the control unit 70 fixes the gate start pulse GSPOI_A at the Lo level and switches the gate error flag A from the Lo level to the Hi level. As a result, the first gate driver 31 is switched from the active state to the inactive state, the operation of the first gate driver 31 is stopped, and a notification message from the notification unit 80 that the first gate driver 31 has failed is sent to the outside. Informed. For example, the LED lamp (first Main) that displays the state of the first gate driver 31 is switched from “green light” indicating a normal state to “red light” indicating an abnormal state. Thereby, the user can recognize that the first gate driver 31 has failed.

  Further, the control unit 70 performs the above determination process and outputs a gate start pulse GSPOI_B to the second gate driver 32 at a predetermined timing (240 lines after the gate start pulse GSPOI_A is output). In FIG. 29, since the second gate driver 32 has not failed, the normal operation shown in FIG. 28 is performed.

  Subsequently, in synchronization with the start timing of the next frame, the control unit 70 switches the gate start pulse GSPOI_C from the Lo level to the output state, and switches the third gate driver 33 from the inactive state to the active state. Thereby, in the next frame, the third gate driver 33 drives the gate lines 12a (G1 to G240). Then, the third gate chip drivers 33 a and 33 b of the third gate driver 33 are sequentially driven, and the gate signal GSPIO_C is output from the third gate chip driver 33 b and input to the control unit 70.

  In the gate output determination unit 75 of the control unit 70, the gate signal GSPIO_C is output 240 lines after the gate start pulse GSPOI_C is output, or the gate signal GSPIO_C is output after the gate start pulse GSPOI_C is output. Whether the signal is not output at a timing after 240 lines is determined by monitoring the gate signal GSPIO_C using a detection pulse as a trigger. In FIG. 29, since the gate signal GSPIO_C is output at a normal timing (circled portion in FIG. 29), the third gate driver 33 is determined to be normal, and the gate error flag C is maintained at the Lo level.

  Accordingly, in the next frame, the gate start pulse GSPOI_C is input again from the control unit 70 to the third gate driver 33, and the same processing as described above is repeated. That is, in FIG. 29, since there is no problem in the third gate driver 33, the process is repeated by the third gate driver 33. At this time, in the first gate driver 31 determined to be out of order, the gate start pulse GSPOI_A is maintained at the Lo level.

  Thus, in the configuration of FIG. 29, when the first gate driver 31 fails in the first frame, the gate line 12a is driven by the third gate driver 33 from the second frame onward, while the gate line 12b is driven. Are driven by the second gate driver 32. If the second gate driver 32 fails in the first frame, the gate line 12a is driven by the first gate driver 31, while the gate line 12b is driven by the fourth gate driver in the second and subsequent frames. 34.

  Next, while using the liquid crystal display device 2 in FIG. 29 (that is, the first (main) gate driver 31 is stopped and the third (sub) gate driver 33 is driven), the third (sub) ) A case where the gate driver 33 fails will be described with reference to FIG. FIG. 30 shows a state in which a certain third gate chip driver 33b (not shown) breaks down and the gate signal GSPIO_C is not output from the third gate chip driver 33b at a normal timing (see a circle in FIG. 30). Dotted line part). For convenience of explanation, it is assumed that the above failure has occurred in the second frame.

  In this case, since the gate signal GSPIO_C is not input to the gate output determination unit 75 at regular timing (240 lines after the gate start pulse GSPOI_C is output), the gate output determination unit 75 includes the third gate driver 33. It is determined that there is a failure. In response to this determination result, the control unit 70 fixes the gate start pulse GSPOI_C at the Lo level. As a result, the third gate driver 33 is switched from the active state to the inactive state, and the operation of the third gate driver 33 is stopped.

  Further, the control unit 70 switches the gate error flag C from the Lo level to the Hi level, so that the notification unit 80 notifies the outside of the message notifying that the third gate driver 33 has failed. For example, the LED lamp (first sub) for indicating the state of the third gate driver 33 is switched from “green lighting” indicating a normal state to “red lighting” indicating an abnormal state. As a result, both the LED lamp (first main) and the LED lamp (first sub) are “lit red”, and the user can recognize that the first and third gate drivers 31 and 33 have failed.

  On the other hand, the control unit 70 performs the determination process and the switching process, and outputs a gate start pulse GSPOI_B to the second gate driver 32. In FIG. 30, since the failure has not occurred in the second gate driver 32, the normal operation shown in FIG. 28 is performed.

  Subsequently, in the third frame, the control unit 70 does not output the gate start pulse GSPOI_C at the start timing of the third frame, but outputs the gate start pulse GSPOI_B after 240 lines. At this time, the control unit 70 supplies the message data stored in the memory unit 76 to the second gate driver 32. The content of the message is a content that warns the user that a failure has occurred in the liquid crystal display device 2, and may further include a contact information of a service center. These messages are registered in advance in the memory unit 76, and can be added or modified as necessary.

  Thereby, in the third frame, nothing is displayed on the upper half of the display screen corresponding to the gate line 12a, and a desired message (warning) is displayed on the lower half of the display screen corresponding to the gate line 12b. Is called.

  Here, the first (main) gate driver 31, the second (main) gate driver 32, and the third (sub) gate driver 33 are stopped, and only the fourth (sub) gate driver 34 is driven. 2, the case where the fourth (sub) gate driver 34 fails will be described.

  In this case, since the gate signal GSPIO_D is not input to the gate output determination unit 75 at regular timing (240 lines after the gate start pulse GSPOI_D is output), the gate output determination unit 75 includes the fourth gate driver 34. It is determined that there is a failure. Receiving this determination result, the control unit 70 fixes the gate start pulse GSPOI_D at the Lo level. As a result, the fourth gate driver 34 switches from the active state to the inactive state, and the operation of the fourth gate driver 34 stops. As a result, in the next frame, all the gate drivers are stopped.

  Further, the control unit 70 switches the gate error flag D from the Lo level to the Hi level, so that the notification unit 80 notifies the outside of the message notifying that the fourth gate driver 34 has failed. For example, the LED lamp (second Sub) that displays the state of the fourth gate driver 34 switches from “green light” indicating a normal state to “red light” indicating an abnormal state. As a result, all the LED lamps are turned “red” and the user can recognize that all the gate drivers have failed.

  In FIG. 29, the case where the gate signal GSPIO (Main) is not output due to the failure of the first gate chip driver 31a is shown. However, as another example of malfunction, the gate signal GSPIO_A is output at an incorrect timing. There is a case where the gate signal GSPIO_A is output at both the regular timing and the incorrect timing. In this regard, according to the gate output determination unit 75 of the present liquid crystal display device 2, whether the gate signal GSPIO_A is output 240 lines after the gate start pulse GSPOI_A is output, and the gate signal GSPIO_A is the gate start pulse. It is possible to reliably detect a failure of the gate driver because it is determined whether the GSPOI_A is output at a timing not later than 240 lines after the output of GSPOI_A.

  In order to improve the detection accuracy, the configuration of shortening the period of the detection pulse and the configuration of including the counter unit 73 and determining the failure of the gate driver based on the number of times of abnormality determination are described in the first embodiment and the source driver It can be applied in the same manner as in the configuration.

  In the above embodiment, the gate signal GSPIO that is input (returned) from the gate driver to the gate output determination unit 75 and is subject to abnormality detection is the final start pulse output GSPIO. However, the present invention is not limited to this. For example, the gate signal GSPIO output from the first gate chip driver 31a may be used. Or it is good also as a structure which inputs the gate signal GSPIO of the 1st gate chip driver 31a into the gate output determination part 75, and determines whether the gate signal GSPIO is abnormal.

  Here, a flowchart corresponding to the above operation example is shown in FIG. As shown in FIG. 31, first, in step S51, the control unit 70 sets the gate start pulse GSPOI_A to an output state. At this time, the Lo level is output for the gate start pulse GSPOI_C, the gate error flag A, and the gate error flag C.

  Next, in step S52, the gate output determination unit 75 determines whether the gate signal GSPIO_A is output at a regular position (timing) and whether the gate signal GSPIO_A is not output at a position other than the regular position. To do.

  If YES in step S52, that is, if the gate signal GSPIO_A is output at a normal position (timing) and not output at a position other than the normal position, the first gate driver 31 is normal. It returns to step S51 and the normal operation is repeated in the first gate driver 31.

  On the other hand, in the case of NO in step S52, that is, when the gate signal GSPIO_A is not output at the regular position (timing), or is output at a position that is not the regular position, or at the regular position. If it is output at another position even though it is output, it is determined that the first gate driver 31 is out of order, and the process proceeds to the next step S53.

  In step S53, based on the determination result of the gate output determination unit 75 (failure of the first gate driver 31), the control unit 70 fixes the gate start pulse GSPOI_A to Lo level and switches the gate start pulse GSPOI_C to the output state. . Further, the gate error flag A is switched to the Hi level. For the gate error flag C, the Lo level is maintained. As a result, the first gate driver 31 is stopped and the third gate driver 33 is driven. At the same time, the failure of the first gate driver 31 is notified to the outside.

  Next, in step S54, as in the process of step S52, in the third gate driver 33, the gate output determination unit 75 monitors the output timing of the gate signal GSPIO_C and determines the state of the third gate driver 33.

  If YES in step S54, that is, if the gate signal GSPIO_C is output at a normal position (timing) and not output at a position other than the normal position, the third gate driver 33 is normal. It returns to step S53 and the normal operation | movement by the 3rd gate driver 33 is repeated.

  On the other hand, if NO in step S54, that is, if the gate signal GSPIO_C is not output at the regular position (timing), or is output at a position that is not the regular position, or at the regular position. If it is output at another position even though it is output, it is determined that the third gate driver 33 has failed, and the process proceeds to the next step S55.

  In step S55, based on the determination result of the gate output determination unit 75 (failure of the third gate driver 33), the control unit 70 fixes the gate start pulse GSPOI_C at the Lo level. Further, the gate error flag C is switched to the Hi level. Thereby, in addition to the first gate driver 31, the operation of the third gate driver 33 is also stopped. Then, the failure of the first and third gate drivers 31 and 33 is notified to the outside. In this case, a warning display (see FIG. 30) is performed on the lower half of the display screen.

  Next, in step S56, it is determined whether or not both of the gate error flags B and D are ON (Hi level). If YES in step S56, that is, if both the gate error flags B and D are at the Hi level, it is determined that all of the first to fourth gate drivers 31 to 34 have failed, and the liquid crystal display The function of the device 2 is stopped (step S57).

  On the other hand, if NO in step S56, that is, if at least one of the gate error flags B and D is at the Lo level, at least one of the second and fourth gate drivers 32 and 34 is normal. It returns to step S55 and the said warning display is repeated (refer FIG. 30).

  As described above, in the liquid crystal display device 2 according to the present embodiment, all the gate lines are divided into a plurality of sets (in FIG. 20, two sets: gate line 12a and gate line 12b). Gate drivers (gate drivers 31 and 32) are individually provided. Thereby, even when any of the gate drivers (for example, the gate driver 31) fails, the corresponding gate line (for example, the gate line 12b) can be driven by the normal gate driver (for example, the gate driver 32). The display function will not stop suddenly. Therefore, it is possible to avoid the problem that nothing is displayed on the display screen during use by the user. In addition, when one gate driver fails, a message indicating the failure is displayed on a part of the display screen due to the operation of the other gate driver, so the user recognizes the cause of the failure (display failure), etc. can do.

  In order to obtain such an effect, the present liquid crystal display device only needs to include at least one source driver for each of the divided sets.

  In addition, since the liquid crystal display device 2 shown in FIG. 20 includes two gate drivers for each of the divided groups, for example, when the first (main) gate driver 31 fails, the liquid crystal display device 2 automatically Since switching to the third (sub) gate driver 32 (redundant circuit), the operation can be continued without stopping the display function. Therefore, it is possible to save the trouble of switching to the redundant circuit at the time of manufacture, and to extend the product life at the time of use by the user.

  Furthermore, in the liquid crystal display device 2 shown in FIG. 20, since a plurality of gate drivers and a plurality of source drivers are individually arranged, the entire display area of the display panel corresponds to one gate driver and one source driver. It can be divided into matrix regions (in the form of FIG. 20, it is divided into four). Since the control unit 70 includes the source output determination unit 74 and the gate output determination unit 75, the first and second source drivers 21 and 22, the first and second gate drivers are based on the determination results of both. 31 and 32 can be controlled. Thereby, since each divided area can be controlled (driven) individually, it is possible to further suppress the occurrence of a problem that nothing is displayed on the display screen during use by the user, and to improve reliability. it can.

  Further, as shown in FIG. 32 (liquid crystal display device 2 ′), a control signal (Hi-Z control signal) may be input from the control unit 70 to each chip driver. In FIG. 32, the second source driver 22, the fourth source driver 24, the second gate driver 32, and the fourth gate driver 34 are omitted. Specifically, in the initial state, the control unit 70 inputs the Hi-level source control signal _A to each of the first source chip drivers 21a, 21b, and 21c, and the third source chip drivers 23a, 23b, and 23c. A low-level source control signal _C is input to each of the first gate chip drivers 31a and 31b, and a high-level gate control signal _A is input to each of the first gate chip drivers 31a and 31b. The Lo level gate control signal _C is input. Here, when the main side fails, the control signal (A) on the main side is switched to the Lo level, and the control signal (C) on the sub side is switched to the Hi level, thereby switching to the redundant circuit. .

  Further, in the configuration shown in FIG. 20, since a control signal is input for each chip driver, the configuration may be switched to a normal chip driver for each chip driver. For example, when the first source chip driver 21b fails, the source control signal _A input to the first source chip drivers 21a and 21c is maintained at the Hi level, and the source control input to the first source chip driver 21b is maintained. The signal control signal _A is switched to the Lo level, and the source control signal _C input to the second source chip driver 22b is maintained at the Lo level, while the source control signal _C input to the second source chip driver 22b is maintained at the Lo level. Switch to. The gate chip driver can have the same configuration. Thereby, since only the failed chip driver can be switched, the reliability can be improved and the product life can be further extended.

  The present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on common general technical knowledge and those obtained by combining them are also included in the embodiments of the present invention.

  The present invention can be particularly preferably applied to driving an active matrix liquid crystal display device.

1, 1 ', 2 and 2' liquid crystal display device (display device)
10 Liquid crystal display panel (display panel)
11, 11a, 11b Source bus line (data signal line)
12, 12a, 12b Gate lines (scanning signal lines)
12x dummy line (dummy scanning signal line)
13 TFT (transistor)
14 Pixel electrodes 20 to 24 Source driver (data signal line drive circuit)
21a to 21c First source chip driver 22a to 22c Second source chip driver 23a to 23c Third source chip driver 24a to 24c Fourth source chip driver 30a First gate driver (scanning signal line driving circuit)
30b Second gate driver (scanning signal line driving circuit)
40a Third gate driver (scanning signal line driving circuit)
40b Fourth gate driver (scanning signal line driving circuit)
50a 1st changeover switch part (switching means)
51a First switch (switching element)
50b 2nd change-over switch part (switching means)
51b Second switch (switching element)
60a Third changeover switch (switching means)
61a Third switch (switching element)
60b 4th change-over switch part (switching means)
61b Fourth switch (switching element)
31a, 31b First gate source chip driver 32a, 32b Second gate chip driver 33a, 33b Third gate chip driver 34a, 34b Fourth gate chip driver 70 Control unit (switching means)
71 Gate output determination unit (determination means)
73 Counter part (measuring means)
74 Source output determination unit (determination means)
75 Gate output determination unit (determination means)
80 Notification unit (notification means)

Claims (13)

A scanning signal line; a transistor that is turned on / off by a scanning signal supplied to the scanning signal line; a pixel electrode connected to one end of the transistor; and a data signal line connected to the other end of the transistor. A display device comprising a display panel comprising:
For at least one signal line of the scanning signal line and the data signal line, at least two sets of adjacent signal lines are provided,
For each of the above groups, at least one signal line driving circuit for driving the signal lines of the group is provided,
Determining means for determining whether or not at least one of the plurality of signal line driving circuits has failed based on an output timing of a signal output from each signal line driving circuit;
When it is determined by the determining means that one signal line driver circuit is out of order, at least a pair of signal lines corresponding to the normal signal line driver circuit is selected by another normal signal line driver circuit. A display device that is driven. For each group, two signal line driving circuits for driving the signal lines of the group are provided,
Switching means for switching to the other normal signal line drive circuit corresponding to the same set when the determination means determines that one signal line drive circuit corresponding to the one set is broken. The display device according to claim 1, wherein the display device is a display device. The determination means determines whether the signal output from each signal line drive circuit is output at a predetermined timing and whether it is not output at a timing other than the predetermined timing,
When a signal output from one signal line driver circuit is output at a predetermined timing and not output at a timing other than the predetermined timing, it is determined that the signal line driver circuit has not failed. on the other hand,
A signal output from one signal line driver circuit is not output at a predetermined timing, or is output at a timing that is not a predetermined timing, or a timing that is not a predetermined timing and a predetermined timing 3. The display device according to claim 2, wherein when the signals are output from both, the signal is determined to be abnormal, and the signal line driving circuit is determined to be faulty.   The display device according to claim 3, wherein the predetermined timing is preset according to the number of signal lines included in each set. The signal line driving circuit is a scanning signal line driving circuit,
In each set, the determination unit is configured to determine whether a scanning signal output from a scanning signal line located at an end portion on the scanning end among a plurality of scanning signal lines is output at the predetermined timing, and The display device according to claim 4, wherein it is determined whether the signal is not output at a timing that is not a predetermined timing. The signal line driving circuit is a scanning signal line driving circuit,
Each scanning signal line drive circuit is connected to the scanning signal line via a switching element corresponding to each scanning signal line driving circuit,
The switching means inputs an OFF signal to the switching element connected to the scanning signal line drive circuit determined to have failed by the determination means, while the switching means is connected to another normal scanning signal line drive circuit. 6. The display device according to claim 2, wherein the scanning signal line driving circuit is switched by inputting an ON signal.   The switching means further stops the output of the gate start pulse to the scanning signal line drive circuit determined to have failed by the determination means, while sending the gate start pulse to other normal scanning signal line drive circuits. The display device according to claim 6, wherein the display device outputs. The signal line drive circuit is a data signal line drive circuit,
In each set, whether the data signal output from the data signal line located at the end on the end side in the data sampling direction is output at the predetermined timing in each set. The display device according to claim 4, wherein it is determined whether the signal is not output at a timing other than the predetermined timing.   The switching means stops outputting the source start pulse to the data signal line driving circuit determined to have failed by the determining means, and outputs the source start pulse to another normal data signal line driving circuit. The display device according to claim 8. A measuring means for measuring the number of times that the determination means determines that the output timing of the signal output from each signal line drive circuit is abnormal,
2. The determination unit according to claim 1, wherein when the number of times of abnormality determination of the signal by the measurement unit reaches a predetermined number, the signal line driving circuit that outputs the signal is determined to be faulty. The display device according to any one of 9. A notification means for notifying the operation state of the signal line drive circuit to the outside;
The said notification means notifies the outside whether each signal line drive circuit is out of order according to the determination result of the said determination means, The one of Claims 1-10 characterized by the above-mentioned. Display device. When all the signal line drive circuits corresponding to one set fail and at least one signal line drive circuit corresponding to another set is normal,
12. A message for notifying the outside of abnormality of the display device is displayed in a display area where a signal line driven by the normal signal line driving circuit is arranged. Item 1. A display device according to item 1. A scanning signal line; a transistor that is turned on / off by a scanning signal supplied to the scanning signal line; a pixel electrode connected to one end of the transistor; and a data signal line connected to the other end of the transistor. Including
For at least one signal line of the scanning signal line and the data signal line, at least two sets of adjacent signal lines are provided,
A driving method of a display device including a display panel, in which at least one signal line driving circuit for driving the signal lines of the set is provided for each of the sets,
A determination step of determining whether or not at least one of the plurality of signal line drive circuits has failed based on an output timing of a signal output from each signal line drive circuit;
If it is determined in the determination step that one of the signal line driver circuits has failed, at least a pair of signal lines corresponding to the normal signal line driver circuit is selected by another normal signal line driver circuit. A driving method of a display device, characterized by driving.

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