JP2010212773A - Sample-hold circuit and feedthrough suppressing method - Google Patents

Abstract

A sample and hold circuit capable of suppressing feedthrough without stopping an input stage differential amplifier circuit.
An input differential pair amplifies input signals IN and INB which are differential signals with a predetermined amplification factor. The hold circuit 20 is connected to one output terminal of the input differential pair 10 and performs a sample operation and a hold operation based on the sampling clock signal. The output buffer 30 buffers the output of the hold circuit 20. The correction circuit 40 generates a feedthrough having a phase opposite to that of the feedthrough generated in the hold circuit 20 during the hold operation. The correction circuit adds the generated feedthrough to the output of the output buffer 30.
[Selection] Figure 1

Description

  The present invention relates to a sample and hold circuit, and more particularly to a source and follower (emitter follower) type sample and hold circuit that performs a sample operation and a hold operation based on a sampling clock signal. The present invention also relates to a feedthrough suppression method during a hold operation in such a sample and hold circuit.

  There is a sample hold circuit that performs a sample operation and a hold operation. A current-switching source follower type sample-and-hold circuit is often used for an analog-digital converter (AD converter) that handles high-speed signals. The sample hold circuit is described in, for example, Patent Document 1.

  FIG. 4 shows a sample and hold circuit described in Patent Document 1. The sample hold circuit includes an input stage differential amplifier circuit (input stage differential pair) 201, a hold circuit 202, and an output circuit (output buffer) 203. In Patent Document 1, a bipolar transistor is used as the transistor, but in FIG. 4, a field effect transistor is used as the transistor.

  The input stage differential amplifier circuit 201 includes resistors R21 to R24 and transistors Tr21 and Tr22. The input signal IN is input to the gate of the transistor Tr21, and the input signal INB is input to the gate of the transistor Tr22. The input stage differential amplifier circuit 201 amplifies the difference voltage between the input signal IN and the input signal INB with a predetermined amplification factor.

  The hold circuit 202 includes transistors Tr23, Tr24, Tr25 and a voltage holding capacitor CH21. The gate of the transistor Tr23 is connected to the output node PREOUT of the input stage differential amplifier circuit 201. The sampling clock signal CLKB is input to the gate of the transistor Tr24, and the sampling clock signal CLK is input to the gate of the transistor Tr25. The voltage holding capacitor CH21 is connected to the source of the transistor Tr23.

  The output circuit 203 includes a transistor Tr26 and a resistor R25. The gate of the transistor Tr26 is connected to the output node VHOLD of the hold circuit 202. The output circuit 203 buffers the output of the hold circuit 202.

  FIG. 5 shows operation waveforms. The sampling clock signal CLK (b) and the sampling clock signal CLKB (c) are signals inverted from each other. That is, when the sampling clock signal CLK is high, the sampling clock signal CLKB is low, and when the sampling clock signal CLK is low, the sampling clock signal CLKB is high. The sample hold circuit performs a sample operation when the sampling clock signal CLK is high, and performs a hold operation when the CLK is low.

  A sample operation will be described. The input stage differential amplifier circuit 201 operates as a simple linear amplifier circuit, and outputs a voltage proportional to the difference voltage between the input signals IN (a) and INB to the node PREOUT (d). In the hold circuit 202, the transistor Tr25 is turned on and the transistor Tr24 is turned off. Therefore, the current from the current source I22 flows through the transistor Tr25, and the transistor Tr23 operates as a simple source follower. The transistor Tr23 outputs the voltage VHOLD corresponding to the PREOUT voltage while charging the voltage holding capacitor CH21 (e).

  The output buffer 203 receives the voltage VHOLD at the output node of the hold circuit 202 with high impedance, and outputs a voltage corresponding to the VHOLD voltage to the output terminal OUT (f). Thus, the sample hold circuit operates as a simple amplifier during the sample operation, and outputs a voltage following the input signal.

  Next, the hold operation will be described. When the sampling clock signal CLK is low and the sampling clock signal CLKB is high, the transistor Tr25 of the hold circuit 202 is turned off and the transistor Tr24 is turned on. When the transistor Tr24 is turned on, the current of the current source I22 flows through the resistor R22 constituting the input stage differential amplifier circuit 201 of the previous stage via the transistor Tr24. For this reason, a voltage drop of R22 × I22 occurs at the node PREOUT, and the transistor Tr23 is turned off.

  When the transistor Tr23 is turned off, the voltage holding capacitor CH21 is disconnected from the hold circuit 202. The voltage holding capacitor CH21 holds the charge at the moment when the sampling clock signal CLK switches from low to high. Accordingly, the voltage VHOLD at the output node of the hold circuit 202 is held by the voltage holding capacitor CH21, and the output of the output buffer 203 is also held at the voltage at the moment of switching to the hold operation. In this way, the sample hold circuit holds the output voltage at the voltage at the time of operation switching during the hold operation.

  Here, in the sample hold circuit, the input stage differential amplifier circuit 201 is operating even during the hold period. For this reason, the gate voltage (PREOUT) of the transistor Tr23 of the hold circuit 202 varies as the output voltage of the input stage differential amplifier circuit 201 varies. When the gate voltage of the transistor Tr23 fluctuates, the gate voltage (PREOUT voltage) leaks into the output node VHOLD of the hold circuit 202 due to the influence of the parasitic capacitance between the gate and the source of the transistor and fluctuates the VHOLD voltage. That is, the problem of feedthrough that the input signal leaks to the output occurs. The feedthrough appears as a minute vibration equal to the RF (Radio Frequency) frequency of the input signal IN in the output voltage during the hold period. Even if the sample-and-hold circuit is used with a differential output, the feedthrough cannot be removed because it has a negative phase noise between the differentials.

  As a countermeasure for the feedthrough, there is a method of connecting the drain terminal of the transistor Tr21 for inputting a data signal of opposite phase and the output node VHOLD of the transistor Tr23 by a feedforward capacitor. By inserting a feedforward capacity, feedthrough can be canceled out with an AC component of reverse phase. However, it is actually difficult to cause the feedthrough amount generated by the operation of the transistor Tr23 during the hold period to be the same as the feedforward capacitance, and the feedthrough cannot be completely canceled out.

  With respect to the problem of the feedthrough, in Patent Document 1, a transistor Tr27 is used as a pull-up circuit. The source / drain of the transistor Tr27 is inserted between the power supply VDD and the connection node between the resistor R23 and the resistor R24 of the input stage differential amplifier circuit 201. A control signal VBHck is input to the gate of the transistor Tr27. The control signal VBHck is controlled to be low during the sample operation and high during the hold operation.

As for the high voltage of the control signal VBHck, the maximum voltage of the input signals IN and INB is Vmax, the resistance between the source and drain of the transistors Tr21 and Tr22 is R _SD , and the current flowing through the resistor R _SD is Io,
VBHck (High)> Vmax-Io.R _SD
It is represented by When the control signal VBHck input to the gate of the transistor Tr27 becomes high, the transistors Tr21 and Tr22 of the input stage differential amplifier circuit 201 are turned off. Since the transistors Tr21 and Tr22 are turned off, the gate voltage of the transistor Tr23 does not change even if the input signals IN and INB change during the hold operation. Therefore, feedthrough is suppressed.

JP-A-9-130168 (paragraphs 0004, 0012, 0013, FIG. 2, FIG. 24) Japanese Patent Laid-Open No. 4-100321

  In Patent Document 1, the transistor Tr27 constituting the pull-up circuit needs to have a forcible force that can turn off the input stage differential amplifier circuit 201. For this reason, it is necessary to use a transistor with a large size as the transistor Tr27. By providing the transistor Tr27, the driving load of the clock signal (CLKB) increases. Theoretically, the feedthrough can be eliminated by stopping the input stage differential amplifier circuit 201. However, it is not realistic to repeatedly change the operation and stop of the input stage differential amplifier circuit 201 at high speed.

  An object of the present invention is to provide a sample hold circuit and a feedthrough suppression method capable of eliminating feedthrough without stopping an input stage differential amplifier circuit.

  In order to achieve the above object, a sample and hold circuit of the present invention is connected to an input stage differential amplifier circuit that amplifies and outputs a differential signal at a predetermined amplification factor, and one output terminal of the input stage differential amplifier circuit. A sample circuit that outputs one of the differential signals based on a sampling clock signal; a hold circuit that performs a hold operation that holds an output voltage; and an output buffer that buffers the output of the hold circuit; And a correction circuit for generating a feedthrough having a phase opposite to that of the feedthrough generated in the hold circuit during the hold operation, and adding the generated feedthrough to the output of the output buffer.

In the feedthrough suppression method of the present invention, one of the differential signals is input to a hold circuit that performs a sample operation and a hold operation based on the sampling clock signal,
During the hold operation, a feedthrough having a phase opposite to that of the feedthrough generated in the hold circuit is generated, and the generated feedthrough is added to the output of the hold circuit.

  The sample hold circuit and the feedthrough suppression method of the present invention can suppress the feedthrough without stopping the differential amplifier circuit in the input stage.

The block diagram which shows the sample hold circuit of 1st Embodiment of this invention. The block diagram which shows the sample hold circuit of 2nd Embodiment of this invention. The block diagram which shows the sample hold circuit which has a differential amplifier. 2 is a block diagram showing a sample and hold circuit described in Patent Document 1. FIG. The figure which shows the operation | movement waveform of the sample hold circuit of FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a sample and hold circuit according to a first embodiment of the present invention. The sample hold circuit includes an input differential pair (input stage differential amplifier circuit) 10, a hold circuit 20, and an output buffer 30. Up to this point, it is the same as a normal source follower (emitter follower) type sample-and-hold circuit. The sample and hold circuit of this embodiment includes a correction circuit 40 in addition to a normal source follower type sample and hold circuit.

  The input differential pair 10 includes resistors R1 to R4, transistors Tr1 and Tr2, and a current source I1. The input differential pair 10 receives an input signal IN and an input signal INB that are differential signals. The hold circuit 20 includes transistors Tr3 to Tr5, a hold capacitor Ch, and a current source I2. The output of the input differential pair 10 and the clock signals CLK and CLKB are input to the hold circuit 20. The output buffer 30 includes a resistor R5 and a transistor Tr6. The output of the hold circuit 20 is input to the output buffer 30.

  The configurations and operations of the input differential pair 10, the hold circuit 20, and the output buffer 30 are the same as those of a normal sample and hold circuit. That is, the input differential pair 10 amplifies and outputs the difference voltage between the input signal IN and the input signal INB with a predetermined amplification factor. The hold circuit 20 is connected to one output terminal of the input differential pair 10. The hold circuit 20 performs a sample operation and a hold operation based on the sampling clocks CLK and CLKB. The hold circuit 20 outputs an analog voltage output from the input differential pair 10 during the sample operation, and holds the analog voltage during the hold operation. The output buffer 30 buffers the output of the hold circuit 20.

  The correction circuit 40 includes transistors Tr7 to Tr10 and a hold capacitor Ch2. The gate of the transistor Tr7 is connected to the drain terminal of the transistor Tr1 of the input differential pair 10. The drain terminal of the transistor Tr7 is connected to the VDD power supply, and the source terminal is connected to the hold capacitor Ch2 and the drain of the transistor Tr8. The transistor Tr3 of the hold circuit 20 is connected to the drain terminal of the transistor Tr2 of the input differential pair 10. On the other hand, since the transistor Tr7 is connected to the drain terminal of the transistor Tr1 on the opposite phase side, the transistor Tr7 is controlled by a signal having a phase opposite to that of the transistor Tr3.

  The source terminal of the transistor Tr8 is connected to the current source I2 of the hold circuit 20. A fixed Low signal is input to the gate of the transistor Tr8, and the transistor Tr8 maintains an off state. The drain terminal of the transistor Tr10 is connected to the gate of the transistor Tr7, and the source terminal is connected to the current source I2 of the hold circuit 20. The clock signal CLKB is input to the gate of the transistor Tr10. The transistor Tr10 is turned on when the clock signal CLKB is High and turned off when the signal is Low. The drain terminal of the transistor Tr9 is connected to the VDD power supply, and the source terminal is connected to the output terminal OUT (the resistor R5 of the output buffer 30). The transistor Tr9 functions as a source follower circuit.

  The correction circuit 40 has a circuit configuration similar to that of the hold circuit 20 and the output buffer 30, and transistors Tr7, Tr8, and Tr10 correspond to the transistors Tr3, Tr5, and Tr4 of the hold circuit 20, respectively. The hold capacitor Ch2 corresponds to the hold capacitor Ch of the hold circuit 20. The transistor Tr9 corresponds to the transistor Tr6 of the output buffer 30. The size of the transistors Tr7 to Tr10 of the correction circuit 40 is equal to the size of the corresponding transistor.

  The operation of the sample and hold circuit will be described. Sampling clock signals CLK and CLKB input to the sample and hold circuit are signals inverted from each other. That is, when the sampling clock signal CLK is High, the sampling clock signal is Low, and when the sampling clock signal CLK is Low, the sampling clock signal CLKB is High. The hold circuit 20 performs a sample operation when the sampling clock signal CLK is High and CLKB is Low, and performs a hold operation when CLK is Low and CLKB is High.

  A sample operation, that is, an operation when the sampling clock signal CLK is High will be described. The input differential pair 10 operates as a linear amplifier circuit, and outputs a voltage proportional to the difference voltage between the input signals IN and INB to the node PREOUT. In the hold circuit 20, the transistor Tr5 is turned on and the transistor Tr4 is turned off. Therefore, the current from the current source I2 flows through the transistor Tr5, and the transistor Tr3 operates as a source follower. The transistor Tr3 outputs a voltage VHOLD corresponding to the PREOUT voltage while charging the hold capacitor Ch.

  The voltage VHOLD output from the hold circuit 20 changes following the change in the input signal IN. The output buffer 30 receives the voltage VHOLD at the output node of the hold circuit 20 with high impedance, and outputs a voltage corresponding to the VHOLD voltage to the output terminal OUT. That is, the output buffer 30 outputs a signal that follows the input signal IN to the output terminal OUT.

  On the other hand, a signal on the opposite phase side of the input differential pair 10 is input to the gate of the transistor Tr7 of the correction circuit 40. During the sample operation, the transistor Tr10 of the correction circuit 40 is off, and the transistor Tr7 operates as a source follower circuit. The transistor Tr7 outputs a voltage corresponding to a signal input to the gate while charging the hold capacitor Ch2. However, since the transistor Tr8 connected to the source terminal of the transistor Tr7 is kept off, there is almost no current flowing through the transistor Tr7. The transistor Tr9 of the correction circuit 40 receives the output of the transistor Tr7 with high impedance, and outputs a voltage according to the output of the transistor Tr7 to the output terminal OUT.

  The signal output from the output terminal OUT is a signal obtained by combining the output signal of the hold circuit 20 and the output signal of the correction circuit 40. However, as described above, since the transistor Tr7 of the correction circuit 40 has a current cut off on the source side, the output level of the transistor Tr7 is negligibly lower than the output level of the transistor Tr3 of the hold circuit 20. That is, the output signal level of the correction circuit 40 is negligibly lower than the output signal level of the output buffer 30. Therefore, the signal output from the output terminal OUT during the sampling operation is a signal that follows the input signal IN.

  Next, a hold operation, that is, an operation when the sampling clock signal CLKB is High will be described. When the sampling clock signal CLK is Low and the sampling clock signal CLKB is High, the transistor Tr5 of the hold circuit 20 is turned off and the transistor Tr4 is turned on. When the transistor Tr4 is turned on, the current of the current source I2 flows through the resistor R2 constituting the input differential pair 10 in the previous stage via the transistor Tr4. Along with this, a voltage drop occurs at the node PREOUT, and the transistor Tr3 is turned off.

  The hold capacitor Ch is disconnected from the hold circuit 20 by turning off the transistor Tr3. The hold capacitor Ch holds a charge at the moment when the sampling clock signal CLK is switched from Low to High. The hold capacitor Ch holds the voltage VHLOD at the output node of the hold circuit 20. The output buffer 30 outputs a signal corresponding to the voltage held by the hold capacitor Ch to the output terminal OUT.

  On the other hand, in the correction circuit 40, the transistor Tr10 is turned on when the sampling clock signal CLKB becomes High. When the transistor Tr10 is turned on, the current of the current source I2 flows through the resistor R1 constituting the input differential pair 10 in the previous stage via the transistor Tr10. Along with this, a voltage drop occurs in the gate voltage of the transistor Tr7, and the transistor Tr7 is turned off. This operation is the same as the operation in which the transistor Tr4 is turned on and the transistor Tr3 is turned off in the hold circuit 20. That is, the transistor Tr is turned off under the same conditions as the transistor Tr3.

  When the transistor Tr7 is turned off, charging to the hold capacitor Ch2 is stopped. The hold capacitor Ch2 holds the charge at the moment when the sampling clock signal CLKB changes from Low to High. The hold capacitor Ch2 holds the voltage of the transistor Tr9. The transistor Tr9 outputs a signal corresponding to the voltage held by the hold capacitor Ch2 to the output terminal OUT.

  The input differential pair 10 continues differential amplification even during the hold period. As a result, the gate voltage of the transistor Tr3 of the hold circuit 20 varies according to the variation of the input signal, and RF signal leakage (feedthrough) occurs. Similarly, in the correction circuit 40, the gate voltage of the transistor Tr7 varies according to the variation of the input signal, and feedthrough occurs. The transistor Tr3 and the transistor Tr7 are in an off state under the same conditions, and the feedthrough through the transistor Tr3 and the feedthrough through the transistor Tr7 are similar.

  The gate of the transistor Tr7 is connected to the resistor R1 side of the input differential pair 10, and is controlled by a signal having a phase opposite to that of the transistor Tr3. For this reason, the feedthrough generated through the transistor Tr7 is in reverse phase to the feedthrough generated through the transistor Tr3. Therefore, in the correction circuit 40, during the hold operation, a feedthrough having a phase opposite to that of the feedthrough generated in the hold circuit 20 occurs. The feedthrough via the transistor Tr3 and the feedthrough via the transistor Tr7 are of the same level, and the two feedthroughs are in a reverse phase relationship. You can cancel out. That is, a signal without feedthrough can be output from the output terminal OUT.

  The sample hold circuit of this embodiment includes an input differential pair 10, a hold circuit 20, an output buffer 30, and a correction circuit 40. The input differential pair 10 amplifies the input signals IN and INB, which are differential signals, with a predetermined amplification factor and outputs the amplified signals. The hold circuit 20 is connected to one output terminal of the input differential pair 10 and outputs a signal corresponding to the input signal IN based on the sampling clock signals CLK and CLKB, and a hold operation that holds the output voltage. I do. The output buffer 30 buffers the output of the hold circuit. The correction circuit 40 generates a feedthrough that is opposite in phase to the feedthrough that occurs in the hold circuit 20 during the hold operation. The correction circuit 40 adds the generated reverse-phase feedthrough to the output terminal OUT of the output buffer 30.

  In the present embodiment, the correction circuit 40 generates a feedthrough that is opposite in phase to the feedthrough that occurs in the hold circuit 20 during the hold operation, and adds this to the output of the output buffer 30. By adding a reverse-phase feedthrough, the influence of the feedthrough can be reduced. In the present embodiment, the input differential pair 10 operates even during the hold operation, and unlike the patent document 1, it is not necessary to stop the input differential pair 10 using a pull-up circuit. That is, in this embodiment, it is possible to suppress feedthrough without stopping the input differential pair 10.

  In the present embodiment, a signal that follows the input signal IN is input to the transistor Tr3 constituting the source follower circuit in the hold circuit 20. The transistor Tr3 outputs a signal that follows the input signal IN during the sampling operation. The transistor Tr3 is controlled to be off during the hold operation. An input signal INB having a phase opposite to that of the input signal IN is input to the transistor Tr7 constituting the source follower circuit in the correction circuit 40. On the source side of the transistor Tr7, the current is cut off by the transistor Tr8 that is always controlled to be off. The transistor Tr7 is controlled to be off during the hold operation.

  In the hold circuit 20, during the hold operation, feedthrough occurs in which the input signal IN leaks to the output side through the transistor Tr3 in the off state. Further, in the correction circuit 40, during the hold operation, feedthrough occurs in which the input signal INB leaks to the output side through the transistor Tr7 in the off state. Since the input signal IN and the input signal INB are in an opposite phase relationship, the feedthrough caused by the input signals having opposite phases occurs in the transistor Tr3 and the transistor Tr7. The feedthrough can be canceled by adding the feedthrough generated in both transistors.

  In the sample operation, since the current on the source side of the transistor Tr7 is cut off, the output of the correction circuit 40 during the sample operation is negligibly small compared to the output of the hold circuit 20. Therefore, the correction circuit 40 does not affect the sample operation.

  The transistor Tr3 of the hold circuit 20 and the transistor Tr7 of the correction circuit 40 are preferably configured with the same size. Further, it is preferable that the transistor Tr3 and the transistor Tr7 are turned off under the same conditions during the hold operation. By configuring both transistors with the same size and turning off both transistors under the same conditions, the amount of generated feedthrough can be made equal. In this case, the feedthrough can be canceled out more effectively.

  In the present embodiment, the correction circuit 40 is necessary for suppressing feedthrough. However, the current is cut off on the source side of the transistor Tr7 in the correction circuit 40, and the transistor Tr8 is always turned off. For this reason, power consumption does not increase greatly by adding the correction circuit 40.

  FIG. 2 shows a sample and hold circuit according to the second embodiment of the present invention. The configuration of the sample and hold circuit of the present embodiment is a configuration in which a hold circuit 50, an output buffer 60, and a correction circuit 70 are added on the opposite phase side to the sample and hold of the first embodiment shown in FIG. . The configurations of the hold circuit 50, the output buffer 60, and the correction circuit 70 are the same as those of the hold circuit 20, the output buffer 30, and the correction circuit 40 of FIG. 1 except that the input signal is in reverse phase.

  Each element in the hold circuit 50, the output buffer 60, and the correction circuit 70 is represented by a subscript b added to each corresponding element in the hold circuit 20, the output buffer 30, and the correction circuit 40. Note that the transistor Tr10 in the correction circuit 40 of FIG. 1 can be replaced by the transistor Tr4b in the hold circuit 50 on the opposite phase side, and thus is not necessary in this embodiment.

  The hold circuit (reverse phase side hold circuit) 50 is connected to the other output terminal of the input differential pair 10. The hold circuit 50 performs a sample operation and a hold operation based on the sampling clocks CLK and CLKB. The hold circuit 50 outputs a negative-phase signal output from the input differential pair during the sample operation, that is, an analog voltage corresponding to the input signal INB, and holds the output voltage during the hold operation. The output buffer (reverse phase side output buffer) 60 buffers the output of the hold circuit 50. The correction circuit (reverse phase side correction circuit) 70 generates a feedthrough having a phase opposite to that of the feedthrough generated in the hold circuit 50, and adds the generated feedthrough to the output of the output buffer 60.

  A sample operation will be described. The operations of the hold circuit 20, the output buffer 30, and the correction circuit 40 are the same as those in the first embodiment. That is, in the hold circuit 20, the transistor Tr5 is turned on and the transistor Tr4 is turned off. A voltage (PREOUT) corresponding to the input signal IN is input to the gate of the transistor Tr3, and the transistor Tr3 outputs an analog voltage corresponding to PREOUT and charges the hold capacitor Ch. The output buffer 30 buffers the output of the hold circuit 20.

  In the correction circuit 40, a voltage (PREOUTB) corresponding to the input signal INB is input to the gate of the transistor Tr7. However, since the current is cut off on the source side of the transistor Tr7, the output of the correction circuit 40 is negligibly smaller than the output of the hold circuit 20. Therefore, the output of the correction circuit 40 does not affect the output of the output buffer 30, and the output buffer 30 outputs a signal that follows the input signal IN from the output terminal OUT.

  The operation on the opposite phase side is the same as described above. That is, in the hold circuit 50, the transistor Tr5b is turned on and the transistor Tr4b is turned off. A voltage (PREOUTB) corresponding to the input signal INB is input to the gate of the transistor Tr3b, and the transistor Tr3b outputs an analog voltage corresponding to PREOUTB and charges the hold capacitor Chb. The output buffer 60 buffers the output of the hold circuit 50.

  In the correction circuit 70, a voltage (PREOUTB) corresponding to the input signal IN is input to the gate of the transistor Tr7b. However, since the current is cut off on the source side of the transistor Tr7b, the output of the correction circuit 70 is negligibly smaller than the output of the hold circuit 50. Therefore, the output of the correction circuit 70 does not affect the output of the output buffer 60, and the output buffer 60 outputs a signal that follows the input signal INB from the output terminal OUTB.

  The hold operation will be described. The operations of the hold circuit 20, the output buffer 30, and the correction circuit 40 are the same as those in the first embodiment. That is, in the hold circuit 20, the transistor Tr4 is turned on and the transistor Tr5 is turned off. The gate voltage of the transistor Tr3 has a voltage drop of R2 × I2 and the transistor Tr3 is turned off. When the transistor Tr3 is turned off, the output of the hold circuit 20 is held at the voltage VHOLD held by the hold capacitor Ch.

  In the correction circuit 40, when the transistor Tr4b is turned on by the hold circuit 50 on the opposite phase side, a voltage drop corresponding to R1 × I2b occurs in the gate voltage of the transistor Tr7, and the transistor Tr7 is turned off. When the transistor Tr7 is turned off, the output of the correction circuit 40 is held at the voltage held by the hold capacitor Ch2.

  In the hold circuit 20, feedthrough occurs in which the input signal IN leaks through the transistor Tr3 that is turned off. Further, in the correction circuit 40, feedthrough occurs in which the input signal INB leaks through the transistor Tr7 that is turned off. Since the transistor Tr3 and the transistor Tr7 are turned off under the same conditions, the amount of generated feedthrough is the same. Since the feedthrough generated in the hold circuit 20 and the feedthrough generated in the correction circuit 40 are in opposite phase to each other, adding them at the output terminal OUT of the output buffer 30 cancels out the feedthrough. Can do.

  The operation on the opposite phase side is the same as described above. That is, in the hold circuit 50, the transistor Tr4b is turned on and the transistor Tr5b is turned off. The gate voltage of the transistor Tr3b has a voltage drop corresponding to R1 × I2b, and the transistor Tr3b is turned off. When the transistor Tr3b is turned off, the output of the hold circuit 50 is held at the voltage VHOLDB held by the hold capacitor Chb.

  In the correction circuit 70, when the transistor Tr4 is turned on by the hold circuit 20 on the opposite phase side, a voltage drop corresponding to R2 × I2 occurs in the gate voltage of the transistor Tr7b, and the transistor Tr7b is turned off. When the transistor Tr7b is turned off, the output of the correction circuit 70 is held at the voltage held by the hold capacitor Ch2b.

  In the hold circuit 50, feedthrough occurs in which the input signal INB leaks through the transistor Tr3b that is turned off. Further, in the correction circuit 70, feedthrough occurs in which the input signal IN leaks through the transistor Tr7b that is turned off. Since the transistor Tr3b and the transistor Tr7b are turned off under the same conditions, the amount of generated feedthrough is the same. Since the feedthrough generated in the hold circuit 50 and the feedthrough generated in the correction circuit 70 are in an opposite phase relationship, the feedthrough is canceled out by adding them at the output terminal OUTB of the output buffer 60. Can do.

  Here, in the hold circuit 20, when the input voltage of the transistor Tr3 increases, a leakage current is generated, and a droop problem that affects the hold voltage occurs. Droop appears as a drop in output voltage during the hold period. The degree of the voltage drop depends on the voltage at the start of the hold, and the droop amount (voltage drop amount) increases as the hold voltage increases. Since the droop amount depends on the voltage at the start of the hold, the droop problem cannot be solved simply by using the sample and hold circuit of FIG. 4 as a differential output.

  In this embodiment, droop can be suppressed by using a differential output between the output OUT and OUTB of the sample and hold circuit. Hereinafter, droop suppression will be described. At the output terminal OUT, the droop amount originating from the input signals having opposite phases to each other via the transistor Tr3 and the transistor Tr7 is added. Similarly, at the output terminal OUTB which is a negative phase side output, the droop amount having the dead-phase input signals via the transistor Tr3b and the transistor Tr7b as the deadline is added. Accordingly, the same degree of droop is output by differential correction.

  When the sample and hold circuit shown in FIG. 4 is used as a differential output, the amount of droop differs depending on the differential compensation. For this reason, droop cannot be canceled even if differential output is taken. In the present embodiment, the same amount of droop is output between the output terminal OUT and the output terminal OUTB. Therefore, if a differential output is taken, it can be canceled as common noise. For example, common noise can be canceled by taking a differential output of OUT and OUTB in a circuit subsequent to the sample hold circuit.

  Alternatively, a differential amplifier may be added to the sample and hold circuit, and common noise may be canceled by the sample and hold circuit. FIG. 3 shows a sample and hold circuit having a differential amplifier. The configuration of the differential amplifier (output differential pair) 80 is the same as that of the input differential pair 10. OUT is connected to one input of the differential amplifier 80, and OUTB is connected to the other. By making the output between the output terminal OUT and the output terminal OUTB of the differential amplifier 80, an output from which the influence of droop is eliminated can be obtained.

  Regarding the droop problem, the A / D converter described in Patent Document 2 solves the droop problem as follows. That is, a predetermined fixed voltage is input to a second SH circuit having the same characteristics as the first sample and hold (SH) circuit and synchronized with the same clock signal. In addition to the first A / D conversion circuit for A / D converting the output of the first SH circuit, a second A / D conversion circuit for A / D converting the output of the second SH circuit is used. The outputs of the first and second A / D conversion circuits are processed by a digital arithmetic circuit, and errors due to droop are canceled.

  However, in Patent Document 2, an extra set of SH circuit and A / D conversion circuit must be prepared in order to solve the droop, and a digital operation circuit is provided for droop cancellation, It is necessary to perform processing. For this reason, the overhead required for LSI for droop processing becomes extremely high. In Patent Document 2, it is assumed that the voltage drop caused by the droop is always constant. However, as described above, since the amount of voltage drop that actually occurs in the droop depends on the voltage at the start of the hold, it is difficult for Patent Document 2 to cancel the error.

  In the present embodiment, the sample hold circuit is used as a differential output. In the present embodiment, feedthrough can be suppressed, and the influence of droop can be suppressed by taking the differential output between the differential outputs. In the present embodiment, an extra sample hold circuit and an A / D converter are unnecessary, and a digital arithmetic unit for droop processing is not separately required. Therefore, the droop problem can be solved without increasing the circuit scale or power consumption.

  As described above, the present invention has been described based on the preferred embodiments. However, the sample hold circuit and the feedthrough suppression method of the present invention are not limited to the above embodiments, and various configurations are possible from the configuration of the above embodiments. Modifications and changes are also included in the scope of the present invention.

10: Input differential pair (input stage differential amplifier circuit)
20, 50: hold circuit 30, 60: output buffer 40, 70: correction circuit 80: differential amplifier (output differential pair)
R1 to R5: resistors Ch, Ch2: hold capacitors Tr1 to Tr10: transistors I1, I2: current sources

Claims (8)

An input stage differential amplifier circuit that amplifies and outputs a differential signal at a predetermined amplification rate; and
A hold circuit that is connected to one output terminal of the input stage differential amplifier circuit and performs a sample operation for outputting one of the differential signals based on a sampling clock signal and a hold operation for holding an output voltage; ,
An output buffer for buffering the output of the hold circuit;
A sample-and-hold circuit including a correction circuit that generates a feedthrough having a phase opposite to that of the feedthrough generated in the hold circuit during the hold operation, and adds the generated feedthrough to the output of the output buffer.   The hold circuit receives one of the differential signals, outputs an input signal during the sample operation, and includes an emitter follower circuit or a source follower circuit in which a transistor is controlled to be off during the hold operation, and the correction The circuit includes the emitter follower circuit or the source follower circuit that receives the other signal of the differential signal, interrupts current on the emitter or source side, and controls a transistor to be turned off during the hold operation. Item 2. The sample-and-hold circuit according to Item 1.   The transistor of the emitter follower circuit or source follower circuit of the hold circuit and the transistor of the emitter follower circuit or source follower circuit of the correction circuit are configured with the same size, and both transistors are turned off under the same conditions during the hold operation. The sample and hold circuit according to claim 2, wherein A negative-phase side hold circuit that is connected to the other output terminal of the input stage differential amplifier circuit and performs a sample operation for outputting the other of the differential signals and a hold operation for holding an output voltage based on a sampling clock signal When,
A negative phase side output buffer for buffering the output of the negative phase side hold circuit;
And a negative phase side correction circuit for generating a feedthrough in the negative phase with the feedthrough generated in the negative phase side hold circuit during the hold operation, and adding the generated feedthrough to the output of the negative phase side output buffer. The sample and hold circuit according to any one of claims 1 to 3.   The negative phase side hold circuit receives the other signal of the differential signal, outputs an input signal during the sampling operation, and an emitter follower circuit or a source follower circuit in which the transistor is controlled to be turned off during the hold operation. The correction circuit inputs one of the differential signals, and the emitter follower circuit or the source follower circuit in which a current is cut off on the emitter or source side and a transistor is controlled to be turned off during the hold operation. 5. The sample and hold circuit according to claim 4, further comprising:   The transistor of the emitter follower circuit or the source follower circuit of the negative phase side hold circuit and the transistor of the emitter follower circuit or the source follower circuit of the negative phase side correction circuit are configured with the same size, and both transistors during the hold operation The sample and hold circuit according to claim 5, wherein is turned off under equivalent conditions.   The sample hold circuit according to any one of claims 4 to 6, further comprising a differential amplifier that differentially amplifies the output of the output buffer and the output of the negative phase side output buffer. One of the differential signals is input to a hold circuit that performs a sample operation and a hold operation based on the sampling clock signal,
A feedthrough suppression method in a sample and hold circuit that generates a feedthrough having a phase opposite to that of the feedthrough generated in the hold circuit during the hold operation, and adds the generated feedthrough to the output of the hold circuit.

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