JP2010203890A - Probe card and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To miniaturize a probe card according to miniaturization of a measuring object. <P>SOLUTION: The probe card 100 includes a conductive contact terminal portion 90, a conductive cantilever portion 92 projecting like a beam from a support portion 94, a wiring layer 96 to be electrically connected to the cantilever portion 92, and a wiring portion 300 supporting the cantilever portion 92, the cantilever portion 92 and the wiring portion 300 being connected with an insulating resin in a manner to cover a connection of the cantilever portion 92 and the wiring layer 96. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a probe card used for measuring electrical characteristics of an integrated circuit or the like and a method for manufacturing the probe card.

  Probe cards are widely used for measuring electrical characteristics of semiconductor integrated circuits and the like. The probe card includes a contactor having a metal probe needle, and supplies a signal to the electric circuit or outputs it from the electric circuit by bringing the contact terminal portion protruding from the tip of the contactor into contact with the electrode pad of the electric circuit. Or detected signals.

  Patent Document 1 and Patent Document 2 disclose a method of manufacturing a probe card that can deal with a measurement object such as a semiconductor integrated circuit that has been highly integrated and miniaturized. Patent Document 3 discloses a technique for increasing the amount of displacement of a pressed portion with respect to an electrode pad without increasing the length of the contactor. Patent Document 4 discloses a technique for providing a step in a beam portion of a probe and extending the probe.

  Patent Document 5 discloses a probe card suitable for measuring electrical characteristics of an integrated circuit or the like that has been miniaturized. Here, a support part, a conduction part formed in the support part, a beam part partially connected to the conduction part and extended so as to protrude from the support part, and formed at the end of the beam part There is disclosed a probe card including a contact terminal portion that has a height that is at least twice the maximum width of the contact terminal portion.

JP 2003-121469 A JP 2003-121470 A JP 2003-57264 A JP 2002-151557 A JP 2008-216206 A

  In recent years, semiconductor integrated devices have been highly integrated and miniaturized, and further miniaturization of probe cards is desired in accordance with changes in the size and pitch of electrode pads, as in the technique described in Patent Document 5.

  On the other hand, even in the case of forming a probe card suitable for a semiconductor integrated device that has been highly integrated and miniaturized, it is preferable that the configuration be as simple as possible. That is, if the configuration of the probe card is complicated, the manufacturing process becomes complicated and the manufacturing cost increases.

  In view of the above-described conventional problems, an object of the present invention is to provide a probe card that can be used for measuring electrical characteristics of an integrated circuit or the like that has been miniaturized, and a method for manufacturing the probe card.

  One aspect of the present invention includes a conductive cantilever portion that has a conductive contact terminal portion and has a structure protruding like a beam from a support portion, and a wiring layer that is electrically connected to the cantilever portion, A wiring portion that supports the cantilever portion, wherein the cantilever portion and the wiring portion are connected by an insulating resin so as to cover a connection portion between the cantilever portion and the wiring layer. The probe card.

  Here, it is preferable that the wiring layer is formed so as to connect the front surface and the back surface of the substrate through through holes formed in the substrate included in the wiring portion.

  Another aspect of the present invention includes a step of forming a conductive cantilever portion including a conductive contact terminal portion on a first substrate, and a step of forming a conductive wiring layer on the second substrate. Connecting the first substrate and the second substrate with an insulating resin so that the cantilever portion and the wiring layer are electrically connected and the connection portion is covered; and And a step of etching the substrate to remove the substrate.

  Here, it is preferable that the step of forming the wiring layer includes a step of embedding a conductive material in a through hole penetrating from the front surface to the back surface of the second substrate.

  According to the present invention, it is possible to provide a probe card having a simple configuration suitable for measurement of highly integrated and miniaturized semiconductor integrated devices.

It is a figure which shows the structure of the probe card in embodiment of this invention. It is sectional drawing which shows the manufacturing method of the probe part in embodiment of this invention. It is sectional drawing which shows the manufacturing method of the probe part in embodiment of this invention. It is sectional drawing which shows the manufacturing method of the probe part in embodiment of this invention. It is a top view which shows the manufacturing method of the probe part in embodiment of this invention. It is sectional drawing which shows the manufacturing method of the wiring part in embodiment of this invention. It is a top view which shows the manufacturing method of the wiring part in embodiment of this invention. It is a top view which shows the manufacturing method of the wiring part in embodiment of this invention. It is sectional drawing which shows the manufacturing method of the probe card in embodiment of this invention.

  The probe card 100 according to the embodiment of the present invention includes a probe unit 200 and a wiring unit 300 as shown in the structural cross-sectional view of FIG.

  The probe unit 200 is a component that includes the probe needle of the probe card 100, and includes a cantilever portion (beam portion) 92. A contact terminal portion 90 is provided in the cantilever portion 92. The contact terminal portion 90 is a portion that is brought into direct contact with the electrode pad of the measurement object.

  The cantilever portion 92 is provided so as to protrude from the support portion 94 in a beam shape. In the probe card 100 according to the present embodiment, a plurality of cantilever portions 92 are arranged adjacent to each other (in the drawing, they are arranged in parallel in the depth direction of the drawing sheet). For example, the cantilevers 92 are arranged side by side with a pitch of 10 μm or less. With such a configuration, the probe card 100 according to the present embodiment can be a measurement target even if it is a semiconductor integrated circuit that has been miniaturized. Each cantilever part 92 is electrically connected to a wiring 98 formed on the surface of the wiring part 300.

  Further, the cantilever portion 92 is processed into a shape bent from the support portion 94 toward the contact terminal portion 90 in the direction in which the contact terminal portion 90 is provided. By providing the bent portion in this manner, the contact terminal portion 90 can be reliably brought into contact with the electrode pad even when the surface of the measurement object has irregularities.

  The contact terminal portion 90 is provided at the distal end portion of the cantilever portion 92. In the present embodiment, the contact terminal portion 90 is configured to protrude substantially perpendicular to the extending direction of the tip portion of the cantilever portion 92. The contact terminal portion 90 preferably has a multilayer structure in which a surface of a highly elastic metal such as titanium is coated with a highly conductive metal such as gold.

  Note that the height of the contact terminal portion 90 is preferably at least twice the maximum width of the contact terminal portion 90. For example, the cantilever portion 92 is processed to a width of 5 μm or less. Since the cantilever portion 92 is processed to have a width of 5 μm or less, the maximum width of the contact terminal portion 90 formed at the tip thereof is also 5 μm or less. At this time, the height of the contact terminal portion 90 is preferably 20 μm or more.

  The wiring unit 300 receives an electrical signal from the probe unit 200 and outputs the electrical signal to a measurement device or the like, or transmits a signal from the measurement device to the probe unit 200. The wiring part 300 includes a support part 94, a through-hole wiring 96 and a wiring 98. The support portion 94 supports the cantilever portion 92 so as to protrude from the end portion. For example, the support portion 94 has a structure in which an insulating member is coated on a substrate. A through-hole wiring 96 is formed so as to penetrate the wiring part 300 from the front surface to the back surface, and each cantilever part 92 is connected to a wiring 98 formed on the surface of the wiring part 300 via the through-hole wiring 96.

  Hereinafter, a method for manufacturing the probe card 100 according to the embodiment of the present invention will be described with reference to FIGS. 2 to 5 show cross sections or planes of workpieces in the respective steps of the manufacturing process of the probe unit 200, and FIGS. 6 to 8 show cross sections of the workpieces in the respective steps of the manufacturing process of the wiring unit 300. Show. FIG. 9 shows a cross section of the workpiece in each step of the connection process between the probe unit 200 and the wiring unit 300.

  In step S10, the substrate 10 is prepared. The probe card 100 is manufactured using a silicon substrate in order to ensure processing accuracy when performing step processing. In the present embodiment, a (100) plane CZ-silicon substrate 10 is used. The thickness of the silicon substrate is preferably 200 μm or more and 600 μm or less, and more preferably 300 μm or more and 400 μm or less. The type of the silicon substrate may be either P type or N type.

  In step S <b> 12, oxide layers 12 are formed on the front and back surfaces of the silicon substrate 10. The oxide layer 12 is preferably performed after cleaning and pretreatment of the front and back surfaces of the silicon substrate 10. The oxidation conditions are not particularly limited. For example, a thermal oxidation forming process may be performed at a substrate temperature of 1100 ° C. for 180 minutes in a wet oxidation method. The thickness of the oxide layer 12 is a thickness that functions as a mask when silicon is etched with tetramethylammonium hydroxide (TMAH) or the like. For example, in order to etch 30 μm of silicon, the film thickness is preferably about 0.5 μm.

  In step S <b> 14, a resist layer 14 is formed on the surface side of the silicon substrate 10 so as to cover the surface of the oxide layer 12 while leaving the end portion of the silicon substrate 10. The resist layer 14 can be patterned by performing photolithography under conditions such as pre-baking, resist coating, post-baking, exposure, development, washing with water, drying, and post-baking according to the type of resist. The film thickness of the resist layer 14 is set in consideration of the selection ratio with the silicon oxide layer in the etching of the oxide layer 12 described below. For example, the thickness is preferably about 4 μm.

  In step S16, the oxide layer 12 is etched using the resist layer 14 as a mask. For the etching process, reactive ion etching (RIE) or chemical dry etching (CDE) can be applied. Thereby, the oxide layer 12 in a region not covered with the resist layer 14 is removed.

In step S18, the resist layer 14 is removed. Resist layer 14 is, for example, be chemically removed using a mixed solution of sulfuric acid (H ₂ SO ₄₎ and hydrogen peroxide (H ₂ O _2). In the present embodiment, sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide solution (H ₂ O ₂ ) are mixed at an appropriate ratio and heated to about 80 ° C. to remove the resist layer 14. After removing the resist layer 14, it is washed with water and spin-dried.

  In step S20, partial etching of the silicon substrate 10 is performed. The silicon substrate 10 exposed at both ends of the oxide layer 12 to be the etching protection layer is etched. Etching is performed so that inclined portions 10a having a predetermined inclination angle (about 55 °) are formed on the silicon substrate 10 at both ends of the oxide layer 12 serving as an etching protective layer. In this embodiment mode, etching using a tetramethylammonium hydroxide aqueous solution (TMAH) or the like is performed. More specifically, for example, etching is performed by about 30 μm while heating to 70 ° C. with 25% TMAH. Then, running water is washed with pure water for 10 minutes and spin-dried.

  In step S22, the oxide layer 12 is removed. Chemical etching can be used for etching. For example, the oxide layer 12 is removed at room temperature using a buffer solution of ammonium fluoride (NH 4 F). Thereafter, it is washed with water and spin-dried.

  In step S24, the oxide layer 16 is formed as a resistant film when performing the nitride layer etching in step S30. The oxide layer 16 is formed on the surface side of the silicon substrate 10. The oxide layer 16 can be formed by thermal oxidation or chemical vapor deposition (CVD). The oxidation conditions are not particularly limited. For example, a thermal oxidation forming process may be performed at a substrate temperature of 1100 ° C. for about 180 minutes in a wet oxidation method. The thickness of the oxide layer 16 is set in consideration of the selection ratio in the nitride layer etching in step S30. For example, the thickness is preferably about 1.0 μm.

In step S <b> 26, a silicon nitride layer (Si ₃ N ₄ ) 18 for reinforcing fixation and support of the cantilever portion 92 is formed on the surface of the oxide layer 16. The silicon nitride layer 18 is formed on the surface side so as to cover the oxide layer 16. The silicon nitride layer 18 is preferably about 1 μm to 2 μm in thickness, for example. The silicon nitride layer 18 can be formed by chemical vapor deposition (CVD), sputtering, or the like. If the silicon nitride layer 18 is deposited by a plate method, reactive silicon etching (RIE) can be applied to the following etching because no silicon nitride layer is formed on the back surface of the silicon substrate 10.

  In step S <b> 28, a resist layer 20 for forming a pattern of the silicon nitride layer 18 is formed on the surface of the silicon nitride layer 18. The resist layer 20 is formed in a rectangular shape on the upper surface of the silicon substrate 10 that has been left to have a trapezoidal cross section in a region away from the inclined portion 10a of the silicon substrate 10 by a predetermined distance. The film thickness and type of the resist layer 20 have resistance to the etching of the silicon nitride layer 18 described below, and photolithography conditions such as pre-baking, post-baking, exposure, and development are appropriately adjusted.

In step S30, the silicon nitride layer 18 is patterned using the resist layer 20. That is, the silicon nitride layer 18 in the region excluding the region masked by the resist layer 20 formed in the rectangular pattern is removed. As an etching method, for example, a wet etching method using a phosphoric acid solution (H ₃ P0 ₄ ) or the like, or a dry etching method such as reactive ion etching or chemical dry etching can be applied. However, high selectivity for the silicon nitride layer 18 is required so that the oxide layer 16 is not removed.

In step S32, the resist layer 20 is removed. The resist layer 20 can be chemically removed using, for example, a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ). In this embodiment, sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide solution (H ₂ O ₂ ) are mixed at an appropriate ratio and heated to about 80 ° C. to remove the resist layer 20. After removing the resist layer 14, it is washed with water and spin-dried.

  In step S34, a resist layer 22 for patterning the oxide layer 16 is formed. The resist layer 22 is formed on the surface of the silicon substrate 10 excluding the region where the contact terminal portion 90 is to be formed. That is, a resist layer 22 having a pattern having a hole 22a is formed in a region where the contact terminal portion 90 is embedded. In the present embodiment, since a plurality of cantilever portions 92 extending from the upper surface of the inclined portion 10a of the silicon substrate 10 toward the end portion of the silicon substrate 10 are formed side by side, the vicinity of the inclined portion 10a of the silicon substrate 10 is formed. The resist layer 22 is patterned so that a plurality of holes 22a are positioned at a predetermined pitch P along the lower side (in the depth direction of the paper surface) of the inclined portion 10a in the region. The hole 22a is provided so that the surface of the oxide layer 16 is exposed.

  The type and thickness of the resist are determined in consideration of the following resistance to deep reactive ion etching (RIE), and photolithography conditions such as pre-baking, post-baking, exposure, and development are appropriately adjusted.

  In step S36, the oxide layer 16 is patterned by an etching method using the resist layer 22 as a mask. That is, the oxide layer 16 in a region exposed from the hole 30 provided in the resist layer 22 is removed, and a hole 16 a is formed in the oxide layer 16. As an etching method, for example, reactive ion etching (RIE) can be applied.

In step S <b> 38, a trench hole 32 for embedding and forming the contact terminal portion 90 is formed in the silicon substrate 10. The trench hole 32 can be formed by performing reactive ion etching (RIE) using the resist layer 22 and the oxide layer 16. For example, it is preferable to form using a Bosch process. The Bosch process is a dry anisotropic etching process. The Bosch process is performed by alternately switching between a process of etching silicon using an etching gas (SF ₆ ) and a deposition process of protecting sidewalls using a deposition gas (C ₄ F ₈ ). This is a process for forming a trench hole 32 having a high aspect ratio. At this time, it is preferable to consider the etching rate difference (selection ratio) between the resist layer 22 and the silicon substrate 10 so that the oxide layer 16 under the resist layer 22 is not etched. In addition, it is preferable that the scallop (side wall roughness) of the formed trench hole 32 be as small as possible.

  The depth of the trench hole 32 is preferably 20 μm to 30 μm or more. By setting the thickness of the oxide layer 16 to about 1.0 μm and applying the Bosch process, the trench hole 32 having a maximum width of 5 μm or less and a depth of 20 μm or more can be formed in the silicon substrate 10. In order to increase the processing accuracy, the depth of the trench hole 32 is preferably suppressed to 50 μm or less.

In step S40, the resist layer 22 is removed. The resist layer 22 can be chemically removed using, for example, a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ). In this embodiment, mixed in appropriate proportions and sulfuric acid (H ₂ SO ₄₎ and hydrogen peroxide (H ₂ O _2), to remove the resist layer 20 is heated to about 80 ° C.. After removing the resist layer 14, it is washed with water and spin-dried. Furthermore, it is preferable to remove deposits attached to the side surfaces in the trench hole 32 when reactive ion etching (RIE) is performed by ashing using oxygen (O 2) plasma.

  In step S42, scallop reduction processing is performed. The scallop reduction process can be a combination of a silicon oxide layer formation process and etching. After performing pretreatment such as surface cleaning, an oxide layer 34 is formed. The oxide layer 34 can be formed by thermal oxidation or chemical vapor deposition (CVD). Although the oxidation conditions are not particularly limited, it is preferable to lower the oxidation temperature in order to reduce the amount of bird-beaks at the film end of the silicon nitride layer 18 and to reduce damage to the silicon nitride layer 18. . Next, the formed oxide layer 34 is etched. Chemical etching can be used for etching. For example, the oxide layer 12 is removed at room temperature using a buffer solution of ammonium fluoride (NH 4 F). At this time, it is preferable to perform etching so that the thickness of the oxide layer 34 remains about 0.1 to 0.2 μm. Thereafter, an oxide layer 34 is further formed. The oxide layer 34 can be formed by thermal oxidation or chemical vapor deposition (CVD), as in the first time. Here, the thickness of the oxide layer 34 is preferably about 0.5 μm. The oxidation process and the etching process in step S42 may be repeated until there is no scallop.

  In step S44, the seed layer 36 is formed. The seed layer 36 can be formed by sputtering, vapor deposition, chemical vapor deposition (CVD), plating, or electroforming. For example, after pretreatment such as surface cleaning, the seed layer 36 is formed by sputtering. The seed layer 36 is formed on the entire surface, and includes at least one metal of nickel, copper, titanium, palladium, platinum, gold, tungsten, and the like, or an alloy thereof, or a highly conductive metal such as a compound thereof. It is preferable to be made of a material. For example, although not limited to this, a laminate of titanium (Ti) -gold (Au) is used. In this case, it is preferable to form the titanium (Ti) layer with a thickness of about 0.1 μm and then form the gold (Au) layer with a thickness of about 1.0 μm. This seed layer 36 finally functions as a conductive contact layer.

  In step S46, a resist layer 38 is formed. The resist layer 38 is used for forming a pattern of the cantilever portion 92. The film thickness of the resist layer 38 is preferably set to such a thickness that the film thickness of the metal layer 40 can be formed even at the step edge portion. The type of the resist layer 38 has resistance to the plating process for forming the metal layer 40 described below, and photolithography conditions such as pre-baking, post-baking, exposure, and development are adjusted as appropriate.

  The resist layer 38 is patterned in accordance with a desired shape of the cantilever portion 92. Specifically, as shown in the plan view of FIG. 5, a plurality of cantilever portions 92 are arranged in parallel at a pitch P, and the cantilever portions 92 rise from the respective trench holes 32 to the inclined portion of the silicon substrate 10 to be on the silicon substrate 10. Patterning is performed so as to form an opening through which the seed layer 36 is exposed, so as to extend to the surface of the formed silicon nitride layer 18.

  In step S48, the metal layer 40 is formed so as to fill the opening provided in the resist layer 38. The metal layer 40 can be formed by a plating process. By applying a voltage to the seed layer 36 and applying a plating process, the metal layer 40 can be formed only in the region of the seed layer 36 exposed in the opening of the resist layer 38.

  The metal layer 40 is preferably composed of a conductive member such as at least one metal selected from nickel, cobalt, copper, titanium, palladium, platinum, gold and tungsten, an alloy thereof, or a compound thereof. It is. For example, a stacked structure of a buried layer of nickel (Ni) -cobalt (Co) alloy and a surface layer of gold (Au) is preferable. In this case, the thickness of the nickel (Ni) -cobalt (Co) alloy buried layer is preferably set from the mechanical strength and electrical characteristics of the metal layer 40.

  In step S50, the oxide layer 12 on the back surface, the resist layer 38, and the fence on the side of the metal layer 40 are removed. Chemical etching can be used to etch the oxide layer 12 on the back surface. For example, the oxide layer 12 is removed at room temperature using a buffer solution of ammonium fluoride (NH 4 F). Thereafter, it is washed with water and spin-dried. Next, the resist layer 38 is removed. For removing the resist layer 38, it is preferable to use a release agent suitable for the resist. Further, after post-treatment such as degreasing, washing with water, and spin drying, the side fence of the metal layer 40 is removed using a diluted solution of tetramethylammonium hydroxide (TMAH).

  In step S52, the seed layer 36 is etched back. For example, ion milling can be applied to the etch-back process. The processing conditions for ion milling are such that only the exposed seed layer 36 is etched in consideration of the etching rate difference (selection ratio) of gold (Au), titanium (Ti), silicon nitride layer, and silicon oxide layer. It is preferable to set.

  In step S <b> 54, a resist layer 42 that serves as a stopper for an insulating resin (NCP) used for bonding to the wiring unit 300 is formed. A resist is applied, and the resist layer 42 is patterned so as to cover at least the tip portion of the cantilever portion 92, that is, the contact terminal portion 90, and to expose at least a part of the upper surface of the inclined portion 10a. Photolithographic conditions such as pre-baking, exposure, development, water washing and spin drying are determined based on the resist type and the like. The type of the resist layer 42 is not particularly limited as long as it can function as a stopper for an insulating resin (NCP) used for bonding to the wiring portion. For example, the film thickness is preferably about 20 μm. .

  The probe part 200 can be formed by the above process. Next, a method for manufacturing the wiring unit 300 will be described with reference to FIGS.

  In step S60, the substrate 50 is prepared. The wiring unit 300 is manufactured using a silicon substrate in order to ensure processing accuracy when performing step processing. In the present embodiment, a CZ-silicon substrate 50 in which the front surface and the back surface of the (100) surface are mirror-finished is used. The thickness of the silicon substrate is preferably 200 μm or more and 600 μm or less, and more preferably 300 μm or more and 400 μm or less. The type of the silicon substrate may be either P type or N type.

  In step S <b> 62, oxide layers 52 are formed on the front and back surfaces on the silicon substrate 50. The oxide layer 52 is preferably performed after cleaning and pretreatment of the front and back surfaces of the silicon substrate 50. The oxidation conditions are not particularly limited. For example, a thermal oxidation forming process may be performed at a substrate temperature of 1100 ° C. for about 180 minutes in a wet oxidation method. The oxide layer 52 has a thickness that functions as a mask for etching silicon with tetramethylammonium hydroxide (TMAH) or the like. For example, the film thickness necessary for etching 50 μm silicon is preferably about 0.5 μm.

  In step S <b> 64, a resist layer 54 is formed on the surface side of the silicon substrate 50 so as to cover the surface leaving the end of the silicon substrate 50. The resist layer 54 can be patterned by performing photolithography under conditions such as pre-baking, resist coating, post-baking, exposure, development, water washing, drying, and post-baking according to the type of resist. The thickness of the resist layer 54 is set in consideration of the selection ratio with the silicon oxide layer in the etching of the oxide layer 52 below.

  In step S66, the oxide layer 52 is etched using the resist layer 54 as a mask. For the etching process, it is preferable to apply reactive ion etching (RIE) or chemical dry etching (CDE). Thereby, the oxide layer 52 in a region not covered with the resist layer 54 is removed.

In step S68, the resist layer 54 is removed. The resist layer 54 can be chemically removed using, for example, a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ). In the present embodiment, sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide solution (H ₂ O ₂ ) are mixed at an appropriate ratio and heated to about 80 ° C. to remove the resist layer 54. After removing the resist layer 54, it is washed with water and spin-dried.

  In step S70, partial etching of the silicon substrate 50 is performed. The silicon substrate 50 exposed at both ends of the oxide layer 52 serving as an etching protective layer is etched. Etching is performed so that inclined portions 50a having a predetermined inclination angle (about 55 °) are formed on the silicon substrate 50 at both ends of the oxide layer 52 serving as an etching protective layer. In this embodiment mode, etching using a tetramethylammonium hydroxide aqueous solution (TMAH) or the like is performed. More specifically, for example, etching is performed for about 50 μm while being heated to 70 ° C. with 25% TMAH, and then washed with pure water for 10 minutes and spin-dried.

  In step S <b> 72, the metal layer 56 is formed on the back surface of the silicon substrate 50. The metal layer 56 is preferably aluminum. The thickness of the metal layer 56 is preferably set in consideration of the resistance to the etching process of the silicon substrate 50, and is set to about 0.1 μm, for example.

  In step S 74, a resist layer 58 is formed on the metal layer 56. The film thickness and type of the resist layer 58 have resistance to etching for forming holes in the silicon substrate 50, and photolithography conditions such as pre-bake, post-bake, exposure, and development are adjusted as appropriate.

  The resist layer 58 is patterned into a pattern having an opening so that a wiring through hole is formed at a position corresponding to each of the cantilever portions 92 of the probe portion 200. When the cantilever portions 92 are provided at intervals of the pitch P, it is preferable to provide a plurality of openings at intervals of the pitch P (in the depth direction of the paper surface) so as to correspond to the cantilever portions 92. Further, photolithography conditions such as pre-baking, post-baking, exposure, and development are adjusted as appropriate. Further, when the developer is NMD3, the metal layer 56 (aluminum) in the region exposed at the opening of the resist layer 58 is also etched and opened.

  In step S76, the resist layer 58 and the metal layer 56 are used as a mask to perform etching so as to form an opening in the oxide layer 52 on the back surface. For the etching process, it is preferable to apply reactive ion etching (RIE) or chemical dry etching (CDE). Thereby, the oxide layer 52 in a region not covered with the resist layer 58 and the metal layer 56 is removed.

  In step S78, the through hole 60 is formed. The through hole 60 is formed by etching the silicon substrate 50 using the oxide layer 52, the metal layer 56, and the resist layer 58 as a mask. The through hole 60 is formed so as to penetrate from the front surface to the back surface of the silicon substrate 50.

The through hole 60 can be formed by performing reactive ion etching (RIE). For example, it is preferable to form using a Bosch process. The Bosch process is a dry anisotropic etching process. The Bosch process is performed by alternately switching between a process of etching silicon using an etching gas (SF ₆ ) and a deposition process of protecting sidewalls using a deposition gas (C ₄ F ₈ ). This is a process for forming a through hole 60 having a high aspect ratio. At this time, in consideration of the difference (selection ratio) between the etching rates of the resist layer 58 and the silicon substrate 50, it is preferable that the oxide layer 52 under the resist layer 58 is not etched. In addition, it is preferable that the scallop (side wall roughness) of the through hole 60 to be formed is as small as possible.

In step S80, the oxide layer 52, the metal layer 56, and the resist layer 58 are removed. First, deposits attached during etching are removed by ashing. Thereafter, the resist layer 58 is removed. The resist layer 58 can be chemically removed using, for example, a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ). In the present embodiment, sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide solution (H ₂ O ₂ ) are mixed at an appropriate ratio and heated to about 80 ° C. to remove the resist layer 14. After removing the resist layer 58, it is washed with water and spin-dried. Further, the oxide layer 52 and the metal layer 56 are removed. Chemical etching can be used for etching. For example, the oxide layer 52 and the metal layer 56 are removed at room temperature using a buffer solution of ammonium fluoride (NH 4 F). Then, it is washed with water and spin-dried.

  In step S82, the surface of the silicon substrate 50 is oxidized to form an oxide layer 62. The oxide layer 62 is preferably performed after cleaning and pretreatment of the front and back surfaces of the silicon substrate 50. The film thickness of the oxide layer 62 only needs to function as an insulating film, and is preferably about 1.5 μm, for example.

  In step S84, a seed substrate 300a is formed separately from the silicon substrate 50. The seed substrate 300 a is formed using a wafer-like substrate 64. A resist layer 66 is formed on the surface of the substrate 64. The film thickness and type of the resist layer 66 may be set in consideration of post-processing for the seed substrate 300a. Next, a seed layer 68 is formed on the resist layer 66. The seed layer 68 can be formed by sputtering, vapor deposition, chemical vapor deposition (CVD), plating, or electroforming. For example, after performing a pretreatment such as surface cleaning, the seed layer 68 is formed by sputtering. The seed layer 68 is preferably made of a material containing a highly conductive metal such as at least one metal among nickel, copper, titanium, palladium, platinum, gold, and tungsten, an alloy thereof, or a compound thereof. is there. Although not limited to this, for example, a laminate of titanium (Ti) -gold (Au) is preferable. In this case, it is preferable to form a titanium (Ti) layer with a film thickness of about 0.05 μm and then form a gold (Au) layer with a film thickness of about 0.3 μm. Next, a resist layer 70 is formed on the seed layer 68. The film thickness and type of the resist layer 70 may be set in consideration of post-processing for the seed substrate 300a.

  In step S86, the silicon substrate 50 and the seed substrate 300a are bonded together. While heating the seed substrate 300a, the silicon substrate 50 and the seed substrate 300a are brought into contact with and pressurized the surface of the silicon substrate 50 on which the inclined portion 50a is provided and the surface of the seed substrate 300a on which the resist layer 70 is provided. to paste together.

  In step S88, the resist layer 70 is removed through the through hole 60. An ashing process using oxygen (O 2) plasma can be applied to the removal of the resist layer 70. By performing ashing from the surface side of the silicon substrate 50, the seed layer 68 functions as a stop layer, and only the resist layer 70 exposed in the through hole 60 is removed.

  In step S90, the buried layer 72 is formed. The buried layer 72 is formed by embedding a conductive material in the through hole 60. For example, the buried layer 72 is a material containing a highly conductive metal such as gold, silver, or copper. In the present embodiment, copper is used as the buried layer 72. The buried layer 72 can be formed by plating. For example, a voltage is intermittently applied to the seed substrate 300 a side, and copper is embedded in the through hole 60 from the front surface to the back surface of the silicon substrate 50 uniformly and automatically and selectively (self-aligned) in the through hole 60. Form.

  In step S92, the seed substrate 300a is peeled from the silicon substrate 50. First, it is preferable to remove the resist layer 66 using a resist stripper, and after stripping, clean the silicon substrate 50 with acetone, isopropyl alcohol (IPA) or the like, perform ultrasonic cleaning in pure water, and spin dry. is there.

  In step S94, the back surface of the silicon substrate 50 is polished, and the surface of the buried layer 72 and the silicon substrate 50 is flattened. For polishing, for example, chemical mechanical polishing (CMP) is preferably used.

  In step S96, the underlayer 74 is formed. The underlayer 74 can be formed by sputtering, vapor deposition, chemical vapor deposition (CVD), plating, or electroforming. For example, after performing pretreatment such as surface cleaning, the base layer 74 is formed by sputtering. The underlayer 74 is preferably composed of a material containing a highly conductive metal such as at least one metal among nickel, copper, titanium, palladium, platinum, gold, and tungsten, or an alloy thereof, or a compound thereof. is there. For example, a laminate of titanium (Ti) -gold (Au) is preferable. In this case, it is preferable to form the titanium (Ti) layer with a thickness of about 0.1 μm and then form the gold (Au) layer with a thickness of about 1.0 μm.

  In step S98, a resist layer 76 is formed. The resist layer 76 is used to form a wiring layer pattern. After post-baking, a resist layer 76 is applied. The type of the resist layer 76 has resistance to the plating process for forming the wiring layer 78 described below, and photolithography conditions such as pre-baking, post-baking, exposure, and development are appropriately adjusted. For example, the resist layer 76 is preferably formed with a thickness of about 10 μm. The resist layer 76 is patterned into a wiring pattern that transmits a signal from each cantilever portion 92.

  In step S100, the wiring layer 78 is formed. The wiring layer 78 is made of a material containing a highly conductive metal such as at least one metal among nickel, cobalt, copper, titanium, palladium, platinum, gold, and tungsten, or an alloy thereof, or a compound thereof. Is preferred. Here, the wiring layer 78 is gold. It is preferable to apply a plating process to the formation of the wiring layer 78. By the plating process, a wiring layer 78 is formed in a region not covered with the resist layer 76 on the back surface of the silicon substrate 50 and a region where the buried layer 72 is exposed on the surface of the silicon substrate 50. By performing a plating process while applying a voltage to the base layer 74 and the buried layer 72, the region not covered with the resist layer 76 on the back surface of the silicon substrate 50 and the buried layer 72 on the surface of the silicon substrate 50 are exposed. The wiring layer 78 can be formed only in the region that is automatically selected (self-alignment). The film thickness of the wiring layer 78 is a thickness capable of transmitting a signal from each cantilever portion 92, and is preferably about 5 μm, for example.

  In step S102, the resist layer 76 is removed. The resist layer 76 can be removed using a resist stripper. Further, it is preferable to clean the silicon substrate 50 with acetone, isopropyl alcohol (IPA), etc., ultrasonically clean in pure water, and spin dry.

  In step S104, the base layer 74 in an unnecessary area is removed. That is, the base layer 74 in a region not covered with the wiring layer 78 is unnecessary and is removed. For the removal of the underlayer 74, for example, ion milling can be applied.

  The wiring part 300 can be formed by the above processing. Next, a method of forming the probe card 100 by connecting the probe unit 200 and the wiring unit 300 will be described with reference to FIG.

  By the manufacturing process, the probe unit 200 and the wiring unit 300 are configured as shown in FIG. The probe unit 200 and the wiring unit 300 are joined to face each other so that the metal layer 40 formed on the surface of the probe unit 200 and the wiring layer 78 formed on the surface of the wiring unit 300 are in corresponding positions.

  In step S110, the probe unit 200 and the wiring unit 300 are aligned. The wiring formed on the surface of the wiring layer 300 and the metal layer 40 formed on the surface of the probe unit 200 in a state where the insulating resin (NCP) 80 is applied to the region surrounded by the resist layer 42 on the surface of the probe unit 200. The layers 78 face each other so that they correspond to each other. For alignment, markers may be formed in advance at positions corresponding to the probe unit 200 and the wiring unit 300, respectively.

  In step S112, the probe part 200 and the wiring part 300 are joined. At the relative position aligned in step S110, the probe resin 200 and the wiring part 300 are pressurized and heated in a state where the metal layer 40 and the wiring layer 78 are in contact with each other, thereby solidifying the insulating resin 80 and The wiring unit 300 is joined. At this time, the resist layer 42 serves as a stopper for the insulating resin 80, and the insulating resin 80 can be prevented from flowing out to an unnecessary region.

  In step S114, the silicon substrate 10 is etched. Chemical etching using a diluted solution of tetramethylammonium hydroxide (TMAH) can be applied to the etching process. For example, the silicon substrate 50 can be completely removed by etching with a diluted solution of tetramethylammonium hydroxide (TMAH) at 70 ° C. The time required for etching is about several hours to several tens of hours. As a result, the seed layer 36 is exposed while being covered with the oxide layer 16.

  In step S116, the resist layer 42 is removed. The resist layer 42 can be chemically removed using a resist stripper. After removing the resist layer 42, it is washed with water and spin-dried.

  In step S118, the oxide layer 16 is removed. Chemical etching can be used for etching the oxide layer 16. For example, the oxide layer 16 is removed using a buffer solution of ammonium fluoride (NH 4 F). Thereby, the cantilever part 92 in which the seed layer 36 and the metal layer 40 are laminated is formed.

  As described above, according to the present embodiment, it is possible to realize the probe card 100 according to the miniaturization of the object to be measured by a simpler manufacturing method than before.

  10 silicon substrate, 10a inclined portion, 12 oxide layer, 14 resist layer, 16 oxide layer, 16a hole, 18 silicon nitride layer, 20 resist layer, 22 resist layer, 22a hole, 30 hole, 32 trench hole, 34 oxide layer, 36 seed layer, 38 resist layer, 40 metal layer, 42 resist layer, 50 silicon substrate, 50 substrate, 50a inclined portion, 52 oxide layer, 54 resist layer, 56 metal layer, 58 resist layer, 60 through hole, 62 oxide layer , 64 substrate, 66 resist layer, 68 seed layer, 70 resist layer, 72 buried layer, 74 underlayer, 76 resist layer, 78 wiring layer, 80 insulating resin, 90 contact terminal portion, 92 cantilever portion, 94 support portion, 96 through-hole wiring, 96 wiring layers, 100 probe card, 200 probe section, 00 wiring portion, 300a seed substrate.

Claims (4)

A conductive cantilever portion having a conductive contact terminal portion and having a structure protruding in a beam shape from the support portion;
A wiring layer electrically connected to the cantilever part, and a wiring part that supports the cantilever part,
The probe card, wherein the cantilever part and the wiring part are connected by an insulating resin so that a connection part between the cantilever part and the wiring layer is covered. The probe card according to claim 1,
The probe card, wherein the wiring layer is formed so as to connect the front surface and the back surface of the substrate through through holes formed in the substrate included in the wiring portion. Forming a conductive cantilever portion comprising a conductive contact terminal portion on a first substrate;
Forming a conductive wiring layer on a second substrate;
Connecting the first substrate and the second substrate with an insulating resin so that the cantilever portion and the wiring layer are electrically connected and the connection portion is covered;
Etching and removing the first substrate;
A method of manufacturing a probe card, comprising: In the manufacturing method of the probe card according to claim 3,
The step of forming the wiring layer includes a step of embedding a conductive material in a through hole penetrating from the front surface to the back surface of the second substrate.

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