JP2010288185A - Charge pump circuit - Google Patents

Abstract

Provided is a charge pump circuit in which an output voltage reaches a specified boost voltage in a short time and thereafter has a small ripple width.
A charge pump circuit includes a control unit, an oscillation circuit, and a boosting unit. The oscillation circuit 20 outputs a pulse signal having a predetermined period. The boosting unit 30 includes n (n ≧ 1) boosting circuits that boost the voltage, and outputs a charge amount according to the pulse signal output from the oscillation circuit 20. The control unit 10 compares the voltage output from the boosting unit 30 with a predetermined specified voltage, and when the voltage output from the boosting unit 30 becomes larger than the specified voltage, one cycle of the pulse signal from the boosting unit 30. The amount of charge supplied per unit is reduced.
[Selection] Figure 1

Description

  The present invention relates to a charge pump circuit that outputs a boosted voltage.

  In recent years, in a nonvolatile semiconductor memory typified by a flash memory or the like, it is necessary to apply a voltage higher than an externally applied voltage (power supply voltage) Vdd to be supplied to a memory cell constituting the nonvolatile semiconductor memory. . A voltage several times higher than the power supply voltage Vdd used when storing (writing) information in the memory cell or erasing (erasing) information stored in the memory cell is an internal booster provided in the nonvolatile semiconductor memory. The power supply voltage Vdd is boosted to a voltage several times higher and supplied by the charge pump circuit. Technologies related to such a charge pump circuit are described in, for example, Patent Document 1 and Patent Document 2.

FIG. 10 is a schematic block diagram showing the configuration of a charge pump circuit 900 according to such a conventional example. The charge pump circuit 900 includes a control unit 91, an oscillation circuit 20, and a boosting unit 93. The load capacity Cload is a capacity that becomes a load of the charge pump circuit 900. For example, when the charge pump circuit 900 is used as an internal booster circuit of a nonvolatile semiconductor memory, the load capacitance Cload increases in proportion to the size of the storage area.
The control unit 91 starts an operation in response to a boosting start signal input from the outside, detects an output voltage Vout output from the boosting unit 93, and oscillates an operation signal Compout indicating whether or not to output a pulse signal Tos. Output to the circuit 20. The oscillation circuit 20 outputs the pulse signal Tos to the booster 93 based on the boost start signal input from the outside and the operation signal Compout output from the controller 91. The booster 93 boosts the power supply voltage Vdd using the pulse signal Tos output from the oscillation circuit 20 and outputs the output voltage Vout.

The control unit 91 includes a reference circuit 11, a detection circuit 12, and a comparator circuit 13. The reference circuit 11 outputs a predetermined reference voltage Vref to the comparator circuit 13. The detection circuit 12 outputs a detection voltage Va used for comparison with the reference voltage Vref according to the output voltage Vout. The detection circuit 12 is composed of, for example, a voltage dividing circuit using resistors connected in series, and converts the output voltage Vout into a comparison detection voltage Va that is proportional to the output voltage Vout and outputs it. Here, the reference voltage Vref is determined according to the boost specified voltage Vload (specified voltage), and is determined to be the same voltage as the detection voltage Va when the output voltage Vout matches the boost specified voltage Vload. Further, the boost specified voltage Vload is an output voltage required for the charge pump circuit 900.
The comparator circuit 13 compares the reference voltage Vref output from the reference circuit 11 with the detection voltage Va detected by the detection circuit 12 and outputs an operation signal Compout to the oscillation circuit 20.

When the L level operation signal Compout is input from the comparator circuit 13, the oscillation circuit 20 periodically outputs the pulse signal Tos. The oscillation circuit 20 is configured by, for example, a ring oscillator circuit.
The booster unit 93 includes n booster circuits 931a1 to 931an. The booster circuits 931a1 to 931an are connected in parallel. Note that the booster circuits 931a1 to 931an have the same configuration. Hereinafter, when any one or all of the booster circuits 931a1 to 931an are shown as representatives, they are referred to as booster circuits 931a. Each booster circuit 931a receives the pulse signal Tos (pulse signal ck) output from the oscillation circuit 20, boosts and outputs the power supply voltage Vdd in accordance with the input pulse signal ck. The output of each booster circuit 931a is connected to the load capacitance Cload via the output terminal 94 of the charge pump circuit 900.

Next, FIG. 11 is a schematic diagram showing the configuration of a booster circuit 931a according to a conventional example. The booster circuit 931a is a circuit that boosts the voltage of the Dickson method as illustrated. The booster circuit 931a includes i diodes 932a1 to 932ai connected in series in the forward direction, capacitors 933a1 to 933aj having one end connected to a connection point between the diodes 932a1 to 932ai, and an input pulse signal. and an inverter 934 that inverts ck.
The power supply voltage Vdd is supplied to the first-stage diode 932a1 of the diodes 932a1 to 932ai connected in series. A boosted voltage is output from the last stage (diode 932ai) of the diodes 932a1 to 932ai connected in series. A signal obtained by inverting the pulse signal ck output from the inverter 934 and the pulse signal ck are alternately input to the other ends of the capacitors 933a1 to 933aj.
In the booster circuit 931a configured as described above, every time the voltage of the input pulse signal ck changes, the electric charge accumulated between the adjacent capacitors 933a1 to 933aj via one of the diodes 932a1 to 932ai. Moves to the next capacitor, and the output voltage is boosted each time it moves.

  Next, the operation of the charge pump circuit 900 will be described. FIG. 12 is a waveform diagram showing the operation of the charge pump circuit 900. As shown in the drawing, at time t0, the detection circuit 12 outputs a detection voltage Va corresponding to the output voltage Vout being 0V. The comparator circuit 13 compares the detection voltage Va output from the detection circuit 12 with the reference voltage Vref output from the reference circuit 11 when the boost start signal changes from L (Low) level to H (High) level. Thus, it is detected that the detection voltage Va is lower than the reference voltage Vref, and an L level operation signal Compout indicating the output of the pulse signal Tos is output to the oscillation circuit 20. The oscillation circuit 20 outputs a pulse signal Tos having a constant period according to the L-level operation signal Compout and the boost start signal output from the comparator circuit 13. In the booster circuit 931a, boosting is performed by the pulse signal Tos output from the oscillation circuit 20, and the output voltage Vout of the charge pump circuit 900 increases. As the output voltage Vout increases, the detection voltage Va also increases.

  When the output voltage Vout becomes higher than the boost specified voltage Vload at time t1, the detection voltage Va output from the detection circuit 12 becomes higher than the reference voltage Vref. The comparator circuit 13 detects that the detection voltage Va is higher than the reference voltage Vref, and outputs an H-level operation signal Compout to the oscillation circuit 20. When the H level operation signal Compout is input, the oscillation circuit 20 outputs the L level pulse signal Tos to the booster circuit 931a. The booster circuit 931a stops the boosting operation because the input pulse signal Tos maintains the L level state. When the booster circuit 931a stops the boosting operation, the charge accumulated in the load capacitor Cload leaks, and the output voltage Vout gradually decreases.

  When the output voltage Vout of the charge pump circuit 900 becomes lower than the specified boost voltage Vload at time t2, the detection voltage Va output from the detection circuit 12 becomes lower than the reference voltage Vref. The comparator circuit 13 detects that the detection voltage Va is lower than the reference voltage Vref, and outputs an L-level operation signal Compout to the oscillation circuit 20. The oscillation circuit 20 outputs a pulse signal Tos having a constant period in accordance with the L level operation signal Compout output from the comparator circuit 13. In the booster circuit 931a, boosting is again performed by the pulse signal Tos output from the oscillation circuit 20, and the output voltage Vout of the charge pump circuit 900 increases. As the output voltage Vout increases, the detection voltage Va also increases.

  When the output voltage Vout becomes higher than the boost specified voltage Vload at time t3, the detection voltage Va output from the detection circuit 12 becomes higher than the reference voltage Vref. The comparator circuit 13 detects that the detection voltage Va is higher than the reference voltage Vref, and outputs an H-level operation signal Compout to the oscillation circuit 20. When the H level operation signal Compout is input, the oscillation circuit 20 outputs the L level pulse signal Tos to the booster circuit 931a. The booster circuit 931a stops the boosting operation because the input pulse signal Tos maintains the L level state. When the booster circuit 931a stops the boosting operation, the charge accumulated in the load capacitor Cload leaks, and the output voltage Vout gradually decreases.

  Thereafter, the operation from time t1 to time t3 described above is repeated. As described above, the charge pump circuit 900 changes in a range in which the output voltage Vout includes the boost specified voltage Vload, and supplies charge to the load capacitor Cload. The state of the charge pump circuit 900 from time t0 to time t1 is referred to as a boosting operation state, and the state of the charge pump circuit 900 after time t1 is referred to as a post-boosting voltage maintaining state. Further, the fluctuation range of the output voltage Vout in the voltage maintaining state after boosting is referred to as ripple.

For example, the ripple width in the case of load capacitance Cload = 100 pF, boost specified voltage Vload = 7 V, boost time Tload ≦ 2.8 μs, and period Tosc = 200 ns of the pulse signal Tos output from the oscillation circuit 20 is as follows. .
Load capacitance Cload = (load charge Qload / boosting specified voltage Vload) = (boosting current Icharge × boosting time Tload) / boosting specified voltage Vload,
Boosting current Icharge = (load capacitance Cload × boosting specified voltage Vload / boosting time Tload) = (100 pF × 7 V / 2.8 μs) = 250 μA.
Therefore, load charge Qload = (boost current Icharge × boost time Tload) = (250 μA × 2.8 μs) = 700 pC.
On the other hand, in the boosting time Tload (2.8 μs), the booster circuit 931 a that operates in the period Tosc (200 ns) operates 14 times (= 2.8 μs / 200 ns). In order to satisfy the boost time Tload (2.8 μs), the charge amount (output charge Qpump) output by the charge pump circuit 900 in one cycle of the pulse signal Tos is 50 pC (= load charge Qload / 14 times = 700 pC / 14 times). ).

  When the output charge Qpump is 50 pC, the change amount ΔVload of the output voltage Vout per cycle of the pulse signal Tos in the post-boosting voltage maintaining state is load charge Qload / load capacitance Cload = 50 pC / 100 pF = 0.5V. At this time, the charge pump circuit 900 supplies a voltage having a ripple width of 7.1% with respect to the boost specified voltage Vload. Further, as can be seen from the above calculation process, the ripple width increases when the boost time Tload is shortened.

The charge pump circuit 900 is in a boost operation state period, that is, a time required for the output voltage Vout to reach the boost specified voltage Vload after the boost start signal is changed from the L level to the H level and the boost operation is started. The interval is determined as the boosting time and is generally required to be short. On the other hand, the ripple width in the voltage maintaining state after boosting varies depending on the voltage supplied by the charge pump circuit 900, and the ripple width is defined by the circuit characteristics of the operating memory cell or the like, and is generally required to be small. Is done.
In the design of the charge pump circuit 900, the amount of charge output from the booster 93 is determined so as to satisfy the boost time. Here, in order to shorten the period of the step-up operation state, the amount of charge output from the step-up unit 93 is increased per cycle of the pulse signal Tos. However, if the amount of charge output from the booster 93 per cycle of the pulse signal Tos is increased, the ripple width in the post-boost voltage maintaining state increases. Thus, shortening the boosting time and reducing the ripple width are in a contradictory relationship.

JP 2004-222396 A JP 2006-42521 A

  As described above, there is a problem that it is difficult to satisfy both of the fact that the output voltage Vout is set to the specified boost voltage Vload in a short time and that the ripple width is reduced.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a charge pump having an output voltage that reaches a specified boost voltage in a short time in a boosting operation state and a small ripple width in a voltage maintaining state after boosting. It is to provide a circuit.

  In order to solve the above problem, the present invention includes an oscillation circuit that outputs a pulse signal having a predetermined period, and n (n ≧ 1) boosting circuits connected in parallel to boost the voltage, A booster that outputs a boosted voltage when a pulse signal is input, a boosted voltage that is output from the booster, and a voltage that is output from the booster by comparing a predetermined specified voltage. And a control unit that reduces the amount of charge output from the boosting unit per one period of the pulse signal in a subsequent boosting operation when the voltage exceeds the specified voltage.

  According to the present invention, in the above-described invention, the n booster circuits output either one of a predetermined first voltage and a second voltage lower than the first voltage. And a booster using a voltage output from the power supply circuit, and when the voltage output from the booster exceeds the specified voltage, the control unit includes the power supply included in the n booster circuits. The voltage output from the circuit is switched from the first voltage to the second voltage, and the power supply circuit receives a predetermined reference voltage at the non-inverting input terminal and the output voltage at the inverting input terminal. A first amplifier to which the compressed voltage is input, a second amplifier to which the output voltage of the first amplifier is input to a non-inverting input terminal, and the second voltage is input to an inverting input terminal; A power supply terminal to which the first voltage is supplied; And a driving transistor whose gate terminal is connected to the output of the second amplifier, and in response to a switching request from the control unit, the first voltage or One of the second voltages is output to the output terminal.

  According to the present invention, in the invention described above, the n booster circuits generate a complementary first and second clock according to the pulse signal, a power supply node, and an output node. A plurality of rectifying elements connected in series with each other, and capacitive elements each having one end connected to a plurality of connection nodes of the plurality of rectifying elements, and from the power supply node of the plurality of connection nodes The other end of the capacitive element connected to the odd-numbered connection node receives the first clock signal, and the other end of the capacitive element connected to the even-numbered connection node from the power supply node of the plurality of connection nodes. Receives the second clock signal, and the controller reduces the driving capability of the clock generation circuit when the voltage output from the booster exceeds the specified voltage.

  Further, according to the present invention, when the voltage output from the boosting unit exceeds the specified voltage, the control unit lowers the frequency of the pulse signal output from the oscillation circuit and supplies the pulse signal to the boosting unit. Features.

  According to the present invention, in the boosting operation state, the charge amount supplied by the boosting unit is set to satisfy the boosting time required for the charge pump circuit, and in the post-boosting voltage maintaining state, the charge amount supplied by the boosting unit is set. The ripple width required for the charge pump circuit can be set. As a result, the charge pump circuit can satisfy the conflicting requirements between the above-described boost time and ripple width.

It is a block diagram which shows the structure of the charge pump circuit which concerns on 1st Embodiment. It is the schematic which showed the structure of the booster circuit which concerns on 1st Embodiment. FIG. 6 is a waveform diagram showing an operation of the charge pump circuit according to the first embodiment. It is a block diagram which shows the structure of the charge pump circuit which concerns on 2nd Embodiment. It is the schematic which showed the structure of the booster circuit which concerns on 2nd Embodiment. It is a wave form diagram showing operation of a charge pump circuit concerning a 2nd embodiment. It is a block diagram which shows the structure of the charge pump circuit which concerns on 3rd Embodiment. It is the schematic which showed the structure of the booster circuit which concerns on 3rd Embodiment. It is a wave form diagram showing operation of a charge pump circuit concerning a 3rd embodiment. It is a block diagram which shows the structure of the charge pump circuit which concerns on a prior art example. It is the schematic which showed the structure of the booster circuit which concerns on a prior art example. It is the wave form diagram which showed operation | movement of the charge pump circuit which concerns on a prior art example.

(First embodiment)
Hereinafter, a charge pump circuit according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic block diagram showing the configuration of the charge pump circuit 100 according to the first embodiment. In this figure, parts corresponding to those in FIG. 10 are denoted by the same reference numerals, and description thereof is omitted. As shown in the figure, the charge pump circuit 100 includes a control unit 10, an oscillation circuit 20, and a boosting unit 30. The load capacity Cload is a capacity that becomes a load of the charge pump circuit 100.
The control unit 10 starts an operation in response to a boosting start signal input from the outside, detects an output voltage Vout output from the boosting unit 30, and generates an operation signal Compout indicating whether or not to output a pulse signal Tos. 20 is output. Further, the control unit 10 outputs a boost signal Cont that switches between the boost operation state and the post-boost voltage maintaining state to the boost unit 30.
The oscillation circuit 20 outputs the pulse signal Tos to the booster 30 based on the boost start signal input from the outside and the operation signal Compout output from the controller 10. The booster 30 outputs a voltage boosted using the pulse signal Tos output from the oscillation circuit 20 and the boost signal Cont output from the controller 10.

  The control unit 10 includes a reference circuit 11, a detection circuit 12, a comparator circuit 13, a flip-flop 14, and an inverter 15. The flip-flop 14 is a set / reset-flip-flop, and the logic inversion signal of the boosting start signal is input to the set terminal S, the operation signal Compout output from the comparator circuit 13 is input to the reset terminal R, and the output terminal Q Are connected to the booster 30 and output a boost signal Cont to the booster 30.

  The booster 30 includes a plurality of booster circuits 31a1 to 31an. The booster circuits 31a1 to 31an are connected in parallel, and each receives a pulse signal Tos (pulse signal ck) output from the oscillation circuit 20, and receives a booster signal Cont (gate signal gate) output from the control unit 10. Is done. The booster circuits 31a1 to 31an have the same configuration, and hereinafter, when any one or all of the booster circuits 31a1 to 31an are shown as representatives, they are referred to as booster circuits 31a.

Next, FIG. 2 is a schematic diagram showing the configuration of the booster circuit 31a according to the first embodiment. As illustrated, the booster circuit 31a is a circuit that boosts the voltage of the Dickson method. The booster circuit 31a includes N-channel transistors 311a1 to 311ai, capacitors 312a1 to 312aj, an inverter 313, an inverter 314, and a power supply circuit.
The N-channel transistors 311a1 to 311ai are used as diode elements in which one of the source and the drain and the gate are connected, and are connected in series in the forward direction. The N-channel transistor 311ai, which is the final stage of the N-channel transistors 311a1 to 311ai connected in series in the forward direction, has one of the source and drain not connected to the gate connected to the output terminal Pout. In the N-channel transistor 311a1, the power supply voltage Vdd is input to one of a source and a drain, the other is connected to the gate of the N-channel transistor 311a2, and the output terminal 345 of the power supply circuit 34 is connected to the gate. Capacitors 312a1 to 312aj have one end connected to a connection point between N-channel transistors 311a1 to 311ai, and the other end connected alternately to the output terminal of one of inverters 313 and 314. In the following, when any one or all of the N-channel transistors 311a1 to 311ai are shown as representative, they are referred to as N-channel transistors 311a. Further, when any one or all of the capacitors 312a1 to 312aj are shown as a representative, they are referred to as a capacitor 312a.

The inverter 313 and the inverter 314 have power supply terminals connected to the output terminal 345 of the power supply circuit 34. As a result, the inverter 313 inverts the input pulse signal ck and outputs a pulse signal obtained by converting (level shifting) the peak value into a voltage input from the power supply circuit 34. The inverter 314 also inverts the pulse signal input from the inverter 313 and outputs a pulse signal obtained by converting the peak value into a voltage input from the power supply circuit 34 (level shift).
The power supply circuit 34 selects and outputs either the power supply voltage Vdd (first voltage) or a lower voltage (second voltage) according to the logic level of the input gate signal gate.

The power supply circuit 34 includes a comparator circuit 340, a resistor 341, a resistor 342, a comparator circuit 343, a P-channel transistor 344, an inverter 346, an inverter 347, a switch SW1, and a switch SW2. In the comparator circuit 340 (first amplifier), the reference voltage Vref2 is input to the non-inverting input terminal, and the voltage at the connection point J2 between the resistor 341 and the resistor 342 is input to the inverting input terminal. The voltage at the connection point J2 is a voltage obtained by dividing the voltage at the connection point J3 between the comparator circuit 340 and the comparator circuit 343 by the resistor 341 and the resistor 342. In the comparator circuit 343 (second amplifier), the voltage at the connection point J3 of the comparator circuit 340 is input to the non-inverting input terminal, the voltage at the connection point J1 is input to the inverting input terminal, and the output voltage is the P-channel transistor 344. Gate voltage. In the P-channel transistor 344, the power supply voltage Vdd is applied to one of a source and a drain, and the voltage at the connection point J1 is applied to the other.
Here, when the resistance values of the resistor 341 and the resistor 342 are Rx and Ry, respectively, the divided voltage (the voltage at the connection point J2) is the voltage at the connection point J3 × Ry / (Rx + Ry). Since the comparator circuit 340 determines the output voltage (the voltage at the connection point J3) so that the voltages at the non-inverting input terminal and the inverting input terminal are equal, the voltage at the connection point J3 = the reference voltage Vref2 × (Rx + Ry) / Ry. It becomes. The comparator circuit 343 also determines the output voltage (the gate voltage of the P-channel transistor 344) so that the voltages at the non-inverting input terminal and the inverting input terminal are equal. Therefore, the voltage at the connection point J1 = the reference voltage Vref2 × (Rx + Ry) / Ry.
The switch SW1 has the power supply voltage Vdd input at one end and the voltage of the output terminal 345 input at the other end. In the switch SW2, the voltage at the connection point J1 is input to one end, and the voltage of the output terminal 345 is input to the other end. The switches SW1 and SW2 are switched according to the logic level of the inverter 346, the inverter 347, and the input gate signal gate. When the gate signal gate is at L level, the switch SW2 is turned on and the switch SW1 is turned off. When the gate signal gate is at H level, the switch SW2 is turned off and the switch SW1 is turned on. That is, the power supply circuit 34 outputs the power supply voltage Vdd (first voltage) to the output terminal 345 when the H level gate signal gate is input. When an L level gate signal gate is input, a voltage of Vref2 × (Rx + Ry) / Ry (step-down voltage Vrr: second voltage) is output.

In the booster circuit 31a configured as described above, when the input gate signal gate is at the H level, the inverter 313 is generated each time the voltage of the input pulse signal ck changes between the power supply voltage Vdd and the ground voltage. Changes the voltage at the node JI1 between the ground voltage and the power supply voltage Vdd. Further, the inverter 314 inverts the voltage at the connection point JI1, and changes the output voltage between the power supply voltage Vdd and the ground voltage. As a result, the accumulated charge moves between the adjacent capacitors 312a via one N-channel transistor 311a (diode element). Each time the charge moves, the voltage at each connection point of the N-channel transistor 311a is increased by the amount of the power supply voltage Vdd by the inflowed charge.
Further, in the booster circuit 31a, when the input gate signal gate is at the L level, the inverter 313 is connected to the connection point JI1 every time the voltage of the input pulse signal ck changes between the power supply voltage Vdd and the ground voltage. The voltage is changed between the ground voltage and the step-down voltage Vrr. Further, the inverter 314 inverts the voltage at the connection point JI1, and changes the output voltage between the step-down voltage Vrr and the ground voltage. As a result, the accumulated charge moves between adjacent capacitors 312a via one N-channel transistor 311. Each time the charge moves, the voltage at each connection point of the N-channel transistor 311a is boosted by the stepped-down voltage Vrr by the inflowing charge.

  Next, the operation of the charge pump circuit 100 will be described. FIG. 3 is a waveform diagram showing the operation of the charge pump circuit 100 according to the first embodiment. The horizontal axis direction represents time, and the vertical axis direction represents the voltage (level) of each signal.

As shown in the drawing, at time t0, the detection circuit 12 outputs a detection voltage Va corresponding to the output voltage Vout being 0V. The comparator circuit 13 compares the detection voltage Va output from the detection circuit 12 with the reference voltage Vref output from the reference circuit 11 when the boost start signal changes from L (Low) level to H (High) level. Thus, it is detected that the detection voltage Va is lower than the reference voltage Vref, and an L level operation signal Compout indicating the output of the pulse signal Tos is output to the oscillation circuit 20. The flip-flop 14 is set in response to the boost start signal transitioning from the L level to the H level, and outputs the boost signal Cont at the H level from the output terminal Q.
The oscillation circuit 20 outputs a pulse signal Tos having a constant period according to the L-level operation signal Compout output from the comparator circuit 13 and the H level of the boost start signal. At this time, the booster circuits 31a1 to 31ai receive the pulse signal Tos (pulse signal ck).

  In the booster circuit 31 a provided in the booster unit 30, boosting is performed by the pulse signal Tos output from the oscillation circuit 20, and the output voltage Vout of the charge pump circuit 100 increases. Here, in the booster circuit 31a, since the input boost signal Cont is at the H level, the inverter 313 is connected to the connection point JI1 every time the voltage of the input pulse signal Tos changes between the power supply voltage Vdd and the ground voltage. Is changed between the ground voltage and the power supply voltage Vdd. Further, the inverter 314 inverts the voltage at the connection point JI1, and changes the output voltage between the power supply voltage Vdd and the ground voltage. As a result, the accumulated charge moves between adjacent capacitors 312a via one N-channel transistor 311a. Each time the charge moves, the voltage at the connection point of the N-channel transistor 311a is increased by the amount of the power supply voltage Vdd by the inflowed charge. Then, the output voltage Vout increases, and accordingly, the detection voltage Va of the detection circuit 12 also increases.

When the output voltage Vout of the charge pump circuit 100 becomes higher than the boost specified voltage Vload (specified voltage) at time t1, the detection voltage Va output from the detection circuit 12 becomes higher than the reference voltage Vref. The comparator circuit 13 detects that the detection voltage Va is higher than the reference voltage Vref, and outputs an H-level operation signal Compout to the oscillation circuit 20. The flip-flop 14 changes to the reset state according to the transition of the operation signal Compout from the L level to the H level, and outputs the L level boost signal Cont from the output terminal Q.
When the H-level operation signal Compout is input, the oscillation circuit 20 outputs an L-level pulse signal Tos to the booster circuit 31a. The booster circuit 31a stops the boosting operation because the input pulse signal Tos maintains the L level state. When the booster circuit 31a stops the boosting operation, the charge accumulated in the load capacitance Cload leaks through the DC current path of the detection circuit 12 and the like, and the output voltage Vout gradually decreases.
In the booster circuit 31a, since the input boost signal Cont is at the L level, the switch SW1 of the power supply circuit 34 is turned off and the switch SW2 is turned on. Thereby, the power supply voltage of the inverter 313 and the inverter 314 becomes the step-down voltage Vrr.

When the output voltage Vout of the charge pump circuit 100 becomes lower than the specified boost voltage Vload at time t2, the detection voltage Va output from the detection circuit 12 becomes lower than the reference voltage Vref. The comparator circuit 13 detects that the detection voltage Va is lower than the reference voltage Vref, and outputs an L-level operation signal Compout to the oscillation circuit 20. The oscillation circuit 20 outputs a pulse signal Tos having a constant period in accordance with the L level operation signal Compout output from the comparator circuit 13. At this time, in the booster circuit 31a, since the input boost signal Cont is at the L level, the inverter 313 is connected to the connection point every time the voltage of the input pulse signal Tos changes between the power supply voltage Vdd and the ground voltage. The voltage of JI1 is changed between the ground voltage and the step-down voltage Vrr. Further, the inverter 314 inverts the voltage at the connection point JI1, and changes the output voltage between the step-down voltage Vrr and the ground voltage. As a result, the accumulated charge moves between adjacent capacitors 312a via one N-channel transistor 311. Each time the charge moves, the voltage at the connection point of the N-channel transistor 311a is boosted by the step-down voltage Vrr by the inflowing charge.
However, the increase in the output voltage Vout is a gradual increase compared to the boosting operation state because the charge output from the boosting unit 30 becomes Vrr / Vdd. As the output voltage Vout increases gradually, the detection voltage Va also increases gradually.

  When the output voltage Vout becomes higher than the boost specified voltage Vload at time t3, the detection voltage Va output from the detection circuit 12 becomes higher than the reference voltage Vref. The comparator circuit 13 detects that the detection voltage Va is higher than the reference voltage Vref, and outputs an H-level operation signal Compout to the oscillation circuit 20. When the H-level operation signal Compout is input, the oscillation circuit 20 outputs an L-level pulse signal Tos to the booster circuit 31a. The booster circuit 31a stops the boosting operation because the input pulse signal Tos maintains the L level state. When the booster circuit 31a stops the boosting operation, the charge accumulated in the load capacitor Cload leaks through the DC current path of the detection circuit 12 or the like, and the output voltage Vout gradually decreases.

Thereafter, the operation from time t1 to time t3 described above is repeated. As described above, the charge pump circuit 100 changes in a range where the output voltage Vout includes the boost specified voltage Vload, and supplies charge to the load capacitor Cload.
As described above, the charge pump circuit 100 outputs the voltage used by the booster circuit 31a for boosting in the post-boosting voltage maintaining state to (Vrr / Vdd) times that of the boosting operation state, so that the voltage is output to the load capacitance Cload. The charge amount to be increased is (Vrr / Vdd) times that of the boosting operation state. Thereby, the width of the ripple generated in the voltage maintaining state after boosting can be reduced.

  By using such a configuration, even if the amount of charge output from the booster 30 per cycle of the pulse signal Tos is increased in order to satisfy the request for the boost time in the boost operation state, the boost in the post-boost voltage maintaining state is achieved. The charge amount per cycle of the pulse signal Tos output from the unit 30 can be reduced to (Vrr / Vdd) times the boost operation state, and exceeds the boost specified voltage Vload of the output voltage Vout in the post-boost voltage maintaining state. The voltage value of the minute can be made small. For example, a comparison with the case where the charge amount is not reduced in the voltage maintaining state after boosting as described above (prior art) is as follows. In the above-described prior art, when the load capacitance Cload = 100 pF, the boost specified voltage Vload = 7 V, the boost time Tload ≦ 2.8 μs, and the period Tosc = 200 ns of the pulse signal Tos output from the oscillation circuit 20, the ripple width is 0. Said 5V. In this case, the voltage exceeding the boost specified voltage Vload was 0.49V. When the charge pump circuit 100 of the first embodiment is calculated by simulation under the same conditions (Vdd = 3.9V, Vrr = 3.0V), the voltage exceeding the boost specified voltage Vload is 0.20V, which is higher than that of the prior art. An amplitude improvement effect of about 60% was shown.

Note that the charge pump circuit 100 can change the amount of charge to be output in the post-boosting voltage maintaining state based on the voltage dividing ratio of the resistor 341 and the resistor 342. As a result, the charge pump circuit 100 can finely adjust the ripple width as compared with the first embodiment.
In addition, since the power supply circuit 34 is composed of two stages of amplifiers, the influence on the voltage fluctuation of the power supply voltage (first voltage) can be reduced. That is, when the divided voltage of the voltage dividing circuit composed of the resistor 341 and the resistor 342 connected in series between the power supply voltage and the ground voltage is directly input to the non-inverting input terminal of the comparator circuit 343, The influence of the fluctuation of the voltage Vdd is transmitted to the step-down voltage Vrr via the voltage dividing node (resistance connection point) of the voltage dividing circuit. However, in the power supply circuit 34 in the present embodiment, the output voltage of the comparator circuit 340 is input to the non-inverting input terminal of the comparator circuit 343, and the voltage dividing circuit is between the output of the comparator circuit 340 and the ground terminal. It is set as the structure provided in. Therefore, the divided voltage of the voltage dividing circuit (the voltage at the connection point J2) is not affected by the voltage fluctuation of Vdd, so that the voltage fluctuation of the step-down voltage Vrr due to the voltage fluctuation of the power supply voltage Vdd can be reduced.

(Second Embodiment)
FIG. 4 is a schematic block diagram showing the configuration of the charge pump circuit 200 according to the second embodiment. In this figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. As shown in the figure, the charge pump circuit 200 includes a control unit 10a, an oscillation circuit 20, and a boosting unit 40. The load capacity Cload is a capacity that becomes a load of the charge pump circuit 200.
The control unit 10a starts an operation in response to a boosting start signal input from the outside, detects an output voltage Vout output from the boosting unit 40, and generates an operation signal Compout indicating whether or not to output a pulse signal Tos. 20 is output. In addition, the control unit 10a outputs a boost signal Cont that switches between the boost operation state and the post-boost voltage maintaining state to the boost unit 40.
The oscillation circuit 20 outputs the pulse signal Tos to the boosting unit 40 based on the boosting start signal input from the outside and the operation signal Compout output from the control unit 10a. The booster 40 outputs a voltage boosted using the pulse signal Tos output from the oscillation circuit 20 and the boost signal Cont output from the controller 10a.

  The control unit 10 a includes a reference circuit 11, a detection circuit 12, a comparator circuit 13, a flip-flop 14, and an inverter 15. The flip-flop 14 is a set / reset-flip-flop, and the logic inversion signal of the boosting start signal is input to the set terminal S, the operation signal Compout output from the comparator circuit 13 is input to the reset terminal R, and the output terminal Q Are connected to the booster 40 and output a boost signal Cont to the booster 40.

  The boosting unit 40 includes a plurality of boosting circuits 41a1 to 41an. The booster circuits 41a1 to 41an are connected in parallel, and each receives the pulse signal Tos (pulse signal ck) output from the oscillation circuit 20 and the booster signal Cont (gate signal gate) output from the control unit 10a. The booster circuits 41a1 to 41an have the same configuration, and hereinafter, when any one or all of the booster circuits 41a1 to 41an are shown as representatives, they are referred to as booster circuits 41a.

  Next, FIG. 5 is a schematic diagram showing the configuration of the booster circuit 41a according to the second embodiment. As illustrated, the booster circuit 41a is a circuit that boosts the voltage of the Dickson method. The booster circuit 41a includes i N-channel transistors 311a1 to 311ai and N-channel transistors 311a1 to 311a1 connected in series in the forward direction between a power supply terminal to which a power supply voltage Vdd is supplied and the output terminal Pout. 311ai includes capacitors 312a1 to 312aj, one end of which is connected to the connection point, inverter 315, inverter 316, inverter 317, inverter 318, switch SW3 and switch SW4. The N-channel transistors 311a1 to 311ai are used as diode elements with either one of the source and drain connected to the gate.

The power supply voltage Vdd is supplied to the anode of the first N-channel transistor 311a1 of the N-channel transistors 311a1 to 311ai connected in series in the forward direction. In addition, a boosted voltage is output from the cathode of the final stage (N-channel transistor 311ai) of N-channel transistors 311a1 to 311ai connected in series in the forward direction. At the other end of each of the capacitors 312a1 to 312aj, a signal obtained by inverting the pulse signal ck output only from the inverter 315 and the inverter 316 or the inverter 315, and a pulse signal ck output only from the inverter 317 and the inverter 318 or the inverter 318, and In-phase signals are alternately input.
In the switch SW3, the output voltage of the inverter 316 is input to one end, and the voltage of the connection point JI2 (output voltage of the inverter 315) is input to the other end. Further, the switch SW4 has one end to which the output voltage of the inverter 318 is input, and the other end to which the voltage at the connection point JI2a (the output voltage of the inverter 317) is input. The switches SW3 and SW4 are switched according to the logic level of the input boost signal Cont. When the boost signal Cont is at the L level, both the switch SW3 and the switch SW4 are turned off, and when the boost signal Cont is at the H level, both the switch SW3 and the switch SW4 are turned on.

That is, the other end of the capacitive element (capacitor 312a1, 312a3...) Connected to the odd-numbered connection node among the connection nodes of the N-channel transistors 311a1 to 311ai connected in series in the forward direction is an H level boost signal. When Cont is input, a signal obtained by inverting the pulse signal ck is input by the inverter 315 and the inverter 316. In addition, a signal in phase with the pulse signal ck is input to the other end of the capacitive element (capacitors 312a2, 312a4...) Connected to the even-numbered connection node by the inverter 317 and the inverter 318.
On the other hand, the other end of the capacitive element (capacitor 312a1, 312a3...) Connected to the odd-numbered connection node among the connection nodes of the N-channel transistors 311a1 to 311ai connected in series in the forward direction is an L level boost signal. When Cont is input, a signal obtained by inverting the pulse signal ck is input only by the inverter 315. Further, the other end of the capacitive element (capacitors 312a2, 312a4,...) Connected to the even-numbered connection nodes receives a signal in phase with the pulse signal ck only by the inverter 317. Therefore, when the switch SW3 and the switch SW4 are turned off, the drive capability of the inverter that drives the other ends of the capacitors 312a1 to 312aj is lower than that when the switch SW3 and the switch SW4 are turned on. As a result, the voltage change at the connection point JI2 and the connection point JI2a becomes gradual, and the movement speed of the accumulated charge between the connection nodes of the N-channel transistors 311a1 to 311ai becomes slow.

In the booster circuit 31a configured as described above, when the input gate signal gate is at the H level, the inverter 315 is output each time the voltage of the input pulse signal ck changes between the power supply voltage Vdd and the ground voltage. The inverter 316 changes the voltage at the node JI2 between the ground voltage and the power supply voltage Vdd. Further, the inverter 317 and the inverter 318 invert the voltage at the connection point JI2, and change the output voltage of the voltage at the connection point JI2a between the power supply voltage Vdd and the ground voltage. As a result, the accumulated charge moves between adjacent capacitors 312a via one N-channel transistor 311a. Each time the charge moves, the voltage at the connection point of the N-channel transistor 311a is increased by the amount of the power supply voltage Vdd by the inflowed charge.
Further, in the booster circuit 31a, when the input gate signal gate is at the L level, only when the voltage of the input pulse signal ck changes between the power supply voltage Vdd and the ground voltage, only the inverter 315 is connected to the connection point. The voltage of JI2 is changed between the ground voltage and the power supply voltage Vdd. Only the inverter 317 inverts the voltage at the connection point JI2 and changes the voltage at the connection point JI2a between the power supply voltage Vdd and the ground voltage. As a result, the accumulated charge moves between the adjacent capacitors 312a via one N-channel transistor 311a. However, compared to the case where the H level boost signal Cont is input, the inverter driving the capacitor Since the driving ability is lowered, the movement speed of the charge between the capacitors is slowed, and the voltage to be added rises gently. Each time the charge moves, the voltage at the connection point of the N-channel transistor 311a is increased by the amount of the power supply voltage Vdd by the inflowed charge. As a result, the boosted voltage output from the cathode (output terminal Pout) of the N-channel transistor 311ai also gradually increases.

  Next, the operation of the charge pump circuit 200 will be described. FIG. 6 is a waveform diagram showing the operation of the charge pump circuit 200 according to the second embodiment. The horizontal axis direction represents time, and the vertical axis direction represents the voltage (level) of each signal.

As shown in the drawing, at time t0, the detection circuit 12 outputs a detection voltage Va corresponding to the output voltage Vout being 0V. The comparator circuit 13 compares the detection voltage Va output from the detection circuit 12 with the reference voltage Vref output from the reference circuit 11 when the boost start signal changes from L (Low) level to H (High) level. Thus, it is detected that the detection voltage Va is lower than the reference voltage Vref, and an L level operation signal Compout indicating the output of the pulse signal Tos is output to the oscillation circuit 20. The flip-flop 14 is set in response to the boost start signal transitioning from the L level to the H level, and outputs the boost signal Cont at the H level from the output terminal Q.
The oscillation circuit 20 outputs a pulse signal Tos having a constant period according to the L-level operation signal Compout output from the comparator circuit 13 and the H level of the boost start signal. At this time, the booster circuits 41a1 to 41ai receive the pulse signal Tos (pulse signal ck).
In the booster circuit 41 a provided in the booster 40, boosting is performed by the pulse signal ck (pulse signal Tos) output from the oscillation circuit 20, and the output voltage Vout of the charge pump circuit 200 increases. Here, in the booster circuit 41a, since the input boost signal Cont is at the H level, the inverter 315 and the inverter 316 change the voltage at the node JI2 between the ground voltage and the power supply voltage Vdd. Further, the inverter 317 and the inverter 318 invert the voltage at the connection point JI2, and change the output voltage of the voltage at the connection point JI2a between the power supply voltage Vdd and the ground voltage. As a result, the accumulated charge moves between adjacent capacitors 312a via one N-channel transistor 311a. Each time the charge moves, the voltage at the connection point of the N-channel transistor 311a is increased by the amount of the power supply voltage Vdd by the inflowed charge. Then, the output voltage Vout increases, and accordingly, the detection voltage Va of the detection circuit 12 also increases.

When the output voltage Vout of the charge pump circuit 200 becomes higher than the boost specified voltage Vload (specified voltage) at time t1, the detection voltage Va output from the detection circuit 12 becomes higher than the reference voltage Vref. The comparator circuit 13 detects that the detection voltage Va is higher than the reference voltage Vref, and outputs an H-level operation signal Compout to the oscillation circuit 20. The flip-flop 14 changes to the reset state according to the transition of the operation signal Compout from the L level to the H level, and outputs the L level boost signal Cont from the output terminal Q.
When the H level operation signal Compout is input, the oscillation circuit 20 outputs the L level pulse signal Tos to the booster circuit 41a. The booster circuit 41a stops the boosting operation because the input pulse signal Tos maintains the L level state. When the booster circuit 41a stops the boosting operation, the charge accumulated in the load capacitance Cload leaks through the DC current path of the detection circuit 12 or the like, and the output voltage Vout gradually decreases.
In the booster circuit 41a, since the input boost signal Cont becomes L level, the switches SW3 and SW4 are turned off, and only the inverter 315 is connected to the connection point JI2 and only the inverter 316 is connected to the connection point JI2a. Is done. That is, the driving capability of the clock generation circuit is reduced compared to the boosting operation state.

  At time t2, when the output voltage Vout of the charge pump circuit 200 becomes lower than the boost specified voltage Vload, the detection voltage Va output from the detection circuit 12 becomes lower than the reference voltage Vref. The comparator circuit 13 detects that the detection voltage Va is lower than the reference voltage Vref, and outputs an L-level operation signal Compout to the oscillation circuit 20. The oscillation circuit 20 outputs a pulse signal ck (pulse signal Tos) having a constant period in accordance with the L level operation signal Compout output from the comparator circuit 13. At this time, in the booster circuit 41a, since the input boost signal Cont is at the L level, when the input gate signal gate is at the L level, the voltage of the input pulse signal ck is between the power supply voltage Vdd and the ground voltage. Only, the inverter 315 alone changes the voltage at the node JI2 between the ground voltage and the power supply voltage Vdd. Only the inverter 317 inverts the voltage at the connection point JI2 and changes the voltage at the connection point JI2a between the power supply voltage Vdd and the ground voltage. That is, by reducing the driving capability of the clock generation circuit, the voltage change at the connection points JI2 and JI2a is made gradual compared to the boosting operation state as shown in FIG. As a result, the accumulated charge moves between the adjacent capacitors 312a through one N-channel transistor 311a, but the movement of charges between capacitors compared to the case where the H level boost signal Cont is input. The speed becomes slow, and the voltage to be added rises gently. Each time the charge moves, the voltage at the connection point of the N-channel transistor 311a is increased and boosted by the power supply voltage Vdd by the inflowed charge, but the voltage change becomes gentle. As a result, the boosted voltage output from the cathode (output terminal Pout) of the N-channel transistor 311ai also gradually increases.

  When the output voltage Vout becomes higher than the boost specified voltage Vload at time t3, the detection voltage Va output from the detection circuit 12 becomes higher than the reference voltage Vref. The comparator circuit 13 detects that the detection voltage Va is higher than the reference voltage Vref, and outputs an H-level operation signal Compout to the oscillation circuit 20. When the H level operation signal Compout is input, the oscillation circuit 20 outputs the L level pulse signal Tos to the booster circuit 41a. The booster circuit 41a stops the boosting operation because the input pulse signal Tos maintains the L level state. When the boosting is stopped, the charge accumulated in the load capacitance Cload leaks through the DC current path of the detection circuit 12 or the like, and the output voltage Vout gradually decreases.

Thereafter, the operation from time t1 to time t3 described above is repeated. As described above, the charge pump circuit 200 changes in a range in which the output voltage Vout includes the boost specified voltage Vload, and supplies charge to the load capacitor Cload.
As described above, the charge pump circuit 200 reduces the amount of charge output to the load capacitance Cload by reducing the drive capability of the clock generation circuit that drives the capacitor used by the booster circuit 41a for boosting in the post-boost voltage maintaining state. . Thereby, the width of the ripple generated in the voltage maintaining state after boosting can be reduced.

  By using such a configuration, even if the amount of charge output from the boosting unit 40 per cycle of the pulse signal Tos is increased in order to satisfy the request for the boosting time in the boosting operation state, the boosting unit in the post-boosting voltage maintaining state It is possible to reduce the amount of charge per cycle of the pulse signal Tos output by 40 as compared with the amount of charge in the boosting operation state, and in the voltage maintaining state after boosting, the voltage that exceeds the boosting specified voltage Vload of the output voltage Vout The value can be small. For example, as in the first embodiment, the charge pump circuit 200 according to the second embodiment is calculated by simulation under the same conditions (the channel width W of the inverter circuit is halved to reduce the inverter driving capability) The voltage exceeding the specified boost voltage Vload was 0.30 V, showing an amplitude improvement effect of about 39% compared to the prior art.

  Note that the charge pump circuit 200 can change the amount of electric charge output in the voltage maintaining state after boosting the inverter by appropriately changing the drive capability ratio of the inverter constituting the clock generation circuit. For example, the ratio W / L between the gate width (W) and the gate length (L) of the transistor is m: n between the inverter 316 and the inverter 315 and between the inverter 318 and the inverter 317, and clock generation is performed. By setting the driving force of the circuit to (m + n): n in the boosting operation state and the boosted voltage maintaining state, it is possible to finely adjust the ripple width.

(Third embodiment)
FIG. 7 is a schematic block diagram showing the configuration of the charge pump circuit 300 according to the third embodiment. In this figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. As shown in the figure, the charge pump circuit 300 includes a control unit 10b, an oscillation circuit 20, and a boosting unit 50. The load capacity Cload is a capacity that becomes a load of the charge pump circuit 300.
The control unit 10b starts an operation in response to a boosting start signal input from the outside, detects an output voltage Vout output from the boosting unit 50, and generates an operation signal Compout indicating whether or not to output the pulse signal Tos. 20 is output.
The oscillation circuit 20 outputs the pulse signal Tos to the frequency divider circuit 21 and the like based on the boosting start signal input from the outside and the operation signal Compout output from the control unit 10b.

  The control unit 10b includes a reference circuit 11, a detection circuit 12, a comparator circuit 13, a flip-flop 14, an inverter 15, a frequency dividing circuit 21, a NAND circuit 22, a NAND circuit 23, an inverter 24, and a NAND circuit 25. The flip-flop 14 is a set / reset-flip-flop, and the logic inversion signal of the boosting start signal is input to the set terminal S, the operation signal Compout output from the comparator circuit 13 is input to the reset terminal R, and the output terminal Q Are connected to the frequency divider circuit 21, the NAND circuit 22 and the inverter 24, and output the boost signal Cont to these circuits. The frequency dividing circuit 21 outputs to the NAND circuit 23 a pulse signal TosHLF in which the frequency of the pulse signal Tos is lowered according to the logic level of the boost signal Cont. In other words, the circuit composed of the frequency divider circuit 21, the NAND circuit 22, the NAND circuit 23, the inverter 24, and the NAND circuit 25 has a pulse signal Tos2 having the same frequency as the pulse signal Tos when the logical level of the boost signal Cont is H level. When the logical level of the boost signal Cont is L level, the pulse signal Tos2 obtained by lowering the frequency of the pulse signal Tos is output to the boost unit 50.

The booster 50 outputs a voltage boosted using the pulse signal Tos2 output from the NAND circuit 25.
The boosting unit 50 includes a plurality of boosting circuits 51a1 to 51an. The booster circuits 51a1 to 51an are connected in parallel, and each receives a pulse signal Tos2 (pulse signal ck) output from the control unit 10b. The booster circuits 51a1 to 51an have the same configuration, and hereinafter, when any one or all of the booster circuits 51a1 to 51an are shown as representatives, they are referred to as booster circuits 51a.

Next, FIG. 8 is a schematic diagram showing the configuration of the booster circuit 51a according to the third embodiment. As illustrated, the booster circuit 51a is a circuit that boosts the voltage of the Dickson method. The booster circuit 51a includes i N-channel transistors 311a1 to 311ai and N-channel transistors 311a1 and 311a1 connected in series in the forward direction between the power supply terminal to which the power supply voltage Vdd is supplied and the output terminal Pout. ˜311ai are constituted by capacitors 312a1 to 312aj having one end connected to a connection point between them. The N-channel transistors 311a1 to 311ai are used as diode elements with either one of the source and drain connected to the gate.
The power supply voltage Vdd is supplied to the anode of the first N-channel transistor 311a1 of the N-channel transistors 311a1 to 311ai connected in series in the forward direction. In addition, a boosted voltage is output from the cathode of the final stage (N-channel transistor 311ai) of N-channel transistors 311a1 to 311ai connected in series in the forward direction. A signal obtained by inverting the pulse signal ck output from the inverter 319 and a signal in phase with the pulse signal ck via the inverters 319 and 320 are alternately input to the other ends of the capacitors 312a1 to 312aj.

In the booster circuit 51a configured as described above, every time the voltage of the input pulse signal ck changes between the power supply voltage Vdd and the ground voltage when the logic level of the booster signal Cont is H level, Inverter 319 changes the voltage at node JI3 between the ground voltage and power supply voltage Vdd. The inverter 320 inverts the voltage at the connection point JI3 and changes the output voltage between the power supply voltage Vdd and the ground voltage. As a result, the accumulated charge moves between adjacent capacitors 312a via one N-channel transistor 311a. Each time the charge moves, the voltage at the connection point of the N-channel transistor 311a is increased by the amount of the power supply voltage Vdd by the inflowed charge.
Further, in the booster circuit 51a, when the logic level of the booster signal Cont is L level, the frequency of the input pulse signal ck decreases, and the voltage change of the connection point JI3 between the ground voltage and the power supply voltage is repeated. The repetition period is extended. As a result, the movement speed of the charge between the capacitors is slowed, and the voltage added to the power supply voltage Vdd gradually increases. As a result, the boosted voltage output from the cathode of the N-channel transistor 311ai also gradually decreases. Will rise.

  Next, the operation of the charge pump circuit 300 will be described. FIG. 9 is a waveform diagram showing the operation of the charge pump circuit 300 according to the third embodiment. The horizontal axis direction represents time, and the vertical axis direction represents the voltage (level) of each signal.

As shown in the drawing, at time t0, the detection circuit 12 outputs a detection voltage Va corresponding to the output voltage Vout being 0V. The comparator circuit 13 compares the detection voltage Va output from the detection circuit 12 with the reference voltage Vref output from the reference circuit 11 when the boost start signal changes from L (Low) level to H (High) level. Thus, it is detected that the detection voltage Va is lower than the reference voltage Vref, and an L level operation signal Compout indicating the output of the pulse signal Tos is output to the oscillation circuit 20. The flip-flop 14 is set in response to the boost start signal transitioning from the L level to the H level, and outputs the boost signal Cont at the H level from the output terminal Q.
The oscillation circuit 20 outputs a pulse signal Tos having a constant period to the frequency divider circuit 21 in accordance with the L level operation signal Compout output from the comparator circuit 13 and the H level of the boost start signal.
Since the logical level of the boost signal Cont is H level, the control unit 10b outputs a pulse signal Tos2 having the same frequency as the pulse signal Tos to the boost unit 50.
In the booster circuit 51a provided in the booster unit 50, boosting is performed by the pulse signal Tos2 output from the control unit 10b, and the output voltage Vout of the charge pump circuit 300 increases. As the output voltage Vout increases, the detection voltage Va of the detection circuit 12 also increases.

When the output voltage Vout of the charge pump circuit 300 becomes higher than the boost specified voltage Vload (specified voltage) at time t1, the detection voltage Va output from the detection circuit 12 becomes higher than the reference voltage Vref. The comparator circuit 13 detects that the detection voltage Va is higher than the reference voltage Vref, and outputs an H-level operation signal Compout to the oscillation circuit 20. The flip-flop 14 changes to the reset state according to the transition of the operation signal Compout from the L level to the H level, and outputs the L level boost signal Cont from the output terminal Q.
When the H-level operation signal Compout is input, the oscillation circuit 20 outputs an L-level pulse signal Tos to the control unit 10b. The control unit 10b sets the logic level of the pulse signal Tos2 to the L level.
The booster circuit 51a stops the boosting operation because the input pulse signal Tos2 maintains the L level state. When the booster circuit 51a stops the boosting operation, the charge accumulated in the load capacitor Cload leaks through the DC current path of the detection circuit 12 or the like, and the output voltage Vout gradually decreases.

At time t2, when the output voltage Vout of the charge pump circuit 300 becomes lower than the boost specified voltage Vload, the detection voltage Va output from the detection circuit 12 becomes lower than the reference voltage Vref. The comparator circuit 13 detects that the detection voltage Va is lower than the reference voltage Vref, and outputs an L-level operation signal Compout to the oscillation circuit 20. The oscillation circuit 20 outputs a pulse signal Tos having a constant period in accordance with the L level operation signal Compout output from the comparator circuit 13. Since the boost signal Cont is at the L level, the control unit 10b outputs the pulse signal Tos2 obtained by lowering the frequency of the pulse signal Tos to the boost unit 50. At this time, in the booster circuit 51a, each time the voltage of the input pulse signal Tos2 changes, the accumulated charge moves between the adjacent capacitors 312a through one N-channel transistor 311a. Each time the charge moves, the voltage at the connection point of the N-channel transistor 311a is increased by the amount of the power supply voltage Vdd by the inflowed charge.
However, the increase in the output voltage Vout causes the frequency of the input pulse signal Tos2 to be lower than that in the step-up operation state, and the repetition period of the voltage change that the node JI3 repeats between the ground voltage and the power supply voltage is extended. As a result, the amount of charge output from the voltage boosting unit 50 per unit time (per cycle of the pulse signal Tos) decreases, and increases more slowly than in the boosting operation state. As the output voltage Vout increases gradually, the detection voltage Va also increases gradually.

  When the output voltage Vout becomes higher than the boost specified voltage Vload at time t3, the detection voltage Va output from the detection circuit 12 becomes higher than the reference voltage Vref. The comparator circuit 13 detects that the detection voltage Va is higher than the reference voltage Vref, and outputs an H-level operation signal Compout to the oscillation circuit 20. When the H-level operation signal Compout is input, the oscillation circuit 20 outputs an L-level pulse signal Tos to the control unit 10b. The controller 10b outputs an L level pulse signal Tos2 to the booster circuit 51a. The booster circuit 51a stops the boosting operation because the input pulse signal Tos2 maintains the L level state. When the booster circuit 51a stops the boosting operation, the charge accumulated in the load capacitor Cload leaks through the DC current path of the detection circuit 12 or the like, and the output voltage Vout gradually decreases.

Thereafter, the operation from time t1 to time t3 described above is repeated. As described above, the charge pump circuit 300 changes in a range in which the output voltage Vout includes the boost specified voltage Vload, and supplies charge to the load capacitor Cload.
As described above, the charge pump circuit 300 outputs to the load capacitance Cload because the amount of charge output per unit time (per cycle of the pulse signal Tos) decreases from the booster 50 in the post-boost voltage maintaining state. Reduce the amount of charge generated. Thereby, the width of the ripple generated in the voltage maintaining state after boosting can be reduced.

  By using such a configuration, even if the amount of charge output from the boosting unit 50 per cycle of the pulse signal Tos is increased in order to satisfy the request for the boosting time in the boosting operation state, the boosting unit in the post-boosting voltage maintaining state 50 can reduce the amount of charge per cycle of the pulse signal Tos output by 50 as compared with the amount of charge in the boosting operation state, and the voltage that exceeds the specified boost voltage Vload of the output voltage Vout in the post-boosting voltage maintenance state The value can be small. For example, as with the first and second embodiments, the charge pump circuit 300 of the third embodiment is calculated by simulation under the same conditions (the frequency of the pulse signal Tos is halved by the frequency divider circuit 21). The voltage exceeding the specified boost voltage Vload was 0.24 V, which showed an amplitude improvement effect of about 50% as compared with the prior art.

  Note that the charge pump circuit 300 can change the amount of charge output in the post-boosting voltage maintaining state by changing the frequency change degree of the frequency divider circuit 21 between the boosting operation state and the post-boosting voltage maintaining state. . As a result, the charge pump circuit 300 can finely adjust the ripple width as compared with the prior art.

  Note that the charge pump circuits of the first embodiment, the second embodiment, and the third embodiment may be appropriately combined. For example, the power supply circuit in the first embodiment, the change in the inverter driving capability in the second embodiment, and the reduction in frequency in the third embodiment may be combined. In order to confirm the effect of this configuration, a simulation was performed under the same conditions as in the conventional technique. As a result, the voltage exceeding the specified boost voltage Vload was 0.14 V, which showed an amplitude improvement effect of about 72% compared to the conventional technique. This proved to further reduce the ripple width.

100, 200, 300, 900 ... charge pump circuit,
10, 10a, 10b, 91 ... control unit,
11 ... reference circuit, 12 ... detection circuit, 13 ... comparator circuit,
14 ... flip-flop, 15 ... inverter, 20 ... oscillation circuit,
30, 40, 50, 93 ... boosting unit,
Compout ... operation signal, Cont ... boost signal, Tos, TosHLF, Tos2 ... pulse signal,
ck ... pulse signal, Q, Pout ... output terminal, gate ... gate signal,
31a, 31a1, 31an ... booster circuit,
312a, 312a1, 312a2, 312aj ... capacitors,
311, 311a, 311a1, 311a2, 311ai ... N-channel transistors,
313, 314, 346, 347 ... inverter,
341, 342 ... resistors, 340, 343 ... comparator circuits,
345 ... Output terminal, J1, J2, J3, JI1, JI2, JI2a, JI3 ... Connection point,
SW1, SW2 ... switch, 34 ... power supply circuit,
344 ... P-channel transistor,
41a, 41a1, 41an ... booster circuit,
315, 316, 317, 318 ... inverter,
SW3, SW4 ... switch,
21 ... frequency divider, 22, 23, 25 ... NAND circuit, 24 ... inverter,
51a, 51a1, 51an ... booster circuit,
319, 320 ... inverter,
931a, 931a1, 931an ... booster circuit,
932a1, 932ai ... diodes,
933a1, 933aj ... capacitors,
934 ... inverter, 94 ... output terminal,
Vload: step-up voltage, Va: detection voltage, Vrr: step-down voltage

Claims (4)

An oscillation circuit that outputs a pulse signal having a predetermined period;
A booster that includes n (n ≧ 1) booster circuits connected in parallel to boost the voltage, and that outputs a boosted voltage when the pulse signal is input;
The boosted voltage output from the boosting unit is compared with a predetermined specified voltage. When the voltage output from the boosting unit exceeds the specified voltage, one cycle of the pulse signal in the subsequent boosting operation A control unit that reduces the amount of charge output from the boosting unit around,
A charge pump circuit comprising: The n booster circuits are:
A power supply circuit that outputs either one of a predetermined first voltage and a second voltage lower than the first voltage;
Boosting using the voltage output from the power supply circuit,
The controller is
When the voltage output from the booster exceeds the specified voltage, the voltage output from the power supply circuit included in the n booster circuits is switched from the first voltage to the second voltage,
The power supply circuit is
A first amplifier to which a predetermined reference voltage is input to the non-inverting input terminal, and a voltage obtained by dividing the output voltage is input to the inverting input terminal;
A second amplifier in which an output voltage of the first amplifier is input to a non-inverting input terminal, and the second voltage is input to an inverting input terminal;
A power supply terminal to which the first voltage is supplied; and a drive transistor connected to an output terminal from which the second voltage is output and a gate terminal connected to the output of the second amplifier;
The charge pump circuit according to claim 1, wherein either the first voltage or the second voltage is output to the output terminal in response to a switching request from the control unit. The n booster circuits are:
A clock generation circuit for generating complementary first and second clocks in response to the pulse signal;
A plurality of rectifying elements connected in series between the power supply node and the output node;
A capacitive element having one end connected to a plurality of connection nodes of the plurality of rectifying elements,
The other end of the capacitive element connected to the odd-numbered connection node from the power supply node of the plurality of connection nodes receives the first clock signal,
The other end of the capacitive element connected to the even-numbered connection node from the power supply node of the plurality of connection nodes receives the second clock signal,
The controller is
3. The charge pump circuit according to claim 1, wherein when the voltage output from the boosting unit exceeds the specified voltage, the driving capability of the clock generation circuit is lowered. The controller is
4. The frequency of the pulse signal output from the oscillation circuit is lowered and supplied to the booster when the voltage output from the booster exceeds the specified voltage. Charge pump circuit.

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