JP2010288145A - Image processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control a drawing process and an image processing process by using the smallest possible buffer memory in a system which draws an image in each tile using a plurality of drawing sections and performs image processing requiring reference pixels in each tile in the subsequent process. <P>SOLUTION: An image processor is configured to have state variables including at least a state representing an initial state, a state representing an already drawn state, and a state representing an already used state, for each tile. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image processing apparatus that performs image processing in units of rectangular blocks on image data expanded in units of rectangular blocks on a memory.

  Conventionally, as image processing performed on image data stored on a memory buffer, there has been image processing performed on a rectangular block area basis. An image processing unit that performs image processing in units of rectangular block processing requires a larger reference area in order to perform image processing on the target rectangular block area (see FIG. 17 of Patent Document 1).

Japanese Patent Laid-Open No. 2004-220484

  In the conventional technique described above, the image processing unit needs to read a reference area wider than the target area from the memory buffer in which the image data is expanded in order to perform image processing of the target area. That is, when an image of a certain rectangular block area is stored in the memory buffer, image processing of that rectangular block area cannot be performed. This is because the reference area covers a part of the surrounding nine rectangular block areas as shown in FIG. Therefore, in the above-described technique, it is necessary to temporarily store an area composed of a large number of rectangular blocks corresponding to one page, for example, in a memory buffer, and then move to the next image processing process.

  The problem to be solved by the present invention is to reduce the size of the memory buffer.

  In order to solve the above-described problem, the present invention stores an image data transferred in units of rectangular blocks in a memory buffer, performs image processing based on the stored image data, and outputs processed data. Take the following measures: That is, it has a means for holding a state variable having at least a state indicating a storable state, a state indicating a stored state, and a state indicating an image processed for each rectangular block unit of the memory buffer.

  Further, the image processing apparatus further comprises means for generating an image processing request command when the above-described arbitrary rectangular block area is ready for image processing.

  Further, the above-described image processing apparatus has a queuing means for holding the above-described image processing request command.

  The first effect of the present invention is that the necessary capacity of the buffer memory can be reduced. Furthermore, since the process can proceed to the next image processing step without ending the storage in the large-capacity memory buffer, the time until the first image processed data is obtained is shortened.

  Further, according to the present invention, it is possible to effectively perform image processing for each subsequent rectangular block from a rectangular block area that is possible even if the processing order is changed without processing each rectangular block area in order. This has the effect of increasing the flexibility of the internal configuration of the image processing apparatus. For example, the upstream image transfer means as viewed from the memory buffer can be easily expanded to improve performance. Similarly, it is easy to improve the performance by expanding the image processing means downstream from the memory buffer to a plurality.

It is a block diagram explaining the image processing apparatus of this invention. It is a figure explaining the relationship between a rectangular block area | region and a reference area. 2 is a diagram illustrating a relationship between a page processed by the image processing apparatus and a buffer memory 101. FIG. It is a figure explaining a response | compatibility with a memory buffer and a flag table. It is a figure explaining a state transition. It is a figure explaining update of a flag table. It is a figure explaining the operation | movement which a control part performs when one rectangular block is written in the buffer memory. It is a figure explaining the operation | movement which a control part performs when the image processing of one rectangular block is completed. 2 is a configuration diagram of a smoothing circuit mounted in each of an image processing unit 1, an image processing unit 2, and an image processing unit 3. FIG. 2 is a block diagram showing detailed configurations of an image processing unit 1, an image processing unit 2, and an image processing unit 3. FIG. 3 is a diagram showing a configuration of a 3-state buffer 24. FIG. 11 is a time chart illustrating an operation of the SRAM peripheral circuit of FIG. 10. It is a figure which shows a 7 * 7 window. It is a figure which shows one example of the smoothing process performed in the logic circuit 41 of FIG. It is a figure which shows one example of the smoothing process performed in the logic circuit 41 of FIG. It is a figure which shows one example of the smoothing process performed in the logic circuit 41 of FIG. It is a figure which shows the example of the image obtained by smoothing.

Example 1
FIG. 1 is a block diagram illustrating the configuration of an image processing apparatus embodying the present invention.

  In the figure, reference numeral 103 denotes a spool memory which spools intermediate data for drawing for each rectangular block area sent from an upstream device (not shown). The drawing unit 1, the drawing unit 2, and the drawing unit 3 are drawing units that generate image data from intermediate data for each rectangular block area spooled in the spool memory 103.

  The rectangular blocks processed by the three drawing units may be determined in advance by equally dividing the page into three vertical columns. Alternatively, the drawing unit 1, the drawing unit 2, and the drawing unit 3 may be swung in order from the upper left rectangular block of the page in the main scanning direction. Alternatively, a method may be used in which a rendering unit that can perform processing without predetermined processing dynamically selects an unprocessed rectangular block.

  The drawing unit 1, the drawing unit 2, and the drawing unit 3 issue a REQ signal to the control unit 102 described later before writing the generated image data of the rectangular block area to the memory buffer 101. Writing to the memory buffer 101 is postponed until an ACK signal is returned. The REQ signal includes information for specifying a rectangular block area. Each drawing unit outputs WriteDONE when the drawing image has been written to the buffer memory 101. Communication of REQ, ACK, and WriteDONE is performed in units of rectangular block areas. Further, the REQ, ACK, and WriteDONE signals exist independently for each of the three drawing units.

  The flag table 106 has a state corresponding to all the rectangular block areas of the buffer memory 101 and is managed by the control unit 102 described later.

  The control unit 102 updates the flag table 106 in accordance with the input of the WriteDONE signal and the DONE signal. Further, referring to the state, drawing is permitted when all nine rectangular blocks including the rectangular block requested to be drawn from each drawing unit are I or W. This is for enabling determination of condition B described later.

  Further, the control unit 102 transmits an image processing request command to the queue 104 when a condition A described later in the flag table 106 is satisfied. The image processing request command is issued in units of drawing one rectangular block area. The image processing request command includes information specifying a rectangular block basin.

  The queue 104 is a queue buffer, and holds an image processing request command so that the command is not lost when none of the image processing unit 1, the image processing unit 2, and the image processing unit 3 is accepted.

  Any one of the image processing unit 1, the image processing unit 2, and the image processing unit 3 that is not performing the image processing operation receives the image processing request command from the queue 104 and performs image processing on the designated rectangular block region. When the image processing is completed, a DONE signal is returned to the control unit 102.

  The image data that has been subjected to image processing by the image processing unit 1, the image processing unit 2, and the image processing unit 3 is transferred to the subsequent buffer 105.

  FIG. 3 is a diagram showing the relationship between the page processed by the image processing apparatus and the buffer memory 101. In this embodiment, one page has a size corresponding to 12 rectangular blocks in the main scanning direction and 15 rectangular blocks in the sub-scanning direction. The size of the buffer memory 101 is 12 rectangular blocks in the main scanning direction and 5 rectangular blocks in the sub-scanning direction.

  FIG. 4 is a diagram for explaining the correspondence between the buffer memory 101 and the flag table 106. In this embodiment, the buffer memory has a rectangular block area of 12 blocks in the main scanning direction and 5 blocks in the sub-scanning direction, and the flag memory has the same configuration and holds a state value for each rectangular block.

  The transition of the state value of each rectangular block will be described with reference to FIG.

  Initially, all blocks are in an initial state and are in a drawable state. This state is represented as I (Initial). When the writing of the drawing unit is completed and WriteDONE is issued, the state is changed to a W (Writeten) state that is a written state. Subsequently, if the corresponding block is used for image processing, the state transits to the U (Used) state. Further, when the condition B described later is satisfied and the necessity of holding the image is eliminated, the state transitions to the first I state.

  FIG. 6 does not explain how the flag table 106 is updated.

  For the sake of explanation, a rectangular block whose position in the main scanning direction is x and whose position in the sub-scanning direction is y is (x, y).

  In FIG. 6A, three blocks have already been written. As described above, the control unit 102 permits drawing when all nine rectangular blocks including the rectangular block requested to be drawn from each drawing unit are I or W. For example, it is assumed that a REQ signal of a rectangular light (4, 0) is generated by any of the drawing units 1, 2, and 3. At time (a), the request is permitted because both the left and right blocks and the two downward blocks are I or W. Originally, (3, 4), (4, 4), (5, 4) should be checked as the upper block.

  FIG. 5B shows a state in which the process has progressed and a condition A (described later) for the rectangular block (6, 0) is satisfied and an image processing request command (6, 0) has been generated. Condition A is that all nine rectangular blocks around the target rectangular block are in the W or U state. Since the buffer memory at (b) corresponds to the upper end of the page, the upper block is out of the necessary condition and the condition A is satisfied.

  When the buffer memory 101 corresponds to the second and subsequent bands of the page memory, that is, when the flag table status is two or more rounds, (5, 4), (6, 4), (7, 4) are set as upward blocks. Need to refer.

  When any of the image processing units 1, 2, and 3 receives an image processing request command and completes the image processing, it is notified by the DONE signal, and the state of the corresponding rectangular block transits to U.

  FIG. 6C shows a state where the state of U is increasing. In the state of (c), a later-described condition B of the rectangular block of (3, 0) is satisfied, and (3, 0) transitions to I in FIG. Condition B is that all nine rectangular blocks around the target rectangular block are in the U or I state. Since the buffer memory at (c) corresponds to the upper end of the page, the upper block is out of the necessary condition and the condition A is satisfied.

  When the buffer memory 101 corresponds to the second and subsequent bands of the page memory, that is, when the flag table state is two or more rounds, (2, 4), (3, 4), (4, 4) are set as upward blocks. Need to refer.

  7 and 8 are diagrams for explaining the flow of processing performed by the control unit 102.

  FIG. 7 is a processing flow generated in the control unit 102 when any of the drawing units 1, 2, and 3 finishes writing the image data of the rectangular block to the buffer memory. In 602 of the figure, the control unit 102 first changes the state of the corresponding rectangular block from I to W. Next, it is checked from 603 to 607 whether there is a state change for each of the nine rectangular blocks that may be affected by the above change.

  First, at 603, one of nine blocks including the block whose state has been changed at 602 is set as a target block. In 604, it is checked whether all the surrounding nine rectangular blocks including the target rectangular block are W or U. This is condition A described above. If Yes, an image processing request command is generated at 606. If No, the target rectangle is changed to the next one in 607 unless the end is determined in 605 and the condition check in 604 is repeated. The condition A check is repeated 9 times and the process is completed.

  FIG. 8 is a processing flow generated in the control unit 102 when any one of the image processing units 1, 2, and 3 finishes the rectangular block image processing. In 702 of the figure, the control unit 102 first changes the state of the corresponding rectangular block from W to U. Next, it is checked from 703 to 707 whether there is a state change for each of the nine rectangular blocks that may be affected by the above change.

  First, in 703, one of nine blocks including the block whose state has been changed in 702 is set as a target block. In 704, it is checked whether all the surrounding nine rectangular blocks including the target rectangular block are U or I. This is condition B described above. If Yes, the target pixel is generated at 705. If the result is No, the target rectangle is changed to the next one in 706 unless the end is determined in 707, and the condition check in 704 is repeated. The condition B check is repeated 9 times and the process ends.

  FIG. 9 shows an example of what is implemented in each of the image processing units 1, 2, and 3. Here, each has a smoothing function. It is possible to improve the overall processing performance by operating the three image processing units in parallel.

  In the image processing unit illustrated in FIG. 9, the interface unit 10 reads necessary image data, that is, image data of an area including an overlapping portion around the rectangular block portion from the main memory 102. Further, the image data of only the area of the rectangular block portion is written back to the output portion 103 after being internally processed. In the figure, the interface unit 10 converts received data into serial data and transfers it to the storage unit 17 in synchronization with VCLK. The storage unit 17 receives the image signal sent from the interface unit 10, the storage unit 17 stores the main scanning 7 lines, and the smoothing unit 18 develops the main scanning 7 dots in a window shape and performs a smoothing process. , It is sent to the printer engine 200.

  Note that even when the image processing unit 107 and the image processing unit 108 perform image processing that performs filtering such as edge enhancement, the circuit configuration is similar in that it refers to peripheral pixels. That is, the storage unit 17 for holding the interface with the image data bus and the peripheral pixels, and the logic determination unit for determining the data of the target pixel from the peripheral pixels. The logic determination unit corresponds to the smoothing unit in FIG.

  FIG. 10 is a block diagram showing a detailed configuration of the image processing unit 20 shown in FIG. The image processing unit shown in FIG. 9 receives the serial image signal from the interface unit 10 of FIG. 9 in synchronization with the image transfer clock VCLK, the system clock SCLK having the same phase as the image clock VCLK and the frequency eight times, and the image clock VCLK. Will be sent.

  The serial image signal is input to the D0 terminal which is one of the input terminals of the three-state latch buffer 24, and the output Q0 of the three-state latch buffer 24 corresponding to D0 is input to the shift register 29 and the data of the SRAM 21. It is also input to the terminal I / O1. The SRAM addresses AD0 to AD6 are connected to seven address lines supplied from the address counter 22. The address length developed by these seven address lines is sufficient to store one line of the rectangular block and peripheral image data.

  Further, the read signal OE to the SRAM, the write signal WE, the latch signal CLK of the three-state buffer 24, the output enable signal OC, and the clear signal RESET of the address counter 22 are generated by the control circuit 23. Will be described later. The control circuit 23 creates a plurality of states by the system clock SCLK during one cycle of the image clock VCLK. Therefore, as described above, since SCLK is eight times the frequency of VCLK, a maximum of eight steps can be executed during one cycle of the image clock VLCK. Each buffer of the three-state latch buffer 24 includes a latch circuit 24a and a buffer circuit 24b as shown in FIG.

  Next, the operation of the SRAM peripheral circuit of FIG. 10 will be described with reference to the time chart shown in FIG. In the following description, the data of the nth pixel is indicated as data (n), and the address where the data is stored is indicated as adr (n). In FIG. 12, the first clock is input after the image clock VLCK (2) reaches the logic low level (time t1). At that time, the output enable signal OC (9) of the 3-state latch buffer 24 is in the FALSE state, and the buffer circuit in the 3-state latch buffer 24 is in the high impedance state. Then, the output of the data data (n−1) (see (10) buffer output) that has been output so far is stopped, and nothing is input to the data bus of the SRAM 21.

  When the second clock is input (time t2), the OE signal (5) becomes TRUE. At the same time, the SRAM 21 enters the read state (see (12) memory state), and the data data (n) stored at the address adr (n) is output onto the data bus (see (6) memory output data). Since the latch clock (7) rises at the third clock (time t3), the data data (n) output on the data bus is latched inside the three-state latch buffer 24. However, at this time, since the output enable signal OC (9) remains in the FALSE state, data is not output to the outside of the 3-state latch buffer 24. Therefore, bus collision does not occur.

  When the fourth clock is input (time t4), the output enable signal OE (5) of the SRAM 21 is in the FALSE state, and the SRAM 21 is in the floating state. When the fifth clock is input (time t5), the output enable signal OC (9) of the three-state latch buffer 24 changes to the TRUE state, and the latched data data (n) is output to the SRAM 21. Sent. However, since the write enable signal WE (11) is in the FALSE state, the SRAM 21 is not written.

  At the sixth clock (time t6), the write enable signal WE (11) of the SRAM 21 is set to TRUE state, and data (n) is written to the SRAM 21. When the seventh clock is input (time t7), the write operation is completed when the write enable signal WE is in the FALSE state. When the eighth clock is input (time t8), the address is updated from adr (n) to adr (n + 1), and a series of operations regarding data of one pixel is completed.

  By performing the above operation in the three-state latch buffer 24 and the SRAM 21, data output from the terminal of the SRAM 21 during one cycle of the image clock VCLK is input to another terminal having the same address. Furthermore, by sequentially sending data, image data of 7 lines is always stored. At the same time, image data is supplied to the shift registers 29 to 35.

  Each of the shift registers 29 to 35 has a bit length of 7 bits. They are developed in units of 7 dots in the main scanning direction by subjecting the 7 lines of image data sent from the 3-state latch buffer 24 to serial-parallel conversion. Send the image data of the dot. In the logic circuit 41, the transmitted 49-bit image data is applied to a 7 × 7 window as shown in FIG. 13, and the pixel of interest D4 is 1 / in the main scanning direction according to the predetermined logic described below. Divide into 4 dots a, b, c, d of size 4. Further, a signal LP for designating the magnitude of the laser light quantity is determined. Here, it is assumed that the laser light quantity designation signal P changes in units of the image clock VCLK.

  This logic circuit 41 is composed of an AND logic circuit, takes a logical product of a total of 49 data from the shift registers 29 to 35, and a, b, c, d obtained by dividing one pixel into four according to the result. A VDO signal indicating printing or non-printing of the section and a laser light quantity designation signal LP are output. The laser light quantity designation signal LP changes in units of 1 dot, and the VDO signal changes in units of 1/4 dots.

  FIG. 14 to FIG. 16 show examples of smoothing processing for lines close to the horizontal. In FIG. 14, the logic shown in the upper right of the figure is established. That is, 3C, 3D, 3E, 3F, 3G, 4A, 4B, and 4C are 0 (white), 4D, 4E, 4F, 4G, 5A, 5B, 5C, 5D, 5E, 5F, and 5G are 1 (black). In this case, the VDO of the target pixel 4D is set to a = 0, b = 1, c = 1, and d = 0. Similarly, in the case of FIG. 15, the VDO of the target pixel 4D is set to a = 0, b = 1, c = 1, and d = 0. In the case of FIG. 16, it is assumed that the VDO of the pixel of interest 4D is a = 0, b = 0, c = 1, and d = 0.

  FIG. 17 shows the printing results obtained by these processes. This figure shows an example when the unit of the rectangular block output by the image processing is 64 × 64. As an image processing unit, a 70 × 70 image region including an overlapping portion is processed.

  As described above, by dividing one pixel into quarters and printing or not printing each section, it is possible to smooth the edges and the outline of the characters. This is because the latent image potential on the photosensitive drum can be smoothed by this processing, and is a phenomenon peculiar to electrophotography. Although the smoothing process for lines close to horizontal has been described here, lines such as lines close to vertical, diagonal lines, and character outlines can also be detected by taking the logical product of logical data of 49 pixels. In either case, the latent image potential on the photosensitive drum is smoothly connected, and the printing area of the target pixel and the laser light quantity are determined so as to smooth the printing result.

  The outputs a, b, c, and d of the logic circuit 41 are converted into a data bus protocol by the bus interface circuit 10 and output.

101 Image buffer memory 102 Control unit 103 Spool memory 104 Queue buffer 105 Buffer

Claims (3)

Image transfer means for transferring image data in units of rectangular blocks;
A memory for storing image data transferred by the image transfer means;
An image processing unit that performs image processing based on the image data stored in the memory and outputs processed data;
An image processing apparatus having a state table having a state variable having at least a state indicating a storable state, a state indicating a stored state, and a state indicating an image processed for each rectangular block unit. The image processing apparatus according to claim 1.
An image processing apparatus comprising: means for generating an image processing request command when an arbitrary rectangular block region is ready for image processing. The image processing apparatus according to claim 2,
An image processing apparatus having a queue for holding an image processing request command.

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