JP2010288005A - Delay locked loop circuit and interface circuit - Google Patents

Abstract

A DLL circuit capable of accurately generating a delayed clock signal having a predetermined phase difference with respect to an external clock signal is provided.
A DLL circuit includes a control unit and n (n is an integer of 2 or more) delay units D connected in series between first and second nodes ND (0) and ND (n). (1) to D (n). An external clock signal CLKIN is input to the first node ND (0). The control unit 10 performs control according to the phase difference between the output signals CLKA and CLKB of two predetermined delay units D (4) and D (n) among the n delay units D (1) to D (n). The voltage VC is output. Each delay unit D has the same configuration, and outputs a delay buffer I that outputs a signal delayed by a delay time according to the control voltage VC with respect to the input signal, and outputs the delay buffer I with the amplitude of the power supply voltage. And a shaping buffer J for shaping and outputting a rectangular wave. Output signals of the delay units D (4) to D (n) are used as delayed clock signals.
[Selection] Figure 1

Description

  The present invention relates to a delay locked loop circuit. The present invention also relates to an interface circuit that converts a serial signal into a parallel signal using a delayed clock signal generated by a delay locked loop circuit.

  A delay locked loop (DLL) circuit is known as a circuit that generates a delayed clock signal using an input clock signal. In a DLL circuit, the accuracy of the generated delayed clock signal is often a problem.

  For example, Japanese Patent Laying-Open No. 2002-163034 (Patent Document 1) discloses a DLL circuit configured so as not to be affected by loop jitter caused by feedback. The DLL circuit of this document includes an input buffer that receives an external clock signal, a multiphase clock generation circuit, a selection circuit, first and second variable delay circuits, a clock buffer dummy, a phase comparison circuit, a filter And a clock buffer. The multiphase clock generation circuit receives the output of the input buffer and generates a multiphase clock. The selection circuit receives the multiphase clock output from the multiphase clock generation circuit and selects one of them. The first variable delay circuit delays the output of the selection circuit. The clock buffer dummy receives the output of the first variable delay circuit. The phase comparison circuit detects a phase difference between the output from the multiphase clock generation circuit and the output of the clock buffer dummy. The filter smoothes the output of the phase comparison circuit. The delay time of the first variable delay circuit varies depending on the filter output. The second variable delay circuit receives the output of the input buffer, and the delay time changes depending on the filter output. The clock buffer receives the output of the second variable delay circuit and outputs the delay clock to the load.

  According to the above configuration, the phase comparison circuit, the filter, the first variable delay circuit, and the clock buffer dummy constitute a control system loop. Since the feedback buffer is not included in the signal paths of the input buffer, the second variable delay circuit, and the clock buffer, the delay clock output from the clock buffer is not affected by jitter due to the feedback loop.

  Japanese Patent Laying-Open No. 2003-264452 (Patent Document 2) discloses a DLL circuit in which the accuracy of the delay time of the delay clock is improved by preventing pseudo lock. The DLL circuit of this document includes a fixed pulse width divider, a delay circuit, an inverter, a phase comparator, a charge pump, and a loop filter. The pulse width fixed frequency divider generates a frequency divider output clock from the basic clock. Of the eight periods of the basic clock, the divider output clock is a high level signal for one period of the basic clock, and a low level signal for the other seven periods. The delay circuit outputs a delay clock obtained by delaying the divider output clock by one period of the basic clock. The inverter outputs a frequency divider output inverted clock obtained by inverting the frequency divider output clock. The phase comparator generates an UP / DOWN pulse from the phase difference between the delay clock and the frequency divider output inverted clock. The charge pump and loop filter generate a control voltage by this UP / DOWN pulse, and control the delay circuit so that the delay clock is locked in one basic clock cycle.

  Japanese Patent Laying-Open No. 2007-110323 (Patent Document 3) discloses a phase adjustment circuit that optimally adjusts the phase relationship between a data signal and a delayed clock signal regardless of the data rate. The phase adjustment circuit discretely adjusts the phases of the data signal and the clock signal, and includes a delay line, a phase comparator, and first and second delay control units. The delay line delays the clock signal to generate a delayed clock signal. The phase comparator compares the phases of the data signal and the delayed clock signal. The first delay control unit outputs a first delay control signal based on the comparison result of the phase comparator. The second delay control unit outputs a second delay control signal based on the frequency of the clock signal. The delay line determines a delay amount of the delayed clock signal with respect to the clock signal based on the first and second delay control signals.

JP 2002-163034 A Japanese Patent Laid-Open No. 2003-264452 JP 2007-110323 A

  By the way, in a display device such as a digital television or a liquid crystal television, it is necessary to transmit a large amount of digital image data from the controller body to the display panel at a high speed. For this reason, high-speed serial transmission technology such as LVDS (Low Voltage Differential Signaling) is used for transmission of image data between the controller and the panel. In LVDS, a data signal and a clock signal are transmitted synchronously, and a serial data signal is converted into a parallel signal by an interface circuit on the receiver side. Here, the DLL circuit is provided to generate a multiphase delayed clock signal used for serial / parallel conversion from the clock signal.

  As the operation speed of the serial interface circuit has been increasing year by year, the demand for the synchronization timing of the delayed clock signal and the data signal has become increasingly severe. In order to increase the accuracy of the synchronization timing between the delayed clock signal and the data signal, it is necessary to strictly control the phase difference between the input clock signal and the plurality of generated delayed clock signals.

  Usually, the multiphase delay clock signal output from the DLL circuit is generated by a plurality of voltage-controlled delay circuits connected in series. Therefore, in order to strictly control the phase difference between the input clock signal and the multi-phase delay clock signal, it is necessary to minimize variations in delay time due to individual voltage control delay circuits. However, the above-described prior art documents do not disclose anything about the variation in delay time of such a delay circuit.

  The present invention has been made in consideration of the above problems. An object of the present invention is to provide a DLL circuit that can accurately generate a delayed clock signal having a predetermined phase difference with respect to an input clock. Another object of the present invention is to provide a serial interface circuit using the DLL circuit.

  A delay locked loop circuit according to an embodiment of the present invention includes a control unit and a delay circuit. The control unit outputs a control signal corresponding to the phase difference between the first and second clock signals. The delay clock generation unit receives a rectangular wave-shaped external clock signal having the amplitude of the power supply voltage at the first node, and generates one or a plurality of delayed clock signals based on the external clock signal. The delay clock generation unit includes a plurality of delay circuits connected in series between the first node and the second node. Each of the plurality of delay circuits receives a common control signal in each delay circuit and outputs a signal delayed by a time corresponding to the control signal with respect to the input signal. When a signal having the same waveform is input to each of the plurality of delay circuits, the delay time of each delay circuit is the same. Each of the plurality of delay circuits shapes and outputs a signal to be output into a rectangular wave signal having the amplitude of the power supply voltage. The first and second clock signals are predetermined two signals of the external clock signal and the output signals of each of the plurality of delay circuits. The one or more delayed clock signals are predetermined one or more signals among the output signals of the plurality of delay circuits.

  According to the above embodiment, the signal output from each delay circuit is a rectangular wave signal having the amplitude of the power supply voltage. Accordingly, since the signal waveforms input to the delay circuits are the same, the delay time for each delay circuit is the same. As a result, it is possible to accurately generate a delayed clock signal having a predetermined phase difference with respect to the input external clock signal.

1 is a block diagram showing a configuration of a DLL circuit 1 according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of a configuration of a delay buffer I in FIG. It is a circuit diagram which shows an example of a structure of the shaping buffer J of FIG. FIG. 2 is a block diagram showing a configuration of a DLL circuit 101 as a comparative example of the DLL circuit 1 of FIG. 1. FIG. 5 is a diagram schematically illustrating a voltage waveform of a delay clock generation unit 120 in FIG. 4. It is a figure which shows typically the voltage waveform of the delay clock generation part 20 of FIG. FIG. 2 is a plan view showing an example of arrangement of a delay clock generation unit 20 in FIG. 3 is a block diagram showing a configuration of a television device 40. FIG. It is a block diagram which shows the structure of the LVDS receiver 45 of FIG. It is a block diagram which shows the structure of the delay clock generation part 61 as a modification of the delay clock generation part 20 of FIG. FIG. 10 is a block diagram illustrating a configuration of a delay clock generation unit 62 as another modification of the delay clock generation unit 20 of FIG. 1.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

[Configuration of DLL Circuit 1]
FIG. 1 is a block diagram showing a configuration of a DLL circuit 1 according to an embodiment of the present invention. Referring to FIG. 1, DLL circuit 1 includes a delay clock generation unit 20, a phase comparator 11, a charge pump 12, and a low-pass filter 13.

  The delay clock generation unit 20 includes n (n is an integer of 2 or more) connected in series between the node ND (0) (first node) and the node ND (n) (second node). Delay circuits D (1) to D (n) are included. FIG. 1 is depicted as n being an integer greater than or equal to 9. The delay clock generation unit 20 transmits the external clock signal CLKIN input to the node ND (0) to the node ND (n) while sequentially delaying the external clock signal CLKIN by the n delay circuits D (1) to D (n). To do. In FIG. 1, the output node of the x-th delay circuit D (x) (x is an integer of 1 to n) is denoted as ND (x). Further, when the delay circuits D (1) to D (n) are collectively referred to or unspecified, they are described as a delay circuit D.

  In the following description, the external clock signal CLKIN is handled as a single-ended signal for simplicity, but the external clock signal may be a differential signal. In this case, each of the delay circuits D (1) to D (n) is configured by a differential buffer.

  Each delay circuit D in FIG. 1 has the same configuration. Specifically, the x-th delay circuit D (x) (x is an integer of 1 to n) includes a delay buffer I (x) and a shaping buffer J (x) connected in series. A signal input to the delay circuit D (x) sequentially passes through the delay buffer I (x) and the shaping buffer J (x). Therefore, as shown in FIG. 1, n delay buffers I (1) to I (n) and n shaping buffers J (1) to J (n) are divided into a node ND (0) and a node ND (n Are alternately connected in series. Note that the delay buffers I (1) to I (n) and the shaping buffers J (1) to J (n) are also referred to as the delay buffer I and the shaping buffer J, respectively, when they are collectively referred to or unspecified. To do.

  Each delay buffer I outputs a signal delayed by a delay time corresponding to the control voltage VC output from the low-pass filter 13 with respect to the input signal. Since each delay buffer I has the same configuration, when a signal having the same waveform is input to each delay buffer I, each delay buffer I receives a signal delayed by the same delay time with respect to the input signal. Output.

  Each shaping buffer J shapes the input signal into a rectangular wave having the amplitude of the power supply voltage and outputs it. Since each shaping buffer J has the same configuration, when a signal having the same waveform is input to each shaping buffer J, each shaping buffer J has the same delay time in each shaping buffer J with respect to the input signal. A signal that is delayed by a certain amount is output.

  FIG. 2 is a circuit diagram showing an example of the configuration of the delay buffer I of FIG. Referring to FIG. 2, delay buffer I includes inverters 71a and 71b having the same configuration and connected in cascade. The number of inverter stages connected in cascade may be increased or decreased according to the required delay time.

  Each of inverters 71a and 71b includes a PMOS (P-channel Metal-Oxide Semiconductor) transistor QP1 and an NMOS (N-Channel Metal-Oxide Semiconductor) transistor QN1 whose gates and drains are commonly connected. The input signal VIN of the delay buffer I is inputted to the gates of the transistors QP1 and QN1 constituting the inverter 71a, and the output signal VOUT of the delay buffer I is outputted from the drains of the transistors QP1 and QN1 constituting the inverter 71b.

  Further, each of inverters 71a and 71b includes PMOS transistor QP2 connected between the source of PMOS transistor QP1 and power supply node VDD, and NMOS transistor QN2 connected between the source of NMOS transistor QN1 and ground node GND. Including. A constant bias voltage VB is input to the gate of the PMOS transistor QP2, and a control voltage VC is input to the gate of the NMOS transistor QN2. These transistors QP2 and QN2 function as voltage controlled current sources whose current amount is controlled by the gate voltage. If the control voltage VC is increased, the response time of the transistor QN1 is accelerated, so that the delay time of the delay buffer I is decreased. To do.

  Instead of the configuration of FIG. 2, the control voltage VC may be input to the gate of the PMOS transistor QP2, and the constant bias voltage VB may be input to the gate of the NMOS transistor QN2. In this case, if the control voltage VC is decreased, the response time of the transistor QP1 is shortened, so that the delay time of the delay buffer I is decreased. If the control voltage VC is increased, the response time of the transistor QP1 is delayed. Time increases.

  Further, the delay time of the delay buffer I may be controlled by inputting the control voltage VC to the gate of the NMOS transistor QN2 and inputting the control voltage VC * to the gate of the PMOS transistor QP2. The control voltage VC * in this case is a signal that changes in the opposite direction to the change in the control voltage VC, and is generated by the low-pass filter 13 together with the control voltage VC.

  FIG. 3 is a circuit diagram showing an example of the configuration of the shaping buffer J of FIG. Referring to FIG. 3, shaping buffer J includes inverters 72a and 72b having the same configuration and connected in cascade. The number of inverter stages connected in cascade may be increased or decreased.

  Each of inverters 72a and 72b includes a PMOS transistor QP3 and an NMOS transistor QN3 connected in common to the gate and drain. The source of transistor QP3 is connected to power supply node VDD, and the source of transistor QN3 is connected in series to ground node GND. The input voltage VIN of the shaping buffer J is applied to the gates of the transistors QP3 and QN3 constituting the inverter 72a, and the output voltage VOUT of the shaping buffer J is output from the drains of the transistors QP3 and QN3 constituting the inverter 72b. The transistors QP3 and QN3 are switched on or off according to the magnitude of the input voltage VIN of the shaping buffer J, whereby the output voltage VOUT changes to the power supply voltage or the ground voltage.

  Referring to FIG. 1 again, the DLL circuit 1 further shapes the output of the fourth to nth delay circuits D (4) to D (n) into rectangular waves having the amplitude of the power supply voltage, respectively. (4) to K (n) are included. Delayed clock signals CLKOUT (4) to CLKOUT (n) are output from the shaping buffers K (4) to K (n), respectively.

  Furthermore, the DLL circuit 1 forms shaping buffers Ka and Kb for shaping the signals output from the fourth and n-th delay circuits D (4) and D (n) into rectangular waves having the amplitude of the power supply voltage, respectively. including. The first and second clock signals CLKA and CLKB output from the shaping buffers Ka and Kb are input to the phase comparator 11.

  The phase comparator 11 compares the phase difference between the clock signals CLKA and CLKB, and outputs an UP pulse or a DOWN pulse according to the phase difference.

  The charge pump 12 generates a charging current or a discharging current according to the UP pulse or the DOWN pulse output from the phase comparator 11.

  The low-pass filter 13 includes, for example, a capacitor and a resistance element, and converts the current generated by the charge pump 12 into a voltage (control voltage VC). Specifically, when a charging current is generated by the charge pump 12, the control voltage VC output from the low-pass filter 13 increases. Conversely, when a discharge current is generated by the charge pump 12, the control voltage VC output from the low pass filter 13 decreases. The delay time of the delay buffers I (1) to I (n) is controlled by the control voltage VC output from the low-pass filter 13.

  As described in relation to FIG. 2, the gate voltages of the transistors QN2 and QP2 may be controlled by the control voltages VC and VC * in the delay buffer I having the configuration of FIG. In this case, the low-pass filter 13 generates control voltages VC and VC * and outputs the generated control voltages VC and VC * to each delay buffer I.

  The output voltage of the fourth delay circuit D (4) and the nth delay circuit D are fed back by the feedback loop constituted by the phase comparator 11, the charge pump 12, the low-pass filter 13, and the delay clock generator 20. The delay times of the delay buffers I (1) to I (n) are adjusted so that the phase difference from the output voltage of (n) becomes substantially zero. The phase comparator 11, the charge pump 12, and the low-pass filter 13 constitute the control unit 10 of the present invention. The control unit 10 outputs a control voltage VC corresponding to the phase difference between the clock signals CLKA and CLKB to the delay clock generation unit 20.

  Next, characteristics of the DLL circuit 1 shown in FIG. 1 will be described in comparison with the configuration and operation of the conventional DLL circuit.

[Problems of conventional DLL circuit]
FIG. 4 is a block diagram showing a configuration of a DLL circuit 101 as a comparative example of the DLL circuit 1 of FIG. The delay clock generation unit 120 of FIG. 4 includes only the delay buffers I (1) to I (n) connected in series without including the shaping buffers J (1) to J (n). Different from the delay clock generator 20. In other respects, the configuration of DLL circuit 101 in FIG. 4 is the same as the configuration of DLL circuit 1 in FIG. 1, and therefore the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  FIG. 5 is a diagram schematically illustrating a voltage waveform of the delay clock generation unit 120 of FIG. FIG. 5 shows the voltage waveform of the external clock signal CLKIN and the output voltage waveforms of the delay buffers I (1) to I (5) and I (n) in order from the top.

  Since the external clock signal CLKIN input to the delay buffer I (1) in FIG. 4 is a digital signal, its waveform is a rectangular wave having the amplitude of the power supply voltage as shown in FIG. On the other hand, as shown in FIG. 5, the outputs of the delay buffers I (1) to I (n) are transmitted as the signals pass through the delay buffers I (1) to I (4) of FIG. The rise and fall gradually become gentler and the amplitude decreases from the power supply voltage. Finally, the output waveform of the delay buffer has a shape close to a sine wave. Specifically, in the case of FIG. 5, the output waveform of the fourth delay buffer I (4) has a shape close to a sine wave, and the output waveform after that hardly changes.

  Here, it should be noted that if the waveform of the signal input to each delay buffer I is different, the delay time of each delay buffer I is different even if each delay buffer I is controlled by a common control voltage VC. That's what it means. In the case of FIG. 4, for the first to fourth delay buffers I (1) to I (4) in which the rising edge of the input waveform becomes gradually gentle, the delay times Td1 to Td4 of each delay buffer I gradually increase. To do. Since the delay times Td1 to Td4 in this case are affected by variations in the manufacturing process of the semiconductor device, the power supply voltage, and the operating temperature, it is difficult to calculate the delay times Td1 to Td4 specifically.

  On the other hand, for the fifth to nth delay buffers I (5) to I (n) in which no change is seen in the input waveform, the individual delay times are substantially equal. In this case, since the output of the fourth delay buffer I (4) and the output of the nth delay buffer I (n) are controlled to be in phase (in the case of FIG. 5, at time t1). If the period of the external clock signal CLKIN is Tp, the delay times of the fifth and subsequent delay buffers are equal to Tp / (n−4).

  Thus, in the case of the DLL circuit 101 of the comparative example, the mutual phase difference between the multiphase delayed clock signals CLKOUT (4) to CLKOUT (n) is strictly controlled. However, the delay times of the first to fourth delay buffers I (1) to I (4) are gradually changed. Therefore, the timing of the delayed clock signals CLKOUT (4) to CLKOUT (n) with respect to the timing of the external clock signal CLKIN is not strictly controlled.

[Operation of DLL circuit 1]
FIG. 6 is a diagram schematically illustrating a voltage waveform of the delay clock generation unit 20 of FIG. 6 shows the voltage waveform of the external clock signal CLKIN of FIG. 1 and the buffers I (1), J (1), I (2), J (2), I (3), J (3) in order from the top. , I (4), J (4), I (n), and J (n) output voltage waveforms.

  Referring to FIG. 1 and FIG. 6, the output waveforms of delay buffers I (1) to I (n) controlled by control voltage VC are such that the rise and fall of the signal are gentler than the rectangular wave and the amplitude is larger. The value is smaller than the power supply voltage. On the other hand, the output waveforms of the shaping buffers J (1) to J (n) are rectangular waves having an amplitude equal to the power supply voltage. Therefore, a rectangular wave having an amplitude equal to the power supply voltage is input to each delay buffer I, and the waveform of the signal input to each delay buffer I is the same.

  As a result, in the case of the DLL circuit 1 of FIG. 1, the delay times of all the delay buffers I (1) to I (n) are the same, and the delays of all the shaping buffers J (1) to J (n). The time will be the same. That is, the delay times of all the delay circuits D (1) to D (n) are the same. As described above, the output of the fourth shaping buffer J (4) and the output of the nth shaping buffer J (n) are controlled so as to be in phase (in the case of FIG. 5). At the time t1, the phases coincide with each other.) When the period of the external clock signal CLKIN is Tp, the delay times of the fifth to nth delay circuits D (5) to D (n) are Tp / (n -4).

  It should be noted that, unlike the DLL circuit 101 of the comparative example, the delay times Td1 to Td4 of the first to fourth delay circuits D (1) to D (4) are also Tp / (n-4). ). Therefore, in the case of the DLL circuit 1 of the first embodiment, the timings of the multiphase delayed clock signals CLKOUT (4) to CLKOUT (n) are strictly controlled with respect to the timing of the external clock signal CLKIN.

  Thus, according to the DLL circuit 1, the signals shaped into rectangular waves by the shaping buffers J (1) to J (n) respectively provided in the delay circuits D (1) to D (n) are transferred to the next stage. Transferred. As a result, the delay time of each of the delay circuits D (1) to D (n) becomes the same, so that the multiphase delay clock signal CLKOUT (4) having a predetermined phase difference with respect to the input external clock signal CLKIN. ) To CLKOUT (n) can be generated with high accuracy.

[Example of Arrangement of Delay Clock Generation Unit 20]
FIG. 7 is a plan view illustrating an arrangement example of the delay clock generation unit 20 of FIG. 1 on the semiconductor substrate SUB.

  Referring to FIG. 7, the region on semiconductor substrate SUB provided with DLL circuit 1 includes first and second regions 31 and 32 that are different from each other. The delay buffers I (1) to I (n) constituting the delay clock generation unit 20 are provided in the first region 31, and are in one direction (hereinafter referred to as the signal transmission order) in the first to nth number order (signal transmission order). , Referred to as the first direction). The shaping buffers J (1) to J (n) constituting the delay clock generation unit 20 are provided in the second region 32. The shaping buffers J (1) to J (n) are arranged in parallel (in the first direction) with the columns of the delay buffers I (1) to I (n) provided in the first area 31, and the first to first buffers Arranged in order of the nth number (signal transmission order). The first and second regions 31 and 32 are arranged in a direction orthogonal to the arrangement direction (first direction) of the delay buffer I and the shaping buffer J. As described above, the delay buffer I and the shaping buffer J are disposed in different regions 31 and 32 on the semiconductor substrate SUB. The reason for this is as follows.

  Since the output signal of the shaping buffer J is a rectangular wave, the output signal includes harmonic components. Therefore, when this harmonic component propagates to the delay buffer I through the power supply wiring or the ground wiring, the operation of the delay buffer I is affected as power supply noise. For this reason, it is necessary to provide the power supply wiring and ground wiring used for the delay buffer I and the power supply wiring and ground wiring used for the shaping buffer J as separate wirings.

  However, if the delay buffer I and the shaping buffer J are provided on the semiconductor substrate SUB, the power supply wiring and ground wiring for the delay buffer I and the power supply wiring and ground wiring for the shaping buffer J always intersect. Will do. As a result, the power supply noise of the shaping buffer J propagates to the delay buffer I via the power supply wiring or the ground wiring due to the coupling between the wirings.

  In order to solve the above problem, the delay clock generator 20 shown in FIG. 7 separates the area 31 in which the delay buffer I is provided and the area 32 in which the shaping buffer J is provided. Accordingly, the power supply wiring and ground wiring for the delay buffer I and the power supply wiring and ground wiring for the shaping buffer J can be arranged so as not to cross each other. As a result, it is possible to suppress the harmonic components included in the output of the shaping buffer J from affecting the delay buffer I as power supply noise.

  Further, the circuit area required for the delay clock generation unit 20 can be reduced by arranging the delay buffer I and the shaping buffer J separately in the regions 31 and 32 as described above.

[Example of application of DLL circuit 1 to a semiconductor device]
Hereinafter, as an application example of the DLL circuit 1 to a semiconductor device, a serial interface for a television (TV) device will be described.

  FIG. 8 is a block diagram showing a configuration of the television device 40. Referring to FIG. 8, television device 40 includes a TV main body 41 having a receiver and the like, and a TV panel device 42. Here, the TV panel device 42 includes an LVDS receiver 45 as an interface circuit, a display control device 46, a source driver group 47, a gate driver group 48, and a liquid crystal panel 49.

  The LVDS receiver 45 receives image data from the TV main body 41. The image data is transmitted to the LVDS receiver 45 as a differential serial signal 44 of the LVDS standard via the cable 43 connecting the TV main body 41 and the LVDS receiver. The differential serial signal 44 of the LVDS standard includes a clock signal (CLKIN in FIG. 9) and m data signals (m is an integer of 1 or more, here several) synchronized with the clock signal (DATA (1) in FIG. 9). -DATA (m)). The LVDS receiver 45 converts the serial image data signal into a parallel signal and outputs the parallel signal to the display control device 46.

  The display control device 46 outputs various control signals to the source driver group 47 and the gate driver group 48 in order to control the display of the liquid crystal panel 49 based on the image data serial / parallel converted by the LVDS receiver 45. The liquid crystal panel 49 displays an image based on various control signals received via the source driver group 47 and the gate driver group 48.

  FIG. 9 is a block diagram showing a configuration of the LVDS receiver 45 of FIG. Referring to FIG. 9, the LVDS receiver 45 includes m data buffers 50 (1) to 50 (m), a clock buffer 51, a DLL circuit 1, and a serial / parallel converter 52 (data conversion circuit). including.

  The data buffers 50 (1) to 50 (m) receive the data signals DATA (1) to DATA (m), respectively, and shape the received data signals into rectangular waves having the amplitude of the power supply voltage. The clock buffer 51 receives the clock signal CLKIN, and shapes the received clock signal CLKIN into a rectangular wave having the amplitude of the power supply voltage.

  The DLL circuit 1 generates a multiphase delayed clock signal based on the clock signal CLKIN whose waveform has been shaped by the clock buffer 51. The configuration of the DLL circuit 1 in FIG. 9 is the same as the configuration of the DLL circuit 1 in FIG. The DLL circuit 1 outputs the generated multiphase delayed clock signal to the serial / parallel converter 52.

  The serial / parallel converter 52 uses the data signals DATA (1) to DATA (m) shaped by the data buffers 50 (1) to 50 (m) based on the multiphase delayed clock signal output from the DLL circuit 1. ) Is converted into a parallel signal DATAOUT. The converted parallel signal DATAOUT is output to the display control device 46 of FIG.

  As described with reference to FIGS. 1 to 6, the timing of the multiphase delayed clock signal generated by the DLL circuit 1 is strictly controlled with respect to the timing of the clock signal CLKIN. Therefore, when the data signals DATA (1) to DATA (m) are converted in parallel by the serial / parallel converter 52, the data signals DATA (1) to DATA (m) and the multi-phase delayed clock signal are almost not converted. It is possible to prevent a phase shift from occurring.

[Modification]
In the DLL circuit 1 of FIG. 1, the output signals of the fourth to nth delay circuits D (4) to D (n) are output to the outside as the delayed clock signals CLKOUT (4) to CLKOUT (n). In addition to the output signals of the delay circuits D (4) to D (n), the output signals of the delay circuits D (1) to D (3) can be used as a delayed clock signal. More generally speaking, one or a plurality of signals output from each of the delay circuits D (1) to D (n) can be used as the delayed clock signal.

  In the DLL circuit 1 of FIG. 1, the outputs of the delay circuits D (4) and D (n) are input to the phase comparator 11 as the phase comparison clock signals CLKA and CLKB. The input is not limited to this. More generally speaking, any two of the external clock signal CLKIN and the output signals of the delay circuits D (1) to D (n) are used as clock signals CLKA and CLKB input to the phase comparator 11. Can be used.

Further, the configuration of the delay clock generation unit 20 in FIG. 1 can be changed.
FIG. 10 is a block diagram showing a configuration of a delay clock generation unit 61 as a modification of the delay clock generation unit 20 of FIG. Each delay circuit D of the delay clock generation unit 61 in FIG. 10 includes two delay buffers Ia and Ib and one shaping buffer J. The signal input to each delay circuit D passes through the delay buffers Ia and Ib and the shaping buffer J in this order. The configurations of the delay buffers Ia and Ib and the shaping buffer J are the same for each delay circuit D.

  Here, assuming that the delay unit DU is configured by the two delay buffers Ia and Ib, and the waveform shaping unit SU is configured by the shaping buffer J, the delay clock generation unit 61 in FIG. The configuration is the same as that of the unit 20. In the case of the delay clock generation unit 20 of FIG. 1, it can be considered that the delay unit DU is configured by one delay buffer I and the waveform shaping unit SU is configured by one shaping buffer J.

  Therefore, in the case of FIG. 10, when a signal is transferred between adjacent delay circuits D, the signal shaped into a rectangular wave by the waveform shaping unit SU provided in each delay circuit D is delayed by the adjacent delay circuit D. Is transferred to the unit DU. As a result, the waveforms of the signals input to the delay units DU are the same, so that the delay times of the delay units DU are the same and the delay times of the waveform shaping units SU are the same. As a result, the delay times of the delay circuits D are also the same. Therefore, if control is performed so that the phase difference between any two of the external clock signal CLKIN and the output signals of the delay circuits D (1) to D (n) coincides with the input external clock signal CLKIN. Thus, a delayed clock signal having a predetermined phase difference can be generated with high accuracy.

  FIG. 11 is a block diagram showing a configuration of a delay clock generation unit 62 as another modification of the delay clock generation unit 20 of FIG. FIG. 11 shows a case where the configurations of the delay circuits D are not the same.

  Each delay circuit D of the delay clock generator 62 in FIG. 11 includes first and second subunits Da and Db. The first subunit Da includes delay buffers Ia and Ib and a shaping buffer Ja. The signal input to the first subunit Da passes through the delay buffers Ia and Ib and the shaping buffer Ja in this order. The second subunit Db includes a delay buffer Ic and a shaping buffer Jb. The signal input to the second subunit Db passes through the delay buffer Ic and the shaping buffer Jb in this order. The configurations of the delay buffers Ia, Ib, Ic and the shaping buffers Ja, Jb are the same for each delay circuit D.

  In the case of the delay clock generation unit 62 in FIG. 11, the arrangement order of the first and second subunits Da and Db differs for each delay circuit D. For example, in the first delay circuit D (1) shown in FIG. 11, signals pass in the order of the first subunit Da (1) and the second subunit Db (1). On the other hand, in the second delay circuit D (2), signals pass in the order of the second subunit Db (2) and the first subunit Da (2).

  Thus, in the case of FIG. 11, the configurations of the delay circuits D are not the same. However, the delay time of each delay circuit D is the same. This is because when signals are transferred between adjacent subunits Da and Db, signals shaped into rectangular waves by the shaping buffers Ja and Jb provided at the output stages of the subunits Da and Db are transferred. It is. In this case, since the configurations of the subunits Da and Db are the same for each delay circuit D, the delay time of the first subunit Da is the same for all the delay circuits D, and the delay time of the second subunit Db. Is the same for all delay circuits D. Accordingly, the delay times of the delay circuits D including one each of the first and second subunits Da and Db are also the same. As a result, if the external clock signal CLKIN and the output signals of the delay circuits D (1) to D (n) are controlled so that the phase difference between any two signals coincides with the external clock signal CLKIN, On the other hand, it becomes possible to control the phase of the multiphase delayed clock signal which is the output signal of the delay circuits D (4) to D (n) with high accuracy.

  In summary, the delay clock generation units 20, 61, and 62 in FIGS. 1, 10, and 11 are both the first node ND (0) and the second node ND to which the external clock signal CLKIN is input. N delay circuits D (1) to D (n) (n is an integer of 2 or more) connected in series with (n). Each delay circuit D receives a common control voltage VC in each delay circuit D and outputs a signal delayed by a delay time corresponding to the control voltage VC with respect to the input signal. Furthermore, when a signal having the same waveform is input to each delay circuit D, each delay circuit D outputs a signal delayed by the same delay time in each delay circuit D with respect to the input signal. Furthermore, each delay circuit D shapes and outputs a signal to be output into a rectangular wave signal having the amplitude of the power supply voltage.

  According to the above configuration, since the waveforms of the signals input to the delay circuits D are the same, the delay times of the delay circuits D can be the same. As a result, if the external clock signal CLKIN and the output signals of the delay circuits D (1) to D (n) are controlled so that the phase difference between any two signals coincides with the external clock signal CLKIN, On the other hand, a delayed clock signal having a predetermined phase difference can be generated with high accuracy.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 DLL circuit, 10 Control part, 11 Phase comparator, 12 Charge pump, 13 Low pass filter, 20, 61, 62 Delay clock generation part, 31, 32 1st, 2nd area | region, 45 LVDS receiver (interface circuit), 52 serial / parallel converter, CLKIN external clock signal, CLKOUT delay clock signal, VC control voltage, I (1) to I (n) delay buffer, J (1) to J (n) shaping buffer, D (1) to D (n) delay circuit, ND (0) to ND (n) node, SUB semiconductor substrate.

Claims (5)

A control unit that outputs a control signal corresponding to the phase difference between the first and second clock signals;
A delay clock generator that receives a rectangular-wave external clock signal having an amplitude of a power supply voltage at a first node and generates one or a plurality of delayed clock signals based on the external clock signal;
The delay clock generation unit includes a plurality of delay circuits connected in series between the first node and the second node;
Each of the plurality of delay circuits receives the control signal common to each delay circuit, and outputs a signal delayed by a time corresponding to the control signal with respect to the input signal,
When a signal having the same waveform is input to each of the plurality of delay circuits, the delay time of each delay circuit is the same,
Each of the plurality of delay circuits shapes and outputs a signal to be output into a rectangular wave signal having the amplitude of the power supply voltage,
The first and second clock signals are predetermined two signals of the external clock signal and output signals of each of the plurality of delay circuits,
The delay locked loop circuit, wherein the one or more delayed clock signals are predetermined one or more signals among output signals of the plurality of delay circuits. Each of the plurality of delay circuits is
A delay unit that outputs a signal delayed by a time corresponding to the control signal with respect to the input signal;
A waveform shaping unit that shapes and outputs the output signal of the delay unit into a rectangular wave signal having the amplitude of the power supply voltage;
When signals having the same waveform are input to the delay units of the plurality of delay circuits, the delay times of the delay units are the same as each other,
2. The delay locked loop circuit according to claim 1, wherein when the same waveform signal is input to each of the waveform shaping units of the plurality of delay circuits, the delay times of the waveform shaping units are the same. Each of the delay units of the plurality of delay circuits has the same configuration.
The delay locked loop circuit according to claim 2, wherein the waveform shaping sections of the plurality of delay circuits have the same configuration. The region on the semiconductor substrate provided with the delay locked loop circuit is:
A first region in which each of the delay units of the plurality of delay circuits is disposed in a first direction in a signal transmission order;
Each waveform shaping section of the plurality of delay circuits includes a second region disposed in the first direction in the signal transmission order;
4. The delay locked loop circuit according to claim 2, wherein the first region and the second region are arranged in a second direction orthogonal to the first direction. 5. A delay locked loop circuit that receives a rectangular-wave external clock signal having an amplitude of a power supply voltage at a first node and generates one or a plurality of delayed clock signals based on the external clock signal;
A data conversion circuit that receives a serial external data signal and performs serial / parallel conversion of the external data signal based on the one or more delayed clock signals;
The delay locked loop circuit includes:
A control unit that outputs a control signal corresponding to the phase difference between the first and second clock signals;
A plurality of delay circuits connected in series between the first node and the second node;
Each of the plurality of delay circuits receives the control signal common to each delay circuit, and outputs a signal delayed by a time corresponding to the control signal with respect to the input signal,
When a signal having the same waveform is input to each of the plurality of delay circuits, the delay time of each delay circuit is the same,
Each of the plurality of delay circuits shapes and outputs a signal to be output into a rectangular wave signal having the amplitude of the power supply voltage,
The first and second clock signals are predetermined two signals of the external clock signal and output signals of each of the plurality of delay circuits,
The interface circuit, wherein the one or more delayed clock signals are predetermined one or more signals among the output signals of the plurality of delay circuits.

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