JP2010287855A - Silicon wafer, method for manufacturing the same, and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon wafer suitable for a semiconductor device, which is thinned in a device post process and subjected to polishing of a rear surface. <P>SOLUTION: A method for manufacturing the silicon wafer includes a process S11a for preparing a silicon substrate 11 and an ion implantation process S13a for implanting ions to the silicon substrate 11 by dose of 1×10<SP>13</SP>to 3×10<SP>14</SP>atoms/cm<SP>2</SP>. A heavy metal which may be introduced in the device post-process by a contamination protection layer 11x formed by the ion implantation is subjected to gettering. Although it is necessary to use a high energy type ion implantation device to carry out ion implantation into a deep position, little dose is used, so that ion implantation time is not sharply increased. Thereby, the method is applied also to mass-production articles. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a silicon wafer and a manufacturing method thereof, and more particularly to a silicon wafer suitable for a semiconductor device mounted on a multichip package (MCP) and a manufacturing method thereof. The present invention also relates to a method for manufacturing a semiconductor device suitable for mounting on an MCP.

  One of the problems in the semiconductor process is that heavy metals as impurities are mixed in the silicon wafer. When heavy metals diffuse into a device region formed on the surface side of a silicon wafer, device characteristics such as pause time failure, retention failure, junction leak failure, and dielectric breakdown of the oxide film are significantly adversely affected. For this reason, in order to suppress the heavy metal mixed in the silicon wafer from diffusing into the device region, the gettering method is generally adopted. Gettering is aimed at preventing heavy metal contamination in a device pre-process for forming a device on the surface of a silicon substrate.

  On the other hand, heavy metal contamination in post-device processes such as thinning of the silicon substrate, wire bonding, or resin encapsulation performed after the pre-device process has not been particularly emphasized. This is a process of grinding and removing the back surface of the silicon wafer in the early stage of the device post-process. Scratches and damage introduced during the back surface grinding act as a gettering source by strong extrinsic gettering (EG). Because.

  However, the final chip thickness is becoming thinner year by year, and in particular, the chip mounted on the MCP is often made thinner to 100 μm or less, and depending on the product, it is currently made thinner to 25 μm or less, and in the future it will be 10 μm or less. Both are predicted. When the thickness of the chip is reduced to 100 μm or less, there arises a problem that the silicon wafer is easily broken due to damage during back grinding. In order to solve such a problem, it is necessary to newly add a process of removing damage after the back surface grinding, that is, a back surface polishing process by the CMP method.

  However, if the damage on the back surface of the silicon wafer is removed by back surface polishing, the back surface gettering source also disappears, and the EG effect is lost. Moreover, since a thin silicon wafer has a thin intrinsic gettering (IG) layer, a sufficient IG effect cannot be expected with a normal IG layer formed of oxygen precipitates. More specifically, even in the case of an epitaxial wafer or silicon wafer using the IG method, a DZ layer having no oxygen precipitation nuclei including the thickness of the epitaxial film is formed by heat treatment to have a thickness of 10 μm or more from the wafer surface. When the final film thickness of the chip becomes thinner, the IG layer hardly exists and the impurity metal generated in the device post-process cannot be gettered at all.

  As described above, in the thin semiconductor device in which the back surface of the silicon wafer is polished, the problem of heavy metal contamination in the device post-process is beginning to become apparent.

  In this regard, Patent Document 1 discloses that a silicon epitaxial film (first layer) containing high-concentration boron is grown on a silicon substrate by about 100 μm, and further a high-resistance silicon epitaxial film (second layer) serving as a device region. ) Is grown about several tens of μm. And after performing a device pre-process using such a silicon wafer, the total thickness is reduced to about 100 μm by grinding the silicon substrate from the back surface, and the back surface is further mirror-polished.

  According to the method described in Patent Document 1, since the first silicon epitaxial film containing high-concentration boron exists below the second silicon epitaxial film serving as the device region, mirror polishing is used. Even if the EG layer disappears, heavy metal, particularly Cu or Fe, can be efficiently gettered by the effect of high-concentration boron.

  However, when an epitaxial film containing a high concentration of impurities such as boron is formed, the specific resistance of the second-layer epitaxial film can be controlled by, for example, boron adhering to a chamber in an epitaxial growth furnace or a susceptor made of silicon carbide. There is a problem of disappearing.

  On the other hand, Patent Document 2 discloses a technique for imparting gettering capability to a thinned wafer back surface by various methods. For example, a method of depositing a polycrystalline silicon film or a nitride film on the back surface of a thinned silicon wafer, a method of damaging the back surface using silica particles, a method of giving a damaged layer on the back surface by ion implantation, etc. Yes. Certainly, these methods are considered to be effective if the chip thickness is thick to some extent, but as already explained, if the final chip thickness is reduced to 100 μm or less, and in the future to about 10 μm, The yield strength is expected to be significantly reduced because the bending strength is reduced due to the introduction of physical damage due to silica particles and the like, resulting in a problem of chip cracking. In addition, it is not practical for a mass-produced product to deposit a polycrystalline silicon film or a nitride film or perform ion implantation in a device post-process.

  On the other hand, Patent Documents 3 and 4 describe techniques in which damage is formed inside a silicon substrate by ion implantation and this is used as a getter site. However, since the methods described in Patent Documents 3 and 4 are intended for gettering in the device pre-process, they are not necessarily appropriate for heavy metal contamination introduced in the device post-process.

  More specifically, heavy metal introduced in the device post-process diffuses from the back side of the silicon wafer. Therefore, in order to prevent reaching the device region, it is necessary to form a damage layer at a certain depth. In order to perform ion implantation at a deep position, it is necessary to use a high-energy ion implantation apparatus. However, since a high-energy ion implantation apparatus has a low output current, it requires a long time to implant high-concentration ions. It is necessary to perform ion implantation over a long period of time, which is not practical for mass-produced products. On the other hand, a high-current ion implantation apparatus can perform high-concentration ion implantation, but cannot perform deep ion implantation because of its short range.

In this regard, Patent Document 3 describes that 1 × 10 ¹⁵ atoms / cm ² of phosphorus is ion-implanted, and Patent Document 4 describes that 3 × 10 ¹⁴ atoms / cm ² or more of phosphorus is ion-implanted. As described above, it is not practical to implant such a high concentration of ions deeply. When ion implantation is performed at such a concentration in a mass-produced product, it is essential to use a high current type ion implantation apparatus. In this case, the implantation depth is limited to 1 μm or less. In particular, it is practically impossible to inject to a depth of 2 μm or more.

  However, since Patent Documents 3 and 4 intend gettering in the device pre-process, it is considered unavoidable to perform ion implantation with such a dose. In the device pre-processes at the time when Patent Documents 3 and 4 were filed, the depth of the well region and the depth of the source / drain were significantly deeper than the current device structure, so several hours in a temperature range exceeding 1150 ° C. This is because the heat treatment for several tens of hours has been performed, and if the dose is small, the ion implantation damage is recovered by the heat treatment for a long time at a high temperature and the gettering ability is lost.

JP 2005-317735 A JP 2006-41258 A Japanese Patent No. 2744022 Japanese Patent No. 2746499

  However, as described above, it is impractical to inject ions with a high dose amount into a deep position from the viewpoint of the characteristics of the ion implantation apparatus. Therefore, the heavy metal introduced in the device post-process in Patent Documents 3 and 4 Applying this gettering is impractical, even if it works. On the other hand, when focusing on the gettering of heavy metals introduced in the device post-process, and when focusing on the temperature history in the recent device pre-process, high-concentration ion implantation described in Patent Documents 3 and 4 is not necessarily required. It is considered unnecessary to do. The present invention has been made based on such technical knowledge.

The silicon wafer according to the present invention is formed to a depth of 1 μm or more and 10 μm or less from the surface on which the device is formed, and the dose amount is 1 × 10 ¹³ / cm ² or more and 3 × 10 ¹⁴ / cm ² or less, preferably 1 × 10. ^It is provided with a contamination protective layer into which non-metallic ions of ¹⁴ / cm ² or less are introduced.

In the method for producing a silicon wafer according to the present invention, the dose is 1 × 10 ¹³ / cm ² or more and 3 × 10 ¹⁴ / cm ² or less, preferably 1 ×, at a depth of 1 μm or more and 10 μm or less from the surface on which the device is formed. It is characterized by comprising a contamination protective layer forming step for forming a maximum concentration peak by ion-implanting non-metallic ions of 10 ¹⁴ / cm ² or less.

In the method of manufacturing a semiconductor device according to the present invention, the dose is 1 × 10 ¹³ / cm ² or more and 3 × 10 ¹⁴ / cm ² or less, preferably at a depth of 1 μm or more and 10 μm or less from the surface of the silicon wafer on which the device is formed. Forms a contamination protective layer by ion-implanting non-metal ions of 1 × 10 ¹⁴ / cm ² or less, and after forming the contamination protective layer, a semiconductor element is formed on the surface After performing the device pre-process and the device pre-process, by removing a part of the silicon wafer from the back side, the thickness of the silicon wafer is reduced to 100 μm or less, and the thickness of the silicon wafer is reduced And a back surface polishing step for polishing the back surface of the silicon substrate.

  According to the present invention, the contamination protective layer is formed by ion-implanting low-concentration non-metallic ions at a certain depth from the surface, so that the heavy metal introduced from the back side of the silicon wafer in the device post-process is Never reach the device area. Contamination protection layer recovers damage after high-temperature and long-time heat treatment, but low-temperature processes are the mainstream in recent device pre-processes, and most high-temperature processes are also completed in a short time. Therefore, the damage is not recovered by the heat treatment. Further, in order to perform ion implantation at a deep position, it is necessary to use a high energy type ion implantation apparatus. However, since the dose is small in the present invention, the ion implantation time does not increase significantly. For this reason, it can be applied to mass-produced products.

  In the present invention, the nonmetallic ion is one or more elements selected from the group consisting of boron, phosphorus, antimony, arsenic, helium, argon, carbon, nitrogen, oxygen, fluorine, silicon, and germanium. preferable. If these ionic species are selected, the contamination protective layer can be formed by ion implantation without adversely affecting the device, or the barrier layer can be formed by various methods.

  Alternatively, an epitaxial film may be formed on the surface of the silicon substrate after the contamination protective layer is formed by ion implantation of the nonmetallic ions to a depth of less than 2 μm from the surface of the silicon substrate. According to this, since a high current type ion implantation apparatus can be used, the time required for ion implantation is shortened.

In the present invention, the initial oxygen concentration of the silicon substrate is preferably 7 × 10 ¹⁷ atoms / cm ³ or more and 2.4 × 10 ¹⁸ atoms / cm ³ or less. According to this, oxygen precipitates are formed on the silicon substrate by heat treatment before or during the device pre-process, and this becomes a gettering source for heavy metals such as Ni.

  As described above, according to the silicon wafer and the manufacturing method thereof according to the present invention, it is possible to prevent heavy metal contamination in the subsequent process of the semiconductor device whose final chip thickness is reduced to 100 μm or less.

  Further, according to the semiconductor device manufacturing method of the present invention, it is possible to mass-produce thin semiconductor devices in which heavy metal contamination is prevented in the subsequent process.

1 is a schematic cross-sectional view showing the structure of a silicon wafer 10 according to a preferred first embodiment of the present invention. It is a schematic sectional drawing which shows the structure of the silicon wafer 20 by preferable 2nd Embodiment of this invention. 1 is a schematic cross-sectional view showing a structure of a semiconductor device 30 that is thinned using a silicon wafer 10. 1 is a schematic cross-sectional view showing the structure of a semiconductor device 40 that has been thinned using a silicon wafer 20. It is a schematic sectional drawing which shows the structure of MCP50 using the semiconductor device 30 or 40 reduced in thickness. 4 is a flowchart for roughly explaining a method for manufacturing the semiconductor device 30 or 40. It is a flowchart for demonstrating the manufacturing process (step S10a) of the silicon wafer 10 by 1st Embodiment. It is a flowchart for demonstrating the manufacturing process (step S10b) of the silicon wafer 20 by 2nd Embodiment. It is a flowchart for demonstrating a device back process.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic cross-sectional view showing the structure of a silicon wafer 10 according to a preferred first embodiment of the present invention.

  As shown in FIG. 1, the silicon wafer 10 according to the present embodiment includes a silicon substrate 11 and a damaged layer 11x formed at a depth of 1 μm or more and 10 μm or less from the surface 11a. The silicon substrate 11 is not particularly limited, but the specific resistance of the silicon substrate 11 based on the dopant concentration is adjusted to 0.2 Ω · cm or more and 200 Ω · cm or less for both p-type and n-type. The surface 11a of the silicon substrate 11 is a region where a device is formed in the device pre-process.

The silicon substrate 11 preferably has an initial oxygen concentration of 7 × 10 ¹⁷ atoms / cm ³ or more and 2.4 × 10 ¹⁸ atoms / cm ³ or less. This is because oxygen precipitates necessary for gettering heavy metals such as Ni are not sufficiently formed when the oxygen concentration is less than 7 × 10 ¹⁷ atoms / cm ³ , and the oxygen concentration is 2.4 × 10 ¹⁸ atoms. This is because crystal pulling by the CZ method at more than / cm ³ is difficult. However, in the silicon wafer 10 according to the present embodiment, since the crystal damage included in the damaged layer 11x functions as a gettering source, the initial oxygen concentration of the silicon substrate 11 is less than 7 × 10 ¹⁷ atoms / cm ^3. I do not care. In addition, all the oxygen concentrations described in this specification are measured values by Fourier transform infrared spectrophotometry standardized by ASTM F-121 (1979).

The initial oxygen concentration of the silicon substrate 11 is preferably higher in a range not exceeding 2.4 × 10 ¹⁸ atoms / cm ³ , and carbon or nitrogen is included in the silicon substrate 11 to promote oxygen precipitation. Is more preferable. The carbon content is preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 1.2 × 10 ¹⁷ atoms / cm ³ or less, and the nitrogen content is 1 × 10 ¹³ atoms / cm ³ or more and 1 It is preferable that it is x10 ¹⁴ atoms / cm ³ or less.

  The oxygen precipitation heat treatment for forming oxygen precipitates on the silicon substrate 11 may be performed before the device pre-process, or may be substituted by a thermal process in the device pre-process. In addition, when performing oxygen precipitation heat processing before a device pre-process, it is preferable to carry out before the ion implantation mentioned later. This is because if the oxygen precipitation heat treatment is performed after forming the damaged layer 11x by ion implantation, the damage is recovered and the gettering effect by the damaged layer 11x may be lost, and the reason is not clear. This is because if ion implantation is performed first, point defects are more likely to be absorbed and released from the implantation damage, resulting in delaying the formation of oxygen precipitate nuclei.

  As shown in FIG. 1, the damage layer 11x is formed on the surface 11a side of the silicon substrate 11, and functions as a gettering site for heavy metals such as Cu and Ni. That is, it functions as a contamination protective layer of the present invention.

  The depth of the damaged layer 11x is 1 μm or more and 10 μm or less, and preferably 2 μm or more and 5 μm or less from the surface 11a of the silicon substrate 11. This is because if the depth of the damage layer 11x is less than 1 μm, the depletion layer of the device may reach the damage layer 11x. In addition, if the depth of the damaged layer 11x exceeds 10 μm, it is difficult to form the damaged layer 11x. Thus, since the formation position of the damaged layer 11x is relatively deep, it is necessary to use a high energy ion implantation apparatus.

The damage layer 11x is formed by implanting a non-metallic ion species that does not contaminate the device layer, and the dose is 1 × 10 ¹³ / cm ² or more and 3 × 10 ¹⁴ / cm ² or less. This is because if the dose amount is less than 1 × 10 ¹³ atoms / cm ² , the silicon substrate 11 is damaged so little that heavy metals such as Cu and Ni cannot be captured sufficiently, and the dose amount is 3 This is because if it exceeds × 10 ¹⁴ atoms / cm ² , it takes too much time for ion implantation using a high-energy ion implantation apparatus. In particular, the dose amount of the damaged layer 11x is preferably 1 × 10 ¹³ / cm ² or more and 1 × 10 ¹⁴ / cm ² or less. According to this, since the time required for ion implantation is shortened, application to a mass-produced product becomes more suitable.

  The ion species used for forming the damaged layer 11x can be selected from an ion species used as a p-type dopant, an ion species used as an n-type dopant, and a non-dopant ion. As the ion species used as the p-type dopant, it is preferable to select boron. Furthermore, it is preferable to select helium, argon, fluorine, oxygen, nitrogen, carbon, silicon, or germanium as the non-dopant.

  If boron is selected as the ion species, not only the occurrence of implantation damage and dislocation generation in the device heat treatment, but also the boron concentration of the silicon substrate 11 is increased. The gettering effect is enhanced with respect to the cationic metal. Moreover, it is preferable to select phosphorus, antimony or arsenic as the ion species used as the n-type dopant. If an n-type dopant is selected as an ion species, not only the occurrence of implantation damage and dislocation, but also the presence of n-type dopant ions at the lattice positions in the vicinity of the region of the damaged layer 11x as a positive ion makes it possible to form Cu rather than a boron substrate. Since the solid solubility of ions is lowered, it is effective as a barrier against Cu ion contamination during back surface grinding and back surface polishing in the device post-process. Further, when a non-dopant ion is selected as the ion species, dislocation occurs due to implantation damage or device heat treatment, which becomes a gettering source, but there is no risk of fluctuation in the threshold value of the transistor.

  FIG. 2 is a schematic cross-sectional view showing the structure of a silicon wafer 20 according to the second preferred embodiment of the present invention.

  As shown in FIG. 2, the silicon wafer 20 according to the present embodiment includes a silicon substrate 21 and an epitaxial film 22 formed on the surface 21a. The silicon substrate 21 is a p-type substrate doped with boron, and the specific resistance of the silicon substrate 21 based on the boron concentration is adjusted to 0.2 Ω · cm to 200 Ω · cm. The specific resistance is the same as above for the n-type substrate. 1 differs from the silicon substrate 11 shown in FIG. 1 in that the damage layer 21x is formed to a depth of less than 2 μm from the surface 21a. However, in this embodiment, since the device region is formed in the epitaxial film 22, the specific resistance of the silicon substrate 21 may be set higher than the specific resistance of the silicon substrate 11 described above. The damaged layer 21x is basically the same as the damaged layer 11x described above except that the depth is different. In this embodiment, since the formation position of the damaged layer 21x is shallow, a high current type ion implantation apparatus can be used.

  The epitaxial film 22 is a part that becomes a device region, and the film thickness is preferably 10 μm or less. This is because when the thickness of the epitaxial film 22 is increased to more than 10 μm, the thickness of the silicon substrate 21 is reduced correspondingly, so that the remaining thickness of the oxygen precipitation layer is reduced, resulting in a decrease in gettering capability and an increase in epitaxial growth. This is because it takes time, and an increase in film thickness leads to deterioration in flatness, which cannot be handled by a state-of-the-art device.

  The above is the configuration of the silicon wafers 10 and 20 according to the first and second embodiments. For such silicon wafers 10 and 20, after the device is formed on the front surface by the device pre-process, the silicon substrates 11 and 21 are partly removed from the back surface side so that the thickness is 100 μm or less. Can do.

  3 and 4 are schematic cross-sectional views showing the structures of thinned semiconductor devices (silicon chips) 30 and 40, respectively. A semiconductor device 30 shown in FIG. 3 is manufactured using the silicon wafer 10 according to the first embodiment, and a semiconductor device 40 shown in FIG. 4 is manufactured using the silicon wafer 40 according to the second embodiment. It has been done. In any of the semiconductor devices 30 and 40, a part of the silicon substrates 11 and 21 is removed from the back surface side by grinding or etching, and the newly exposed back surfaces 11b and 21b are mirror-polished. Thereby, even when the total thickness is reduced to 100 μm or less, the bending strength is ensured, so that it is possible to prevent chip cracking.

  FIG. 5 is a schematic cross-sectional view showing the structure of the MCP 70 using the thinned semiconductor device 30 or 40. The MCP 50 shown in FIG. 5 has a configuration in which four semiconductor devices 30 or 40 are stacked on a package substrate 51. The semiconductor device 30 or 40 and the package substrate 51 adjacent to each other in the vertical direction are fixed by an adhesive 52. Further, the semiconductor device 30 or 40 and the package substrate 51 are connected by a bonding wire 53, whereby each semiconductor device 30 or 40 is externally connected via an internal wiring (not shown) provided on the package substrate 51. It is electrically connected to the electrode 54. Further, a sealing resin 55 for protecting the semiconductor device 30 or 40 and the bonding wire 53 is provided on the package substrate 51.

  In the MCP 50 having such a configuration, since the thickness of one semiconductor device 30 or 40 is reduced to, for example, about 25 μm, the thickness of the entire MCP can be reduced to, for example, about 1 mm. For this reason, the application to the use as which a low profile is requested | required, such as a mobile apparatus, is suitable.

  Next, a method for manufacturing the semiconductor device 30 or 40 will be described with reference to a flowchart.

  FIG. 6 is a flowchart for roughly explaining a method for manufacturing the semiconductor device 30 or 40. As shown in FIG. 6, the manufacturing process of the semiconductor device 30 or 40 is roughly divided into a silicon wafer manufacturing process (steps S10a and S10b), a device pre-process (step S20), and a device post-process (step S30). are categorized. Hereinafter, each process will be described in detail.

  FIG. 7 is a flowchart for explaining the manufacturing process (step S10a) of the silicon wafer 10 according to the first embodiment.

In the present embodiment, first, the silicon substrate 11 is prepared (step S11a). The silicon substrate 11 is a CZ wafer cut out from a silicon ingot pulled up by the Czochralski (CZ) method. As described above, the specific resistance is preferably 0.2 Ω · cm or more and 200 Ω · cm or less. The initial oxygen concentration is preferably 7 × 10 ¹⁷ atoms / cm ³ or more and 2.4 × 10 ¹⁸ atoms / cm ³ or less. The specific resistance can be adjusted by the amount of boron and the amount of n-type dopant added to the silicon melt, and the initial oxygen concentration can be adjusted by convection control of the silicon melt.

  Next, an oxygen precipitation heat treatment is performed on the silicon substrate 11 (step S12a). Although it is not essential to perform the oxygen precipitation heat treatment in the present invention, by performing this, an oxygen precipitate is formed, and the gettering effect of heavy metals can be enhanced. Although not particularly limited, the oxygen precipitation heat treatment can be performed by the following two methods.

  In the first method, first, an oxygen precipitation heat treatment is performed at a temperature of 600 ° C. to 900 ° C. for 15 minutes to 4 hours. Thereby, oxygen contained in the silicon substrate 11 forms precipitation nuclei, which function as a gettering site by growing in a device process. In addition, since the slip dislocation hardly occurs in the heat treatment under such a temperature condition, it is possible to suppress a decrease in yield.

  In the second method, first, the silicon substrate 11 is heated at a temperature of 1100 ° C. or higher and 1350 ° C. or lower for 1 second to 300 seconds in a nitrogen atom-containing atmosphere, and then the temperature is decreased at 10 ° C./second or higher. A first heat treatment is performed. Thereby, the void | hole is frozen by the silicon surface layer part. Next, following the first heat treatment, a second heat treatment may be performed by heating at a temperature of 700 ° C. to 1000 ° C. for 10 minutes to 4 hours. Thereby, oxygen precipitation nuclei grow from the vacancies formed in the first heat treatment. Next, the nitride formed on the surface of the silicon substrate 11 is removed by polishing the surface of the silicon substrate 11. The polishing amount is preferably 0.5 μm or more and 5 μm or less.

When the oxygen precipitation heat treatment (step S12a) is completed in this way, next, the silicon substrate 11 is 1 × 10 ¹³ atoms / cm ² or more and 3 × 10 ¹⁴ atoms / cm ² or less, preferably 1 × 10 ^13. Ion implantation is performed with a dose amount of atoms / cm ² or more and 1 × 10 ¹⁴ atoms / cm ² or less (step S13a). The implantation energy is set so that the implantation depth is 1 μm or more and 10 μm or less, preferably 2 μm or more and 5 μm or less. In order to perform ion implantation at such a depth, it is necessary to use a high energy ion implantation apparatus. As a result, a damage layer 11x is formed on the silicon substrate 11 in a region having a depth of 1 μm or more and 10 μm or less from the surface 11a. Preferred ionic species are as described above. Although not particularly shown, oxygen precipitation heat treatment may be performed after ion implantation. However, although the reason is not clear, if ion implantation is performed first, point defects are more likely to be absorbed and released from the implantation damage, resulting in delaying the formation of oxygen precipitate nuclei.

  The above is the manufacturing process (step S10a) of the silicon wafer 10 according to the first embodiment.

  FIG. 8 is a flowchart for explaining the manufacturing process (step S10b) of the silicon wafer 20 according to the second embodiment.

  Also in this embodiment, first, the silicon substrate 21 is prepared (step S11b), and preferably oxygen precipitation heat treatment (step S12b) is performed. Since these details are the same as those of steps S11a and S12a shown in FIG.

Next, 1 × 10 ¹³ atoms / cm ² or more and 3 × 10 ¹⁴ atoms / cm ² or less, preferably 1 × 10 ¹³ atoms / cm ² or more, so that the implantation depth is less than 2 μm with respect to the silicon substrate 21. Ion implantation is performed at a dose of 1 × 10 ¹⁴ atoms / cm ² or less (step S13b). In order to perform ion implantation at such a depth, it is not always necessary to use a high energy ion implantation apparatus, and a high current ion implantation apparatus can be used. Thereby, a damage layer 21x is formed in a region having a depth of 2 μm or less from the surface 21a of the silicon substrate 21. Preferred ionic species are as described above.

  Then, an epitaxial film 22 is formed on the surface of the silicon substrate 21 (step S14b). The film thickness of the epitaxial film 22 is preferably 10 μm or less. Thus, the silicon wafer 20 is completed. Thus, since the ion implantation for forming the damaged layer 21x is performed before the formation of the epitaxial film 22, the epitaxial film 22 is not damaged by the ion implantation. In addition, since the oxygen precipitation heat treatment is performed before the ion implantation, there is little suppression of oxygen precipitation nucleation for the above reason. However, if this heat treatment condition is used, ion implantation may be performed first. This method is not limited to the above. From the evaluation result, after step S13a, step S12a may be performed at the final stage, and after steps S13b and S14b are performed in this order, the step is performed at the final stage. It is clear that S12b may be performed.

  The above is the manufacturing process (step S10b) of the silicon wafer 20 according to the second embodiment.

  The above is the manufacturing process (steps S10a and S10b) of the silicon wafers 10 and 20 according to the first and second embodiments. As shown in FIG. 6, when the silicon wafer manufacturing process (steps S10a and S10b) is completed, a device pre-process (step S20) is performed next. The device pre-process (step S20) is a process of forming a semiconductor element or the like on the surface of the silicon wafer, but since it differs depending on the type of semiconductor device to be manufactured, its details are omitted. Examples of the semiconductor device include logic semiconductor devices such as MPU and DSP, and memory semiconductor devices such as DRAM and flash memory. However, in the device pre-process (step S20), when performing heat treatment using a batch heat treatment furnace, heat treatment is preferably performed in a temperature range not exceeding 1100 ° C., and heat treatment is performed using a single wafer lamp furnace or a laser annealer. In some cases, there are processes that exceed 1100 ° C, but it is an ultra-short heat treatment in milliseconds, and even a normal RTP process consists of a short heat treatment for a few seconds to a few minutes. Therefore, the damage at the time of ion implantation does not disappear.

  FIG. 9 is a flowchart for explaining the device post-process (step S30).

  As shown in FIG. 9, in the device post-process, first, the back grinding of the silicon wafers 10 and 20 is performed (step S31). The back surface grinding is performed by rough grinding a part of the silicon substrates 11 and 21 from the back surface side, thereby reducing the thickness of the silicon wafers 10 and 20 to 100 μm or less. Note that this step is not limited to grinding, and can be performed by wet etching or dry etching.

  Next, the back surfaces of the ground silicon substrates 11 and 21 are mirror-polished (step S32), whereby the damage introduced by the back surface grinding (step S31) is removed and the mechanical strength is increased.

  Next, the silicon wafers 10 and 20 are diced into individual chips (step S33). Thereby, the separated chips (semiconductor devices 30 and 40) are completed.

  After that, when the separated semiconductor devices 30 and 40 are mounted on a package substrate or the like and wire bonding or resin sealing is performed, the MCP 50 is completed (step S34).

  In such a device post-process (step S30), heavy metals such as Cu and Ni may be mixed into the silicon substrates 11 and 21, particularly in the back grinding process (step S31) and the back polishing process (step S32). In the silicon wafers 10 and 20 according to the present embodiment, since the damage layers 11x and 21x serving as the contamination protection layers are provided on the silicon substrates 11 and 21, heavy metals such as Cu and Ni may reach the device region. Disappear.

  As described above, according to the present embodiment, since the damage layer serving as the contamination protection layer is provided on the silicon substrate, the final chip thickness is reduced to 100 μm or less, and the back surface is mirror-polished. Even in such a case, it is possible to ensure gettering ability and mechanical strength. In addition, since it is not necessary to inject a high concentration impurity to a deep position of the silicon substrate in order to form a damaged layer, application to a mass-produced product is also preferable.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

[Comparative Example 1]
A plurality of boron-doped CZ wafers having a diameter of 100 mm, a thickness of 525 μm, an initial oxygen concentration of 1.1 × 10 ¹⁸ atoms / cm ³ and a specific resistance of 10 Ω · cm were prepared.

[Comparative Example 2]
One sample of Comparative Example 1 was used, and silicon epitaxial growth was performed on the surface. As a condition, a p-type epitaxial film having a specific resistance of 5 Ω · cm was grown to a thickness of 3 μm by flowing diborane gas simultaneously with trichlorosilane gas.

[Example 1]
Four samples of Comparative Example 1 were used, and boron was ionized from the surface side of the substrate using a high energy ion implantation apparatus. The implantation energy was adjusted so that the concentration peak was 3 μm deep from the surface. The dose was set to 1 × 10 ¹³ atoms / cm ² , 5 × 10 ¹³ atoms / cm ² , 9 × 10 ¹³ atoms / cm ² , and 3 × 10 ¹⁴ atoms / cm ² for each sample.

[Comparative Example 3]
A sample of Comparative Example 3 was produced under the same conditions as in Example 1 except that one sample of Comparative Example 1 was used and the dose was set to 1 × 10 ¹⁵ atoms / cm ² .

[Example 2]
Four samples of Comparative Example 1 were used, and ion implantation was performed from the surface side of the substrate using a high current ion implantation apparatus. As the ion species, nitrogen, carbon, oxygen, phosphorus, antimony, silicon, argon, and fluorine were selected for each sample. The implantation energy was adjusted so that the concentration peak had a depth of 0.4 μm or less from the surface. The dose was set to 7.5 × 10 ¹³ atoms / cm ² .
Next, silicon epitaxial growth was performed on the surface of the ion-implanted substrate. As conditions, a p-type epitaxial film having a specific resistance of 5 Ω · cm was grown to a thickness of 3 μm by using diborane gas and trichlorosilane gas.

[Example 3]
A plurality of high-concentration boron-doped CZ wafers having a diameter of 100 mm, a thickness of 525 μm, an initial oxygen concentration of 1.3 × 10 ¹⁸ atoms / cm ³ , and a specific resistance adjusted to 200 mΩ · cm to 250 mΩ · cm were prepared. Ions were implanted from the surface side of the substrate using a high current type ion implantation apparatus. Boron, silicon or argon was selected for each sample. The implantation energy was adjusted so that the concentration peak had a depth of 0.3 μm or less from the surface. The dose was set to 7.5 × 10 ¹³ atoms / cm ² .
Next, silicon epitaxial growth was performed on the surface of the ion-implanted substrate. As conditions, a p-type epitaxial film having a specific resistance of 5 Ω · cm was grown to a thickness of 3 μm by using diborane gas and trichlorosilane gas.

[Evaluation 1]
All samples were subjected to a heat treatment simulating a low-temperature process in the device pre-process, and then a back grind tape was attached to the surface and ground from the back surface side, so that the final thickness was 100 μm. Next, the ground surface was polished by 3 μm with a slurry to which 20 ppb Cu was added.
The obtained sample was allowed to stand for 30 days and then the Cu concentration diffused on the surface was measured by total reflection fluorescent X-ray evaluation.
As a result, in Comparative Examples 1 and 2, 1.2 × 10 ¹¹ atoms / cm ² of Cu was detected on the surface. On the other hand, in the samples of Examples 1 to 3 and Comparative Example 3, it was confirmed that the Cu concentration on the surface was 1.0 × 10 ¹⁰ atoms / cm ² or less.
However, the sample of Comparative Example 3 requires 2.5 to 100 times the injection time as compared with the sample of Example 1, and it is considered that application to a mass-produced product is not realistic.

[Evaluation 2]
All samples were contaminated with Ni at a surface concentration of 1 × 10 ¹² atoms / cm ² and heat-treated at 1000 ° C. for 30 minutes. Thereafter, selective etching (Wright Etching) was performed, and surface defects were observed. As a result, Ni-induced surface defects were not observed in the ion-implanted sample, but many defects occurred on the surface of the sample that was not implanted.

DESCRIPTION OF SYMBOLS 10,20 Silicon wafer 11,21 Silicon substrate 11a, 21a Silicon substrate surface 11b, 21b Silicon substrate back surface 11x, 21x Damage layer 22 Epitaxial film 30, 40 Semiconductor device 50 MCP
51 Package Substrate 52 Adhesive 53 Bonding Wire 54 External Electrode 55 Sealing Resin

Claims (8)

A contamination protective layer formed at a depth of 1 μm or more and 10 μm or less from a surface on which a device is formed and introduced with nonmetallic ions having a dose of 1 × 10 ¹³ / cm ² or more and 3 × 10 ¹⁴ / cm ² or less A silicon wafer comprising:   The nonmetal ion is one or more elements selected from the group consisting of boron, phosphorus, antimony, arsenic, helium, argon, carbon, nitrogen, oxygen, fluorine, silicon, and germanium. Item 2. The silicon wafer according to Item 1.   3. The silicon wafer according to claim 1, further comprising a silicon substrate and an epitaxial film formed on the silicon substrate, wherein the surface is constituted by the epitaxial film.   The silicon wafer according to claim 3, wherein the contamination protective layer is formed to a depth of less than 2 μm from the surface of the silicon substrate. Maximum concentration peak is formed by ion implantation of nonmetallic ions having a dose of 1 × 10 ¹³ / cm ² or more and 3 × 10 ¹⁴ / cm ² or less at a depth of 1 μm or more and 10 μm or less from the surface on which the device is formed. A method for producing a silicon wafer, comprising a contamination protective layer forming step.   The nonmetal ion is one or more elements selected from the group consisting of boron, phosphorus, antimony, arsenic, helium, argon, carbon, nitrogen, oxygen, fluorine, silicon, and germanium. Item 6. A method for producing a silicon wafer according to Item 5. The contamination protective layer forming step is performed by ion-implanting the non-metal ions to a depth of less than 2 μm from the surface of the silicon substrate,
The method for manufacturing a silicon wafer according to claim 5, further comprising an epitaxial step of forming an epitaxial film on a surface of the silicon substrate after performing the contamination protective layer forming step. Contamination protection by implanting non-metallic ions with a dose of 1 × 10 ¹³ / cm ² or more and 1 × 10 ¹⁴ / cm ² or less to a depth of 1 μm to 10 μm from the surface of the silicon wafer on which the device is formed A contamination protective layer forming step for forming a layer;
A device pre-process for forming a semiconductor element on the surface after performing the contamination protective layer forming step,
After performing the device pre-process, by removing a part of the silicon wafer from the back side, a thinning process to make the thickness of the silicon wafer 100 μm or less,
And a back surface polishing step for polishing the back surface of the thinned silicon substrate.

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