JP2010287845A - Manufacturing method of semiconductor integrated circuit device - Google Patents

Abstract

In the manufacturing process of a nonvolatile memory device, the film thickness of each layer is measured by spectroscopic ellipsometry of the film thickness of a so-called ONO film. However, with the miniaturization of devices, the film thickness variation in the wafer increases, and there is a problem that it does not fall within the management range. According to the study by the present inventor, it has been clarified that the main cause of such an increase in the variation is not the variation in the process but the lack of film thickness separation between the multilayer films of the spectroscopic ellipsometry.
In the present invention, when measuring / analyzing the thickness of an ONO insulating film constituting a non-volatile memory cell by spectroscopic ellipsometry, the combined thickness of the lower silicon oxide film and the upper silicon oxide film (both The film thickness of the upper silicon oxide film is obtained by subtracting the film thickness of the lower silicon oxide film previously measured for a single layer.
[Selection] Figure 7

Description

  The present invention relates to a technique effective when applied to an insulation film thickness inspection technique in a method for manufacturing a semiconductor integrated circuit device (or a semiconductor device).

  In Japanese Patent Laid-Open No. 2004-286468 (Patent Document 1), when measuring / analyzing the thickness of a multilayer insulating film composed of three layers of silicon oxide film / silicon nitride film / silicon oxide film by spectroscopic ellipsometry In addition, a technique for improving the analysis accuracy by reducing the parameters by adopting a model in which the optical constants of the upper and lower silicon oxide films are the same and the silicon oxide film including voids is used as the optical constant of the silicon nitride film is disclosed. .

  Japanese Unexamined Patent Application Publication No. 2004-356112 (Patent Document 2) discloses a technique for evaluating the film thickness of a multilayer insulating film composed of three layers of silicon oxide film / silicon nitride film / silicon oxide film by single-wavelength ellipsometry. Has been.

  Japanese Patent Application Laid-Open No. 11-94525 (Patent Document 3) discloses a technique for determining the presence or absence of the uppermost film of a multilayer film by interference spectroscopy.

  In Japanese Patent Laid-Open No. 7-4922 (Patent Document 4), Fourier IR spectroscopic data is converted to obtain a spatial waveform for fitting the thickness of a compound semiconductor multilayer epitaxial film. Techniques to do are disclosed.

JP 2004-286468 A JP 2004-356112 A Japanese Patent Laid-Open No. 11-94525 Japanese Patent Laid-Open No. 7-4922

  In the manufacturing process of a nonvolatile memory device such as a flash memory, it is important to manage the film thickness of a multilayer insulating film composed of three layers of silicon oxide film / silicon nitride film / silicon oxide film. For this reason, generally, the film thickness of each layer is measured / analyzed by spectroscopic ellipsometry using continuous spectrum light.

  However, with the miniaturization of devices, the film thickness variation in the wafer increases, and there is a problem that it does not fall within the management range. According to the study by the present inventor, it is clear that the main cause of such an increase in the variation is not the variation in the process, but the lack of film thickness separation between the multilayer films of the spectroscopic ellipsometry. became.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a manufacturing process of a highly reliable semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, one invention of the present application is to determine the film thickness of a multilayer insulating film (so-called ONO insulating film) composed of three layers of a lower layer silicon oxide film / an intermediate silicon nitride film / an upper layer silicon oxide film constituting a nonvolatile memory cell. When measuring / analyzing using spectroscopic ellipsometry, obtain the composite thickness (sum of both thicknesses) of the lower silicon oxide film and upper silicon oxide film, and then measure the lower layer previously measured as a single layer. The film thickness of the upper silicon oxide film is obtained by subtracting the film thickness of the silicon oxide film.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the thickness of a multilayer insulating film (so-called ONO insulating film) composed of three layers of a lower silicon oxide film / intermediate silicon nitride film / upper silicon oxide film constituting a nonvolatile memory cell is measured by spectroscopic ellipsometry / When analyzing, obtain the composite film thickness of the lower silicon oxide film and upper silicon oxide film (sum of both film thicknesses), and then calculate the thickness of the lower silicon oxide film that was measured in advance for a single layer. By subtracting, by obtaining the film thickness of the upper silicon oxide film, it is possible to eliminate the influence of the lower film as much as possible and to realize highly accurate film thickness measurement.

1 is a schematic cross-sectional view of a main part of a memory cell of a split gate type MONOS (Metal Oxide Semiconductor Semiconductor) memory device manufactured by a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present application; It is a principal part schematic sectional drawing of the flash memory cell of the flash memory mounting device manufactured by the manufacturing method of the semiconductor integrated circuit of one embodiment of this application. It is a wafer top view which illustrates distribution in the wafer of the inspection field (film thickness measurement pad) used as the object of film thickness measurement in the manufacturing method of the semiconductor integrated circuit of one embodiment of this application. FIG. 4 is an enlarged plan view of the periphery of the inspection region (film thickness measurement pad) in FIG. 3. FIG. 5 is an enlarged schematic cross-sectional view around the film thickness measurement pad of FIG. 4. It is a schematic cross section of a device to be inspected and an inspection apparatus showing a state of a film thickness measurement step in the method for manufacturing a semiconductor integrated circuit according to one embodiment of the present application. FIG. 5 is a process block flow diagram showing a flow of main processes in a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present application. It is a plot figure which shows the correlation of the upper layer oxide film thickness measured value (Toxt) and silicon nitride film thickness measured value (Tsin) in the multilayer film thickness measurement by ellipsometry. It is a plot figure which shows the correlation of the upper layer oxide film thickness measured value (Toxt) and the lower layer oxide film thickness measured value (Toxb) in the multilayer film thickness measuring method by ellipsometry. It is the measurement data distribution figure in a wafer which compared the upper layer oxide film thickness measured value (Toxt) in the multilayer film thickness measuring method by ellipsometry, and the total film thickness measured value (Toxt + Toxb) of an upper layer oxide film thickness and a lower layer oxide film thickness.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a first silicon oxide film in each of a chip region and an inter-chip region on the first main surface of the semiconductor wafer;
(B) a step of optically measuring the thickness of the first silicon oxide film;
(C) a step of forming a silicon nitride film on the first silicon oxide film in each region after the step (b);
(D) forming a second silicon oxide film on the silicon nitride film in each region;
(E) After the step (d), spectroscopic ellipsometry is performed on the inspection region including the first silicon oxide film, the silicon nitride film, and the second silicon oxide film in the inter-chip region. A step of measuring a composite film thickness composed of the first silicon oxide film and the second silicon oxide film.

2. In the method of manufacturing a semiconductor integrated circuit device according to the item 1,
(F) A step of obtaining film thickness information of the second silicon oxide film based on the results of the step (b) and the step (e).

3. In the method of manufacturing a semiconductor integrated circuit device according to the item 1 or 2,
(G) before the step (a), forming a gate insulating film on the first main surface of the semiconductor wafer in each region;
(H) before the step (a), a step of forming a silicon-based conductor film on the gate insulating film in each region;
(I) A step of removing the gate insulating film and the silicon-based conductor film in the inspection region before the step (a).

  4). In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 1 to 3, the region including the first silicon oxide film, the silicon nitride film, and the second silicon oxide film in the chip region is , A memory cell of a non-volatile memory device.

  5. 5. The method for manufacturing a semiconductor integrated circuit device according to item 4, wherein the nonvolatile memory device is a split gate type MONOS memory device.

  6). 5. The method for manufacturing a semiconductor integrated circuit device according to the item 4, wherein the nonvolatile memory device is a flash memory device.

  7). In the method for manufacturing a semiconductor integrated circuit device according to any one of the above items 1, the optical film thickness measurement in the step (b) is performed on a portion corresponding to the inspection region.

  8). 8. In the method of manufacturing a semiconductor integrated circuit device according to any one of 1 to 7, the optical film thickness measurement is performed by ellipsometry.

  9. In the method of manufacturing a semiconductor integrated circuit device according to any one of 2 to 8, the acquisition of the film thickness information of the second silicon oxide film is measured in the step (b) from the composite film thickness. This is performed by subtracting the thickness of the first silicon oxide film.

  10. 10. The method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 9, wherein the semiconductor wafer is a silicon-based semiconductor wafer.

  11. 11. In the method of manufacturing a semiconductor integrated circuit device according to any one of 2 to 10, the acquisition of the film thickness information of the second silicon oxide film and the first silicon oxide film measured in the step (b) The film thickness information is acquired by the same apparatus, and is executed by acquiring the film thickness information obtained by subtracting the film thickness of the first silicon oxide film from the total film thickness.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor integrated circuit device” mainly refers to a device in which resistors, capacitors, and the like are integrated on a semiconductor chip or the like (for example, a single crystal silicon substrate) mainly with various transistors (active elements). . Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, as a typical integrated circuit configuration, a CMIS (Complementary Metal Insulator Semiconductor) integrated circuit represented by a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit in which an N-channel MISFET and a P-channel MISFET are combined. Can be illustrated.

  A semiconductor process of today's semiconductor integrated circuit device, that is, a LSI (Large Scale Integration) wafer process is usually performed from the introduction of a silicon wafer as a raw material to a pre-metal process (between the lower end of the M1 wiring layer and the gate electrode structure). Starting from the formation of interlayer insulation film, contact hole formation, tungsten plug, embedding, etc. (FEOL (Front End of Line) process) and M1 wiring layer formation, the final The process can be roughly divided into a BEOL (Back End of Line) process up to the formation of the pad opening in the passivation film (including the process in the wafer level package process). Of the FEOL process, the gate electrode patterning process, the contact hole forming process, and the like are microfabrication processes that require particularly fine processing. On the other hand, in the BEOL process, a via and trench formation process, in particular, a relatively lower local wiring (for example, M1 to M3 in a buried wiring having a structure of about four layers, M1 in a buried wiring having a structure of about 10 layers. In particular, fine processing is required for fine embedded wiring from M to around M5. Note that “MN (usually N = 1 to 15)” represents the N-th layer wiring from the bottom. M1 is a first layer wiring, and M3 is a third layer wiring.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or Carbon-doped Silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NSC), etc., coated silicon oxide, silica-based low-k insulating film (porous) with pores introduced in the same materials Needless to say, it includes a composite insulating film and other silicon-based insulating films having these as main components.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  Note that SiC has similar properties to SiN, but SiON is often rather classified as a silicon oxide insulating film.

  The silicon nitride film is frequently used as an etch stop film in SAC (Self-Aligned Contact) technology, and also used as a stress applying film in SMT (Stress Memory Technique).

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device or an electronic device) is formed. Insulation of an epitaxial wafer, an SOI substrate, an LCD glass substrate, etc. Needless to say, it includes a composite wafer such as a substrate and a semiconductor layer.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

  The details of the split gate type MONOS (Metal Oxide Semiconductor Semiconductor) memory device are described in detail in Japanese Unexamined Patent Publication No. 2009-54707 by Ishimaru et al. The description of will not be repeated.

1. Description of various examples of target devices in a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present application (mainly FIGS. 1 and 2)
FIG. 1 is a schematic cross-sectional view of a main part of a memory cell of a split gate type MONOS (Metal Oxide Semiconductor Semiconductor) memory device manufactured by a method of manufacturing a semiconductor integrated circuit according to an embodiment of the present application. FIG. 2 is a schematic cross-sectional view of a main part of a flash memory cell of a flash memory mounted device manufactured by the method for manufacturing a semiconductor integrated circuit according to the embodiment of the present application.

  First, the main part related to the present invention among the memory cells of the split gate type MONOS memory device will be described with reference to FIG. As shown in FIG. 1, for example, a 300-phi (200-phi or 450-phi) p-type single crystal silicon wafer 1 (which may be an n-type substrate as required. A multilayer insulating film 7 is provided on the device surface of the SOI substrate (which may be an SOI substrate), that is, the first main surface 1a (the back surface, that is, the surface opposite to the second main surface 1b). A memory gate electrode 5 (silicon conductor film such as a polysilicon film) and a control gate electrode 6 (polysilicon film) constituting the gate are provided. The multilayer insulating film 7 is a single layer of only the silicon oxide film 2 under the control gate electrode 6. However, the lower layer silicon oxide film 2 (first oxide film 2) is provided under the memory gate electrode 5 and between both gates. (Silicon film), intermediate silicon nitride film 3 (silicon nitride film), and upper silicon oxide film 4 (second silicon oxide film). Further, n-type source / drain regions 13 are provided in the surface region of the semiconductor substrate 1 on both sides of both gate electrodes (the same applies to FIG. 2). Here, the film thickness management target portion 14 is shown surrounded by a broken line (the same applies to FIG. 2).

  Next, a main part related to the present invention in the flash memory cell will be described with reference to FIG. As shown in FIG. 2, as in the case of FIG. 1, for example, on the device surface of the 300-phi p-type single crystal silicon wafer 1, that is, on the first main surface 1a, the gate insulating film 8 is interposed, A floating memory gate electrode 5 (silicon conductor film such as a polysilicon film) is provided. On the floating memory gate electrode 5, a multilayer insulating film 7 having the same multilayer structure is provided. Further thereon, a control gate electrode 6 (polysilicon film) is provided.

  The film thickness measurement technique described below is particularly suitable when applied mainly to the film thickness measurement of a multilayer insulating film such as the nonvolatile memory exemplified here.

2. Outline of film thickness measurement in manufacturing method of semiconductor integrated circuit device of one embodiment of the present application (mainly FIGS. 3 to 6)
Here, an outline of film thickness measurement during the device manufacturing process will be described.

  FIG. 3 is a wafer top view illustrating the distribution in the wafer of the inspection region (film thickness measurement pad) to be subjected to film thickness measurement in the method of manufacturing a semiconductor integrated circuit according to the embodiment of the present application. FIG. 4 is an enlarged plan view of the periphery of the inspection region (film thickness measurement pad) of FIG. FIG. 5 is an enlarged schematic cross-sectional view around the film thickness measurement pad of FIG. FIG. 6 is a schematic cross-sectional view of a device to be inspected and an inspection apparatus showing a state of a film thickness measurement step in the method for manufacturing a semiconductor integrated circuit according to one embodiment of the present application.

  Film thickness measurement during the manufacturing process is mainly performed to manage film thickness variations of various films within or between wafers. Therefore, as shown in FIG. 3, there are a plurality of inspection areas 9 (film thickness measurement pads) as indicated by broken circles in the entire area where the chip area 11 is provided on the device surface 1 a of the product wafer 1. Arranged (here, for example, 9).

  As shown in FIG. 4, the inspection area 9 (film thickness measurement pad) is provided in the scribe area 12 (interchip area) (the length of one side of the film thickness measurement pad is, for example, 50 to 70 micrometers). degree). As shown in FIG. 5, a lower silicon oxide film (first silicon oxide film) 2, an intermediate silicon nitride film (silicon nitride film) 3, and an upper silicon oxide film (first film) constituting the multilayer insulating film 7 in the inspection region 9. 2 is formed simultaneously with each element film by the same film formation process as each element film of the multilayer insulating film 7 in the chip region 11 of FIG. 1 or FIG.

  Actual film thickness measurement of the multilayer film is executed as shown in FIG. As shown in FIG. 6, for example, white inspection light 16 from a continuous spectrum light source 15 (for example, a wavelength of about 250 nm to about 800 nm) such as a xenon lamp enters the film thickness measurement pad 9 and is reflected by multiple reflections. 17 is detected by a photodetector 18 (generally a Fourier spectroscopic system including a polarizer), and is electrically or electronically decomposed into each wavelength component of the amplitude. Thereafter, in the ellipsometer 19, a theoretical value created according to a predetermined model and a fitting process for each amplitude component are executed, and an appropriate measurement value is output.

3. Description of principal part process flow in manufacturing method of semiconductor integrated circuit device according to one embodiment of the present application (mainly FIG. 7, refer to FIGS. 1 to 6 as appropriate)
Here, based on the above description, the details of the main part process flow in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  FIG. 7 is a process block flow diagram showing a flow of main processes in the method of manufacturing a semiconductor integrated circuit according to the embodiment of the present application.

  A process flow in the case of the device structure as shown in FIG. 1 will be described with reference to FIG. First, the device surface 1a of the semiconductor substrate 1 (wafer) is thermally oxidized, for example, to form a gate insulating film 10 (for example, a film thickness of about 2 to 7 nm), and a polysilicon film 6 is formed thereon by CVD. To do. The polysilicon film 6 and the gate insulating film 10 are patterned by ordinary lithography, thereby forming a gate structure including the left control gate electrode 6 and the gate insulating film 10 therebelow. At this time, since the polysilicon film 6 and the gate insulating film 10 are removed from the film thickness measurement pad 9 (inspection region), the device surface 1a of the semiconductor substrate 1 is exposed.

  Next, as shown in FIG. 7, the lower silicon oxide film 2 (first oxidized film) is formed by subjecting almost the entire device surface 1a of the semiconductor substrate 1 and the surface of the control gate electrode 6 to thermal oxidation. (Silicon film) is formed (for example, the film thickness is about 2 to 7 nm). At the same time, the lower silicon oxide film 2 is also formed in the inspection region 9 (lower oxide film forming step 21). Next, the film thickness Toxb of the lower silicon oxide film 2 is measured by an optical method such as ellipsometry (or other film thickness measurement method), for example, in the inspection region 9 (for example, 9 points in FIG. 3) ( Lower oxide film thickness measurement step 22). The film thickness data acquired here is stored in the control management system 20 of the ellipsometer 19 (FIG. 6). The film thickness measurement here may use the inspection region 9.

  Next, a silicon nitride film 3 (for example, a film thickness of about 7 to 20 nm) is formed by CVD on substantially the entire device surface 1a of the semiconductor substrate 1 and on the surface (including side surfaces) of the control gate electrode 6 (intermediate thickness). Nitride film forming step 23). At the same time, the silicon nitride film 3 is also formed in the inspection region 9.

  Subsequently, for example, by oxidizing the surface of the silicon nitride film 3 by thermal oxidation, an upper silicon oxide film 4 (second silicon oxide film) is formed (upper oxide film forming step 24). At the same time, the upper silicon oxide film 4 is also formed in the inspection region 9. At this time, the thickness of the upper silicon oxide film 4 is about 2 to 7 nm.

  Next, by spectroscopic ellipsometry using an ellipsometer 19 (FIG. 6), for example, in the inspection region 9 (for example, 9 points in FIG. 3), the sum of the thickness of the lower silicon oxide film 2 and the upper silicon oxide film 4 is summed. (Total oxide film thickness) is measured (multilayer film thickness measuring step 25). Actual measurement and acquisition of desired film thickness data (acquisition of total oxide film thickness data) are performed by well-known spectroscopic ellipsometry, but in principle, measured amplitude data and total oxide film thickness (Toxb + Toxt) ) And the theoretical amplitude data using the silicon nitride film thickness Tsin as a parameter, the parameter value when both coincide is output as the detected total oxide film thickness value. When the variation in the silicon nitride film thickness Tsin is relatively small, the fitting process speed can be increased by fixing the average value.

  The total oxide film thickness data obtained here is stored in the control management system 20 of the ellipsometer 19 (FIG. 6) and used for film thickness management and feedback to the process, as before. When necessary, the difference between the total oxide film thickness and the previously obtained lower silicon oxide film 2 thickness, that is, the film thickness Tox of the upper silicon oxide film 4 based on the difference is output to control the film thickness. Used for feedback to processes.

  Next, a polysilicon film is formed on almost the entire surface of the upper silicon oxide film 4 by CVD, and this is patterned together with the multilayer insulating film 7 by, for example, anisotropic dry etching, etc., and the memory gate electrode 5 (silicon System conductor film). Further, the source / drain regions 13 on both sides are introduced by ion implantation or the like. The subsequent processes are standard processes common to the manufacture of ordinary semiconductor integrated circuit devices, and will not be repeated here.

  Next, the process flow in the case of the device structure as shown in FIG. 2 will be described with reference to FIG. Here, only a different part from the case of FIG. 1 is demonstrated. As shown in FIG. 2, in the case of a flash memory device, the portion to be subjected to film thickness management is on the memory gate electrode 5 (silicon-based conductor film). ), It is necessary to remove the silicon-based conductor film 5 and the gate insulating film 8 of the memory gate before measurement. Hereinafter, the formation of the gate insulating film 8 of the memory gate will be described.

  First, as shown in FIG. 2, the gate insulating film 8 of the memory gate is formed by subjecting the device surface 1a of the semiconductor substrate 1 to thermal oxidation. At the same time, the gate insulating film 8 is also formed in the inspection region 9. Subsequently, a polysilicon film 5 serving as a floating gate is formed on the gate insulating film 8 by CVD. At the same time, the polysilicon film 5 is also formed in the inspection region 9.

  Here, as shown in FIG. 7, in the inspection region 9, the polysilicon film 5 and the gate insulating film 8 are removed by dry etching or the like (may be wet etching) (insulating film & polysilicon film removing step 26). ). This is because it is difficult to measure the thickness of the multilayer film if there is a polysilicon film, another silicon oxide film, or the like on the base. This step is performed simultaneously with the patterning in the direction perpendicular to the plane of the drawing for the polysilicon film 5 to be the floating gate of FIG. 2, for example.

  The subsequent steps from the lower oxide film forming step 21 to the multilayer film thickness measuring step 25 in FIG. 7 are substantially the same as those described with reference to FIG. 1, and will not be repeated here.

  After the multilayer film thickness measurement step 25 in FIG. 7, as shown in FIG. 2, a polysilicon film to be the control gate electrode 6 is formed on the upper silicon oxide film 4 (multilayer insulating film 7) by CVD. Subsequently, the polysilicon film 6, the multilayer insulating film (ONO film) 7, the polysilicon film 5, and the gate insulating film 8 are patterned by normal lithography to form a gate structure as shown in FIG. Further, the source / drain regions 13 on both sides are introduced by ion implantation or the like. The subsequent processes are standard processes common to the manufacture of ordinary semiconductor integrated circuit devices, and will not be repeated here.

  As for the thermal oxidation of the silicon-based member or silicon nitride-based member used in each of the above-described steps, ISSG (InSG) using a general dry oxidation, wet oxidation, or a lamp heating oxidation furnace of Applied Materials, etc. It may be based on the Situ Steam Generation method.

  The silicon nitride film used in each process described above by CVD may be formed by a batch LP-CVD method, a single wafer LP-CVD method or an ALD (Atomic Layer Deposition) method.

4). Explanation and discussion of data (mainly Fig. 8 to Fig. 10)
FIG. 8 is a plot diagram showing the correlation between the upper layer oxide film thickness measurement value (Toxt) and the silicon nitride film thickness measurement value (Tsin) in the multilayer film thickness measurement by ellipsometry. FIG. 9 is a plot diagram showing the correlation between the measured value of the upper oxide film thickness (Toxt) and the measured value of the lower oxide film thickness (Toxb) in the multilayer film thickness measurement method using ellipsometry. FIG. 10 is an in-wafer measurement data distribution diagram comparing the upper layer oxide film thickness measurement value (Toxt) in the multilayer film thickness measurement method by ellipsometry with the total film thickness measurement value of the upper layer oxide film thickness and the lower layer oxide film thickness (Toxt + Toxb). It is.

  As shown in FIG. 9, when the ONO film 7 is measured by ordinary spectroscopic ellipsometry, there is a correlation between the lower oxide film thickness Toxb and the upper oxide film thickness Toxt. As a result, only the upper oxide film thickness Tox is separated. Difficult to do.

  As shown in FIG. 8, when the ONO film 7 is measured by ordinary spectroscopic ellipsometry, the fluctuation of the upper oxide film thickness Toxt is caused by the film thickness fluctuation of the silicon nitride film thickness Tsin, that is, the upper layer oxidation shown in FIG. It becomes difficult to separate the film thickness Tox from the lower oxide film thickness.

  Further, as shown in FIG. 10, the variation in the upper oxide film thickness Toxt within the wafer when the ONO film 7 is measured by the normal spectroscopic ellipsometry is relatively large, but the total film thickness measured by the spectroscopic ellipsometry is measured. It can be seen that the value obtained by subtracting the lower oxide film thickness Toxb measured in the case of a single layer from the measured value (Toxt + Toxb), that is, the upper oxide film thickness Toxt as a difference has small variations in the wafer. That is, since the lower layer silicon oxide film 2 (first silicon oxide film) and the upper layer silicon oxide film 4 (second silicon oxide film) are optically homogeneous films, it is not possible to separate both in the multilayer film measurement. Although it is difficult, it is difficult to separate the intermediate silicon nitride film 3 (silicon nitride film) having different optical characteristics from that of the lower silicon oxide film 2 and the upper silicon oxide film 4 by spectroscopic ellipsometry. It is relatively easy.

  Therefore, as described in section 3, when the thickness of the ONO film 7 is managed using the lower layer oxide film thickness Toxb measured in a single layer and the total film thickness measurement value (Toxt + Toxb) as management parameters, the upper layer oxide film thickness Toxt Monitoring and management can be performed with high accuracy.

5). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the ONO film has been specifically described. However, the present invention is not limited thereto, and can be similarly applied to a next-generation film including a high dielectric film. Needless to say. In the above-described embodiment, the three-layer film has been specifically described. However, the present invention is not limited thereto, and it goes without saying that the present invention can be similarly applied to a multilayer film such as a four-layer film and a five-layer film. Yes.

  In the above embodiment, the flash memory has been specifically described by taking the NOR type as an example. However, the present invention is not limited to this, and other types of flash memory such as a NAND type are available. Needless to say, the present invention can be applied to a memory device, a flash memory mounted device, and the like.

  In the above-described embodiment, the thickness data of the lower oxide film and the upper oxide film are separately transferred to the control management system, but measured by the same device, and the lower layer thickness is subtracted from the total thickness in the device. Needless to say, this can also be achieved by sending the film thickness to the control management system.

1 Wafer (semiconductor substrate)
1a Device surface of wafer (first main surface)
1b Wafer back surface (second main surface)
2 Lower silicon oxide film (first silicon oxide film)
3 Intermediate silicon nitride film (silicon nitride film)
4 Upper layer silicon oxide film (second silicon oxide film)
5 Memory gate electrode (silicon conductor film)
6 Control gate electrode 7 Multilayer insulation film (ONO film)
8 Gate insulating film (for memory gate) 9 Inspection area (film thickness measurement pad)
10 Gate insulating film (of control gate) 11 Chip region 12 Scribe region (inter-chip region)
Reference Signs List 13 Source / drain region 14 Controlled part 15 Light source 16 Inspection light 17 Reflected light 18 Photodetector (Fourier spectroscopic system generally including polarizer)
19 Ellipsometer 20 Ellipsometer control management system 21 Lower oxide film formation process 22 Lower oxide film thickness measurement 23 Intermediate nitride film formation process 24 Upper oxide film formation process 25 Multilayer film thickness measurement process 26 Gate insulating film & polysilicon film removal process Toxb Lower layer Oxide thickness Toxt Upper oxide thickness Tsin Silicon nitride thickness

Claims (11)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a first silicon oxide film in each of a chip region and an inter-chip region on the first main surface of the semiconductor wafer;
(B) a step of optically measuring the thickness of the first silicon oxide film;
(C) a step of forming a silicon nitride film on the first silicon oxide film in each region after the step (b);
(D) forming a second silicon oxide film on the silicon nitride film in each region;
(E) After the step (d), spectroscopic ellipsometry is performed on the inspection region including the first silicon oxide film, the silicon nitride film, and the second silicon oxide film in the inter-chip region. A step of measuring a composite film thickness composed of the first silicon oxide film and the second silicon oxide film. In the method of manufacturing a semiconductor integrated circuit device according to the item 1,
(F) A step of obtaining film thickness information of the second silicon oxide film based on the results of the step (b) and the step (e). In the method of manufacturing a semiconductor integrated circuit device according to the item 1,
(G) before the step (a), forming a gate insulating film on the first main surface of the semiconductor wafer in each region;
(H) before the step (a), a step of forming a silicon-based conductor film on the gate insulating film in each region;
(I) A step of removing the gate insulating film and the silicon-based conductor film in the inspection region before the step (a).     2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the region including the first silicon oxide film, the silicon nitride film, and the second silicon oxide film in the chip region is a nonvolatile memory device. Memory cell.     5. The method for manufacturing a semiconductor integrated circuit device according to item 4, wherein the nonvolatile memory device is a split gate type MONOS memory device.     5. The method for manufacturing a semiconductor integrated circuit device according to the item 4, wherein the nonvolatile memory device is a flash memory device.     In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the optical film thickness measurement in the step (b) is performed on a portion corresponding to the inspection region.     In the method of manufacturing a semiconductor integrated circuit device according to the item 7, the optical film thickness measurement is performed by ellipsometry.     In the method of manufacturing a semiconductor integrated circuit device according to the item 2, the acquisition of the film thickness information of the second silicon oxide film is performed by measuring the first silicon oxide film measured in the step (b) from the composite film thickness. This is done by subtracting the film thickness.     In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the semiconductor wafer is a silicon-based semiconductor wafer.     In the method of manufacturing a semiconductor integrated circuit device according to the item 2, the acquisition of the film thickness information of the second silicon oxide film and the measurement of the film thickness information of the first silicon oxide film measured in the step (b). Acquisition is performed by the same apparatus, and is performed by acquiring film thickness information obtained by subtracting the film thickness of the first silicon oxide film from the total film thickness.

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