JP2010283288A - Wiring forming method and semiconductor device - Google Patents

Abstract

A fine via pattern can be formed while reducing the number of pattern design steps, the number of masks used, and overlay deviation.
An opening 21 corresponding to a second-layer wiring pattern in a hard mask film 18 and a portion exposed in a region where a first-layer wiring pattern and a corresponding opening 23 in a third resist pattern 22 are overlapped. Via openings 26 and 27 are formed by etching the interlayer insulating film 19A.
[Selection] Figure 3

Description

  The present invention relates to a wiring forming method and a semiconductor device, and more particularly to a dual damascene wiring forming method and a semiconductor device having a multilayer wiring structure.

  In recent years, as the miniaturization of semiconductors has accelerated, a structure for miniaturization has also been developed for a multilayer wiring structure. In particular, a damascene wiring structure formed by embedding copper in a groove and a dual damascene wiring structure formed by simultaneously embedding copper in a via hole and an upper layer wiring groove connecting multilayer wirings are becoming mainstream. . The dual damascene wiring forming method is roughly classified into a via first method in which an upper layer wiring groove is formed by etching after opening a via first, and a trench first method in which a via is opened after first forming an upper layer wiring groove. The trench first method has a drawback that a step in the trench pattern causes a focus shift during exposure when forming a via, and thus the via first method has been conventionally used.

  However, in order to improve the drawbacks of the trench first method, a method has been proposed in which the level difference is reduced by etching only a thin hard mask before forming a trench (wiring groove).

  On the other hand, with the progress of miniaturization, it becomes difficult to form via holes with a fine pitch. The reason for this is that the focal depth required when forming the hole pattern on the step of the multilayer wiring cannot be ensured, and that the annular illumination brings about the effect of improving the resolution and the focal depth in the formation of the line pattern. For example, oblique incidence illumination cannot be used to form a hole-based pattern because the focal depth of an isolated hole is reduced. In such a situation, pattern formation by multiple exposures has been proposed instead of pattern formation by single exposures conventionally performed (see, for example, Patent Document 1).

  Hereinafter, with reference to FIGS. 11A to 11C, FIGS. 12A to 12H, and FIGS. 13A to 13H, the wiring forming method in Patent Document 1, specifically, The trench first dual damascene wiring forming method will be described. 11A to 11C are plan views of masks used in the wiring forming method in Patent Document 1. FIG. FIGS. 12A, 12C, 12E, and 12G are cross-sectional views showing the steps of the wiring forming method in Patent Document 1, and FIGS. 12B, 12D, 12F. ) And (h) are plan views corresponding to FIGS. 12 (a), (c), (e) and (g), respectively. Here, FIG. 12A is a sectional view taken along line bb ′ of FIG. 12B, and FIG. 12C is a sectional view taken along line dd ′ of FIG. 12 (e) is a sectional view taken along line ff ′ of FIG. 12 (f), and FIG. 12 (g) is a sectional view taken along line hh ′ of FIG. 12 (h). Further, FIGS. 13A, 13C, 13E, and 13G are cross-sectional views showing respective steps of the wiring forming method in Patent Document 1, and FIGS. 13B, 13D, 13F. ) And (h) are plan views corresponding to FIGS. 13A, 13C, 13E, and 13G, respectively. Here, FIG. 13A is a cross-sectional view taken along line bb ′ in FIG. 13B, and FIG. 13C is a cross-sectional view taken along line dd ′ in FIG. 13 (e) is a cross-sectional view taken along line ff ′ of FIG. 13 (f), and FIG. 13 (g) is a cross-sectional view taken along line hh ′ of FIG. 13 (h).

  First, as shown in FIGS. 12A and 12B, after applying a resist 88A on the interlayer insulating film 90, a first-layer wiring mask having a first-layer wiring pattern 83 shown in FIG. 11A. 82 is used for pattern exposure, and then development is performed. As a result, as shown in FIGS. 12C and 12D, a resist pattern 88 having an opening 89 corresponding to the wiring pattern 83 is formed.

  Next, the interlayer insulating film 90 is etched using the resist pattern 88 as a mask to form a wiring groove, a metal is embedded in the wiring groove, and then the metal protruding from the wiring groove is removed by polishing. As a result, as shown in FIGS. 12E and 12F, a first layer metal wiring 91 is formed in the interlayer insulating film 90.

  Next, as shown in FIGS. 12G and 12H, a liner film 92, an interlayer insulating film 93, and a hard mask film 94 are sequentially deposited on the interlayer insulating film 90 and the first metal wiring 91. After that, a resist (not shown) is applied on the hard mask film 94, and then pattern exposure and development using the second-layer wiring mask 84 having the second-layer wiring pattern 85 shown in FIG. Do it sequentially. The hard mask film 94 is etched using the resist pattern (not shown) formed thereby as a mask, and then the resist pattern is removed. As a result, as shown in FIG. 12H, the hard mask film 94 is formed with a groove 95 corresponding to the second-layer wiring pattern extending in the vertical direction.

  Next, after applying a resist on the hard mask film 94 including the inside of the trench 95, pattern exposure and development processing using the via forming mask 86 having the via forming pattern 87 shown in FIG. Do. Thereby, as shown in FIGS. 13A and 13B, a resist pattern 96 having openings 97 extending in the lateral direction is formed. Here, the surface of the interlayer insulating film 93 is exposed at the intersection of the opening 97 extending in the horizontal direction in the resist pattern 96 and the groove (second wiring pattern) 95 extending in the vertical direction in the hard mask film 94. There is a square opening 98.

  Next, as shown in FIGS. 13C and 13D, a square via hole 99 is formed by selectively etching the portion of the interlayer insulating film 93 exposed in the square opening 98. .

  Next, after removing the resist pattern 96, as shown in FIGS. 13E and 13F, using the hard mask film 94 in which the groove (second-layer wiring pattern) 95 is formed as a mask, an interlayer insulating film 93 is formed. Is etched by a predetermined film thickness. As a result, a second-layer wiring trench 100 connected to the square via hole 99 is formed in the interlayer insulating film 93.

  Next, the portion of the liner film 92 exposed in the square via hole 99 is removed, and then metal is embedded in the via hole 99 and the second-layer wiring groove 100, and then the metal protruding from the second-layer wiring groove 100 is removed by polishing. To do. As a result, as shown in FIGS. 13G and 13H, the second-layer metal wiring 102 is formed and the metal via 101 connecting the first-layer metal wiring 91 and the second-layer metal wiring 102 is formed. It is formed. Here, the hard mask film 94 is removed when the metal is removed by polishing.

  According to the multilayer wiring forming method described above, the via forming pattern that should be originally formed in a square shape is formed in a rectangular shape (line shape), and the rectangular via forming pattern (the horizontal pattern in the resist pattern 96) is formed. By forming a substantial via pattern (square opening 98) at the intersection of the opening 97 extending in the direction and the second-layer wiring pattern (groove 95 extending in the vertical direction in the hard mask film 94), a via pattern is formed. The resolution and depth of focus during exposure can be improved.

JP 2005-150493 A

  However, according to the above-described wiring formation method of Patent Document 1, when forming the via, a resist pattern having a trench (opening extending in the lateral direction) intersecting with the second-layer wiring pattern of the hard mask film is formed, By etching only the interlayer insulating film exposed at the intersection between the second-layer wiring pattern and the trench, a via hole is formed. That is, the via formation mask pattern used for forming the via is a line pattern intersecting with the second-layer wiring pattern, and is different from the shape of the finally formed via. Therefore, it is necessary to design as a simple mask pattern. For this reason, the problem that a pattern design man-hour will increase arises.

  In addition, the number of masks used in the wiring formation method of Patent Document 1 described above is the same as that of a conventional via forming mask (the via forming mask pattern used at the time of forming the via has the same shape as the finally formed via. The number of masks is the same as when using For this reason, time and cost are required for the process accompanying the optical proximity effect correction and the mask defect inspection process.

  Further, compared to the conventional technique in which vias are formed by one mask (that is, one exposure), in the above-described conventional wiring forming method, vias are formed using two masks each having a line pattern. Therefore, since the influence of the overlay deviation at the time of mask pattern transfer is received from the exposure by each of the two masks, there is a concern that the overlay deviation between the via and the first layer wiring may be increased. The

  In view of the foregoing, an object of the present invention is to provide a wiring forming method and a semiconductor device that enable formation of a fine via pattern while reducing the number of pattern design steps, the number of masks used, and overlay deviation.

  In order to achieve the above object, according to the wiring forming method of the present invention, a first resist pattern is formed on a first interlayer insulating film using a first mask, and then the first resist pattern is formed. (A) forming a first wiring groove in the first interlayer insulating film as an etching mask; and removing the first resist pattern and then embedding a conductive material in the first wiring groove A step (b) of forming a first wiring; a step (c) of sequentially forming a second interlayer insulating film and a hard mask film on the first interlayer insulating film and on the first wiring; (D) forming a second resist pattern on the hard mask film using a second mask and then patterning the hard mask film using the second resist pattern as an etching mask; 2 Regis (E) forming a third resist pattern on the patterned hard mask film using the first mask after removing the pattern; and opening portions of the patterned hard mask film; A step (f) of forming a via opening by etching the portion of the second interlayer insulating film that is exposed in a region overlapping with the opening of the third resist pattern; (G) forming a second wiring groove connected to the via opening in the second interlayer insulating film using the patterned hard mask film as an etching mask after removing the resist pattern; Step (h) of forming a second wiring and a via for connecting the first wiring and the second wiring by embedding a conductive material in the second wiring groove and the via opening. It is equipped with a.

  In the wiring forming method according to the present invention, the first resist pattern and the third resist pattern may be formed using the same resist material.

  In the wiring formation method according to the present invention, the first resist pattern and the third resist pattern may be formed using the same exposure illumination conditions. In this case, the illumination stop under the same exposure illumination condition may be in a ring shape, a quadrupole shape, or a dipole shape.

  In the wiring formation method according to the present invention, in the step (e), the third resist pattern may be formed in alignment with the first wiring.

  In the wiring forming method according to the present invention, the via opening may be a via hole.

  In the wiring formation method according to the present invention, in the step (h), the vias may be formed in all portions of the second wiring that intersect with the first wiring.

  In the wiring forming method according to the present invention, the first wiring includes at least two kinds of wirings having different potentials, and in the step (g), the second wiring groove is formed of the first wiring. Of these, it may be formed only on a wiring having the same potential as the second wiring.

  In the wiring forming method according to the present invention, before the step (a), a third interlayer insulating film serving as a base of the first interlayer insulating film is formed on the substrate on which the active region and the gate electrode are formed. Then, the method further includes a step (i) of forming a plurality of contacts connected to each of the active region and the gate electrode in the third interlayer insulating film, and in the step (a), the first wiring The groove may be formed to reach the plurality of contacts. That is, a contact may be provided as a local wiring that connects each of the active region (source / drain region) and the gate electrode to the first wiring.

  The wiring forming method according to the present invention may further include a step (j) of forming a gap in the second interlayer insulating film after the step (h). That is, the wiring forming method according to the present invention may be combined with a so-called air gap wiring process.

  The semiconductor device according to the present invention includes a first wiring and a second wiring formed on the upper side of the first wiring, and all portions of the second wiring that intersect with the first wiring. In addition, a via for connecting the first wiring and the second wiring is formed.

  In the semiconductor device according to the present invention, the top surface shape of the via may have four or more sides.

  In the semiconductor device according to the present invention, at least one side of the upper surface shape of the via may be on the same line as the lower surface end of the second wiring. In this case, the other side of the upper surface shape of the via may be on the same line as the upper surface end of the first wiring.

  In the semiconductor device according to the present invention, the via may have a side surface continuous with a side surface of the second wiring.

  According to the present invention, since the first mask (first wiring formation mask) can be used as a via formation mask, the number of masks used can be reduced and the layout design of a new via formation mask pattern can be omitted. Therefore, the cost required for mask manufacturing, inspection, design, etc. can be reduced.

  According to the present invention, since the second wiring groove is formed using the hard mask pattern, the third resist pattern (via forming resist pattern) can be formed on the hard mask pattern having a small step. Therefore, even if the distance between vias is near the resolution limit, the vias can be separated and formed well, and the chip size can be reduced.

  Further, according to the present invention, since the first wiring and the via are formed using the same mask, the first wiring and the via are compared with the case where the first wiring and the via are formed using different masks. The overlay deviation with the via can be greatly reduced. Accordingly, since the connection area between the first wiring and the via can be increased, disconnection can be prevented and the wiring yield can be improved.

  Furthermore, according to the present invention, since the via shape is set by the intersection shape of the first wiring groove pattern and the second wiring groove pattern, the via shape is not limited to the conventional hole shape, but is also a line shape or a polygonal shape. Therefore, even when an air gap wiring structure is used, the mechanical strength of the multilayer wiring structure can be increased and the yield and reliability can be improved.

FIGS. 1A to 1D are plan views of a mask used in the wiring forming method according to the first embodiment of the present invention. FIGS. 2A, 2C and 2E are cross-sectional views showing respective steps of the wiring forming method according to the first embodiment of the present invention, and FIGS. 2B, 2D and 2F. These are the top views corresponding to each of Drawing 2 (a), (c), and (e). FIGS. 3A, 3C and 3E are cross-sectional views showing the steps of the wiring forming method according to the first embodiment of the present invention, and FIGS. 3B, 3D and 3F. These are the top views corresponding to each of Drawing 3 (a), (c), and (e). 4 (a), 4 (c) and 4 (e) are cross-sectional views showing respective steps of the wiring forming method according to the first embodiment of the present invention, and FIGS. 4 (b), 4 (d) and 4 (f). These are the top views corresponding to each of Drawing 4 (a), (c), and (e). FIGS. 5A and 5B are plan views of a mask used in the wiring formation method according to the comparative example, and FIG. 5C is a plan view of the semiconductor device according to the comparative example. (E) is sectional drawing of the yy 'line | wire and xx' line | wire of FIG.5 (c), respectively. FIGS. 6A to 6C are plan views of a mask used in the wiring forming method according to the first modification of the first embodiment of the present invention, and FIG. 6D is the first embodiment of the present invention. FIG. 6E and FIG. 6F are cross-sectional views taken along lines yy ′ and xx ′ of FIG. 6D, respectively. FIGS. 7A to 7C are plan views of masks used in the wiring forming method according to the second modification of the first embodiment of the present invention, and FIG. 7D is the first embodiment of the present invention. 7E is a plan view of a semiconductor device according to a second modification of the embodiment, and FIGS. 7E and 7F are cross-sectional views taken along lines yy ′ and xx ′ of FIG. 7D, respectively. FIG. 8A is a cross-sectional view of a semiconductor device according to a third modification of the first embodiment of the present invention, and FIG. 8B is a top view corresponding to FIG. FIG. 9 is a sectional view of a semiconductor device according to a fourth modification of the first embodiment of the present invention. FIG. 10 is a plan view showing an example of a via shape in the semiconductor device according to the first embodiment of the present invention. 11A to 11C are plan views of masks used in the wiring forming method in Patent Document 1. FIG. 12 (a), (c), (e), and (g) are cross-sectional views showing the steps of the wiring forming method in Patent Document 1, and FIGS. 12 (b), (d), (f), and FIG. (H) is a top view corresponding to each of Drawing 12 (a), (c), (e), and (g). 13 (a), (c), (e) and (g) are cross-sectional views showing the steps of the wiring forming method in Patent Document 1, and FIGS. 13 (b), (d), (f) and FIG. (H) is a top view corresponding to each of Drawing 13 (a), (c), (e), and (g).

(First embodiment)
Hereinafter, a wiring forming method according to a first embodiment of the present invention, specifically, a method based on a trench first dual damascene wiring forming method will be described with reference to the drawings.

  1A to 1D are plan views of a mask used in the wiring formation method of the present embodiment. 2A, 2C, and 2E are cross-sectional views showing the steps of the wiring forming method of the present embodiment, and FIGS. 2B, 2D, and 2F are diagrams. It is a top view corresponding to each of 2 (a), (c), and (e). 2A is a cross-sectional view taken along the line bb ′ of FIG. 2B, and FIG. 2C is a cross-sectional view taken along the line dd ′ of FIG. 2 (e) is a cross-sectional view taken along line ff ′ of FIG. 2 (f). 3A, 3C, and 3E are cross-sectional views showing the steps of the wiring forming method of the present embodiment, and FIGS. 3B, 3D, and 3F are diagrams. It is a top view corresponding to each of 3 (a), (c), and (e). Here, FIG. 3A is a cross-sectional view taken along the line bb ′ of FIG. 3B, and FIG. 3C is a cross-sectional view taken along the line dd ′ of FIG. 3 (e) is a cross-sectional view taken along the line ff ′ of FIG. 3 (f). Further, FIGS. 4A, 4C and 4E are cross-sectional views showing respective steps of the wiring forming method of the present embodiment, and FIGS. 4B, 4D and 4F are diagrams. It is a top view corresponding to each of 4 (a), (c), and (e). 4A is a sectional view taken along line bb ′ in FIG. 4B, and FIG. 4C is a sectional view taken along line dd ′ in FIG. 4 (e) is a sectional view taken along line ff ′ of FIG. 4 (f).

  First, as shown in FIGS. 2A and 2B, after forming the gate electrode 10 on the active region surrounded by the element isolation region 11 a in the substrate 11, the insulating side is formed on both side surfaces of the gate electrode 10. A wall spacer 10 a is formed, and then an interlayer insulating film 7 is formed on the substrate 11 including the gate electrode 10. Subsequently, a resist pattern (not shown) having an opening corresponding to the contact pattern 2 is formed using the contact formation mask 1 having the contact pattern 2 shown in FIG. Etching is performed on the interlayer insulating film 7 as a mask. As a result, a contact hole 8 reaching the gate electrode 10 and a contact hole 9 reaching the substrate 11 are formed.

  Next, as shown in FIGS. 2C and 2D, after the metal is buried in the contact holes 8 and 9, the metal protruding from the contact holes 8 and 9 is removed by polishing, and the gate electrode 10 is removed. And a metal contact 16 connected to the substrate 11 are formed. Thereafter, an interlayer insulating film 14 is formed on the interlayer insulating film 7 including the metal contacts 15 and 16, and then a resist is applied on the interlayer insulating film 14, and then, as shown in FIG. Development is performed after pattern exposure using the first layer wiring formation mask 3 having the layer wiring pattern 4. As a result, the resist in the portion irradiated with the light transmitted through the light transmitting portion that becomes the first layer wiring pattern 4 in the first layer wiring formation mask 3 is removed, and the portions shown in FIGS. A first resist pattern 12 is formed. The first resist pattern 12 has an opening (groove) 13 corresponding to the first-layer wiring pattern 4.

  Next, as shown in FIGS. 2E and 2F, the first resist pattern 12 is used as a mask to etch the interlayer insulating film 14 to form a first-layer wiring groove 14a, and then the first resist The pattern 12 is removed. Subsequently, after the metal is buried in the first layer wiring groove 14 a, the metal protruding from the first layer wiring groove 14 a is removed by polishing to form the first layer metal wiring 17.

  Next, as shown in FIGS. 3A and 3B, the liner film 20 </ b> A, the interlayer insulating film 19 </ b> A, and the hard mask film 18 are sequentially formed on the interlayer insulating film 14 including the first metal wiring 17. accumulate. Subsequently, after applying a resist (not shown) on the hard mask film 18, pattern exposure is performed using the second-layer wiring formation mask 5 having the second-layer wiring pattern 6 shown in FIG. Thereafter, development is performed. Using the second resist pattern (not shown) formed in this manner as a mask, the hard mask film 18 is etched, and then the second resist pattern is removed. Here, the hard mask film 18 has an opening (groove) 21 corresponding to the second-layer wiring pattern 6.

  Next, as shown in FIGS. 3C and 3D, after applying a resist on the hard mask film 18 including the opening 21, the first-layer wiring pattern 4 shown in FIG. 1B is provided. Pattern exposure is performed using the first layer wiring formation mask 3, and then development is performed. As a result, the resist in the portion irradiated with the light transmitted through the light transmitting portion that becomes the first-layer wiring pattern 4 in the first-layer wiring forming mask 3 is removed, as shown in FIGS. 3C and 3D. A third resist pattern 22 is formed. The third resist pattern 22 has an opening (groove) 23 corresponding to the first-layer wiring pattern 4. Here, at the intersection between the opening 23 corresponding to the first-layer wiring pattern 4 in the third resist pattern 22 and the opening 21 corresponding to the second-layer wiring pattern 6 in the hard mask film 18, there is an interlayer. There are a square opening 24 and a rectangular opening 25 that expose the surface of the insulating film 19A.

  Next, as shown in FIGS. 3E and 3F, by selectively etching the interlayer insulating film 19A in the square openings 24 and the portions exposed in the rectangular openings 25, an etching process is performed. Square via holes 26 and rectangular via openings 27 are formed.

  Next, after removing the third resist pattern 22, as shown in FIGS. 4A and 4B, the hard mask film 18 having the opening 21 corresponding to the second-layer wiring pattern 6 is used as a mask. The interlayer insulating film 19A is etched by a predetermined thickness. As a result, a second-layer wiring trench 28 connected to each of the square via hole 26 and the rectangular via opening 27 is formed in the interlayer insulating film 19A.

  Next, after removing the portion of the liner film 20A exposed in the square via hole 26 and the rectangular via opening 27, a metal is embedded in the square via hole 26 and the rectangular via opening 27 and the second-layer wiring groove 28, and then The metal protruding from the second-layer wiring groove 28 is removed by polishing. As a result, as shown in FIGS. 4C and 4D, the second-layer metal wiring 29 is formed, and the square metal vias connecting the first-layer metal wiring 17 and the second-layer metal wiring 29, respectively. 30 and a rectangular metal via 31 are formed. Here, the hard mask film 18 is removed when the metal is polished and removed.

  Next, as shown in FIGS. 4E and 4F, a liner film 20B, an interlayer insulating film 19B, and a hard mask film (not shown) are formed on the interlayer insulating film 19A including the second-layer metal wiring 29. ) Are sequentially deposited. Then, according to the procedure similar to the procedure from the process shown in FIGS. 3A and 3B to the process shown in FIGS. 4C and 4D described above, 3 shown in FIG. Using the third layer wiring formation mask 34 having the layer wiring pattern 35 and the second layer wiring formation mask 5 having the second layer wiring pattern 6 shown in FIG. In addition, a third-layer metal wiring 32 is formed, and a metal via 33 that connects the second-layer metal wiring 29 and the third-layer metal wiring 32 is formed.

  In this embodiment, a multilayer wiring having a three-layer structure is formed. However, a multilayer wiring having a structure of four or more layers may be formed by using the same procedure.

  As described above, according to the wiring forming method of the present embodiment, the via pattern that should be originally formed by exposure using the via forming mask is the opening corresponding to the second wiring pattern 6 in the hard mask film 18. It is formed as an intersection of the opening 21 corresponding to the first wiring pattern 4 in the portion 21 and the third resist pattern 22. For this reason, since the first layer wiring formation mask 3 can be used as a via formation mask, it is not necessary to use a via formation mask. Therefore, the manufacture and inspection of the via formation mask and the via formation mask pattern are eliminated. Layout design becomes unnecessary. In semiconductor device manufacturing, the ratio of costs related to masks used for lithography is increasing with miniaturization. However, in this embodiment, the mask-related costs are reduced by reducing the number of masks used. Can be suppressed.

  Further, according to the present embodiment, since the second layer wiring groove 28 is formed using the hard mask film 18 having the opening 21 corresponding to the second layer wiring pattern 6, the hard mask film 18 having a small step is formed on the hard mask film 18. A third resist pattern (via formation resist pattern) 22 can be formed. Therefore, even if the distance between vias is near the resolution limit, the vias can be separated and formed well, and the chip size can be reduced.

  In this embodiment, the first exposure using the first-layer wiring formation mask 3 for forming the first-layer wiring and the second exposure using the first-layer wiring formation mask 3 for forming vias are performed. In addition to using the same mask, the same resist material and the same exposure illumination conditions are used in the exposure of the first resist pattern 12 formed by the first exposure, and 2 The upper surface shape of the third resist pattern 22 formed by the second exposure can be made substantially the same. In this case, when the illumination diaphragm of the exposure illumination condition is in a ring shape, a quadrupole shape, or a dipole shape, an improvement in resolution and an increase in the depth of focus can be realized as compared with the conventional exposure for via formation.

  That is, by forming the first layer metal wiring 17 and the metal vias 30 and 31 using the same mask, compared to the case where the first layer metal wiring 17 and the metal vias 30 and 31 are formed using different masks. Thus, the overlay deviation between the first-layer metal wiring 17 and the metal vias 30 and 31 can be greatly reduced.

  In particular, by forming the third resist pattern 22 formed in the second exposure using the first-layer wiring formation mask 3 for via formation in alignment with the first-layer metal wiring 17, The metal vias 30 and 31 can be aligned with the first-layer metal wiring 17 with high accuracy.

  According to recent studies, it has been found that as one of the factors of mask pattern misalignment, the contribution of overlay misalignment caused by individual manufacturing differences between masks is large. However, according to the present embodiment, since the first-layer metal wiring 17 and the metal vias 30 and 31 are formed using the same mask, the influence of overlay deviation caused by individual manufacturing differences between the masks is reduced. It becomes smaller than the case where a via forming mask is used.

  As described above, according to the present embodiment, since the connection area between the first-layer metal wiring 17 and the metal vias 30 and 31 can be increased, disconnection can be prevented and the wiring yield can be improved.

  In addition, the semiconductor device manufactured by the wiring forming method according to the present embodiment (hereinafter referred to as the semiconductor device according to the present embodiment) has one layer at all intersections between the first layer metal wiring 17 and the second layer metal wiring 29. A via that connects the metal wiring 17 and the second metal wiring 29 is formed. When there are a plurality of first-layer wirings and second-layer wirings at different nodes, similar characteristics exist for each group. In the case where the third-layer metal wiring and the third-layer metal wiring are also formed in the same procedure as the second-layer metal wiring 29, the intersection between the second-layer metal wiring 29 and the third-layer metal wiring, and Similar characteristics also exist at other intersections of upper-layer wirings.

  In the semiconductor device of this embodiment, at least one side of the upper surface shape of the metal vias 30 and 31 is on the same line as the lower surface end of the second-layer metal wiring 29. In other words, the metal vias 30 and 31 have side surfaces that are continuous with the side surfaces of the second-layer metal wiring 29. Further, the other sides of the upper surface shape of the metal vias 30 and 31 are on the same line as the upper surface edge of the first layer metal wiring 17.

  In the semiconductor device of the present embodiment, the metal vias 30 and 31 have a square shape and a rectangular shape, respectively. However, the via shape is not limited to these, and various other via shapes, specifically, Can be any via shape having four or more sides. FIG. 10 is a plan view showing an example of such a via shape. As shown in FIG. 10, a via 81 having six sides is formed at the intersection of the first layer wiring 79 and the second layer wiring 80.

  In this embodiment, the roundness of the connecting portion (corner portion) of each side of the via upper surface shape is not particularly mentioned, but the effect of the above-described embodiment can be obtained regardless of the presence or absence of the rounding. Needless to say.

(Comparative example)
Hereinafter, a wiring forming method and a semiconductor device according to a comparative example will be described with reference to the drawings.

  FIGS. 5A and 5B are plan views of masks used in the wiring formation method of the comparative example, and FIG. 5C is a plan view of the semiconductor device of the comparative example, and FIGS. ) Are sectional views taken along lines yy ′ and xx ′ in FIG.

  In this comparative example, a multilayer wiring having a two-layer structure shown in FIGS. 5C to 5E is formed according to the same procedure as the wiring forming method according to the first embodiment described above. As shown in FIGS. 5C to 5E, in the semiconductor device of this comparative example, the first-layer wiring 42, the second-layer wiring 43, and the first-layer wirings 42 and 2 are included in the interlayer insulating film 40. A via 41 connecting the layer wiring 43 is formed. Here, in FIG. 5C, the second-layer wiring 43 is not shown in order to show the arrangement of the vias 41.

  A method for forming a multilayer wiring having a two-layer structure shown in FIGS. 5C to 5E is as follows. First, pattern exposure and development are performed on the resist using the first-layer wiring formation mask 36 having the first-layer wiring patterns 37A, 37B, and 37C shown in FIG. 5A, and the resist formed thereby. Using the pattern as a mask, the interlayer insulating film is etched to form a first layer wiring groove. Next, after the metal is buried in the first layer wiring groove, the metal protruding from the first layer wiring groove is removed by polishing to form the first layer wiring 42. Thereafter, after sequentially depositing an interlayer insulating film and a hard mask film on the first layer wiring 42, a resist is formed using a second layer wiring forming mask 38 having a second layer wiring pattern 39 shown in FIG. Pattern exposure and development are performed on Using the resist pattern thus formed as a mask, the hard mask film is etched to form a second-layer wiring groove pattern. Next, after applying a resist on the hard mask film including the second-layer wiring groove pattern, the resist is exposed to the resist using the first-layer wiring forming mask 36 shown in FIG. Development is performed, and the interlayer insulating film is etched using the resist pattern and hard mask film formed thereby as a mask to form a via hole. Here, the via hole is formed in a region where the opening of the resist pattern (first-layer wiring groove pattern) and the second-layer wiring groove pattern of the hard mask film overlap. Thereafter, after removing the resist pattern, the interlayer insulating film is etched using the hard mask film on which the second-layer wiring groove pattern is formed as a mask to form a second-layer wiring groove. Thereafter, the via hole and the second-layer wiring groove are filled with metal, and the metal protruding from the second-layer wiring groove is removed by polishing to form the via 41 and the second-layer wiring 43. As described above, the multilayer wiring having the two-layer structure shown in FIGS. 5C to 5E is formed.

  In this comparative example, a via 41 is always formed at the intersection of the first layer wiring 42 and the second layer wiring 43. Here, the first layer wirings 42 respectively corresponding to the first layer wiring patterns 37A and 37C of the first layer wiring forming mask 36 have the same electric potential, and the first layer wiring forming mask 36 is. Only the first layer wiring 42 corresponding to the first layer wiring pattern 37B has a potential different from that of the other first layer wirings 42. In this case, the first-layer wirings 42 respectively corresponding to the first-layer wiring patterns 37A and 37C are electrically connected to each other, while the first-layer wiring 42 corresponding to the first-layer wiring pattern 37B is the other first-layer wiring 42. It is necessary not to be electrically connected to the wiring 42. However, in the structure of the comparative example shown in FIGS. 5C to 5E, the first-layer wiring 42 corresponding to the first-layer wiring patterns 37A and 37C via the via 41 and the second-layer wiring 43, Since the first-layer wiring 42 corresponding to the first-layer wiring pattern 37B is electrically connected to each other, a desired circuit may not be formed.

(First modification of the first embodiment)
Hereinafter, a wiring forming method and a semiconductor device according to a first modification of the first embodiment of the present invention will be described with reference to the drawings. This modified example solves the problems of the comparative example described above. Specifically, in this modification, a short circuit between the first layer wirings is avoided by the third layer wiring connection.

  6A to 6C are plan views of a mask used in the wiring forming method of the present modification, and FIG. 6D is a plan view of the semiconductor device of the present modification, and FIG. (F) is sectional drawing of the yy 'line | wire and xx' line | wire of FIG.6 (d), respectively. In FIG. 6D, illustration of the second layer wiring, the third layer wiring, and the like is omitted to show the arrangement of the vias. 6E and 6F, a laminated structure of a plurality of interlayer insulating films is shown as an interlayer insulating film 49.

  In the wiring forming method of this modification, first, pattern exposure is performed on the resist using the first-layer wiring forming mask 44 having the first-layer wiring patterns 45A, 45B, and 45C shown in FIG. Development is performed, and the interlayer insulating film is etched using the formed resist pattern as a mask to form a first layer wiring groove. Next, after the metal is buried in the first layer wiring groove, the metal protruding from the first layer wiring groove is removed by polishing to form the first layer wiring 51. Thereafter, after sequentially depositing an interlayer insulating film and a hard mask film on the first layer wiring 51, a resist is formed using a second layer wiring forming mask 46 having a second layer wiring pattern 47 shown in FIG. Pattern exposure and development are performed on Using the resist pattern thus formed as a mask, the hard mask film is etched to form a second-layer wiring groove pattern. Next, after applying a resist on the hard mask film including the second-layer wiring groove pattern, the resist is patterned using the first-layer wiring forming mask 44 shown in FIG. Development is performed, and the interlayer insulating film is etched using the resist pattern and hard mask film formed thereby as a mask to form a via hole. Here, the via hole is formed in a region where the opening of the resist pattern (first-layer wiring groove pattern) and the second-layer wiring groove pattern of the hard mask film overlap. Thereafter, after removing the resist pattern, the interlayer insulating film is etched using the hard mask film on which the second-layer wiring groove pattern is formed as a mask to form a second-layer wiring groove. Thereafter, metal is buried in the via hole and the second-layer wiring groove, and then the metal protruding from the second-layer wiring groove is removed by polishing to form the via 50 and the second-layer wiring 52. Thereafter, using the third-layer wiring formation mask 48 having the third-layer wiring pattern 48a shown in FIG. 6C, the same procedure is repeated until the third-layer wiring is formed. Specifically, after forming a via 53 on the second layer wiring 52, a third layer wiring 54 electrically connected to the second layer wiring 52 through the via 53 is formed on the via 53. A multilayer wiring having a three-layer structure shown in FIGS. 6D to 6F is formed.

  In this modification, the first-layer wirings 51 corresponding to the first-layer wiring patterns 45A and 45C of the first-layer wiring forming mask 44 shown in FIG. 6A have the same electric potential. It is assumed that only the first layer wiring 51 corresponding to the first layer wiring pattern 45B of the first layer wiring forming mask 44 has a potential different from that of the other first layer wirings 51.

  On the other hand, in the present modification, the second-layer wiring 52 corresponding to the second-layer wiring pattern 47 of the second-layer wiring forming mask 46 shown in FIG. 6B is the 1st layer shown in FIG. It is designed not to overlap the first layer wiring 51 corresponding to the first layer wiring pattern 45B of the layer wiring forming mask 44. Further, the third-layer wiring 54 corresponding to the third-layer wiring pattern 48a of the third-layer wiring forming mask 48 shown in FIG. 6C is separated from the second-layer wiring 52 in the vertical direction of the drawing. It is designed to be electrically connected to each other through a via 53.

  Specifically, as shown in FIG. 6E, the first layer wiring 51 corresponding to the first layer wiring pattern 45A and the first layer wiring 51 corresponding to the first layer wiring pattern 45C are the third layer. The third-layer wiring 54 is provided so as to straddle the first-layer wiring 51 corresponding to the first-layer wiring pattern 45B, while being electrically connected via the wiring 54.

  Further, as shown in FIG. 6F, the second layer wiring 52 does not exist above the first layer wiring 51 corresponding to the first layer wiring pattern 45B, and only the third layer wiring 54 exists. To do. That is, the first layer wiring 51 corresponding to each of the first layer wiring patterns 45A and 45C and the first layer wiring 51 corresponding to the first layer wiring pattern 45B are electrically separated.

  As described above, in the present modification, when the first layer wiring 51 includes at least two types of wirings having different potentials, only the first layer wiring 51 having the same potential as the second layer wiring 52 is used. By providing the second-layer wiring 52, the above-mentioned problems of the comparative example are solved.

  In this modification, the first-layer wirings having the same potential are electrically connected to each other by the detour connection using the third-layer wiring. Instead, the detour using the upper-layer wiring of the fourth layer or higher is used instead. It goes without saying that the first-layer wirings having the same potential may be electrically connected by connection.

(Second modification of the first embodiment)
Hereinafter, a wiring formation method and a semiconductor device according to a second modification of the first embodiment of the present invention will be described with reference to the drawings. This modified example solves the problems of the comparative example described above. Specifically, in this modification, a short circuit between the second layer wirings is avoided by local wiring connection using a contact layer.

  FIGS. 7A to 7C are plan views of a mask used in the wiring forming method according to the present modification, and FIG. 7D is a plan view of the semiconductor device according to the present modification. (F) is sectional drawing of the yy 'line | wire and xx' line | wire of FIG.7 (d), respectively. In FIG. 7D, the second-layer wiring is not shown in order to show the arrangement of vias. 7E and 7F, a laminated structure of a plurality of interlayer insulating films is shown as an interlayer insulating film 60.

  In the wiring forming method of the present modification, first, after forming an interlayer insulating film on the substrate 65 on which an active region (source / drain region), a gate electrode and the like (not shown) are formed, as shown in FIG. Then, pattern exposure and development are performed on the resist using the contact layer forming mask 55 having the local wiring pattern 55a. Using the resist pattern thus formed as a mask, the interlayer insulating film is etched to form a local wiring groove reaching the substrate 65, and then metal is embedded in the local wiring groove and then protrudes from the local wiring groove. The local wiring 62 is formed by removing the metal by polishing. Thereafter, after depositing an interlayer insulating film on the local wiring 62, pattern exposure and development are performed on the resist using the first-layer wiring forming mask 56 having the first-layer wiring pattern 56a shown in FIG. 7B. Using the resist pattern thus formed as a mask, the interlayer insulating film is etched to form a first layer wiring groove. Next, after the metal is buried in the first layer wiring groove, the metal protruding from the first layer wiring groove is removed by polishing to form the first layer wiring 63. Thereafter, after sequentially depositing an interlayer insulating film and a hard mask film on the first layer wiring 63, a second layer wiring forming mask 57 having second layer wiring patterns 58A, 58B and 58C shown in FIG. The resist is subjected to pattern exposure and development using. Using the resist pattern thus formed as a mask, the hard mask film is etched to form a second-layer wiring groove pattern. Next, after applying a resist on the hard mask film including the second-layer wiring groove pattern, pattern exposure using the first-layer wiring forming mask 56 shown in FIG. Development is performed, and the interlayer insulating film is etched using the resist pattern and hard mask film formed thereby as a mask to form a via opening. Here, the via opening is formed in a region where the opening of the resist pattern (first-layer wiring groove pattern) and the second-layer wiring groove pattern of the hard mask film overlap. Thereafter, after removing the resist pattern, the interlayer insulating film is etched using the hard mask film on which the second-layer wiring groove pattern is formed as a mask to form a second-layer wiring groove. Thereafter, metal is buried in the second layer wiring groove and the via opening, and then the metal protruding from the second layer wiring groove is removed by polishing to remove the second layer wiring 64, the first layer wiring 63, and the second layer. A via 61 that connects the wiring 64 is formed. As a result, a multilayer wiring having a two-layer structure shown in FIGS. 7D to 7F is formed.

  In this modification, the second-layer wirings 64 respectively corresponding to the second-layer wiring patterns 58A and 58C of the second-layer wiring forming mask 57 shown in FIG. 7C have the same electric potential. Only the second-layer wiring 64 corresponding to the second-layer wiring pattern 58B of the second-layer wiring forming mask 77 has a potential different from that of the other second-layer wirings 64.

  On the other hand, in the present modification, the second layer wiring 64 is always formed on the first layer wiring 63. The plurality of local wirings 62 formed in the contact layer have a wiring pattern corresponding to the local wiring pattern 55a of the contact layer forming mask 55 (FIG. 7A). The local wiring 62 functions as a contact for electrically connecting each of the active region (source / drain region) and gate electrode formed on the substrate 65 and the first-layer wiring 63, as will be described later. Also functions as local wiring.

  Specifically, in the present modification, as shown in FIG. 7E, the second-layer wirings 64 corresponding to the second-layer wiring patterns 58A and 58C of the second-layer wiring forming mask 57 are The local wiring 62 is electrically connected through the via 61 and the first layer wiring 63. Further, as shown in FIGS. 7E and 7F, the first layer wiring 63 exists under the second layer wiring 64 corresponding to the second layer wiring pattern 58B of the second layer wiring forming mask 57. Accordingly, the second layer wiring 64 corresponding to the second layer wiring patterns 58A and 58C and the second layer wiring 64 corresponding to the second layer wiring pattern 58B are electrically separated.

  As described above, in the present modification, when the second layer wiring 64 includes at least two types of wirings having different potentials, only under the second layer wiring 64 having the same potential as the first layer wiring 63. In addition, the first-layer wiring 63 is provided, and the active region (source / drain region) on the substrate 65, the gate electrode, and the like are electrically connected to the first-layer wiring 63 with the second-layer wiring 64 having the same potential. The problem of the comparative example is solved by functioning as a local wiring for connecting the two.

(Third Modification of First Embodiment)
Hereinafter, a wiring forming method and a semiconductor device according to a third modification of the first embodiment of the present invention will be described with reference to the drawings. In this modification, the wiring forming method and the semiconductor device according to the first embodiment are applied to an SRAM (static random access memory) circuit.

  FIG. 8A is a cross-sectional view of the SRAM circuit according to this modification, in which the active region formed on the substrate is extracted from the second layer wiring, and FIG. 8B is the same as FIG. 8A. It is a corresponding top view. FIG. 8A is a cross-sectional view taken along the line b-b ′ of FIG. In FIG. 8B, the illustration of the interlayer insulating film is omitted for convenience of explanation.

  As shown in FIGS. 8A and 8B, an element isolation region 67 made of an oxide film or the like is disposed in order to electrically isolate the active region 66 in which the source region and the drain region of the transistor are formed. Yes. A gate electrode 68 is formed on the active region 66, and a contact (local wiring) 69 is formed so as to be connected to each of the active region 66 and the electrode 68. Further, a first layer wiring 70 connected to the contact (local wiring) 69, a via 71 connected to the first layer wiring 70, and a second layer wiring 72 connected to the first layer wiring 70 via the via 71 are sequentially provided. Is formed.

  In this modification, a via 71 is always formed at a portion where the first-layer wiring 70 and the second-layer wiring 72 intersect when viewed from the upper surface side. Further, as shown in FIG. 8B, instead of the first-layer wiring connecting the gate electrode 68 and the active region 66, a gate (contact wiring) 69 represented by a local wiring 74, for example, is used. The electrode 68 and the active region 66 are connected. As described above, the wiring forming method and the semiconductor device according to the first embodiment can be applied to a conventional SRAM circuit.

(Fourth modification of the first embodiment)
Hereinafter, a wiring formation method and a semiconductor device according to a fourth modification of the first embodiment of the present invention will be described with reference to the drawings.

  The feature of this modification is that a gap is provided in the interlayer insulating film between the first layer wirings, between the second layer wirings, and between the first layer wirings and the second layer wirings. That is, in this modification, a so-called air gap wiring process is applied to the wiring forming method and the semiconductor device according to the first embodiment.

  FIG. 9 is a cross-sectional view of the semiconductor device of the present modification. As shown in FIG. 9, a gap 73 is formed in the interlayer insulating film 78 existing between the first layer wiring 75 and the second layer wiring 76. Here, the gap 73 may be formed after the second-layer wiring 76 is formed in the interlayer insulating film 78. Similarly, a gap 73 may be formed between the second layer wiring 76 and the third layer wiring 77.

  In this modification, air may exist in the gap 73, or the gap 73 may be in a vacuum. The presence of such a gap 73 can reduce the dielectric constant between the wirings, thereby reducing the signal delay.

  By the way, in the conventional air gap wiring, since there is no interlayer insulating film, there is a problem that the wiring collapses due to the mechanical pressure generated in the process of polishing and removing excess metal when forming the upper wiring. In particular, in the prior art, all the vias (vias connecting the upper and lower wirings) are formed so as to have a uniform diameter substantially the same as the minimum wiring width, in other words, because the cross-sectional area of the vias is small, From the viewpoint of mechanical strength, it has been difficult to form a gap near the via.

  On the other hand, in this modification, the via shape is set by the intersection shape of the lower wiring groove pattern and the upper wiring groove pattern, so that the via shape is not only the conventional hole shape, but also the line shape or polygonal shape. Etc. can also be used, so that the cross-sectional area of the via becomes larger than the conventional one. For this reason, even when the air gap wiring structure is used, the mechanical strength of the multilayer wiring structure can be increased to improve the yield and reliability.

  The present invention relates to a wiring forming method and a semiconductor device, and particularly when applied to a dual damascene wiring forming method and a semiconductor device having a multilayer wiring structure, while reducing the number of pattern design steps, the number of masks used, and overlay deviation, A fine via pattern can be formed, which is useful.

DESCRIPTION OF SYMBOLS 1 Contact formation mask 2 Contact pattern 3 1st layer wiring formation mask 4 1st layer wiring pattern
5 Mask for forming second layer wiring 6 Second layer wiring pattern 7 Interlayer insulating film 8 Contact hole 9 Contact hole 10 Gate electrode 10a Insulating sidewall spacer 11 Substrate 11a Element isolation region 12 First resist pattern 13 Opening (groove) )
14 Interlayer insulating film 14a First layer wiring groove 15 Metal contact 16 Metal contact 17 First layer metal wiring 18 Hard mask film 19A, 19B Interlayer insulating film 20A, 20B Liner film 21 Opening (groove)
22 Third resist pattern 23 Opening (groove)
24 square opening 25 rectangular opening 26 square via hole 27 rectangular via opening 28 second layer wiring groove 29 second layer metal wiring 30 square metal via 31 rectangular metal via 32 third layer metal wiring 33 metal via 34 third layer wiring Formation mask 35 Third layer wiring pattern 36 First layer wiring formation mask 37A, 37B, 37C First layer wiring pattern 38 Second layer wiring formation mask 39 Second layer wiring pattern 40 Interlayer insulating film 41 Via 42 First layer First wiring 43 Second layer wiring 44 First layer wiring formation mask 45A, 45B, 45C First layer wiring pattern 46 Second layer wiring formation mask 47 Second layer wiring pattern 48 Third layer wiring formation mask 48a Three layers Eye wiring pattern 49 Interlayer insulating film 50 Via 51 First layer wiring 52 Second layer wiring 53 Via 54 Third layer wiring 55 Contact layer forming mask 55a Local wiring pattern 56 First layer wiring forming mask 56a First layer wiring pattern 57 Second layer wiring forming mask 58A, 58B, 58C Second layer wiring pattern 60 Interlayer insulating film 61 Via 62 Local wiring 63 First layer wiring 64 Second layer wiring 65 Substrate 66 Active region 67 Element isolation region 68 Gate electrode 69 Contact (local wiring)
70 First layer wiring 71 Via 72 Second layer wiring 73 Air gap 74 Local wiring 75 First layer wiring 76 Second layer wiring 77 Third layer wiring 78 Interlayer insulating film 79 First layer wiring 80 Second layer wiring 81 Via

Claims (14)

A first resist pattern is formed on the first interlayer insulating film using a first mask, and then a first wiring groove is formed in the first interlayer insulating film using the first resist pattern as an etching mask. Step (a) to perform,
(B) forming a first wiring by burying a conductive material in the first wiring groove after removing the first resist pattern;
A step (c) of sequentially forming a second interlayer insulating film and a hard mask film on the first interlayer insulating film and on the first wiring;
Forming a second resist pattern on the hard mask film using a second mask, and then patterning the hard mask film using the second resist pattern as an etching mask;
(E) forming a third resist pattern on the patterned hard mask film using the first mask after removing the second resist pattern;
A via opening is formed by etching the second interlayer insulating film at a portion exposed in a region where the opening of the patterned hard mask film and the opening of the third resist pattern overlap. Forming (f);
(G) forming a second wiring groove connected to the via opening in the second interlayer insulating film using the patterned hard mask film as an etching mask after removing the third resist pattern )When,
(H) forming a second wiring and a via connecting the first wiring and the second wiring by embedding a conductive material in the second wiring groove and the via opening; A method of forming a wiring, comprising: In the wiring formation method according to claim 1,
The wiring formation method, wherein the first resist pattern and the third resist pattern are formed using the same resist material. In the wiring formation method according to claim 1,
The wiring forming method, wherein the first resist pattern and the third resist pattern are formed using the same exposure illumination conditions. In the wiring formation method according to claim 3,
The wiring forming method according to claim 1, wherein the illumination stop under the same exposure illumination condition has a ring shape, a quadrupole shape or a dipole shape. In the wiring formation method according to claim 1,
In the step (e), the third resist pattern is formed in alignment with the first wiring. In the wiring formation method according to claim 1,
The wiring formation method, wherein the via opening is a via hole. In the wiring formation method according to claim 1,
In the step (h), the via is formed in all the portions of the second wiring that intersect the first wiring. In the wiring formation method according to claim 1,
The first wiring includes at least two kinds of wirings having different potentials from each other,
In the step (g), the second wiring trench is formed only on the wiring having the same potential as the second wiring in the first wiring. In the wiring formation method according to claim 1,
Before the step (a), a third interlayer insulating film serving as a base of the first interlayer insulating film is formed on the substrate on which the active region and the gate electrode are formed, and then the third interlayer insulating film is formed. Further comprising the step (i) of forming a plurality of contacts connected to each of the active region and the gate electrode in the film,
In the step (a), the first wiring groove is formed so as to reach the plurality of contacts. In the wiring formation method according to claim 1,
A wiring forming method, further comprising a step (j) of forming a gap in the second interlayer insulating film after the step (h). A first wiring;
A second wiring formed on the upper side of the first wiring,
A semiconductor device, wherein a via for connecting the first wiring and the second wiring is formed in all portions of the second wiring intersecting with the first wiring. The semiconductor device according to claim 11,
The semiconductor device according to claim 1, wherein the via has an upper surface shape having four or more sides. The semiconductor device according to claim 11,
At least one side of the upper surface shape of the via exists on the same line as the lower surface edge of the second wiring. The semiconductor device according to claim 11,
The via has a side surface continuous with a side surface of the second wiring.

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