JP2010283011A - Thin film transistor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress an increase in off current of a TFT with light. <P>SOLUTION: A thin film transistor substrate 20 is provided for each pixel G with a thin film transistor 5a including a gate electrode 11aa provided on a substrate 10a, a gate insulating film 12 provided covering the gate electrode 11aa, a semiconductor layer 13a provided in an island shape on the gate insulating film 12 to overlap the gate electrode 11aa, and a source electrode 14aa and a drain electrode 14ba provided on the semiconductor layer 13a to overlap the gate electrode 11aa, respectively, a peripheral end of the semiconductor layer 13a being positioned inside a peripheral end of the gate electrode 11aa in plane view. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a thin film transistor substrate, and more particularly to a thin film transistor substrate constituting a liquid crystal display panel.

  The liquid crystal display panel is, for example, a TFT substrate provided with a thin film transistor (hereinafter referred to as “TFT”) or the like as a switching element, and a color filter (hereinafter referred to as “CF”) disposed opposite the TFT substrate. Etc., and a liquid crystal layer provided between the TFT substrate and the CF substrate, and by changing the alignment state of the liquid crystal layer according to the applied voltage, from an externally provided backlight An image is displayed by adjusting the transmittance of incident light.

  In the semiconductor layer constituting the TFT, for example, when light from a backlight is incident, a leak current is generated in an off state due to photoexcitation, so that the off-current of the TFT increases. In this case, the display quality of the liquid crystal display panel is deteriorated. Therefore, in the TFT substrate, it is necessary to sufficiently shield the TFT semiconductor layer.

  For example, Patent Document 1 discloses an active matrix substrate in which a light shielding metal layer is provided on an upper layer of a TFT channel layer via an interlayer insulating film.

JP-A-10-186402

  FIG. 10 is a plan view of a conventional TFT 105, and FIG. 11 is a cross-sectional view of the TFT 105 along the line XI-XI in FIG.

  As shown in FIGS. 10 and 11, the TFT 105 includes a gate electrode 111 which is a part of a gate line provided on the glass substrate 110, a gate insulating film 112 provided so as to cover the gate electrode 111, a gate, The semiconductor layer 113 provided in an island shape so as to cover the gate electrode 111 with the insulating film 112 interposed therebetween, and the source electrode 114a and the drain provided on the semiconductor layer 113 so as to overlap the gate electrode and to face each other And an electrode 114b.

  In the TFT 105, as shown in FIG. 11, for example, as in the active matrix substrate disclosed in Patent Document 1, the end of the semiconductor layer 113 is exposed from the gate electrode 111. Is incident on the semiconductor layer 113 from the periphery of the gate electrode 111, a photocurrent is generated in the semiconductor layer 113, and the off-current of the TFT 105 may increase.

  The present invention has been made in view of such a point, and an object of the present invention is to suppress an increase in the off-current of the TFT due to light.

  In order to achieve the above object, according to the present invention, the peripheral edge of the semiconductor layer is positioned more inside than the peripheral edge of the gate electrode in plan view.

  Specifically, the thin film transistor substrate according to the present invention includes a gate electrode provided on the substrate, a gate insulating film provided so as to cover the gate electrode, and an island shape on the gate insulating film so as to overlap the gate electrode. A thin film transistor substrate provided for each pixel, wherein the thin film transistor includes a semiconductor layer provided on the semiconductor layer and a source electrode and a drain electrode provided on the semiconductor layer so as to overlap the gate electrode, The peripheral edge is located inside the peripheral edge of the gate electrode in plan view.

  According to the above configuration, the semiconductor layer is not exposed from the gate electrode because the peripheral end of the semiconductor layer is located inside the peripheral end of the gate electrode in plan view. As a result, for example, light from a backlight provided under the substrate is suppressed from entering the semiconductor layer, and generation of photocurrent in the semiconductor layer is suppressed. It is suppressed.

  A plurality of gate lines provided so as to extend in parallel with each other; each of the gate lines has a narrow portion and a wide portion having different line widths for each of the pixels; and the gate electrode has the wide width Part.

  According to the above configuration, since the gate electrode is the wide part of the gate line, the thin film transistor is formed inside the wide part of the gate line in plan view. Since the portion other than the portion constituting the thin film transistor of the gate line becomes a narrow portion, the aperture ratio of the pixel can be improved as compared with the case where the gate line is formed wide as a whole.

  The drain electrode may be provided in the center of the semiconductor layer in plan view, and the source electrode may be provided around the drain electrode.

  According to the above configuration, since the drain electrode is provided in the center of the semiconductor layer and the source electrode is provided around the drain electrode, the thin film transistor in which the source electrode is arranged around the drain electrode is specifically described. Constructed.

  A plurality of source lines provided so as to extend in parallel to each other in a direction intersecting with each of the gate lines, and each of the source lines has a protruding portion protruding laterally for each of the pixels; The electrode may include the protruding portion.

  According to the above configuration, since the source electrode includes the protruding portion of the source line, the portion functioning as the source electrode is increased, and the channel width of the semiconductor layer is designed to be large.

  The source electrode may be provided in a ring shape so as to surround the drain electrode.

  According to the above configuration, the drain electrode is provided in the center of the semiconductor layer in plan view, and the source electrode is provided in a ring shape so as to surround the drain electrode. It is defined in a frame shape along an intermediate position between the source electrode and the drain electrode in the layer. Accordingly, the channel width of the semiconductor layer is designed to be large, so that a thin film transistor having a large drain current is specifically configured.

  According to the present invention, since the peripheral edge of the semiconductor layer is located on the inner side in a plan view than the peripheral edge of the gate electrode, an increase in the off current of the TFT due to light can be suppressed.

1 is a plan view of a TFT substrate 20 according to Embodiment 1. FIG. It is sectional drawing of the TFT substrate 20 and the liquid crystal display panel 50 provided with it along the II-II line | wire in FIG. 3 is a cross-sectional view schematically showing the incidence of light on a TFT 5a constituting a TFT substrate 20. FIG. It is a top view of TFT5b which is a modification of TFT5a. It is a top view of TFT5c which is a modification of TFT5a. 6 is a plan view of a TFT 5d that constitutes a TFT substrate according to Embodiment 2. FIG. It is a top view of TFT5e which is a modification of TFT5d. It is a top view of TFT5f which is a modification of TFT5d. 6 is a plan view of a TFT 5g that constitutes a TFT substrate according to Embodiment 3. FIG. It is a top view of the conventional TFT105. It is sectional drawing of TFT105 along the XI-XI line in FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments.

Embodiment 1 of the Invention
1 to 5 show Embodiment 1 of a thin film transistor substrate according to the present invention.

  Specifically, FIG. 1 is a plan view of the TFT substrate 20 of the present embodiment, and FIG. 2 is a cross-sectional view of the TFT substrate 20 and a liquid crystal display panel 50 including the same along the line II-II in FIG. FIG.

  As shown in FIG. 2, the liquid crystal display panel 50 includes a TFT substrate 20 and a CF substrate 30 that are arranged to face each other, a liquid crystal layer 40 provided between the TFT substrate 20 and the CF substrate 30, and the TFT substrate 20. And a sealing material (not shown) for adhering the liquid crystal layer 40 between the TFT substrate 20 and the CF substrate 30.

  1 and 2, the TFT substrate 20 includes an insulating substrate 10a such as a glass substrate, a plurality of gate lines 11aa provided on the insulating substrate 10a so as to extend in parallel to each other, and the gate lines 11aa. A plurality of capacitor lines 11b provided so as to extend in parallel with each other, a plurality of source lines 14aa provided so as to extend in parallel with each other in the direction orthogonal to each gate line 11aa and each capacitor line 11b, and each gate A plurality of TFTs 5a provided for each intersection of the line 11aa and each source line 14aa, that is, for each pixel G, an interlayer insulating film 15 provided so as to cover each TFT 5a, and a matrix on the interlayer insulating film 15 A plurality of pixel electrodes 16 provided in a shape and an alignment film (not shown) provided so as to cover each pixel electrode 16 are provided.

  The gate line 11aa has a narrow portion Ba (for example, a width of 16 μm) and a wide portion Bb (for example, a width of 21 μm) having different line widths for each pixel G. Note that the size of each pixel G is, for example, 450 μm long × 150 μm wide.

As shown in FIGS. 1 and 2, the TFT 5a includes a gate electrode Bb that is a wide portion (Bb) of each gate line 11aa, a gate insulating film 12 provided so as to cover the gate electrode Bb, and a gate insulating film 12 The semiconductor layer 13a is provided in an island shape so as to overlap the gate electrode Bb, and the source electrode (14aa) and the drain electrode 14ba are provided on the semiconductor layer 13a so as to overlap the gate electrode Bb. . Here, the semiconductor layer 13a includes a lower intrinsic amorphous silicon layer (not shown) whose channel region (not shown) is defined on the upper surface, and an n ⁺ amorphous silicon layer (not shown) provided on the upper layer. As shown in FIG. 1, the peripheral end thereof is located inside the peripheral end of the gate electrode Bb in plan view. Thereby, since the semiconductor layer 13a is not exposed from the gate electrode Bb, the light P from the backlight provided below the substrate can be prevented from entering the semiconductor layer 13a as shown in FIG. The generation of photocurrent in the semiconductor layer 13a can be suppressed. FIG. 3 is a cross-sectional view schematically showing the incidence of light on the TFT 5a. As shown in FIGS. 1 and 2, the drain electrode 14ba is provided in a square shape at the center of the semiconductor layer 13a in plan view, and is connected via a contact hole (not shown) formed in the interlayer insulating film 15. It is connected to the pixel electrode 16. Further, as shown in FIGS. 1 and 2, the source electrode (14aa) is constituted by a part of each source line 14aa and a protruding portion J protruding laterally for each pixel G of each source line 14aa. The ring electrode 14ba is provided in a ring shape so as to surround the drain electrode 14ba. In the TFT 5a, as shown in FIG. 1, the channel width W is defined in a frame shape along the intermediate position between the source electrode (14aa) and the drain electrode 14ba in the semiconductor layer 13a, and the channel length L is the source in the semiconductor layer 13a. It is defined by the distance between the electrode (14aa) and the drain electrode 14ba.

  As shown in FIG. 2, the CF substrate 30 includes an insulating substrate 10b such as a glass substrate, a black matrix 21a provided in a frame shape on the insulating substrate 10b and in a lattice shape in the frame, and a black matrix 21a. A color filter layer 21b composed of a red layer, a green layer, a blue layer, and the like provided between the lattices, a common electrode 22 provided to cover the black matrix 21a and the color filter layer 21b, and a common electrode 22 And an alignment film (not shown).

  The liquid crystal layer 40 is made of a nematic liquid crystal material having electro-optical characteristics.

  The liquid crystal display panel 50 configured as described above applies a predetermined voltage for each pixel G to the liquid crystal layer 40 disposed between each pixel electrode 16 on the TFT substrate 20 and the common electrode 22 on the counter substrate 30. By changing the alignment state of the liquid crystal layer 40, the transmittance of light transmitted through the panel is adjusted for each pixel G, and an image is displayed.

  Next, a method for manufacturing the liquid crystal display panel 50 of the present embodiment will be described. Here, the manufacturing method of this embodiment includes a TFT substrate manufacturing process, a CF substrate manufacturing process, and a liquid crystal injection process.

<TFT substrate manufacturing process>
First, for example, a titanium film (thickness of about 350 mm), an aluminum film (thickness of about 3600 mm), a titanium film (thickness of about 1000 mm), and the like are sequentially formed on the entire substrate of the insulating substrate 10a such as a glass substrate by a sputtering method. Then, patterning is performed using photolithography to form the gate line 11aa having the gate electrode Bb and the capacitor line 11b.

  Subsequently, for example, a silicon nitride film (thickness of about 4100 mm) is formed on the entire substrate on which the gate line 11aa and the capacitor line 11b are formed by a plasma CVD (Chemical Vapor Deposition) method, and the gate insulating film 12 is then formed. Form.

Further, for example, an intrinsic amorphous silicon film (thickness of about 2050 mm) and phosphorus-doped n ⁺ amorphous silicon film (thickness of about 550 mm) are formed on the entire substrate on which the gate insulating film 12 is formed by plasma CVD. Films are continuously formed, and then patterned into island shapes on the gate electrode Bb using photolithography to form the semiconductor layer 13a.

  Then, for example, a titanium film (thickness of about 350 mm), an aluminum film (thickness of about 3600 mm), and the like are sequentially formed on the entire substrate on which the semiconductor layer 13a is formed by sputtering, and then photolithography is used. Patterning is performed to form a source line 14aa having a source electrode and a drain electrode 14ba.

Subsequently, the n ⁺ amorphous silicon layer of the semiconductor layer 13a is etched using the source electrode (14aa) and the drain electrode 14ba as a mask to pattern the channel portion, thereby forming the TFT 5a.

  Further, after an inorganic insulating film (thickness of about 2650 mm) such as a silicon nitride film is formed on the entire substrate on which the TFT 5a is formed by a plasma CVD method, for example, an acrylic photosensitive material is formed by a spin coating method. A resin or the like is applied to a thickness of about 3.6 μm. Thereafter, the applied photosensitive resin is exposed and developed through a photomask to form an organic insulating film having a contact hole on the drain electrode 14ba, and then the inorganic insulating film exposed from the organic insulating film is etched. Then, an interlayer insulating film 15 is formed by forming a contact hole.

  Then, an ITO (Indium Tin Oxide) film (thickness of about 1300 mm) is formed on the entire substrate on the interlayer insulating film 15 by sputtering, and then patterned using photolithography to form the pixel electrode 16. To do.

  Finally, a polyimide resin is applied to the entire substrate on which the pixel electrodes 16 are formed by a printing method, and then a rubbing process is performed to form an alignment film with a thickness of about 1000 mm.

  The TFT substrate 20 can be manufactured as described above.

<CF substrate manufacturing process>
First, an acrylic photosensitive resin in which fine particles such as carbon are dispersed is applied to the whole substrate of the insulating substrate 10b such as a glass substrate by a spin coating method, and the applied photosensitive resin is applied to a photomask. Then, the black matrix 21a is formed to a thickness of about 2.0 μm by developing after exposure.

  Subsequently, for example, an acrylic photosensitive resin colored in red, green, or blue is applied onto the substrate on which the black matrix 21a is formed, and the applied photosensitive resin is exposed through a photomask. Later, patterning is performed by developing to form a colored layer (for example, a red layer) of a selected color with a thickness of about 2.0 μm. Further, the same process is repeated for the other two colors to form other two colored layers (for example, a green layer and a blue layer) with a thickness of about 2.0 μm, thereby forming the color filter layer 21b. .

  Further, the common electrode 22 is formed by forming, for example, an ITO film (thickness of about 1000 mm) on the substrate on which the color filter layer 21b is formed by a sputtering method.

  Thereafter, a polyimide resin is applied to the entire substrate on which the common electrode 22 is formed by a printing method, and then a rubbing process is performed to form an alignment film with a thickness of about 1000 mm.

  The CF substrate 30 can be manufactured as described above.

<Liquid crystal injection process>
First, for example, a sealing material made of a thermosetting resin is formed on the CF substrate 30 manufactured in the CF substrate manufacturing process in a frame-like pattern having a liquid crystal injection port by a screen printing method, and in the TFT substrate manufacturing process. A spherical spacer made of resin is dispersed on the manufactured TFT substrate 20.

  Subsequently, after the TFT substrate 20 and the counter substrate 30 are bonded together, an empty cell is formed by curing the sealing material between the substrates.

  Further, a liquid crystal material is injected between the TFT cell 20 and the counter substrate 30 of the empty cell by a dipping method to form the liquid crystal layer 40, and then the liquid crystal injection port is sealed.

  As described above, the liquid crystal display panel 50 of the present embodiment can be manufactured.

  As described above, according to the TFT substrate 20 of the present embodiment, the peripheral end of the semiconductor layer 13a is located on the inner side in plan view with respect to the peripheral end of the gate electrode Bb. Not exposed from. Thereby, the light P from the backlight provided below the TFT substrate 20 can be prevented from entering the semiconductor layer 13a, and the generation of photocurrent in the semiconductor layer 13a can be suppressed. The increase in the off-current of the TFT due to can be suppressed.

  Further, according to the TFT substrate 20 of the present embodiment, since the gate electrode Bb is the wide portion of the gate line 14aa, the TFT 5a is formed inside the wide portion of the gate line 14aa in plan view. Since the portion other than the portion constituting the TFT 5a of the gate line 14aa becomes the narrow portion Ba, the aperture ratio of the pixel G can be improved as compared with the case where the gate line 11ac is formed wide as a whole (see FIG. 5). . Here, FIG. 5 is a plan view of a TFT 5 c which is a modification of the TFT 5 a constituting the TFT substrate 20. The TFT 5c can be formed by changing the pattern shape when forming the gate line 11aa and the like in the TFT substrate manufacturing process.

  Further, according to the TFT substrate 20 of the present embodiment, the source electrode (14aa) includes the protruding portion J of the source line 14aa and is provided in a ring shape so as to surround the drain electrode 14ba, and thus functions as the source electrode. Thus, the channel width W of the semiconductor layer 13a can be designed to be large, and the drain current of the TFT 5a can be increased.

  Further, in the present embodiment, the configuration in which the wide portion (Bb) is formed by projecting the gate line 14aa to one side is illustrated. However, as shown in FIG. The wide part (Bb) may be formed by projecting to the side. Here, FIG. 4 is a plan view of a TFT 5b which is a modification of the TFT 5a constituting the TFT substrate 20. FIG. The TFT 5b can be formed by changing the pattern shape when forming the gate lines 11aa and the like in the TFT substrate manufacturing process.

<< Embodiment 2 of the Invention >>
6 to 8 show Embodiment 2 of the thin film transistor substrate according to the present invention. Specifically, FIG. 6 is a plan view of a TFT 5d constituting the TFT substrate of this embodiment, FIG. 7 is a plan view of a TFT 5e that is a modification of the TFT 5d, and FIG. 8 is a modification of the TFT 5d. It is a top view of TFT5f. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same part as FIGS. 1-5, and the detailed description is abbreviate | omitted.

  In the first embodiment, the source line 14aa has the U-shaped (U-shaped) protruding portion J. However, in the present embodiment, the source lines 14ab to ad have protruding portions of other shapes. Yes.

  In the TFT 5d, as shown in FIG. 6, the source line 14ab has a pair of L-shaped protrusions J for each pixel.

  In the TFT 5e, as shown in FIG. 7, the source line 14ac has a pair of linear protrusions J for each pixel.

  In the TFT 5f, as shown in FIG. 8, the source line 14ad has one L-shaped protrusion J for each pixel.

  Here, the TFTs 5d to 5f change the pattern shape when forming the gate line 11aa and the like and change the pattern shape when forming the source line 14aa and the like in the TFT substrate manufacturing process of the first embodiment. Etc. can be formed.

  According to the TFT substrate of the present embodiment, the peripheral end of the semiconductor layer 13a is located on the inner side in a plan view than the peripheral end of the gate electrode Bb, as in the first embodiment. Can be suppressed.

<< Embodiment 3 of the Invention >>
FIG. 9 is a plan view of a TFT 5g constituting the TFT substrate of this embodiment.

  In the first and second embodiments, the TFTs 5a to 5f are formed in the wide portion of the gate lines 14aa to 14af. In the present embodiment, the TFT 5g is formed on the narrow gate line 11ad.

  In the TFT 5g, as shown in FIG. 9, the gate electrode is a part of a narrow gate line 11ad (for example, 16 μm wide), the semiconductor layer 13b is provided in a vertically long rectangular shape, and the source electrode is the source electrode. A part of the line 14ae and the L-shaped protrusion J are formed, and the drain electrode 14bb is provided in a vertically long rectangular shape. The TFT 5g is obtained by changing the pattern shape when forming the gate line 11aa and the like and changing the pattern shape when forming the source line 14aa and the like in the TFT substrate manufacturing process of the first embodiment. Can be formed.

  According to the TFT substrate of this embodiment, the peripheral end of the semiconductor layer 13b is located on the inner side in a plan view than the peripheral end of the gate electrode, as in the first embodiment. Increase can be suppressed.

  In each of the above embodiments, the configuration in which the source electrode is arranged around the drain electrode has been exemplified, but the present invention can also be applied to the configuration in which the drain electrode is arranged around the source electrode.

  As described above, the present invention can suppress an increase in off-current of a TFT due to light, and thus is useful for a TFT substrate constituting a liquid crystal display panel.

Ba Narrow part Bb Wide part, gate electrode G Pixel J Protrusion part 5a-5g TFT
10a glass substrate 11aa to 11ad gate line 12 gate insulating films 13a and 13b semiconductor layers 14aa to 14ae source electrode, source lines 14ba and 14bb drain electrode 20 TFT substrate

Claims (5)

A gate electrode provided on the substrate;
A gate insulating film provided to cover the gate electrode;
A semiconductor layer provided in an island shape on the gate insulating film so as to overlap the gate electrode;
A thin film transistor substrate provided with a source electrode and a drain electrode provided on the semiconductor layer so as to overlap with the gate electrode, for each pixel,
A thin film transistor substrate, wherein a peripheral edge of the semiconductor layer is located on an inner side in a plan view than a peripheral edge of the gate electrode. The thin film transistor substrate according to claim 1,
A plurality of gate lines provided so as to extend in parallel to each other;
Each of the gate lines has a narrow part and a wide part with different line widths for each pixel,
The thin film transistor substrate, wherein the gate electrode is the wide portion. In the thin film transistor substrate according to claim 1 or 2,
The drain electrode is provided in the center of the semiconductor layer in plan view,
The thin film transistor substrate, wherein the source electrode is provided around the drain electrode. The thin film transistor substrate according to any one of claims 1 to 3,
A plurality of source lines provided to extend in parallel to each other in a direction intersecting with each of the gate lines;
Each of the source lines has a protruding portion protruding laterally for each of the pixels,
The thin film transistor substrate, wherein the source electrode includes the protruding portion. In the thin film transistor substrate according to claim 3,
The thin film transistor substrate, wherein the source electrode is provided in a ring shape so as to surround the drain electrode.

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