JP2010272711A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to provide a highly reliable semiconductor device in which connection resistance associated with connection between an electrode such as an emitter electrode and a lead frame is reduced, and a manufacturing method thereof.
An electrode formed on a surface of a semiconductor layer, an additional electrode formed on the electrode and solderable to a lead frame, the electrode and the additional electrode are covered with the electrode, and the semiconductor layer is covered And a passivation film formed by providing an opening on the surface of the additional electrode.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device having an electrode formed on its surface and a method for manufacturing the same.

  An emitter electrode and a control electrode are formed on the surface of the power device, and a collector electrode is formed on the back surface. The emitter electrode is mechanically and electrically connected to the lead frame by a lead wire such as Au or Al. This connection is often made by a well-known wire bonding method. The same applies to the control electrode. Then, the lead frame connected to the emitter electrode via the lead wire extends to the outside of the package formed of a resin casing or the like, and connects the emitter electrode and the outside.

  Here, the connection using the lead wire will be briefly described with reference to FIG. As shown in FIG. 12, lead frames 102 and 104 are arranged on the base plate 100. A semiconductor device 106 is mounted on the lead frame 102. The semiconductor device 106 includes emitter electrodes 108 and 110 and a control electrode 112 on the surface. The emitter electrodes 108 and 110 are connected to the lead frame 104 by lead wires 114 and 116, respectively.

  From the viewpoint of reliability, it is preferable that the connection resistance of the connection between the emitter electrode and the lead frame (referred to as the electrical resistance generated by the connection, hereinafter the same) is sufficiently low and heat generation is suppressed. Patent Documents 1-6 disclose an electrode structure of a semiconductor device manufactured in consideration of connection resistance and the like.

Japanese Utility Model Publication No. 62-134237 Japanese Patent Laid-Open No. 04-218919 Japanese Patent Laid-Open No. 06-021058 JP 2000-058820 A JP 2007-142138 A JP 60-119777 A

  Semiconductor devices including power devices are fields in which the area reduction and the increase in current are remarkable. Accordingly, the resistance of the semiconductor device itself has been reduced. However, when the connection between the electrode of the semiconductor device and the lead frame is made with the lead wire, the connection resistance is not sufficiently reduced and the heat generation is large, and the reliability against the deterioration of the semiconductor device, the breakage of the lead wire, and the peel strength of the connection portion. There has been a problem of deterioration of the properties.

  The present invention has been made to solve the above-described problems, and reduces the connection resistance between the electrode of the semiconductor device and the lead frame, reduces the heat generated by the connection, and improves the reliability. It aims at providing the manufacturing method.

  A semiconductor device according to the invention of the present application includes an electrode formed on a surface of a semiconductor layer, an additional electrode formed on the electrode and solderable to a lead frame, and the additional electrode together with the electrode, And a passivation film formed by providing an opening on the surface of the additional electrode so as to cover the semiconductor layer.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming an electrode that is an Al, AlSi, or AlCu film on a semiconductor layer by a sputtering method, and the electrode is formed at 400 to 470 ° C. in a hydrogen or nitrogen atmosphere. A step of heating, a step of forming a passivation film made of silicon nitride by a plasma CVD method, a step of forming an opening of the passivation film on the electrode, and an integral on the opening and the passivation film. Forming an additional electrode. The additional electrode includes a barrier layer made of a Ti layer or a Mo layer, a conductor layer made of a Ni layer on the barrier layer, and an antioxidant layer made of an Au layer or an Ag layer on the conductor layer. It is characterized by that.

  According to the present invention, the connection resistance between the electrode and the lead frame can be reduced.

It is a top view of the semiconductor device of an embodiment. It is XX sectional drawing of FIG. It is a figure explaining the semiconductor device to which the lead frame was soldered. It is a flowchart explaining the manufacturing method of a semiconductor device. It is a figure explaining the process of forming an electrode. It is a figure explaining the process of forming a passivation film. It is a figure explaining the process of forming the opening of a passivation film. It is a figure explaining the process of forming the opening of a passivation film. It is a figure explaining the process of patterning a photoresist. It is a figure explaining the process of forming an additional electrode. It is a figure explaining lift-off. It is a figure explaining background art.

Embodiment The embodiment will be described with reference to FIGS. In some cases, the same material or the same and corresponding components are denoted by the same reference numerals, and description thereof is omitted a plurality of times.

  FIG. 1 is a plan view of the semiconductor device 10. First, the semiconductor device 10 according to the present embodiment is roughly divided into a region covered with the passivation film 24 and a region not covered with the passivation film 24. In FIG. 1, the passivation film 24 is indicated by oblique lines, and the other portions are indicated by no pattern. In the present embodiment, the passivation film 24 is silicon nitride formed by a plasma CVD method.

  In portions not covered with the passivation film 24, the antioxidant layers 28 and 30, the first control electrode 16, the second control electrode 18, the third control electrode 20, and the fourth control electrode 22 appear. Here, a part of the first control electrode 16 appears on the surface of the semiconductor device 10 through the first control opening 32 which is an opening of the passivation film 24. The same applies to the other control electrodes.

  Antioxidation layers 28 and 30 connect the first emitter electrode 12 and the second emitter electrode 14 to the outside. Reference is made to FIG. 2 to describe the lower layers of the antioxidant layers 28 and 30 and the periphery thereof. 2 is a cross-sectional view taken along line XX in FIG. As can be seen from FIG. 2, the semiconductor device 10 of the present embodiment includes the first emitter electrode 12 on the front surface side of the semiconductor layer 50 and the collector electrode 52 on the back surface. The first emitter electrode 12 is Al, AlSi, or AlCu formed by sputtering and heated at 400 to 470 ° C. in a hydrogen or nitrogen atmosphere.

  A barrier layer 54 is provided on the first emitter electrode 12. The barrier layer 54 is made of a Ti layer or a Mo layer. A conductor layer 56 made of a Ni layer is provided on the barrier layer 54. On the conductor layer 56, an antioxidant layer 28 made of an Au layer or an Ag layer is provided. The barrier layer 54, the conductor layer 56, and the antioxidant layer 28 are collectively referred to as an additional electrode 58. The additional electrode 58 is directly soldered to the lead frame as will be described later. The additional electrode 58 is formed so as to cover the first emitter electrode 12 together with the passivation film 24. Therefore, the first emitter electrode 12 is not directly exposed to the outside.

  As described above, the additional electrode 58 is disposed so as to be in contact with the first emitter electrode 12 at the opening of the passivation film 24 (shown by a broken line in FIGS. 1 and 2), and a part of the additional electrode 58 rests on the passivation film 24. Are integrally formed. For this reason, the area of the additional electrode 58 is larger than the area of the opening of the passivation film 24. The same applies to the second emitter electrode 14.

  FIG. 3 is a mounting example of the semiconductor device 10 having the above-described configuration. The collector electrode 52 of the semiconductor device 10 is connected to the lead frame 72. The antioxidant layers 28 and 30 are directly connected to the lead frame 74 by solder 76. The structure configured as described above is mounted on the base plate 70.

  Next, a method for manufacturing a semiconductor device of this embodiment will be described with reference to FIGS. The description will proceed with reference to FIG. 4 which is a flowchart for explaining the manufacturing method. 4 to 11 explain a place corresponding to the YY cross section in FIG.

  In step 80 in FIG. 4, an electrode is formed on the semiconductor layer 50. The electrodes are the first emitter electrode 12, the second emitter electrode 14, the first control electrode 16, the second control electrode 18, the third control electrode 20, and the fourth control electrode 22. These electrodes are Al, AlSi, or AlCu films formed by sputtering. In addition, after the electrode is formed, heat treatment is performed to heat the electrode at 400 to 470 ° C. in a hydrogen or nitrogen atmosphere. This heat treatment increases the crystal size and improves flatness. Therefore, the coverage of the additional electrode 58 described later can be improved.

  When step 80 is completed, the process proceeds to step 81. Step 81 will be described with reference to FIG. As can be seen from FIG. 6, the passivation film 24 is formed in step 81. The passivation film 24 is made of a silicon nitride layer formed by plasma CVD.

  When step 81 is completed, the process proceeds to step 82. Step 82 will be described with reference to FIGS. First, a photoresist 92 is formed, and the photoresist 92 is patterned so as to have openings on the electrodes as shown in FIG. Next, the passivation film 24 not covered with the photoresist 92 is etched by dry etching to form openings 94 and 96. After dry etching, the photoresist 92 is ashed by oxygen plasma.

  When step 82 is completed, the process proceeds to step 83. Step 83 will be described with reference to FIG. In step 83, a photoresist 98 is formed. The photoresist 98 is patterned to expose the opening 94.

  When step 83 is completed, the process proceeds to step 84. In step 84, the additional electrode 58 is integrally formed on the opening 94, that is, on the first emitter electrode 12 and on the passivation film 24. The additional electrode 58 includes a barrier layer 54 made of a Ti layer or a Mo layer, a conductor layer 56 made of a Ni layer on the barrier layer 54, and an antioxidant layer 28 made of an Au layer or an Ag layer on the conductor layer 56. . These are formed by sputtering or vapor deposition.

  When step 84 is completed, the process proceeds to step 85. In step 85, the photoresist 98 and the additional electrode 58 thereon are removed by a lift-off process. An example of the lift-off process is the following process. First, the photoresist 98 is dissolved using thinner as an organic solvent. Next, thinner or pure water is applied to the wafer at a high pressure to physically remove the photoresist 98 and the additional electrode 58 formed thereon. The method for manufacturing a semiconductor device of this embodiment includes the above-described steps.

  According to the configuration of the semiconductor device of this embodiment, the additional electrode 58 and the lead frame (lead frame 74) are directly connected by solder. Therefore, compared with the case where the emitter electrode and the lead frame are connected with a lead wire or the like, the connection area between the two can be increased, and thus the connection resistance can be reduced.

  Further, since the area of the additional electrode 58 is larger than the area of the opening of the passivation film 24, the additional electrode 58 and the lead frame 74 can be connected in a large area without being limited by the area of the opening 27. With such a feature, the degree of freedom of the connection area between the additional electrode 58 and the lead frame 74 can be increased, and a desired connection resistance can be obtained.

  Further, the first emitter electrode 12 and the second emitter electrode 14 of this embodiment are covered with the additional electrode 58 and the passivation film 24 and are not exposed to the outside. The outermost surface of the additional electrode 58 is the antioxidant film 28. Therefore, characteristic deterioration due to oxidation of the first emitter electrode 12 and the second emitter electrode 14 can be avoided.

  The passivation film 24 is silicon nitride formed by plasma CVD, and is formed so as to surround the first emitter electrode 12 and the second emitter electrode 14. For this reason, it is difficult for Al, Ni oxides and hydroxides to penetrate into the antioxidant layer 28 (Au layer), and contamination due to the penetration can be avoided.

  Further, since the additional electrode 58 protrudes from the passivation film 24, the ease of soldering with the lead frame is increased and the workability is improved. Accordingly, the passivation layer 24 can easily solder the additional electrode and the lead frame while protecting the semiconductor layer 50 and the electrode.

  Moreover, according to the manufacturing method of the semiconductor device of this embodiment, the lead wire and the wire bonding process are not required, which contributes to reducing the environmental load of the production process. Further, since the connection resistance can be reduced, the product yield can also be improved.

  The semiconductor layer 50 of this embodiment may constitute a power MOSFET, or may constitute another device such as a rectifier diode. In either case, the effect of the present invention can be obtained if the surface has an electrode to be connected to the lead frame. In the case of a MOSFET, the electrode is an emitter electrode, and in the case of a rectifier diode, the electrode is an anode electrode. Accordingly, although the electrode is an emitter electrode throughout the present embodiment, the present invention is not particularly limited to this. Furthermore, the present invention can be applied to semiconductor devices in general without any particular reason to be limited to power devices.

  In addition, various modifications can be made without departing from the characteristics of the present invention.

  DESCRIPTION OF SYMBOLS 10 Semiconductor device, 12 1st emitter electrode, 14 2nd emitter electrode, 24 Passivation film, 30 Antioxidation film, 54 Barrier layer, 56 Conductor layer, 58 Additional electrode

Claims (8)

An electrode formed on the surface of the semiconductor layer;
An additional electrode formed on the electrode and solderable to the lead frame;
A semiconductor device comprising: a passivation film which covers the electrode together with the additional electrode and is formed by providing an opening on the surface of the additional electrode so as to cover the semiconductor layer.   The semiconductor device according to claim 1, wherein the electrode is Al, AlSi, or AlCu formed by a sputtering method and heated at 400 to 470 ° C. in a hydrogen or nitrogen atmosphere.   The semiconductor device according to claim 1, wherein the passivation film is silicon nitride formed by a plasma CVD method.   The semiconductor device according to claim 1, wherein the additional electrode is integrally formed on the opening and the passivation film, and an area of the additional electrode is larger than an area of the opening. . The semiconductor layer constitutes a power MOSFET,
The semiconductor device according to claim 1, wherein the electrode is an emitter electrode. The semiconductor layer constitutes a rectifier diode;
The semiconductor device according to claim 1, wherein the electrode is an anode electrode. The additional electrode is
A barrier layer comprising a Ti layer or a Mo layer;
A conductor layer made of a Ni layer formed on the barrier layer;
The semiconductor device according to claim 1, further comprising an antioxidant layer made of an Au layer or an Ag layer formed on the conductor layer. A step of forming an electrode that is an Al, AlSi, or AlCu film on the semiconductor layer by a sputtering method;
Heating the electrode at 400 to 470 ° C. in a hydrogen or nitrogen atmosphere;
Forming a passivation film made of silicon nitride by a plasma CVD method;
Forming an opening of the passivation film on the electrode;
Forming an additional electrode integrally on the opening and the passivation film,
The additional electrode includes a barrier layer made of a Ti layer or a Mo layer, a conductor layer made of a Ni layer on the barrier layer, and an antioxidant layer made of an Au layer or an Ag layer on the conductor layer. A method of manufacturing a semiconductor device.

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