JP2010272597A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

In a semiconductor device having a fuse element on a substrate, it is easy to cut a fuse and a fuse cut state is reliably obtained.
A semiconductor device includes a MOS transistor having a MIPS structure and a fuse element on a substrate. The fuse element 100 includes a metal film 28 provided on the substrate 10, an insulating film 30 provided on the metal film 28, a silicon layer 34 provided on the insulating film 30, and a silicon layer 34. A silicide layer 73 covering at least a part of the upper surface.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device including a fuse element and a manufacturing method thereof.

  As a fuse element in a semiconductor device, a structure in which a silicide layer is formed on polysilicon is known. The fuse is cut by passing an overcurrent through the silicide layer. For example, Patent Document 1 discloses a technique in which a polysilicon layer and a silicide layer are formed on an STI (Shallow Trench Isolation) and used as a fuse element in the same manufacturing process as a gate electrode on a Si substrate.

  On the other hand, with the progress of miniaturization of LSIs, there is a problem of deterioration of drive current due to depletion of polysilicon gate electrodes constituting each MOSFET. Therefore, a technique for avoiding depletion of the electrode by using a metal gate electrode has been studied. For example, Patent Document 2 discloses a MIPS (Metal Inserted Poly-Silicon Stacks) structure in which a metal gate electrode is inserted between a high-k film and a polysilicon gate electrode as one of the structures using a metal gate electrode. Has been.

JP 2007-266061 A JP 2007-19400 A

  In the technique of Patent Document 1, a fuse element is formed on an STI in the same manufacturing process as a gate electrode on a Si substrate. For this reason, when the MIPS structure of Patent Document 2 is simply applied to the technique of Patent Document 1, there is a problem that the fuse is not easily cut. This is due to the following reason.

  FIG. 11A is a cross-sectional view of a fuse element having a configuration similar to that of Patent Document 1. FIG. FIG. 11B is a cross-sectional view showing the configuration of the fuse element on the Si substrate when it is assumed that the MIPS structure of Patent Document 2 is simply applied to the technique of Patent Document 1.

  When the fuse element is formed of polysilicon, the polysilicon 106 is formed on the STI region 104 and the silicide layer 108 is formed on the polysilicon 106. In this case, a current flows through the silicide layer 108 as shown in FIG. However, in the fuse element of FIG. 11B, since the metal electrode 114 exists under the polysilicon 106, there are two current paths: the silicide layer 108 and the metal electrode 114. Therefore, overcurrent hardly flows through the silicide layer 108 on the surface, and it becomes difficult to cut the fuse.

  Even if the silicide layer 108 can be cut, a current flows through the metal electrode 114 having a resistance lower than that of the polysilicon 106, so that the fuse cannot be cut.

  According to the present invention, there is provided a semiconductor device including a fuse element on a substrate, wherein the fuse element is provided on a metal film, an insulating film provided on the metal film, and the insulating film. There is provided a semiconductor device comprising a silicon layer and a silicide layer covering at least a part of the silicon layer.

  According to the present invention, there is also provided a method for manufacturing a semiconductor device including a fuse element on a substrate, the step of forming a metal film on the substrate, and the step of forming an insulating film on the metal film. Forming a silicon layer on the insulating film; and forming a silicide layer on the silicon layer, wherein the fuse element includes the metal film, the insulating film, the silicon layer, and A method for manufacturing a semiconductor device, comprising the silicide layer, is provided.

  According to the above configuration, since the insulating film is interposed between the silicon layer and the metal film constituting the fuse element, by preventing the current from flowing through the metal film, an overcurrent is passed through the silicide layer, Easy to cut. Further, by preventing the current from flowing through the metal film even after the silicide layer is cut, a fuse cut state can be obtained with certainty.

  According to the present invention, in a semiconductor device including a fuse element on a substrate, it is possible to prevent an electric current from flowing through a metal film, thereby allowing an overcurrent to flow through the silicide layer and facilitating the cutting of the fuse. Further, by preventing the current from flowing through the metal film even after the silicide layer is cut, a fuse cut state can be obtained with certainty.

It is sectional drawing which shows the semiconductor device of 1st Embodiment by this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. (A) is sectional drawing which shows the fuse element which consists of a polysilicon layer. (B) is sectional drawing explaining the subject of this application.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  FIG. 1 is a cross-sectional view showing a semiconductor device 1 according to the first embodiment. The semiconductor device 1 includes a fuse element 100 on a substrate 10. In the present embodiment, the substrate 10 is a semiconductor substrate.

  The fuse element 100 includes a metal film 28, an insulating film 30 provided on the metal film 28, a silicon layer 34 provided on the insulating film 30, and a silicide covering at least part of the silicon layer 34. And a layer 73. In the present embodiment, the silicon layer 34 is non-doped silicon. In the present embodiment, the fuse element 100 has a gate insulating film 65 located under the metal film 28. The gate insulating film 65 is formed on the element isolation insulating film 14.

  The fuse element 100 has contact plugs 80 (first contact plugs) and contact plugs 82 (second contact plugs) arranged on the silicon layer 34 at intervals. A silicide layer 73 is interposed between the contact plug 80 and the silicon layer 34 and between the contact plug 82 and the silicon layer 34.

  The substrate 10 of the semiconductor device 1 has an element isolation region where the element isolation insulating films 12 and 14 are formed and an element formation region where an active element such as a transistor is formed. A fuse element 100 is formed in at least a part of the element isolation region. An N channel MOSFET and a P channel MOSFET are formed in the element formation region. The N-channel MOSFET and the P-channel MOSFET have a metal film 28 as a metal gate electrode.

  The N-channel MOSFET is provided on the P-type well 16, a gate insulating film 64 provided in the element formation region, a metal film 28 as a metal gate electrode provided on the gate insulating film 64, and a metal film 28. The silicon electrode 35, the extension region 48, and the deep SD region 58 are included. That is, the N channel MOSFET has a MIPS structure. A silicide layer 72 is formed on the silicon electrode 35 and the Deep SD region 58. The gate electrode 66 of the N channel MOSFET has a metal film 28, a silicon electrode 35, and a silicide layer 72.

  The P-channel MOSFET is provided on the N-type well 18, the gate insulating film 65 provided in the element formation region, the metal film 28 as a metal gate electrode provided on the gate insulating film 65, and the metal film 28. The silicon electrode 37, the extension region 52, and the deep SD region 62 are included. The P channel MOSFET also has a MIPS structure like the N channel MOSFET. A silicide layer 73 is formed on the silicon electrode 37 and the Deep SD region 62. The gate electrode 67 of the P-channel MOSFET has a metal film 28, a silicon electrode 37, and a silicide layer 73.

  The P-channel MOSFET and the N-channel MOSFET are connected to contact plugs 78 embedded in the interlayer insulating film 76, respectively.

  Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to cross-sectional views in FIGS.

  First, as shown in FIG. 2A, element isolation insulating films 12 and 14 are formed on a substrate 10. As the substrate 10, for example, a silicon substrate can be used. The formation method of the element isolation insulating films 12 and 14 is STI (Shallow Trench Isolation). Next, the P-type well 16 is formed in the region where the N-channel MOSFET is formed, and the N-type well 18 is formed in the region where the P-channel MOSFET is formed.

  Next, as shown in FIG. 2B, a 1.0 nm oxynitride film is formed as the interface insulating film 20. The interfacial insulating film 20 is formed by performing plasma nitridation after forming a silicon oxide film by, for example, sulfuric acid / hydrogen peroxide mixture, ozone water, hydrochloric acid / ozone water, and after thermal oxidation.

  Thereafter, as shown in FIG. 2C, a La film 22 is formed on the entire surface of the substrate 10 by sputtering. The film thickness of the La film 22 is in the range of 0.1 nm to 2.0 nm. La is a metal for controlling the threshold voltage of the N-channel MOSFET. In addition to La, Dy can also be used.

  Then, as shown in FIG. 3A, a resist mask 24 is formed. Thereafter, the La film 22 on the N-type well 18 and the element isolation insulating film 14 is removed by wet processing. Diluted hydrochloric acid is used for the wet treatment. Then, as shown in FIG. 3B, after removing the La film 22, the resist mask 24 is removed by ashing.

Next, a high dielectric constant gate insulating film 26 is formed as shown in FIG. The high dielectric constant gate insulating film 26 is an insulating film selected from, for example, HfO ₂ , ZrO ₂ , HfSiON, La ₂ O ₃ , and HfAlO. The film thickness is 1.0 nm or more and 5.0 nm or less. The high dielectric constant gate insulating film 26 can be formed using any one of a CVD method, an AL (Atomic Layer) CVD method, and a sputtering method. Subsequently, a metal film 28 as a metal gate electrode is formed on the high dielectric constant gate insulating film 26. The metal film 28 is at least one metal selected from, for example, TiN, W, TaN, TaSiN, Ru, TiAl, and Al. The film thickness of the metal film 28 is 1.0 nm or more and 20.0 nm or less.

Next, as shown in FIG. 4A, an insulating film 30 is formed on the metal film 28. As a material of the insulating film 30, a silicon oxide film, a silicon nitride film, HfSiON, HfO ₂ , ZrO ₂ , HfAlO, Al ₂ O ₃ or the like can be used. The thickness of the insulating film 30 is 1.0 nm to 20.0 nm. As a method for forming the insulating film 30, a CVD method, a sputtering method, or the like can be used.

  Subsequently, a resist mask 32 is formed as shown in FIG. 4B, and openings located on the N-type well 18 region and the P-type well 16 region are formed in the resist mask 32. Next, as shown in FIG. 4C, the insulating film 30 in the N-type well 18 region and the P-type well 16 region is removed by etching using the resist mask 32 as a mask. In this state, the metal film 28 in the N-type well 18 region and the P-type well 16 region is not covered with the insulating film 30. Thereafter, the resist mask 32 is removed.

  Then, as shown in FIG. 5A, a silicon layer 34 is formed on the entire surface including the metal film 28 and the insulating film 30 in the N-type well 18 region and the P-type well 16 region. The silicon layer 34 in the present embodiment is amorphous silicon. The film thickness of amorphous silicon is 10 nm or more and 100 nm or less. Polysilicon may be used as the material of the silicon layer 34.

  Subsequently, as shown in FIG. 5B, a hard mask 40 is formed on the silicon layer 34, and a resist mask 42 is further formed on the hard mask 40. The hard mask 40 is a film selected from a silicon oxide film and a silicon nitride film.

  Next, by dry etching and wet processing, gate electrodes 66 and 67 of the N-channel MOSFET and P-channel MOSFET and the fuse element 100 are formed as shown in FIG.

  Then, a silicon nitride film is formed by ALCVD, and an offset spacer film 44 is formed on the gate electrodes 66 and 67 and the fuse element 100 as shown in FIG. The offset spacer film 44 may be a silicon oxide film or a stacked structure of silicon nitride film / silicon oxide film.

Thereafter, as shown in FIG. 6B, after covering the N-type well 18 and the fuse element 100 with a resist mask 46, an extension region 48 is formed in the P-type well 16 by ion implantation. The implantation conditions are, for example, BF ₂ 50 keV 3E13 atoms / cm ² 30 degrees and As 2 keV 8E14 atoms / cm ² 0 degrees.

Subsequently, after removing the resist mask 46, as shown in FIG. 7A, the P-type well 16 and the fuse element 100 are similarly covered with the resist mask 50, and then the extension region 52 is ionized in the N-type well 18. Form by injection. The implantation conditions are, for example, As 50 keV 3E13 atoms / cm ² 30 degrees and BF ₂ 3 keV 8E14 atoms / cm ² 0 degrees.

  Next, after removing the resist mask 50, a silicon nitride film or a silicon oxide film is formed, and a sidewall spacer film 54 is formed by dry etching as shown in FIG. 7B.

Thereafter, as shown in FIG. 8A, after covering the N-type well 18 and the fuse element 100 with a resist mask 56, a Deep SD region 58 is formed in the P-type well 16 by ion implantation. The implantation conditions are, for example, Ge 30 keV 5E14 atoms / cm ² 0 degrees, As 15 keV 3E15 atoms / cm ² 0 degrees, and P 20 keV 5E13 atoms / cm ² 0 degrees.

Subsequently, after removing the resist mask 56, as shown in FIG. 8B, the P-type well 16 and the fuse element 100 are similarly covered by the resist mask 60, and then the Deep SD region 62 is formed in the N-type well 18. It is formed by ion implantation. The implantation conditions are, for example, Ge 30 keV 5E14 atoms / cm ² 0 degrees, B 7 keV 5.0E13 atoms / cm ² 0 degrees, and BF ₂ 9 keV 2E15 atoms / cm ² 0 degrees.

  In the steps shown in FIGS. 6B, 7A, 8A, and 8B, the fuse element 100 is covered with a resist mask. For this reason, impurities are not implanted into the silicon layer 34 of the fuse element 100.

  Then, after removing the resist mask 60, heat treatment is performed to activate the extension and deep SD regions. The heat treatment conditions are, for example, 1050 ° C. and 0 seconds. At this time, La in the N channel MOSFET formation region diffuses into the high dielectric constant gate insulating film 26. Thereby, the La-containing high dielectric constant insulating film 27 is formed in the N-channel MOSFET.

  Next, as shown in FIG. 9A, a NiPt film 68 is formed by, for example, a sputtering method. Then, after forming a primary silicide layer by heat treatment, the surplus NiPt film 68 is removed with aqua regia and further heat treated, thereby forming a NiPtSi film as a secondary silicide layer as shown in FIG. 9B. Some silicide layers 72 and 73 are formed. As the silicide layers 72 and 73, NiSi, PtSi, or the like can be used in addition to NiPtSi.

  Subsequently, as shown in FIG. 10A, a contact etching stopper film 74 is formed. The contact etching stopper film 74 is a silicon nitride film, for example, and has a film thickness of 10 nm to 100 nm. Then, as shown in FIG. 10B, an interlayer insulating film 76 made of a silicon oxide film is formed. Further, by forming the contact plugs 78, 80, 82, the semiconductor device 1 of FIG. 1 is obtained.

  Next, the operation and effect of this embodiment will be described. In the fuse element 100 according to the present embodiment, an insulating film 30 is interposed between the silicon layer 34 and the metal film 28. Therefore, when a current is passed from the contact plug 80 to the contact plug 82 in order to cut the fuse element 100, the current flows to the silicide layer 73 without flowing to the metal film 28. Therefore, an overcurrent can be passed through the silicide layer 73, a disilicide layer or a disconnected portion is formed in the silicide layer 73, and the silicide layer 73 has a high resistance. When the resistance of the silicide layer 73 is increased, it becomes difficult for a current to flow through the silicide layer 73 even when a voltage is applied between the contact plug 80 and the contact plug 82. In addition, since the insulating film 30 is interposed between the silicon layer 34 and the metal film 28, the current is suppressed from flowing through the metal layer 28 even if the current does not easily flow through the silicide layer 73. Therefore, current does not easily flow through the fuse element 100. Therefore, the resistance of the fuse element 100 is increased. Using this resistance difference, the fuse element 100 can be reliably given a function as a fuse.

  The fuse element 100 of this embodiment has the same configuration as that of the N-channel MOSFET and the P-channel MOSFET except that the insulating film 30 is interposed between the silicon layer 34 and the metal film 28. Therefore, it can be manufactured simultaneously with the N-channel MOSFET and the P-channel MOSFET in the element formation region without complicating the manufacturing process. Therefore, it can suppress that manufacturing cost increases.

  In FIG. 11B, when the MIPS structure of Patent Document 2 is simply applied to the technique of Patent Document 1, a configuration in which the metal electrode 114 is not provided in the fuse element may be considered. However, in such a configuration, the height of the fuse element is lower than that of a transistor (not shown) provided in the element formation portion. Such a difference in height causes a step in the subsequent interlayer insulating film forming process, which has an adverse effect. Furthermore, there is a problem that the manufacturing process becomes complicated.

  On the other hand, the fuse element 100 according to the present embodiment has the same configuration as the N-channel MOSFET and the P-channel MOSFET except that the insulating film 30 is interposed between the silicon layer 34 and the metal film 28. The height of the element and the MOSFET is substantially the same, and there is no influence on subsequent processes.

  The semiconductor device according to the present invention is not limited to the above embodiment, and various modifications are possible. For example, in the above-described embodiment, an example in which the silicon layer 34 of the fuse element is non-doped has been shown. , P-type or N-type impurities may be doped.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Semiconductor substrate 12 Element isolation insulating film (STI)
14 Device isolation insulating film (STI)
16 P-type well 18 N-type well 20 Interfacial insulating film 22 La film 24, 32, 42, 46, 50, 56, 60 Resist mask 26 High dielectric constant gate insulating film 27 La-containing high dielectric constant gate insulating film 28 Metal film 30 Insulating film 35 Silicon layer 34 Silicon electrode 37 Silicon electrode 40 Hard mask 44 Offset spacer film 48 Extension region 52 Extension region 54 Side wall spacer film 58 Deep SD region 62 Deep SD region 64 Gate insulating film 65 Gate insulating film 66 Gate electrode 67 Gate Electrode 68 NiPt film 72, 73 Silicide layer 74 Contact etching stopper film 76 Interlayer insulating film 78 Contact plug 80 Contact plug 82 Contact plug 100 Fuse element

Claims (11)

A semiconductor device comprising a fuse element on a substrate,
The fuse element is:
A metal film,
An insulating film provided on the metal film;
A silicon layer provided on the insulating film;
A silicide layer covering at least a part of the silicon layer;
A semiconductor device comprising: The semiconductor device according to claim 1,
The semiconductor device has at least one selected from a silicon oxide film, a silicon nitride film, HfSiON, HfO ₂ , ZrO ₂ , HfAlO, and Al ₂ O _{3 as the} insulating film. The semiconductor device according to claim 1 or 2,
The fuse device further includes a gate insulating film located between the substrate and the metal film. The semiconductor device according to claim 1,
The substrate is partitioned into an element isolation region and an element formation region,
The fuse element is provided in at least a part of the element isolation region,
The device forming region further includes a MOS transistor having a metal gate electrode. The semiconductor device according to claim 4,
The MOS transistor is
A gate insulating film provided on the substrate;
The metal gate electrode provided on the gate insulating film;
A silicon electrode provided on the metal gate electrode;
A silicide layer provided on the silicon electrode;
A semiconductor device including: The semiconductor device according to claim 1,
A first contact plug and a second contact plug which are spaced apart from each other on the silicide layer of the fuse element;
The semiconductor device in which the first contact plug and the second contact plug are electrically connected by the silicide layer. The semiconductor device according to claim 1,
A first contact plug and a second contact plug which are spaced apart from each other on the silicide layer of the fuse element;
A semiconductor device in which the silicide layer has a disilicided or disconnected region between the first contact plug and the second contact plug. A method of manufacturing a semiconductor device comprising a fuse element on a substrate,
Forming a metal film on the substrate;
Forming an insulating film on the metal film;
Forming a silicon layer on the insulating film;
Forming a silicide layer on the silicon layer,
The method of manufacturing a semiconductor device, wherein the fuse element includes the metal film, the insulating film, the silicon layer, and the silicide layer. In the manufacturing method of the semiconductor device according to claim 8,
The substrate is partitioned into an element isolation region in which the fuse element is formed at least in part and an element formation region in which a MOS transistor is formed,
Forming the metal film on the substrate includes forming the metal film of the fuse element in the element isolation region and simultaneously forming the metal gate electrode of the MOS transistor in the element formation region;
In the step of forming the insulating film on the metal film, the insulating film is formed on the metal film of the fuse element and the insulating film is formed on the metal gate electrode in the element isolation region. Without
The step of forming the silicon layer on the insulating film forms a silicon layer on the insulating film of the fuse element in the element isolation region, and at the same time, forms the metal gate electrode of the MOS transistor in the element forming region. Forming a silicon electrode on the substrate. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 8 or 9,
A method of manufacturing a semiconductor device, further comprising a step of forming a gate insulating film on the substrate before the step of forming the metal film on the substrate. In the manufacturing method of the semiconductor device according to claim 10,
The step of forming the gate insulating film on the substrate forms a gate insulating film located below the metal layer in the element isolation region and simultaneously forms a gate insulating film of the MOS transistor in the element forming region. A method for manufacturing a semiconductor device, comprising the step of:

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