JP2010259060A - Driver comparator circuit and testing apparatus using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driver comparator circuit having an interactive interface which cancels a transmission signal transmitted by itself and evaluates a signal component, by extracting only the signal component from a device of a communication partner in a bidirectional transmission. <P>SOLUTION: A first resistor R1 has a first terminal to which a first voltage VH' is applied and a second terminal which is connected to an input-output terminal P1. A second resistor R2 has a first terminal to which the first voltage VH' is applied. A tail current source 12 generates a predetermined tail current Ia'. A current switch 10 receives data PAT to be transmitted to a second device 102; selects either the second terminal of the first resistor R1 or the second terminal of the second resistor R2 according to a value of the PAT; and connects the selected one to the tail current source 12. A voltage divider circuit DIV1 includes a third resistor R3 and a fourth resistor R4, arranged in series between the second terminal of the first resistor R1 and the second terminal of the second resistor R2. A load balancer LB1 includes a fifth resistor R5, having a first terminal to which a second voltage VLB is applied and a second terminal which is connected to the second terminal of the second resistor R2. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a driver / comparator circuit having a driver function for outputting a signal via a single transmission line and a comparator function for determining the level of an input signal.

  When data is transmitted and received between two semiconductor devices, bidirectional transmission may be performed via a single transmission line. When a device having such a bidirectional interface is tested, the amplitude of a signal output from the device under test (DUT) is compared with a threshold voltage, and the quality is determined.

  Consider a test device for inspecting a DUT having a bidirectional interface. The test apparatus is provided with a transmitter (driver) and a receiver (comparator) connected to a common transmission line. The driver transmits a test pattern to the DUT, and the comparator determines the logical value of the signal output from the DUT or checks the amplitude of the signal.

  The comparator of the test apparatus is connected to the DUT via the transmission line and is also connected to the driver on the test apparatus side. Therefore, it is necessary to design a DUT test apparatus having a bidirectional interface so that the comparator is not affected by the output signal of an adjacent driver.

  Most primitively, during the period in which the signal output from the DUT propagates through the transmission line, bidirectional transmission can be realized by fixing the output of the driver to a predetermined termination voltage. However, with this method, when the signal transmission direction is switched, overhead (referred to as a round trip delay) is generated for the length of the transmission line. In a test apparatus that supplies a very long test pattern to the DUT and determines a signal from the DUT, the round trip delay may cause a problem of an increase in test time and may contribute to a decrease in productivity.

  Such a problem occurs not only in the test apparatus but also in bidirectional transmission between semiconductor devices, and the round trip delay causes a reduction in the transmission rate.

  Various methods for solving the problem of round trip delay have been proposed. For example, Patent Documents 1 and 2 disclose circuits (hybrid circuits) that cancel only their own transmission signals and receive only signals from the other party in bidirectional communication.

JP 47-11702 A US Pat. No. 3,725,582 JP-A-8-23354 JP 2006-23233 A US Pat. No. 6,573,764B1 US Pat. No. 7,190,194B2 US Pat. No. 6,133,725 US Pat. No. 6,703,825

  The present invention has been made in such a situation, and one of exemplary purposes of an embodiment thereof is to provide a driver / comparator circuit having a bidirectional interface.

One embodiment of the present invention relates to a driver / comparator circuit that bidirectionally transmits a signal to / from a communication partner device via a transmission line. The driver / comparator circuit includes a voltage dividing circuit and a load balancer in addition to an input / output terminal connected to the transmission line, a driver amplifier, and a comparator.
The driver amplifier has a first resistor to which a first voltage is applied, a second resistor having a second terminal connected to the input / output terminal, a second resistor having a first voltage applied to the first terminal, A tail current source that generates a predetermined tail current and data to be transmitted to a communication partner device are selected, and one of the second terminal of the first resistor and the second terminal of the second resistor is selected according to the value, A current switch coupled to the tail current source. The voltage dividing circuit includes a third resistor and a fourth resistor provided in series between the second terminal of the first resistor and the second terminal of the second resistor. The load balancer includes a fifth resistor in which a second voltage is applied to the first terminal and the second terminal is connected to the second terminal of the second resistor. The comparator compares the potential at the connection point of the third and fourth resistors with a predetermined first threshold voltage.

  According to this aspect, the voltage at the second terminal of the first resistor and the voltage at the second terminal of the second resistor transition in opposite phases. Therefore, when the two voltages are divided by the third and fourth resistors, the signal component sent from the driver amplifier to the communication partner device can be canceled, and the comparator thresholds the signal component transmitted by the communication partner device. Can be compared with value voltage. Also, by providing the fifth resistor, the voltage amplitude of the second terminal of the first resistor and the voltage amplitude of the second terminal of the second resistor can be balanced.

Another aspect of the present invention relates to a test apparatus for inspecting a device under test by bidirectionally transmitting a signal to and from the device under test (DUT) via a transmission line. This test apparatus includes the above-described driver / comparator circuit that uses a device under test as a communication partner.
According to this aspect, only the signal component from the DUT can be compared with the threshold voltage, and the influence of the round trip delay can be reduced, so that the test time can be shortened.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other between methods and apparatuses are also effective as an aspect of the present invention.

  According to a driver / comparator circuit of an aspect of the present invention, it is possible to cancel a signal transmitted by itself and extract and evaluate only a signal component from a communication partner device.

1 is a circuit diagram showing a configuration of a driver / comparator circuit according to an embodiment. FIG. 2A and 2B are circuit diagrams showing a configuration example of the current switch of FIG. It is a circuit diagram which shows the structure of a basic driver / comparator circuit. FIGS. 4A and 4B are circuit diagrams in which only circuit elements related to the impedance of the driver / comparator circuit of FIGS. 3 and 1 are extracted. FIGS. 5A and 5B are circuit diagrams in which only circuit elements related to the voltages of the driver / comparator circuits of FIGS. 3 and 1 are extracted. FIGS. 6A and 6B are circuit diagrams in which only circuit elements related to the voltages of the driver / comparator circuits in FIGS. 3 and 1 are extracted. FIGS. 7A and 7B are circuit diagrams showing a part of the driver / comparator circuit to which the second device is connected. FIG. 6 is a circuit diagram showing a configuration of a driver / comparator circuit according to a first modification. FIG. 10 is a circuit diagram showing a configuration of a driver / comparator circuit according to a second modification. FIGS. 10A and 10B are circuit diagrams showing the configuration of the driver / comparator circuit according to the third modification.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  The embodiment described below relates to a driver / comparator circuit having a bidirectional interface. FIG. 1 is a circuit diagram showing a configuration of a driver / comparator circuit 100 according to the embodiment.

  The driver / comparator circuit 100 is an interface circuit of a first device, and is connected to a communication partner device (hereinafter referred to as a second device) 102 via a transmission line 104, and outputs a signal Vdp to the second device 102. The signal Vu outputted or outputted from the second device 102 is received.

  Alternatively, the driver / comparator circuit 100 is also suitable for use as an interface circuit (also referred to as pin electronics) of an automatic test equipment (ATE). That is, the driver / comparator circuit 100 outputs pattern data to the second device (DUT) and receives a signal from the DUT and determines its amplitude (level).

  The second device 102 includes a driver amplifier DRV2 and an output resistor Ru. The signal Vu output from the driver amplifier DRV2 is input to the input / output terminal P1 of the driver / comparator circuit 100 via the transmission line 104. The driver amplifier DRV2 is provided with an output resistor Ru. The following description will be made on the assumption that the characteristic impedance Zo of the transmission line 104 is matched with the output resistance Ru of the second device 102.

  The driver / comparator circuit 100 includes an input / output terminal P1 to which the transmission line 104 is connected. The driver / comparator circuit 100 further includes a driver amplifier DRV1, a load balancer LB1, a voltage dividing circuit DIV1, and a comparator CMP1.

  The driver amplifier DRV1 is a CML (Current Mode Logic) type driver suitable for high-speed transmission, and includes a first voltage source VS1, a first resistor R1, a second resistor R2, a current switch 10, and a tail current source 12.

  The first voltage source VS1 generates a first voltage VH ′. The first voltage VH ′ may be a power supply voltage or any other voltage.

  The first resistor R1 has a first voltage VH ′ applied to one end (first terminal) on the high potential side, and the other end (second terminal) on the low potential side connected to the input / output terminal P1. The second resistor R2 is applied with the first voltage VH ′ at one end (first terminal) on the high potential side. The resistance values of the first resistor R1 and the second resistor R2 are equal, and will be referred to as Ra 'below. The tail current source 12 generates a predetermined tail current Ia '. The current switch 10 receives pattern data PAT to be transmitted to the second device 102, selects one of the second terminal of the first resistor R1 and the second terminal of the second resistor R2 according to the value, and generates a tail current source. 12 is combined.

  In the driver amplifier DRV1, when PAT = 1, the tail current Ia ′ flows to the second resistor R2 side. Therefore, the voltage Vdp of the second terminal of the first resistor R1 becomes a voltage corresponding to the high level, and PAT = 0. Since the tail current Ia ′ flows to the first resistor R1 side, the voltage Vdp becomes a voltage corresponding to the low level.

  2A and 2B are circuit diagrams showing a configuration example of the current switch 10 of FIG. Each of the current switches 10a and 10b in FIGS. 2A and 2B includes a first transistor Tr1 and a second transistor Tr2. The transistors Tr1 and Tr2 in FIG. 2A are NPN bipolar transistors. The first terminal (collector) of the first transistor Tr1 is pulled up to the first voltage VH ′ via the first resistor R1. The first terminal (collector) of the second transistor Tr2 is pulled up to the first voltage VH ′ via the second resistor R2. The second terminals (emitters) of the first transistor Tr1 and the second transistor Tr2 are connected in common and connected to the tail current source 12 that supplies the tail current Ia '. Pattern data PAT is input to control terminals (bases) of the first transistor Tr1 and the second transistor Tr2.

  The current switch 10b in FIG. 2B has a configuration in which the transistors Tr1 and Tr2 are replaced with N-channel MOSFETs, and the first terminal may be read as the drain, the second terminal as the source, and the control terminal as the gate.

  However, the configuration of the current switch 10 is not limited to the differential transistor pair shown in FIGS. 2A and 2B, and a switching element other than the transistor may be used.

  Returning to FIG. The voltage dividing circuit DIV1 includes a third resistor R3 and a fourth resistor R4 provided in series between the second terminal of the first resistor R1 and the second terminal of the second resistor R2. The voltage dividing circuit DIV1 divides the voltage Vdp of the second terminal of the first resistor R1 and the second terminal Vdn of the second resistor R2. The resistance values of the third resistor R3 and the fourth resistor R4 may be equal. Hereinafter, the two resistance values are denoted as Rb.

The resistance value Rb of the third resistor R3 and the fourth resistor R4 may be arbitrary, but is sufficiently larger than the resistance value Ra of the fifth resistor R5, for example, a large value of about several tens of times (10 to 100 times) It is preferable that In this case, the influence of the voltage dividing circuit DIV1 on the output signal Vdp of the driver amplifier DRV1 can be suppressed.
On the other hand, since the third resistor R3 and the fourth resistor R4 constitute a low-pass filter together with the input capacitance of the comparator CMP1, if the resistance value Rb is too large, the responsiveness of the comparator CMP1 is deteriorated.
For example, Ra = 50Ω and Rb = 1kΩ may be used as an example of realistic values.

  The load balancer LB1 is provided to balance the impedance component connected to the second terminal of the first resistor R1 with the impedance component connected to the second terminal of the second resistor R2. Specifically, the load balancer LB1 includes a second voltage source VS2 and a fifth resistor R5. The second voltage source VS2 generates a predetermined second voltage VLB. The second voltage VLB is applied to one end (first terminal) on the high potential side of the fifth resistor R5, and the other end (second terminal) on the low potential side is connected to the second terminal of the second resistor R2. Is done.

  For example, the second voltage VLB may be an arbitrary fixed voltage, but is preferably near the average value of the voltage output from the second device 102. In this case, the differential voltage components Vdp and Vdn of the driver amplifier DRV1 can be well balanced.

  The comparator CMP1 compares the output voltage of the voltage dividing circuit DIV1, that is, the voltage Vc at the connection point of the third resistor R3 and the fourth resistor R4, with a predetermined first threshold voltage VOH ′.

  The above is the basic configuration of the driver / comparator circuit 100. Next, the operation of the driver / comparator circuit 100 will be described.

  The voltage Vdp at the second terminal of the first resistor R1 and the voltage Vdn at the second terminal of the second resistor R2 transition in opposite phases according to the pattern data PAT. Focusing on the output voltage Vc of the voltage dividing circuit DIV1, since it is a voltage obtained by dividing the two voltages Vdp and Vdn, the component that varies in accordance with the pattern data PAT is partially or completely canceled. The comparator CMP1 converts the signal component transmitted by the second device 102 into the threshold voltage VOH ′ in a partially or completely free state from the influence of the signal component transmitted by the driver amplifier DRV1 to the second device 102. Can be compared.

  If there is no load balancer LB1, the amplitude of the voltage Vdn is about twice the amplitude of the voltage Vdp. Therefore, even if the voltage is divided by the voltage dividing circuit DIV1, the signal component sent out by the driver amplifier DRV1 cannot be canceled. By providing the load balancer LB1, the amplitudes of the differential voltages Vdp and Vdn can be made uniform.

  The advantages of the driver / comparator circuit 100 of FIG. 1 become clear by comparison with the driver / comparator circuit 300 of FIG. FIG. 3 is a circuit diagram showing a configuration of a basic driver / comparator circuit 300. The driver / comparator circuit 300 of FIG. 3 has a configuration in which the voltage dividing circuit DIV1 and the load balancer LB1 are omitted from the driver / comparator circuit 100 of FIG.

The behavior of the driver / comparator circuit 300 of FIG. 3 will be described. Here, it is assumed that the driver / comparator circuit 300, the second device 102, and the transmission line 104 are impedance matched. That means
Ra = Zo = Ru (A)
Is true.

In the driver / comparator circuit 300 of FIG. 3, the input voltage Vd of the comparator CMP1 is given by the expression (1a) if the delay time due to the transmission line 104 is ignored. When formula (A) is applied to formula (1a), formula (1b) is obtained.

The comparator CMP1 compares the voltage Vd with the threshold voltage VOH,
When Vd> VOH, SH = low level. When Vd <VOH, a determination signal SH that generates SH = high level is generated. As is clear from the equation (1b), the voltage Vd input to the comparator CMP1 is a combination of the pattern data PAT output by the driver and the output voltage Vu of the second device 102.

This means that if a signal is output from the driver amplifier DRV1 during the output of the signal of the second device 102, the determination result of the high level and the low level in the comparator CMP1 is affected.
On the other hand, according to the driver / comparator circuit 100 of FIG. 1, the influence of the pattern data PAT on the voltage Vc input to the comparator CMP1 can be reduced or eliminated as will be described in detail later.

  Hereinafter, a design method of each voltage and resistance value of the driver / comparator circuit 100 will be described. The design guideline is to make the characteristics of the driver / comparator circuit 100 of FIG. 1 coincide with the characteristics of the driver / comparator circuit 300 of FIG.

(First condition)
The first condition is that the impedance Z1 desired from the input / output terminal P1 of the driver / comparator circuit 100 in FIG. 1 is the impedance Z2 desired from the input / output terminal P1 in the driver / comparator circuit 300 in FIG. Is equal to

  4A and 4B are circuit diagrams in which only circuit elements related to the impedance of the driver / comparator circuit 300 of FIG. 3 and the driver / comparator circuit 100 of FIG. 1 are extracted.

In order for the two impedances Z1 and Z2 to be equal,
Ra = Ra ′ // (2 × Rb + Ra // Ra ′) (2)
Must hold. Here, “//” means the combined resistance value of the parallel resistors. In other words, “//”
A // B = A × B / (A + B)
Can be regarded as an operator. In addition, this operator has a coupling rule A // (B // C) = (A // B) // C
Holds.

When equation (2) is solved for Ra ′, equation (3) is obtained.

  The resistance value Ra of the first resistor R1 of the driver / comparator circuit 300 and the resistance value Ra of the fifth resistor R5 of the driver / comparator circuit 100 must both be equal to the characteristic impedance of the transmission line 104. Therefore, if the resistance value Rb of the voltage dividing circuit DIV1 is determined, the resistance value Ra 'of the first resistor R1 and the second resistor R2 can be determined. Alternatively, Ra ′ may be determined first, and Rb may be determined so as to satisfy Equation (3).

  When Expression (3) is satisfied, impedance matching of the driver / comparator circuit 100, the second device 102, and the transmission line 104 can be achieved, and signal reflection can be suppressed.

(Second condition)
The second condition is that the voltage level of the signal Vd output from the input / output terminal P1 of the driver / comparator circuit 300 in FIG. 3 is equal to the voltage of the signal Vdp output from the input / output terminal P1 of the driver / comparator circuit 100 in FIG. Is equal to the level.

  FIGS. 5A and 5B are circuit diagrams in which only circuit elements related to the voltage Vd of the driver / comparator circuit 300 of FIG. 3 and the voltage Vdp of the driver / comparator circuit 100 of FIG. 1 are extracted. FIGS. 5A and 5B show a state where PAT = 0.

Equation (4) is obtained from FIG. Moreover, Formula (5) is obtained from FIG.5 (b).

In order for FIG. 5A and FIG. 5B to be equivalent, Vd = Vdp may be satisfied. Formula (6) is obtained when an equation is established using Formula (5).

  Next, consider the case of PAT = 1. 6A and 6B are circuit diagrams in which only circuit elements related to the voltage Vd of the driver / comparator circuit 300 of FIG. 3 and the voltage Vdp of the driver / comparator circuit 100 of FIG. 1 are extracted.

Equation (7) is obtained from FIG. 6 (a), and equations (8a) and (8b) are obtained from FIG. 6 (b).

In order for FIG. 6 (a) and FIG. 6 (b) to be equivalent, Vd = Vdp needs to be established. When equations are established using Equations (7) and (8), Equation (9) is obtained. obtain.

When equations (6) and (9) are solved simultaneously, equations (10) and (11) are obtained.

  In the driver / comparator circuit 100 of FIG. 1, when the first voltage VH ′ and the tail current Ia ′ satisfy the expressions (10) and (11), the driver / comparator circuit 100 of FIG. 1 and the driver / comparator circuit of FIG. A signal Vdp having the same amplitude as 300 can be generated. In other words, when viewed from the second device 102, the driver / comparator circuit 100 and the driver / comparator circuit 300 cannot be distinguished from each other.

Subsequently, the input voltage Vc of the comparator CMP1 will be examined. FIG. 7A is a circuit diagram showing a part of the driver / comparator circuit 100 to which the second device 102 is connected. FIG. 7B is a modification of the driver / comparator circuit 100 ′ of FIG. In FIG. 7B,
Ra = Ru
When the circuit network is solved, the input voltage Vc of the comparator CMP1 is obtained as shown in Expression (12).

  The voltage Vc represented by Expression (12) does not include the PAT term. That is, it is supported that the output signal of the driver amplifier DRV1 does not affect the level determination in the comparator CMP1.

If Vu in equation (12) is replaced with VOH, threshold voltage VOH ′ in FIG. 1 can be determined as in equation (13).

  The configuration and operation of the driver / comparator circuit 100 according to the present embodiment have been described. Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(First modification)
FIG. 8 is a circuit diagram showing a configuration of the driver / comparator circuit 100a according to the first modification. In this modification, the second voltage VLB is equal to the first voltage VH ′, and the first terminals of the first resistor R1, the second resistor R2, and the third resistor R3 receive the voltage VH ′ from the common voltage source VS1. receive. According to this modification, the second voltage source VS2 can be omitted.
Further, in this modification, the relational expression that each parameter should satisfy is the relational expression obtained by the driver / comparator circuit 100 of FIG. 1 described above plus the constraint condition VLB = VH ′.

(Second modification)
FIG. 9 is a circuit diagram showing a configuration of a driver / comparator circuit 100b according to a second modification. In this modification, in addition to the driver / comparator circuit 100 of FIG. 1, a level shift circuit LS1 for level shifting the input voltage Vc of the comparator CMP1 is provided.

  The level shift circuit LS1 includes a sixth resistor R6 and a third voltage source VS3. The third voltage source VS3 generates a predetermined third voltage Vcs. One end (first terminal) of the sixth resistor R6 is connected to a connection point of the third resistor R3 and the fourth resistor R4 (that is, an input terminal of the comparator CMP1), and a third voltage is connected to the other end (second terminal). Vcs is applied. The resistance value of the sixth resistor R6 is denoted as Rc.

  The level shift circuit LS1 shifts the level of the input voltage Vc of the comparator CMP1. When the comparator CMP1 having a narrow allowable input voltage range is used, the input voltage Vc of the comparator CMP1 can be set to an appropriate value by providing the level shift circuit LS1.

When the first condition is applied to the modified example of FIG. 9, Equation (14) is obtained.
Ra ′ // {(Ra ′ // Ra + Rb) // Rc + Rb)} = Ra (14)
When equation (14) is solved for Ra ′, equation (15) is obtained. Expression (15) is a relational expression that the resistance value of each resistor should satisfy in the driver / comparator circuit 100b of FIG.

When the second condition is applied to the modified example of FIG. 9, equations (16) and (17) are obtained.

VH ′ and Ia ′ can be obtained by using the above formula, formula (10), and formula (11). Further, when Expression (12) is used, Expression (18) is obtained.

  In equation (18), when Vu is replaced with VOH, a threshold voltage VOH ′ is obtained.

(Third Modification)
FIGS. 10A and 10B are circuit diagrams showing the configuration of the driver / comparator circuit 100c according to the third modification. In FIG. 10A, at least one of the termination circuit 20a including the first voltage source VS1 and the first resistor R1, the termination circuit 20b including the first voltage source VS1 and the second resistor R2, and the termination circuit 20c of the load balancer LB1 is FIG. 10B shows the configuration of the termination circuit 20 shown in FIG.

  As shown in FIG. 10B, the termination circuit 20 includes a Thevenin termination circuit 22 and an R-2R termination circuit 24 whose output terminals are connected in common.

  The termination circuit 20 is controlled according to digital control data B of (K + L) bits (K and L are natural numbers). The upper K bits of the control data B are allocated to the Thevenin termination circuit 22, and the lower L bits are allocated to the R-2R termination circuit 24. FIG. 10 shows a case where K = 4 and L = 3.

The Thevenin termination circuit 22 includes Σ _{i = 1: K} 2 ⁱ⁻¹ = 2 ^K −1 parallel-connected pairs of a buffer BUF and a resistor R. Σ _{i = 1: K} indicates that the variable i is added while being incremented from 1 to K. The buffer and resistor pairs are grouped into K pieces, and the pairs belonging to the same group have the input terminal and the output terminal connected in common. The i-th (1 ≦ i ≦ K) group includes 2 ⁱ⁻¹ pairs, and B [i + L] of the lower (i + L) -th bit of the control data is input to the i-th group. The The output terminals of all pairs are connected in common.

  The R-2R termination circuit 24 includes (L + 1) stages of R-2R type networks and (L + 1) buffers that apply a voltage to one end of the resistor R of each stage. The lower L bits of the control data B are assigned to each buffer in order from the closest to the output terminal, and a fixed potential (for example, ground potential) is input to the buffer farthest from the output terminal.

  According to the modification of FIG. 10, the first voltage VH ′, the second voltage LB, and the third voltage Vcs in FIG. 9 are suitable in accordance with the value of each bit B [6: 0] of the control data. Can be controlled.

In the modification of FIG. 10, the impedance viewed from the output terminal of the Thevenin termination circuit 22 is R / (2 ^K −1). The impedance of the R-2R termination circuit 24 viewed from the output terminal is R.
Impedance looking into the inside thereof from the output terminal of the termination circuit 20 is given by the synthesis of Thevenin termination circuit 22 and the R-2R termination circuit 24, the R / 2 ^K. Therefore, the values of the resistors R and R / 2 may be determined so that this combined impedance is equal to the resistance values Ra ′, Ra, or Rc.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and arrangements can be made without departing from the scope.

DESCRIPTION OF SYMBOLS 100,300 ... Driver / comparator circuit, 102 ... 2nd device, 104 ... Transmission line, P1 ... Input / output terminal, DRV1 ... Driver amplifier, CMP1 ... Comparator, DIV1 ... Voltage divider circuit, LB1 ... Load balancer, 10 ... Current switch , 12 ... tail current source, VS1 ... first voltage source, VS2 ... second voltage source, VS3 ... third voltage source, LS1 ... level shift circuit, 20 ... termination circuit, 22 ... thevenin termination circuit, 24 ... R-2R Termination circuit, R1 ... first resistor, R2 ... second resistor, R3 ... third resistor, R4 ... fourth resistor, R5 ... fifth resistor, R6 ... sixth resistor.

Claims (8)

A driver / comparator circuit that bidirectionally transmits signals to / from a communication partner device via a transmission line,
An input / output terminal connected to the transmission line;
A first resistor having a first voltage applied to the first terminal and a second terminal connected to the input / output terminal;
A second resistor having the first voltage applied to the first terminal;
A tail current source for generating a predetermined tail current;
A current switch that receives data to be transmitted to the communication partner device, selects one of the second terminal of the first resistor and the second terminal of the second resistor according to the value, and is coupled to the tail current source When,
A voltage dividing circuit including a third resistor and a fourth resistor provided in series between the second terminal of the first resistor and the second terminal of the second resistor;
A load balancer including a fifth resistor having a second voltage applied to the first terminal and the second terminal connected to the second terminal of the second resistor;
A comparator that compares the potential at the connection point of the third and fourth resistors with a predetermined first threshold voltage;
A driver / comparator circuit comprising: 2. The resistance value Ra ′ of the first and second resistors, the resistance value Rb of the third and fourth resistors, and the resistance value Ra of the fifth resistor satisfy the following formula (1). Driver / comparator circuit.

  3. The driver according to claim 1, wherein the first voltage and the second voltage are equal, and the first terminals of the first, second, and third resistors each receive a voltage from a common voltage source.・ Comparator circuit.   4. The driver / comparator circuit according to claim 1, wherein the second voltage is a substantially average value of voltages output from the communication partner device. 5.   The first terminal is connected to a connection point of the third and fourth resistors, and the second terminal further includes a sixth resistor to which a predetermined third voltage is applied. Driver / comparator circuit described. The resistance value Ra ′ of the first and second resistors, the resistance value Rb of the third and fourth resistors, the resistance value Ra of the fifth resistor, and the resistance value Rc of the sixth resistor satisfy the following formula (2). The driver / comparator circuit according to claim 5.

At least one of the first, second, and third resistors is:
2. The driver / comparator circuit according to claim 1, wherein each output terminal is replaced with a Thevenin termination circuit connected in common and an R-2R termination circuit including an R-2R type resistor network. A test apparatus that bi-directionally transmits a signal to and from a device under test via a transmission line and inspects the device under test,
A test apparatus comprising the driver / comparator circuit according to claim 1, wherein the device under test is a communication partner.

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