JP2010258234A - Layout design method, layout design program, layout design apparatus - Google Patents

Abstract

A semiconductor integrated circuit having a plurality of power supply systems in an internal circuit region can generate a layout having a small chip area.
A power supply line for a first power supply is generated in an internal region. An arrangement of each of the plurality of primitive cells is generated so as to be connected to the power supply line. It is confirmed whether or not the timing of the signal supplied from the power supply line of the first power supply to each of the plurality of primitive cells satisfies a predetermined standard. After confirming that the predetermined standard is satisfied, the second power source generates the second potential instead of the first potential supplied by the first power source for at least one power source separation target cell among the plurality of primitive cells. Wiring is performed to supply two potentials.
[Selection] Figure 13

Description

  The present invention relates to a layout design of a semiconductor integrated circuit. The present invention particularly relates to a layout design of a semiconductor integrated circuit having a plurality of power supply systems.

  In semiconductor integrated circuits, power supply noise such as fluctuations in power supply voltage is generated by the operation of the constituent elements. Due to power supply noise, jitter that is a delay variation amount of a signal is generated. In recent years, semiconductor integrated circuits have been increased in speed and voltage, and an increase in jitter cannot be ignored.

  Normally, a semiconductor integrated circuit has a plurality of power supply systems that supply power to an internal circuit area and an input / output buffer circuit area, respectively. Furthermore, a semiconductor integrated circuit having a plurality of power sources in an internal circuit area is known. By preparing a plurality of systems of power supplies in the internal circuit area, it is possible to reduce power supply noise and consequently suppress an increase in jitter.

  However, in the layout design of a semiconductor integrated circuit having a plurality of power supply systems in the internal circuit area, it is necessary to secure an element arrangement possible area for each power supply system. Furthermore, it is necessary to design a layout in consideration of the power supply wiring and the timing between elements as the speed and voltage are reduced. Due to these factors, an increase in circuit area is inevitable. Therefore, in a layout design method for a semiconductor integrated circuit having a plurality of power supply systems in the internal circuit region, a technique for realizing power supply separation that suppresses an increase in area is required.

  FIG. 1 shows a flowchart of a layout design method in Patent Document 1. Referring to FIG. 1, the layout design method includes a step of identifying a power supply system, a step of performing a floor plan for each power supply system, a step of wiring a power supply line for supplying power to a primitive cell, A step of arranging primitive cells with respect to the net name of the power supply line, and a step of wiring between the primitive cells. As described above, a known method is used for wiring the power supply line to supply power to the primitive cell.

  A power line wiring process (step A5 in FIG. 1) for supplying power to the primitive cells is performed between the floor plan process and the primitive cell placement process. In the primitive cell placement step, the cell is placed by searching for an area where the wiring name added to the power supply line matches the power supply information of the primitive cell (step A6-A9 in FIG. 1). By arranging in this way, power supply separation is realized.

  In the following, the operation of an embodiment in which the prior art is applied to a circuit having two power sources, VDD1 and VDD2, will be described in detail with reference to the flowchart of FIG. First, in a semiconductor integrated circuit composed of a plurality of power supplies, as shown in FIG. 3, the VDD1 system circuit and the VDD2 system circuit are classified by power supply system (step A1 in FIG. 1).

  Next, in step A4 in FIG. 1, an arrangement region is designated for each power supply system classified in step A1. As shown in FIG. 5, the arrangement areas are designated so that different arrangement areas overlap each other in order to increase the degree of freedom of wiring in power line wiring (step A5) described later. In the example shown in FIG. 5, the primitive cells 121 and 122 shown in FIG. 4 are arranged on the arrangement area 123 side on one power supply system side, and the arrangement area 124 and the arrangement area 123 on another power supply system side are Some overlap each other.

  Next, the power supply line is wired (step A5 in FIG. 1). As shown in FIG. 2, power supply lines 107 and 108 for supplying power to the power supply terminals 103 and 104 of the primitive cell 101 and power supply terminals 105 and 106 of the primitive cell 102 are wired. The wiring of the power supply line is performed based on the floor plan specified in step A4. As shown in FIG. 6, the power supply line is divided by using a vertical path or the like.

  Next, the primitive cell placement process will be described. Based on the circuit connection information, an area where the wiring name of the power supply line wired in step A5 matches the power supply information of the primitive cell is searched, and the arrangement area of the primitive cell is determined (steps A6 to A6 in FIG. 1). A9).

  The arrangement process will be described by taking as an example the case where the power supply terminal of the primitive cell is used as the power supply information of the primitive cell. As shown in FIG. 6, when arranging the primitive cell 134 having the VDD1 terminal 135 and the GND terminal 136, the terminal name of each power supply terminal included in the primitive cell 134 based on the circuit information, and step A5. A region where the line names of the power supply lines wired in (1) match is searched (step A6 in FIG. 1).

  Next, in step A7 in FIG. 1, it is confirmed whether the power supply line name and the power supply terminal name of the primitive cell coincide with the primitive cell arrangement position determined by the search. As a result of the confirmation, as shown in FIG. 7, when the power terminal 142 of VDD1 included in the primitive cell 141 is arranged on the power supply line 144 of VDD2, the arrangement position of the primitive cell 141 is re-searched. (Return to step A6).

  Further, as shown in FIG. 8, when the power terminals 152 and 153 included in the primitive cell 151 are disposed on the power lines 156 and 155, respectively, and the power systems match, the arrangement position is determined. (Step A8 in FIG. 1), the next step is executed. In the next step A9, the presence / absence of unplaced cells is confirmed, and steps A6 to A9 are repeated until there are no unplaced cells. After the arrangement of all the cells is completed, a wiring plan is made based on the circuit connection information as a schematic wiring (step A10 in FIG. 1).

  In step A11 in FIG. 1, it is determined whether or not wiring is possible based on the result of the schematic wiring (step A10). If it is determined that wiring is impossible, the return destination of the flow differs depending on the situation described below. As a first situation, when the wiring for the entire chip is strict and a fundamental review of the chip size is necessary, the return destination is step A2, and the chip size is adjusted. As a second situation, as shown in FIG. 9, when the wiring 161 is strict in the region 161 where the power source is separated or in the vicinity thereof, and it is necessary to review the expansion of the region, the return destination is shown in FIG. 1 step A5, and the wiring of the power supply line is adjusted. FIG. 10 shows an example of the result of arranging the primitive cells by adjusting the wiring of the power supply line VDD2 in FIG. If it is determined in step A11 in FIG. 1 that wiring is possible, the final detailed wiring is performed to complete the layout. By the above method, the power supply separation of the semiconductor integrated circuit constituted by a plurality of power supplies is realized.

  Patent Document 2 is an example of a power supply separation layout design method. This document describes a technique for performing power source separation in a semiconductor integrated circuit having power source wiring layers as many as the number of power source systems, unlike the above power source separation in the same wiring layer.

JP-A-11-297844 JP 2006-278404 A

  In the technique of Patent Document 1, the primitive cell arrangement area is specified in step A4 which is the floor plan process of FIG. Therefore, when performing power source separation of a semiconductor integrated circuit having a plurality of power source systems in the internal circuit region, it is necessary to secure a primitive cell arrangement region for each power source system in the floor plan process. In such a layout design method, there is a problem that the arrangement area is enlarged because an arrangement area having a margin is required in addition to the arrangement area necessary for the function of the circuit. A mechanism for causing this problem will be described below with reference to FIGS. 11 and 12.

  FIG. 11 is a schematic diagram of a layout design in which power supply separation is performed in a semiconductor integrated circuit having two power supply systems of a first potential and a second potential in an internal circuit. As an example, a clock is distributed from the clock supply block 165 to the memory interface control blocks 163 and 164, and a signal from the outside of the chip is input from the signal input terminal 166 to the RAM 176 arranged in the chip arrangement area 167.

  In FIG. 11, a first potential generated by a first power source that is a main power source of the chip is supplied to the chip arrangement region 167. The memory interface control blocks 163 and 164 and the clock supply block 165 are connected to a second power source for generating a second potential as a dedicated power source. The primitive cell area 162 is separated from the chip placement area 167 by the power source. In the primitive cell area 162, primitive cells 168, 169, and 170 for relaying in consideration of waveform blunting when the clock is distributed from the clock supply block 165 to the memory interface control blocks 163 and 164 are arranged. A potential is supplied. When an external signal from the signal input terminal 166 is input to the RAM 176, the first potential is supplied to the RAM 176. For this reason, the primitive cells 171, 172, and 173 for relay in consideration of the waveform dullness are arranged in the chip arrangement area 167.

  FIG. 12 is an enlarged view showing details of power source separation of the primitive cell region 162 in the schematic diagram of FIG. The primitive cell region 162 to which the second potential is supplied is separated from the chip arrangement region 167 to which the first potential is supplied.

  A second potential is supplied to the primitive cell arrangement region 162 from a power supply line in which an upper power supply line 175a and a lower power supply line 175b of the second potential are arranged in a grid pattern. The first potential is supplied to the chip placement region 167 through a power supply line in which an upper power supply line 174a and a lower power supply line 174b of the first potential are arranged in a grid pattern. In the primitive cell arrangement area 162, primitive cells 168, 169, and 170 having the second potential are arranged. In the chip placement region 167, primitive cells 171, 172, 173 having the first potential are placed.

  In this technique, the chip placement area 167 in which the first potential primitive cells 171, 172, 173 can be placed and the primitive cell area 162 in which the second potential primitive cells 168, 169, 170 can be placed in FIG. 1 is determined in step A4 of the floor plan process of FIG. In step A5 of the power supply / GND wiring process, power supply wiring of the first potential power supply lines 174a and 174b and the second potential power supply lines 175a and 175b is performed in the primitive cell region 162 and the chip placement region 167, respectively. .

  By the way, there is a case where a primitive cell is added or a primitive cell size is changed in order to correct a circuit or adjust timing after the detailed wiring process. When the arrangement of the primitive cell area 162 is determined in the floor plan process, it is necessary to secure the primitive cell area 162 so as to have a margin for such addition or change.

  The reason is as follows. After the detailed wiring process step A12 in FIG. 1, it is necessary to change the additional primitive cell and the primitive cell size by circuit correction, timing adjustment, and the like. As a result, the additional primitive cell and the primitive are added in the primitive cell area 162.・ Change in cell size may not be achieved. In such a case, the process goes back to step A4 of the floor plan process, which causes a redesign.

  At the stage of the floor plan process, it is uncertain whether primitive cells will be added or modified after the detailed wiring process. However, in order to avoid redoing the design, it is necessary to predict the addition or modification of primitive cells at the stage of the floor plan process, and to secure the primitive cell arrangement area including those margins. For example, as shown in FIG. 12, in the primitive cell arrangement area 162, it is necessary to predict and secure how many primitive cells are added in addition to the three cells of the primitive cells 168, 169, and 170. . Therefore, in such a layout design method, there arises a problem that the arrangement area of the primitive cells subject to power source separation is enlarged.

  Hereinafter, means for solving the problem will be described using the numbers used in [DETAILED DESCRIPTION] in parentheses. These numbers are added to clarify the correspondence between the description of [Claims] and [Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

  A layout design method according to an aspect of the present invention includes a step (S4) of generating a wiring of a power supply line of a first power source in an internal region layout, and a plurality of primitive cells (6, 6) connected to the power supply line. 7, 8, 9, 10, 11) (S 5 to S 9) and the timing of signals supplied from the power supply line of the first power source to each of the plurality of primitive cells is a predetermined reference. A step (S10) for confirming whether or not the predetermined condition is satisfied, and after confirming that the predetermined standard is satisfied, for at least one power source separation target cell (6, 7, 8) among the plurality of primitive cells And a wiring step (S11) for supplying a second potential generated by the second power source instead of the first potential supplied by the first power source.

  A layout design program according to an aspect of the present invention causes a computer to execute each process included in a layout design method according to an aspect of the present invention.

  A layout design apparatus (40) according to an aspect of the present invention includes a wiring unit (41) that generates a power supply line of a first power source in a layout of an internal region, and a plurality of primitives connected to the power supply line. A primitive cell generation unit (42) for generating each arrangement of the cells (6, 7, 8, 9, 10, 11), and a signal supplied to each of the plurality of primitive cells from the power supply line of the first power supply. A timing confirmation unit (43) for confirming whether or not the timing satisfies a predetermined criterion, and at least one power source separation target cell (6) among a plurality of primitive cells after confirming that the predetermined criterion is satisfied. , 7, 8), a potential switching unit (44) wired to supply a second potential generated by the second power source instead of the first potential supplied by the first power source.

  According to the present invention, a layout having a small chip area can be generated for a semiconductor integrated circuit having a plurality of power supply systems in the internal circuit region.

FIG. 1 is a flowchart of a layout design method of the background art. FIG. 2 is a layout diagram for explaining the background art. FIG. 3 is a layout diagram for explaining the background art. FIG. 4 is a layout diagram for explaining the background art. FIG. 5 is a layout diagram for explaining the background art. FIG. 6 is a layout diagram for explaining the background art. FIG. 7 is a layout diagram for explaining the background art. FIG. 8 is a layout diagram for explaining the background art. FIG. 9 is a layout diagram for explaining the background art. FIG. 10 is a layout diagram for explaining the background art. FIG. 11 is a layout diagram for explaining the background art. FIG. 12 is a layout diagram for explaining the background art. FIG. 13 is a flowchart of a layout design method for a semiconductor integrated circuit according to the embodiment. FIG. 14 is a layout diagram for explaining an embodiment of the present invention. FIG. 15 is a layout diagram for explaining an embodiment of the present invention. FIG. 16 is a system configuration diagram for carrying out the present invention. FIG. 17 is a layout diagram for explaining an embodiment of the present invention. FIG. 18 is a layout diagram for explaining an embodiment of the present invention. FIG. 19 is a layout diagram for explaining an embodiment of the present invention. FIG. 20 is a detailed flowchart of a potential switching step in one embodiment of the present invention. FIG. 21 is a layout diagram for explaining an embodiment of the present invention. FIG. 22 is a block diagram of a layout design apparatus according to an embodiment of the present invention.

  An embodiment of the present invention will be described with reference to FIG. FIG. 16 is a system configuration diagram for implementing the layout design method according to the present embodiment. This system includes a computer device 16, a server 17, and a network 19. The server 17 includes a storage medium 18. The storage medium 18 stores an execution program for causing a computer to execute the layout design method. The server 17 is connected to a computer device 16 such as an engineering workstation via a network 19 such as the Internet. The execution program stored in the recording medium 18 is downloaded to the computer device 16 via the network 19. The downloaded program is stored in a local hard disk or memory of the computer device 16 and executed by the computer device 16.

  The operation of this embodiment will be described with reference to FIGS. 13, 14, and 15. FIG. 13 is a flowchart of the layout design method of the semiconductor integrated circuit according to the present embodiment. A procedure for power source separation in a semiconductor integrated circuit having a plurality of power source systems in an internal circuit is shown.

  FIG. 14 is a schematic diagram of a layout design in which power supply separation is performed for a semiconductor integrated circuit having two power supply systems of a first potential and a second potential in an internal circuit using the flowchart of FIG. 13 of the present embodiment. In this example, a clock signal is distributed from the clock supply block 3 to the memory interface blocks 1 and 2, and a signal from the outside of the chip may be input to the RAM 31 arranged in the chip arrangement area 5 via the signal input terminal 4. It is shown.

  In FIG. 14, the chip placement region 5 is supplied with a first potential which is the main power source of the chip. A second potential is supplied to the memory interface control blocks 1 and 2 and the clock supply block 3 as a dedicated power source. The relay primitive cells 6, 7, 8 are arranged in the chip arrangement area 5 in consideration of waveform dullness when the clock is distributed from the clock supply block 3 to the memory interface control blocks 1, 2. The primitive cells 6, 7, and 8 are separated from the main power supply and supplied with the second potential. In consideration of waveform dullness when an external signal from the signal input terminal 4 is input to the RAM 31, the relay primitive cells 9, 10, 11 are arranged in the chip arrangement area 5. A first potential is supplied to the primitive cells 9, 10, 11.

  FIG. 15 is a diagram showing details of power source separation in the schematic diagram of FIG. Primitive cells 9, 10 and 11 to which the first potential is supplied are arranged in the chip arrangement region 5 to which the first potential is supplied. The primitive cells 6, 7, and 8 to which the second potential is supplied are separated from the power source and placed in the chip placement region 5. The primitive cells 9, 10, and 11 are supplied with a first potential by a power supply line in which an upper layer power supply line 15 a and a lower layer power supply line 15 b are wired in a grid pattern. The second potential is supplied to the primitive cells 6, 7, and 8 through the power supply lines 12, 13, and 14.

  The person in charge of design downloads an execution program from the server 17 to the computer device 16 shown in FIG. 16 and starts layout design. Hereinafter, all the processing steps to be described are steps performed by the computer device 16, and data input to the processing steps, output data, and the like are exchanged with the storage medium 18.

  Next, in step S1, each part of the semiconductor integrated circuit driven by a plurality of power supplies is classified by power supply system. For example, as shown in FIG. 17, the first potential circuit group 20 and the second potential circuit group 21, which are the main power sources of the chip, are classified by power supply system. FIG. 17 shows a classification result of the semiconductor integrated circuit in the schematic diagram of FIG. This semiconductor integrated circuit has two types of power supply systems of a first potential and a second potential. Primitive cells 9, 10, and 11 belong to the first potential, and primitive cells 6, 7, and 8 belong to the second potential.

  Next, as a floor plan process, a chip size is estimated in step S2, and a hard macro such as a memory block such as a RAM or a functional block is arranged in step S3.

  In step S4, power supply lines are wired, and in step S5, all primitive cells on the chip are arranged. The execution results of step S4 and step S5 are shown in FIG. FIG. 18 shows that the primitive cells 6, 7, 8, 9, 10, and 11 arranged in step S5 are arranged on the power supply lines 15a and 15b wired in step S4. In step S4, only a single power source for driving the first potential circuit group 20 supplies power without separating the first potential circuit group 20 and the second potential circuit group 21 shown in FIG. Wiring the power supply line as a thing. In step S5, arrangement is performed without restricting the arrangement location depending on which power source system the primitive cells 6, 7, 8, 9, 10, and 11 belong to.

  FIG. 19 shows the details of the power supply line to the primitive cell 8 of FIG. 18 wired as a single power source in step S4. The primitive cell 8 belongs to the circuit group of the second potential in FIG. 17, but is wired so that the first potential is supplied at this stage of the design. Specifically, the first potential is supplied from the power supply line 15a to the primitive cell 8 through the through hole 25 and the power supply line 15b. The primitive cell 8 is further supplied with a GND potential by a GND supply line 22.

  Next, in step S6, it is confirmed whether there are any unplaced primitive cells on the chip. Steps S5 to S6 are repeated until the arrangement of all primitive cells is completed. When the arrangement of all the primitive cells is completed, rough wiring is performed in step S7. In step S8, it is determined whether or not detailed wiring is possible based on the result of rough wiring. If it is determined that wiring is possible, detailed wiring is performed in step S9. If it is determined that detailed wiring is not possible, the process returns to the chip size estimating step S2 to readjust the chip size.

  Next, in step S10, a timing check for determining whether or not the timing of the signal supplied to each primitive cell satisfies a predetermined standard is performed. If it is determined that there is no problem in timing, the process proceeds to a wiring process (hereinafter referred to as “potential replacement”) for supplying power from the corresponding power source to the primitive cell to be separated in step S11. If it is determined that there is a problem in timing and rewiring is necessary, the process returns to step S7 in the loop A, and rough wiring is performed again. If it is determined that there is a problem in timing and the program does not require a fundamental review of the chip size but circuit correction or primitive cell addition / change is necessary, the process returns to step S5 in the loop B. , Rearrange. If it is determined that there is a problem in timing and it is automatically determined that a fundamental review of the chip size is necessary according to the predetermined procedure described in the program, the chip size estimating step S2 in the loop C Return to, and readjust the chip size.

  Next, in step S11, the potential is switched. FIG. 20 shows a detailed flowchart of step S11 which is a potential switching step. First, in step S12, potential recognition is performed. In step S12, the potential supplied after the power source separation to the primitive cell as the power source separation target is recognized by referring to the net list inputted in advance. For example, in FIG. 19, the primitive cell 8 to which the second potential is supplied after the power source separation is recognized.

  Next, in step S13, an upper connection layer is selected. In step S12, a power supply wiring for supplying power after power source separation to the primitive cell to be power source separated is recognized. This recognition is performed based on data indicating the arrangement positions of the primitive cells and the power supply wiring generated in advance up to this step. Here, the recognition and selection of the power supply wiring is performed from the power supply wiring in the lowest layer for supplying power to the primitive cells to be separated from the power supply wiring to the uppermost power supply wiring in order. For example, in FIG. 19, as the wiring for supplying power to the primitive cell 8, first, the lowermost power supply line 15 b connected to the primitive cell 8 is recognized and selected. Next, the uppermost power supply line 15a connected via the through hole 25 is recognized and selected. Here, FIG. 19 shows an example in which there are two wiring layers. Similarly, in the case of two or more layers, the layers are similarly recognized and selected from the bottom layer to the top layer.

  Next, in step S14, the power supply wiring selected in step S13 is cut. In step S15, through-hole deletion is performed so that the potential supplied after power source separation to the power source wiring cut in step S14 and the potential supplied before power source separation are not short-circuited.

  FIG. 21 is a diagram showing a result of performing the steps S14 and S15 on the primitive cell 8 shown in FIG. The power supply lines 14, 26, 28, and 29 cut in step S14 and the through hole 27 deleted in step S15 are shown.

  In step S14, the lowermost power supply line 15b of FIG. 19 selected in step S13 is cut at the boundary portion of the primitive cell 8 and divided into power supply lines 28, 29, and 30. Further, in order to connect one end of the power supply line 15a in the uppermost layer of FIG. 19 to the second potential after the power source separation, one end side not connected to the second potential after the power source separation is cut at the boundary portion of the primitive cell 8 It is divided into a supply line 14 and a power supply line 26.

  In step S15, the power supply line 14 is separated from the main power supply by removing the through hole 27 that connects the power supply line 14 divided in step S14 and the power supply line of the main power supply.

  Next, in step S16, power supply source connection is performed. In step S16, a second power source for generating a second potential is connected to the power supply line 14 of FIG. As a result, the second potential is supplied from the power supply line 14 through the through hole 25 to the primitive cell 8 from the power supply line 28.

  As described above, upon completion of step S16, the potential replacement in step S11 of FIG. 13 is completed, and the procedure of power supply separation is completed.

  In the layout design method of the present embodiment, power supply separation is performed for a semiconductor integrated circuit having a plurality of power supply systems in the internal region. When there is no problem in timing, there is a step of wiring a power supply line with the internal region as a single power source (step S4), a step of arranging and wiring all primitive cells, a step of checking timing, and a timing. A step (step S11) of supplying a potential from another power source to a primitive cell having a power system different from the power source wired as one power source is performed.

  In the above process, power supply wiring is performed using a plurality of power supplies as a single power supply in step S4 which is a single power supply / GND wiring process. Therefore, it is not necessary to secure a primitive cell arrangement area for each power supply system. Further, the arrangement, wiring, and timing of all primitive cells are checked with a single power source, and potential adjustment is performed after repeated timing adjustment until there is no problem in timing. After confirming that there is no problem in timing, the potentials of the primitive cells subject to power source separation are exchanged. Therefore, the primitive cell arrangement subject to power source separation is performed as in the technique illustrated with reference to FIGS. It is no longer necessary to secure an extra area to accommodate additional primitive cell placement such as circuit correction or timing adjustment that occurs after the detailed wiring process for the area, and the problem that the placement area is expanded can be solved. .

  The first effect obtained by this embodiment is that the chip area can be reduced. The reason is as follows. By switching the potential after the primitive cells are arranged, a different potential can be supplied only to the primitive cells of different power supply systems. Therefore, it is not necessary to secure a primitive cell area to cope with additional primitive cell arrangement such as circuit correction and timing adjustment generated after the detailed wiring process, and solves the problem of the prior art that the arrangement area is expanded. I can do it.

  The second effect is that the design period can be shortened. The reason is as follows. By performing the potential replacement step after the placement and wiring, the influence on the wiring property due to the power source separation is eliminated. Therefore, unlike the techniques described with reference to FIGS. 11 and 12, the region where the potential is switched does not have a sufficient region for wiring, and a reverse flow that requires a region review is unnecessary.

  The third effect is that the speed can be increased as compared with the prior art. The reason is as follows. By performing the single power supply / GND wiring process (step S4) and the potential switching process (step S11), it is not necessary to secure primitive cell regions of circuit groups having different power supply systems. Therefore, it is not necessary to arrange the primitive cells of the circuit group supplied with the main power of the chip so as to bypass the primitive cell regions having different power supply systems. As a result, the delay between primitive cells can be shortened.

  FIG. 22 shows a layout design apparatus for executing the layout design method in the present embodiment. The layout design device 40 includes a single power supply wiring unit 41, a primitive cell generation unit 42, a timing confirmation unit 43, and a potential switching unit 44. Each of these units is a functional block realized by a CPU of a computer such as a personal computer reading a program stored in a storage device and performing data processing according to the description of the program.

  The single power supply wiring unit 41 executes wiring by a single power supply in step S4 of FIG. 13 based on the net list input in advance. The primitive cell generation unit 42 performs the operations of Steps S5 to S9 to arrange and wire the primitive cells so as to be connected to a single power supply line. The timing confirmation unit 43 performs the operation of step S10 to confirm timing. The potential switching unit 44 performs the potential switching operation in step S11.

  The potential switching unit 44 includes a potential recognition unit 45, a power source separation wiring recognition unit 46, a cutting unit 47, a deletion unit 48, and a connection unit 49. The potential recognition unit 45 performs the potential recognition operation in step S12. The power separation wiring recognition unit 46 recognizes the power separation power wiring used for supplying the second potential to the power separation target cell after the power separation among the wirings generated by the single power wiring part 41. Thus, the upper connection layer selection in step S13 is executed. The cutting unit 47 performs an operation of cutting the power supply wiring in step S14. The deletion unit 48 executes the operation of step S15 by deleting a through hole that supplies a potential other than the second potential such as the first potential generated by the main power source to each of the power source separation target cells after the disconnection. . The connection unit 49 executes the operation of step S16. With the above operation, the layout design apparatus can execute the layout design method according to the present embodiment.

DESCRIPTION OF SYMBOLS 1 Memory interface control block 2 Memory interface control block 3 Clock supply block 4 Signal input terminal 5 Chip arrangement | positioning area | region 6 Primitive cell 7 Primitive cell 8 Primitive cell 9 Primitive cell 10 Primitive cell 11 Primitive cell 12 Power supply line 13 power supply line 14 power supply line 15a power supply line 15b power supply line 16 computer device 17 server 18 recording medium 19 network 20 circuit group 21 circuit group 22 GND supply line 25 through hole 26 power supply line 27 through hole 28 power supply line 29 Power supply line 30 Power supply line 31 RAM
40 Layout design device 41 Single power supply wiring part 42 Primitive cell generation part 43 Timing confirmation part 44 Potential switching part 45 Potential recognition part 46 Power supply separation power line recognition part 47 Cutting part 48 Deletion part 49 Connection part 101 Primitive cell 102 Primitive Cell 103 Power supply terminal 104 Power supply terminal 105 Power supply terminal 106 Power supply terminal 107 Power supply line 108 Power supply line 121 Primitive cell 122 Primitive cell 123 Arrangement area 124 Arrangement area 134 Primitive cell 135 VDD1 terminal 136 GND terminal 141 GND cell 141 Primitive cell 142 VDD1 Power supply terminal 144 Power supply line 151 Primitive cell 152 Power supply terminal 153 Power supply terminal 155 Power supply line 156 Power supply line 161 Power supply isolation region 162 Primitive cell region 1 3 Memory interface control block 164 Memory interface control block 165 Clock supply block 166 Signal input terminal 167 Chip placement area 168 Primitive cell 169 Primitive cell 170 Primitive cell 171 Primitive cell 172 Primitive cell 173 Primitive cell 174a Power supply line 174b Power supply line 175a Power supply line 175b Power supply line 176 RAM

Claims (6)

Generating a wiring of the power supply line of the first power source in the layout of the internal region;
Generating an arrangement of each of a plurality of primitive cells to be connected to the power supply line;
Confirming whether or not the timing of a signal supplied to each of the plurality of primitive cells from the power supply line of the first power supply satisfies a predetermined standard;
After confirming that the predetermined criterion is satisfied, a second power source is generated instead of the first potential supplied by the first power source for at least one of the plurality of primitive cells. And a wiring design process for supplying a second potential. A layout design method according to claim 1,
Wiring for supplying the second potential comprises:
Recognizing a potential supplied to each of the at least one power source separation target cell;
A power supply wiring for power separation used for supplying the second potential to each of the at least one power source separation target cell among the power supply lines of the first power source generated in the step of generating the wiring. The process of recognizing;
Cutting the power separation power supply wiring between the first power source and each of the at least one power source separation cell;
After the cutting step, removing a through hole that supplies a potential other than the second potential to each of the at least one power source separation target cell;
A step of connecting the second power source to the power source wiring for power source separation. Generating a wiring of the power supply line of the first power source in the internal region;
Generating an arrangement of each of a plurality of primitive cells to be connected to the power supply line;
Confirming whether or not the timing of a signal supplied to each of the plurality of primitive cells from the power supply line of the first power supply satisfies a predetermined standard;
After confirming that the predetermined criterion is satisfied, a second power source is generated instead of the first potential supplied by the first power source for at least one of the plurality of primitive cells. A layout design program for causing a computer to execute a wiring process for supplying a second potential. A layout design program according to claim 3,
Wiring for supplying the second potential comprises:
Recognizing a potential supplied to each of the at least one power source separation target cell;
A power supply wiring for power separation used for supplying the second potential to each of the at least one power source separation target cell among the power supply lines of the first power source generated in the step of generating the wiring. The process of recognizing;
Cutting the power source separation wiring between the first power source and each of the at least one power source separation cell;
After the cutting step, removing a through hole that supplies a potential other than the second potential to each of the at least one power source separation target cell;
And a step of connecting the second power source to the power source separation wiring. A single power supply wiring section for generating a wiring of the power supply line of the first power supply in the layout of the internal region;
A primitive cell generation unit that generates an arrangement of each of a plurality of primitive cells to be connected to the power supply line;
A timing confirmation unit for confirming whether a timing of a signal supplied from the power supply line of the first power source to each of the plurality of primitive cells satisfies a predetermined criterion;
After confirming that the predetermined criterion is satisfied, a second power source is generated instead of the first potential supplied by the first power source for at least one of the plurality of primitive cells. A layout design apparatus comprising: a potential switching unit that performs wiring to supply a second potential. The layout design apparatus according to claim 5,
The potential switching unit includes:
A potential recognition unit for recognizing a potential supplied to each of the at least one power source separation target cell;
A power supply wiring for power separation used for supplying the second potential to each of the at least one power source separation target cell among the power supply lines of the first power source generated in the step of generating the wiring. A power supply wiring recognition unit for power supply separation to be recognized;
A cutting unit for cutting the power source wiring for power separation between the first power source and each of the at least one power source separation target cells;
A deletion unit that deletes a through hole that supplies a potential other than the second potential to each of the at least one power source separation target cell after the cutting step;
A layout design apparatus comprising: a connecting portion that connects the second power source to the power source wiring for power source separation.

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