JP2010258105A - Manufacturing control apparatus and manufacturing control method - Google Patents

Abstract

Disclosed is a manufacturing control device and a manufacturing control method capable of reducing variations in transistor characteristics by suppressing variations in film thickness.
A manufacturing control apparatus (20) for calculating a control parameter (deposition time t _target ) for controlling a film forming apparatus (30) for depositing an insulating film on a first semiconductor wafer, the second wafer surface area of a second semiconductor wafer. As L ₁ increases, a control parameter (deposition time t _target ) for depositing the insulating film thicker on the film forming apparatus 30 is calculated. The manufacturing control device 20 may comprise a second deposition time calculation unit 116 as the deposition time is larger wafer surface area L ₁ t _target to calculate the deposition time t _target to be longer.
[Selection] Figure 6

Description

  The present invention relates to a manufacturing control apparatus and a manufacturing control method, and more particularly to a manufacturing control apparatus that calculates a control parameter for controlling a film forming apparatus for depositing an insulating film on a semiconductor wafer.

  In recent years, the gate length of MIS transistors has been miniaturized in order to realize the demand for higher integration of MIS (Metal Insulator Semiconductor) type semiconductor devices. In such a miniaturized MIS transistor, an extension region is formed using low energy ion implantation in order to form a shallow junction in the surface region of the silicon substrate. This extension region is formed under the end of the gate electrode as a part of the source / drain region (see, for example, Patent Document 1).

  31A to 31D and FIGS. 32A to 32C are cross-sectional views showing the manufacturing process of a conventional semiconductor device.

First, in a step shown in FIG. 31A, on a silicon substrate 301, an element isolation insulating film 304 of trench partitioning the nMIS transistor forming region R _TN and pMIS transistor forming region R _TP. Thereafter, a gate insulating film 302 made of, for example, a silicon oxide film and a polysilicon film are sequentially formed on the entire surface of the silicon substrate 301. Thereafter, the polysilicon film is patterned using a dry etching method or the like, thereby forming the gate electrodes 303 of the nMIS transistor and the pMIS transistor.

Next, in a step shown in FIG. 31B, a sidewall insulating film 305 made of a silicon oxide film is deposited on the entire surface of the substrate by using a CVD (Chemical Vapor Deposition) method. As a result, the entire nMIS transistor formation region R _TN and pMIS transistor formation region R _TP including the respective gate electrodes 303 are covered with the sidewall insulating film 305.

Next, in the step shown in FIG. 31C, the sidewall insulating film 305 is selectively formed on the side surface of the gate electrode 303 by anisotropic dry etching the sidewall insulating film 305 using CF ₄ / O ₂ / Ar gas. Form. At this time, in the dry etching using CF ₄ / O ₂ / Ar gas, the etching rate for the deposition film generated by the dry etching is fast. For this reason, almost no deposition film is formed on the surface of the silicon substrate 301 in the source / drain formation region, and the surface of the silicon substrate 301 is exposed.

Next, in a step shown in FIG. 31D, it has an opening on the nMIS transistor forming region R _TN, and a resist mask 307 covering the pMIS transistor forming the upper region R _TP.

Thereafter, using the gate electrode 303, the sidewall insulating film 306, and the resist mask 307 as a mask, arsenic (As +) ions 308, which are n-type impurities, are implanted at an energy of about 5 keV and a dose of 5 × 10 ^{14 to} 5 × 10. Ion implantation is performed under the condition of ¹⁵ / cm ² . This forms n-type extension regions 309 in the nMIS transistor forming region R _TN.

Next, in the step shown in FIG. 32A, the resist mask 307 is removed. Next, in a step shown in FIG. 32B, having a window on pMIS transistor forming region R _TP, a resist mask 310 covering the nMIS transistor forming region R _TN.

Thereafter, using the gate electrode 303, the sidewall insulating film 306, and the resist mask 310 as a mask, boron (B +) ions 311 that are p-type impurities are implanted at an energy of about 1 keV and a dose amount of 8 × 10 ^{13 to} 6 × 10. Ion implantation is performed under the condition of ¹⁴ / cm ² . This forms a p-type extension regions 312 in the pMIS transistor forming region R _TP.

  Next, in the step shown in FIG. 32C, the resist mask 310 is removed.

  In the above-described transistor, the implantation region is controlled by the sidewall insulating film 306 formed from the sidewall insulating film 305 formed mainly by using the CVD method shown in FIG. 31B. That is, when the thickness of the sidewall insulating film 305 varies, the thickness of the sidewall insulating film 306 varies. Therefore, as the miniaturization of the transistor progresses, the so-called short channel effect, in which the transistor characteristic variation due to the variation in the film thickness of the sidewall insulating film 306 increases, becomes a problem.

  From such a background, the importance of film thickness control in forming the sidewall insulating film 305 using the CVD method is very high. For example, in the LP-CVD (Low Pressure CVD) method, for the purpose of reducing the input monitor wafer and improving the accuracy, a recipe is created for each number of pieces put into the furnace, and the optimum number of pieces put into the furnace at the time of product processing is created. A technique for selecting a recipe has been studied (see, for example, Patent Document 2).

  Hereinafter, the technique described in Patent Document 2 will be described.

  FIG. 33 is a flowchart showing the flow of processing in the production control apparatus described in Patent Document 2.

  As shown in FIG. 33, first, the conventional manufacturing control apparatus reads the number of wafers W (S100). Next, the conventional manufacturing control apparatus reads a recipe having the smallest batch size BS from among a plurality of recipes of the determined processing types (S102). Next, the conventional manufacturing control apparatus determines whether or not the number of wafers W is smaller than the batch size BS (S104). If the number of wafers W is larger than the batch size BS (No in S104), the conventional manufacturing control apparatus reads the recipe of the next smallest batch size BS (S106), and performs the determination in step S104 again.

  On the other hand, if the number of wafers W is smaller than the batch size BS (Yes in S104), the conventional manufacturing control apparatus determines the current batch size as the final batch size (S108), and the selected processing recipe Is output (S110).

  As described above, the technique of Patent Document 2 has the same result as the case where the wafer is accommodated in all the supports, even if the wafer is accommodated in all the supports (boats) in the reaction chamber of the semiconductor manufacturing apparatus. Obtainable. In this case, it is presumed that the wafer is housed in all the supports and is in a stable state with the least variation.

Japanese Patent Laying-Open No. 2004-103899 (Section 8, FIG. 3, FIG. 4) Japanese Patent Laying-Open No. 2005-93747 (Section 13, FIG. 5, FIG. 6)

  However, the deposited film thickness of the insulating film varies depending on factors other than the number of wafers. In other words, the technique described in Patent Document 2 has a problem that the film thickness variation of the insulating film cannot be sufficiently suppressed.

  Therefore, an object of the present invention is to provide a manufacturing control apparatus and a manufacturing control method that can reduce variations in transistor characteristics by further suppressing film thickness fluctuation.

  In order to achieve the above object, a manufacturing control apparatus according to the present invention is a manufacturing control apparatus for calculating a control parameter for controlling a film forming apparatus for depositing an insulating film on a first semiconductor wafer, wherein the first semiconductor As the first surface area of the wafer is larger, the control parameter for depositing the insulating film thicker on the film forming apparatus is calculated.

  According to this configuration, the manufacturing control apparatus according to the present invention can suppress the variation in the deposited film thickness of the insulating film depending on the wafer surface area, so that the variation in transistor characteristics can be further reduced.

  The manufacturing control apparatus further includes a deposition time calculation unit that calculates a first deposition time for the deposition apparatus to deposit the insulating film on the first semiconductor wafer as the control parameter, and the deposition time calculation unit The first deposition time may be calculated such that the first deposition time increases as the first surface area increases.

  According to this configuration, the manufacturing control apparatus according to the present invention can calculate the first deposition time during which the variation of the deposited film thickness of the insulating film depending on the wafer surface area can be suppressed.

  In addition, the manufacturing control apparatus further acquires a target deposition thickness acquisition unit that acquires a target deposition thickness, and a deposition rate that is a thickness of the insulating film deposited per unit time by the deposition apparatus. And a film thickness that depends on the first surface area among the film thicknesses of the insulating film deposited by the film forming apparatus by multiplying the first surface area by a first coefficient. A first variable film thickness calculation unit that calculates one variable film thickness, and the deposition time calculation unit calculates a first estimated film thickness by adding the target deposition film thickness and the first variable film thickness Then, the first deposition time may be calculated by dividing the first estimated film thickness by the film formation rate.

  According to this configuration, the manufacturing control apparatus according to the present invention calculates the first variable film thickness of the insulating film depending on the wafer surface area, and can calculate the first deposition time using the first variable film thickness.

  The manufacturing control device further includes a second surface area acquisition unit that acquires a second surface area of the second semiconductor wafer, and a deposition time when an insulating film is deposited on the second semiconductor wafer by the film formation device. A processing time acquisition unit that acquires a certain processing time, and a measured film thickness that acquires a measured film thickness that is a thickness of the insulating film when the insulating film is deposited on the second semiconductor wafer by the film forming apparatus. An acquisition unit and a second variable film having a thickness depending on the second surface area of the insulating film deposited by the film forming apparatus by multiplying the second surface area by the first coefficient A second variable film thickness calculating unit for calculating a thickness; a second estimated film thickness is calculated by subtracting the second variable film thickness from the measured film thickness; and the calculated second estimated film thickness is used as the processing time. The film formation rate is calculated by dividing by A rate calculating unit, the film forming rate acquisition unit may acquire the deposition rate calculated by the deposition rate calculation unit.

  According to this configuration, the production control apparatus according to the present invention can reduce the variation between apparatuses by calculating the film formation rate from the film thickness of the insulating film formed by the same film formation apparatus.

  The deposition apparatus deposits the insulating film on a plurality of first semiconductor wafers including the first semiconductor wafer, and the plurality of first semiconductor wafers includes a plurality of types of wafers on which different patterns are formed. In addition, the surface area may be an average value of a maximum surface area and a minimum surface area among the surface areas of the plurality of types of wafers.

  The deposition apparatus deposits the insulating film on a plurality of first semiconductor wafers including the first semiconductor wafer, and the plurality of first semiconductor wafers includes a plurality of types of wafers on which different patterns are formed. And the total surface area may be a total surface area of the plurality of semiconductor wafers.

  According to this configuration, the manufacturing control apparatus according to the present invention can further suppress fluctuations in the deposited film thickness of the insulating film depending on the wafer surface area.

  Further, the semiconductor control device including the film forming apparatus manufactures a semiconductor device including a transistor on the first semiconductor wafer, and the semiconductor device manufacturing process by the semiconductor control device forms a gate electrode pattern of the transistor. A first step, and a second step in which the film deposition apparatus deposits the insulating film after the first step, and the first surface area is formed per unit area after the first step. It may be a ratio of the area of the gate electrode pattern.

  Further, the semiconductor control device including the film forming apparatus manufactures a semiconductor device including a transistor on the first semiconductor wafer, and the semiconductor device manufacturing process by the semiconductor control device forms a gate electrode pattern of the transistor. A first step and a second step in which the film deposition apparatus deposits the insulating film after the first step, and the first surface area is determined by the gate electrode pattern per unit area after the first step. The ratio of the area which is not formed may be sufficient.

  Further, the semiconductor control device including the film forming apparatus manufactures a semiconductor device including a transistor on the first semiconductor wafer, and the semiconductor device manufacturing process by the semiconductor control device forms a gate electrode pattern of the transistor. A first step, and a second step in which the film deposition apparatus deposits the insulating film after the first step, and the first surface area is formed per unit area after the first step. It may be the peripheral length of the gate electrode pattern.

  Further, the semiconductor control device including the film forming apparatus manufactures a semiconductor device including a transistor on the first semiconductor wafer, and the semiconductor device manufacturing process by the semiconductor control device forms a gate electrode pattern of the transistor. A first step and a second step in which the film deposition apparatus deposits the insulating film after the first step, and the first surface area is a peripheral length of the gate electrode pattern formed in the first step. May be the sum of

  The semiconductor control device including the film forming apparatus manufactures a semiconductor device including a transistor on the first semiconductor wafer, and the manufacturing process of the semiconductor device by the semiconductor control device includes forming a gate electrode of the transistor. And a second step in which the film formation apparatus deposits the insulating film used as a sidewall insulating film of the gate electrode after the first step, and the manufacturing control apparatus further includes a step after the first step. And according to the first measurement value, a first measurement value acquisition unit for acquiring a first measurement value indicating the shape of the structure of the transistor formed on the first semiconductor wafer before the second step, The corrected target film thickness is corrected by correcting the target deposited film thickness so that the transistor characteristics are changed in the direction opposite to the direction in which the transistor characteristics are changed in the first step. A target deposited film thickness correcting unit that generates a film thickness; and the deposition time calculating unit calculates a first estimated film thickness by adding the target deposited film thickness and the first variable film thickness, The first deposition time may be calculated by dividing the first estimated film thickness by the film formation rate.

  According to this configuration, the manufacturing control apparatus according to the present invention corrects the target deposited film thickness so as to return the variation in transistor characteristics caused by the structure formed in the previous process. Thereby, the manufacturing control apparatus according to the present invention can reduce variations in transistor characteristics between apparatuses and between lots.

  In addition, the first measurement value acquisition unit acquires the dimension or angle of the gate electrode as the first measurement value, and the target deposited film thickness correction unit is configured so that the dimension of the gate electrode is smaller, or The target deposited film thickness may be increased as the angle of the gate electrode is increased.

  In the first step, a first sidewall insulating film of the gate electrode is further formed, and in the second step, the film forming apparatus is formed on a side surface of the first sidewall insulating film. The insulating film used for the second sidewall insulating film of the electrode is deposited, and the first measurement value acquisition unit acquires a width or an angle of the first sidewall insulating film as the first measurement value, and the target deposition The film thickness correction unit may increase the target deposited film thickness as the width of the first sidewall insulating film is smaller or as the first sidewall insulating film is larger.

  In addition, the target deposition film thickness correction unit may change the threshold voltage in a direction opposite to the direction in which the threshold voltage of the transistor fluctuated in the first step according to the first measurement value. The film thickness may be corrected.

  According to this configuration, the manufacturing control device according to the present invention can reduce the variation in the threshold voltage of the transistor between devices and between lots.

  The semiconductor control device including the film forming apparatus manufactures a semiconductor device including a transistor on the first semiconductor wafer, and the manufacturing process of the semiconductor device by the semiconductor control device includes forming a gate electrode of the transistor. And a second step of depositing a contact etch stop layer as the insulating film on the gate electrode after the first step, and the manufacturing control apparatus further includes the first step. A measurement value acquisition unit for acquiring a measurement value indicating a shape of a structure of the transistor formed on the first semiconductor wafer after and before the second step, and the first measurement value according to the first measurement value Correction is performed by correcting the target deposited film thickness so that the driving capability is changed in a direction opposite to the direction in which the driving capability of the transistor is changed in the process. A target deposited film thickness correcting unit that generates a target deposited film thickness, and the deposition time calculating unit calculates a first estimated film thickness by adding the target deposited film thickness and the first variable film thickness; The first deposition time may be calculated by dividing the first estimated film thickness by the film formation rate.

  According to this configuration, the manufacturing control apparatus according to the present invention can reduce variations in the driving capability of the transistors between the apparatuses and between the lots.

  The semiconductor control device including the film forming apparatus manufactures a semiconductor device including a transistor on the first semiconductor wafer, and the manufacturing process of the semiconductor device by the semiconductor control device forms a first gate electrode of the transistor. And a first step in which the film formation apparatus deposits the insulating film used as a sidewall insulating film of the gate electrode, and after the first step, the first gate electrode is removed, and the first gate electrode And a second step of embedding a gate electrode material in the region from which the substrate is removed, and the manufacturing control device is further formed on the first semiconductor wafer after the first step and before the second step. A second measurement value acquisition unit configured to acquire a second measurement value indicating the shape of the structure of the transistor; and according to the second measurement value, the characteristics of the transistor in the first step are The kinematic the direction opposite to the direction A, and a gate electrode characteristic determining section for determining the characteristics of the gate electrode to vary the characteristics of the transistors in the second step.

  According to this configuration, the manufacturing control apparatus according to the present invention determines the characteristics of the gate electrode so as to return the variation in transistor characteristics caused by the structure formed in the previous process. Thereby, the manufacturing control apparatus according to the present invention can reduce variations in transistor characteristics between apparatuses and between lots.

  The gate electrode characteristic determining unit may determine a film type, film quality, or film thickness of the gate electrode material as the characteristic of the gate electrode.

  The gate electrode characteristic determination unit determines the characteristic of the gate electrode having a work function for changing the threshold voltage in the second step in a direction opposite to the direction in which the threshold voltage of the transistor has changed in the first step. May be.

  According to this configuration, the manufacturing control device according to the present invention can reduce the variation in the threshold voltage of the transistor between devices and between lots.

  In the second step, a high dielectric film serving as a gate insulating film of the transistor is formed in a region where the first gate electrode is removed, and the gate electrode is formed on the formed high dielectric film. The material may be embedded, and the gate electrode characteristic determining unit may determine the film type, film quality, or film thickness of the high dielectric film as the characteristics of the gate electrode.

  The present invention can be realized not only as such a production control apparatus, but also as a production control method using characteristic means included in the production control apparatus as a step, or such characteristic steps in a computer. It can also be realized as a program to be executed. Needless to say, such a program can be distributed via a recording medium such as a CD-ROM and a transmission medium such as the Internet.

  Furthermore, the present invention can be realized as a semiconductor integrated circuit (LSI) that realizes part or all of the functions of such a manufacturing control apparatus, or as a manufacturing system including such a manufacturing control apparatus. This can be realized as a semiconductor device manufacturing method including a simple manufacturing control method.

  As described above, the present invention can provide a manufacturing control apparatus and a manufacturing control method that can reduce variations in transistor characteristics by further suppressing film thickness fluctuation.

It is a figure which shows the deposited film thickness of the product from which a wafer surface area differs. It is a figure which shows the relationship between a wafer surface area and a deposited film thickness. It is a figure which shows the deposited film thickness when the case where only the product A is introduced and the case where the product A and the product B are mixed and introduced. It is a figure which shows the relationship between the case where only the product A is introduce | transduced in the inside of a support body, and the case where the product A and another product are mixed, and the position inside a support body. It is a figure which shows transition of a product deposition rate. It is a block diagram which shows the structure of the manufacturing system which concerns on the 1st Embodiment of this invention. It is a flowchart which shows the flow of a process of the manufacturing system which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the manufacturing control apparatus which concerns on the 1st Embodiment of this invention. It is a flowchart which shows the flow of the calculation process of the estimated film-forming rate by the 1st process part which concerns on the 1st Embodiment of this invention. It is a flowchart which shows the flow of the calculation process of the deposition time by the 2nd process part which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the manufacturing control apparatus which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the manufacturing control apparatus which concerns on the 3rd Embodiment of this invention. It is a flowchart which shows the flow of a process of the manufacturing system which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the structure of the manufacturing control apparatus which concerns on the 4th Embodiment of this invention. It is a flowchart which shows the flow of the calculation process of the deposition time by the 2nd process part which concerns on the 4th Embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on 13th-37th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on 13th-37th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on 13th-37th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on 13th-37th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on 13th-37th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on 13th-37th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on 13th-37th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on 13th-37th embodiment of this invention. It is a sectional view showing the structure in the manufacturing process of the semiconductor device manufactured by the manufacturing system according to the thirty-eighth embodiment of the present invention. It is a sectional view showing the structure in the manufacturing process of the semiconductor device manufactured by the manufacturing system according to the thirty-eighth embodiment of the present invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 39th-44th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 39th-44th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 39th-44th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 39th-44th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 39th-44th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 39th-44th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 39th-44th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 39th-44th embodiment of this invention. It is a block diagram which shows the structure of the manufacturing control apparatus which concerns on 39th-44th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on 45th-52nd embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on 45th-52nd embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on 45th-52nd embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on 45th-52nd embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on 45th-52nd embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 53rd-58th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 53rd-58th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 53rd-58th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 53rd-58th embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 59th-61st embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 59th-61st embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the semiconductor device manufactured by the manufacturing system which concerns on the 59th-61st embodiment of this invention. It is sectional drawing which shows the structure in the manufacture process of the conventional semiconductor device. It is sectional drawing which shows the structure in the manufacture process of the conventional semiconductor device. It is sectional drawing which shows the structure in the manufacture process of the conventional semiconductor device. It is sectional drawing which shows the structure in the manufacture process of the conventional semiconductor device. It is sectional drawing which shows the structure in the manufacture process of the conventional semiconductor device. It is sectional drawing which shows the structure in the manufacture process of the conventional semiconductor device. It is sectional drawing which shows the structure in the manufacture process of the conventional semiconductor device. It is a flowchart of the manufacturing method of the conventional semiconductor device.

  The inventors have found that there is a film thickness variation caused by three variable factors, in addition to the fact that the film formation state changes depending on the total number of wafers accommodated in the support body of the semiconductor manufacturing apparatus.

  As the first film thickness variation, the inventors have found that the film thickness varies depending on the surface area of the wafer to be processed.

  As the second film thickness variation, the inventors have found that the film thickness varies depending on the total surface area of the wafer accommodated in the support.

  As the third film thickness variation, the inventors have found that the film thickness varies due to variations in apparatus parameters due to maintenance or the like.

  First, the first film thickness variation will be described with reference to FIGS. 1A and 1B.

Figure 1A, SiO ₂ film thickness and a SiO ₂ film upon which contains alternately two kinds of product A wafer surface area are different, and the product B to the support of the batch type CVD film forming apparatus was formed It is a figure which shows the result of having measured. Here, the surface area of the product A is smaller than the surface area of the product B. The X axis indicates the position inside the support (furnace position), and the Y axis indicates the SiO ₂ film thickness (deposition film thickness) of the product.

  As shown in FIG. 1A, the film thickness of the product B is always thinner than that of the product A despite being accommodated in the same support. The difference is almost constant regardless of the position of the support. This difference is unlikely to be influenced by the position inside the support, that is, by the temperature distribution of the semiconductor manufacturing apparatus or the gas flow rate distribution.

FIG. 1B is a graph plotting the deposited film thickness against the wafer surface area of several products. The X axis is the wafer surface area of the product normalized by the wafer surface area of the product B, and the Y axis is the SiO ₂ film thickness (deposited film thickness) of the product. As shown in FIG. 1B, it can be seen that the film thickness deposited on the product has a good correlation with the wafer surface area of the product, and is particularly inversely proportional.

  Further, since the above correlation shows almost the same tendency at the position inside the support, it is considered that the correlation is caused by a kind of loading effect depending on the wafer surface area.

  Next, the second film thickness variation will be described with reference to FIGS. 2A and 2B.

  FIG. 2A is a diagram showing a result obtained by superimposing the film forming process on the condition shown in FIG. 1A and FIG. 1B after putting only the product A into the support and performing the film forming process. . FIG. 2B is a graph in which the difference value of the film thickness of the product A in FIGS. 1A and 1B is plotted from the film thickness when the film formation process is performed after only the product A is added.

  As shown in FIG. 2B, the deposited film thickness difference increases as the position in the furnace changes from Bottom to Top. Here, since the evaluated batch type CVD apparatus introduces gas from the bottom side, the reaction gas is used by reacting from the bottom side. Therefore, it is considered that the partial pressure of the reaction gas is reduced as it goes to Top. Thereby, it is thought that the fluctuation | variation of the deposited film thickness difference according to the said position in a furnace has arisen.

  Further, since the reaction gas is consumed more as the surface area is larger, a difference occurs in the deposited film thickness depending on the position inside the support between the case where a small surface area is introduced and the case where a large surface area is introduced. Therefore, as shown in FIG. 2B, it is considered that a difference in the deposited film thickness occurs when the surface area of the introduced product changes.

  As shown in FIG. 2B, this relationship has a high correlation with the sum of the number of sheets introduced into the support × the product surface area.

  Next, the third film thickness variation will be described.

  FIG. 3 is a diagram showing fluctuation data of the deposition rate during a certain period when the same product is formed with the same processing number and the same apparatus.

  As shown in FIG. 3, it can be seen that the deposition rate fluctuates before and after maintenance. This is because the equipment state changes at every maintenance, so that the deposition rate varies even in the same apparatus, and it is considered that the deposition rate fluctuates before and after the maintenance.

  Further, as shown in FIG. 3, there are places where the deposition rate fluctuates during maintenance. This is considered to be because the deposition rate fluctuates because the heat capacity of the support changes due to the accumulation of films formed on the support surface, and the equipment state changes accordingly.

  Embodiments of a semiconductor device manufacturing management apparatus according to the present invention will be described below in detail with reference to the drawings.

  In the following embodiments, a manufacturing system for manufacturing a semiconductor device will be described as an example in consideration of at least one of the first to third film thickness variations.

(First embodiment)
The manufacturing system according to the first embodiment of the present invention increases the deposition time as the wafer surface area increases. Thereby, the manufacturing system according to the first embodiment of the present invention can suppress the variation in the deposited film thickness depending on the wafer surface area (the first film thickness variation), and thus can reduce the variation in transistor characteristics.

  First, the configuration of the manufacturing system according to the first embodiment of the present invention will be described.

  FIG. 4 is a block diagram showing the configuration of the manufacturing system 10 according to the first embodiment of the present invention.

  The manufacturing system 10 illustrated in FIG. 4 includes a manufacturing control device 20, a film forming device 30, and a measuring device 40.

The film forming apparatus 30 deposits an insulating film on a semiconductor wafer (hereinafter also simply referred to as “wafer”) by using a CVD method. For example, the film forming apparatus 30 forms a SiO ₂ film using the LP-CVD method.

  The measuring device 40 measures the film thickness etc. of the insulating film produced | generated on the wafer.

  The production control apparatus 20 calculates control parameters for controlling the film forming apparatus 30. In addition, the manufacturing control apparatus 20 controls the film thickness of the insulating film deposited by the film forming apparatus 30 using the calculated control parameter. Specifically, the control parameters include deposition time, temperature, power, pressure, partial pressure, output, input, gas flow rate, exhaust pressure, and the like during film formation by the film forming apparatus 30. The manufacturing control apparatus 20 calculates a control parameter for depositing an insulating film thicker on the film forming apparatus 30 as the surface area of the semiconductor wafer is larger.

  For example, the manufacturing control device 20 is a computer including a processor such as a CPU and a memory, and is a personal computer, for example.

  In the following, a case where the control parameter is the deposition time will be described as an example.

  Next, an overall processing flow in the manufacturing system 10 will be described.

  FIG. 5 is a flowchart showing a process flow of the manufacturing system 10.

  As shown in FIG. 5, first, the film forming apparatus 30 deposits an insulating film on the first lot wafer (S11). Next, the measuring device 40 measures the film thickness of the insulating film deposited in step S11 (S12).

Next, the production control apparatus 20 calculates the estimated film formation rate R ₀ of the film formation apparatus 30 using the film thickness of the insulating film measured in step S12 (S13). Here, the estimated film formation rate R ₀ is the film thickness of the insulating film deposited per unit time by the film formation apparatus 30.

Next, the manufacturing control apparatus 20 calculates the deposition time t _target of the insulating film by the film forming apparatus 30 for the second lot wafer using the calculated estimated film forming rate R ₀ (S14).

Next, the film forming apparatus 30 deposits an insulating film at the deposition time t _target calculated by the manufacturing control apparatus 20 (S15).

  Hereinafter, the structure and operation of the manufacturing control apparatus 20 will be described in detail.

  FIG. 6 is a block diagram showing a configuration of the production control apparatus 20 according to the first embodiment of the present invention.

  The manufacturing control apparatus 20 illustrated in FIG. 6 includes a first processing unit 21 and a second processing unit 22.

The first processing unit 21 calculates an estimated film formation rate R ₀ using the first wafer surface area L ₀ of the first lot wafer, the processing time t _0, and the measured film thickness T _0, and calculates the calculated estimated component. The film rate R ₀ is output to the second processing unit 22. The first processing unit 21 includes a first wafer surface area acquisition unit 101, a first wafer surface area storage unit 102, a first variable film thickness calculation unit 103, a processing time acquisition unit 104, a processing time storage unit 105, A measured film thickness acquisition unit 106, a measured film thickness accumulation unit 107, an estimated film formation rate calculation unit 108, and an estimated film formation rate accumulation unit 109 are provided.

The first wafer surface area acquisition unit 101 acquires the first wafer surface area L ₀ of the first lot wafer introduced into the support body of the film forming apparatus 30 from the film forming apparatus 30. The first wafer surface area L ₀ is, for example, a value obtained by averaging the maximum value and the minimum value of the wafer surface areas of a plurality of wafers included in the first lot. Each lot includes a plurality of types of products having different patterns. That is, each lot includes a plurality of types of wafers having different wafer surface areas. In the present invention, “Lot” refers to one or more products processed simultaneously on the same support of the film forming apparatus 30 and corresponds to a so-called batch.

The first wafer surface area accumulation unit 102 accumulates the first wafer surface area L ₀ acquired by the first wafer surface area acquisition unit 101.

The first variable film thickness calculation unit 103 uses the first wafer surface area L ₀ stored in the first wafer surface area storage unit 102 to calculate a first variable film thickness T _A0 for the first wafer surface area L ₀ . Here, the first variable film thickness T _A0 corresponds to a film thickness that varies depending on the first wafer surface area L ₀ among the film thickness of the insulating film deposited on the wafer. Specifically, the first variable film thickness calculation unit 103 calculates the first variable film thickness T _A0 by multiplying the first wafer surface area L ₀ by the variable film thickness dependency coefficient A ₀ . That is, as the first wafer surface area L ₀ is larger, the first variable film thickness T _A0 is larger.

The processing time acquisition unit 104 acquires a processing time t ₀ that is a period (deposition time) in which the film formation apparatus 30 has deposited an insulating film in the first lot from the film formation apparatus 30.

The processing time storage unit 105 stores the processing time t ₀ acquired by the processing time acquisition unit 104.

The measured film thickness acquisition unit 106 acquires, from the measurement device 40, the measured film thickness T ₀ that is measured by the measurement device 40 and is the thickness of the insulating film formed by the film formation device 30 in the first lot.

The measured film thickness accumulating unit 107 accumulates the measured film thickness T ₀ acquired by the measured film thickness acquiring unit 106.

The estimated film formation rate calculation unit 108 divides the film thickness obtained by subtracting the first variable film thickness T _A0 from the measured film thickness T ₀ accumulated in the measured film thickness accumulation unit 107 by the processing time t _0. The film rate R ₀ is calculated. That is, the estimated film formation rate R ₀ is per unit time excluding the film thickness component that varies depending on the first wafer surface area L _{0 from} the film thickness of the insulating film deposited by the film formation apparatus 30. This is the thickness of the insulating film to be deposited. That is, R ₀ = (T ₀ −T _A0 ) / t ₀ .

The estimated film formation rate accumulation unit 109 accumulates the estimated film formation rate R ₀ calculated by the estimated film formation rate calculation unit 108.

The second processing unit 22 performs the estimated deposition rate R ₀ calculated by the first processing unit 21 and the second Lot in the previous process of the second Lot after the first Lot film formation and before the second Lot film formation. The deposition time t _target is calculated using the second wafer surface area L ₁ of the wafer and the target deposition film thickness T _target, and the calculated deposition time t _target is output to the film forming apparatus 30. Here, the target deposited film thickness T _target is a _target film thickness of the insulating film formed in the second lot. Further, the deposition time t _target is the time for the film forming apparatus 30 to form the insulating film in the second lot.

  The second processing unit 22 includes a second wafer surface area acquisition unit 110, a second wafer surface area accumulation unit 111, a second variable film thickness calculation unit 112, a target deposition film thickness acquisition unit 113, and a target deposition film thickness accumulation. Unit 114, estimated film formation rate acquisition unit 115, deposition time calculation unit 116, deposition time accumulation unit 117, and deposition time output unit 118.

The second wafer surface area acquisition unit 110 acquires from the film formation apparatus 30 the second wafer surface area L ₁ of the second lot wafer to be introduced next to the support of the film formation apparatus 30. For example, the second wafer surface area L ₁ is a value obtained by averaging the maximum value and the minimum value of the wafer surface areas of the plurality of wafers included in the second lot.

The second wafer surface area accumulation unit 111 accumulates the second wafer surface area L ₁ acquired by the second wafer surface area acquisition unit 110.

The second thickness variation calculating section 112 uses a second wafer surface area L ₁ stored in the second wafer surface storage unit 111, to calculate a second variation thickness T _A1 with respect to the second wafer area L _1. Here, the second variable film thickness T _A1 corresponds to a film thickness that varies depending on the second wafer surface area L ₁ out of the film thickness of the insulating film deposited on the wafer. Specifically, the second variable film thickness calculation unit 112 calculates the second variable film thickness T _A1 by multiplying the second wafer surface area L ₁ by the variable film thickness dependency coefficient A ₀ . In other words, the second variable film thickness T _A1 increases as the second wafer surface area L ₁ increases.

The target deposited film thickness acquisition unit 113 acquires the target deposited film thickness T _target of the processing target wafer from the film forming apparatus 30.

The target deposited film thickness accumulating unit 114 accumulates the target deposited film thickness T _target acquired by the target deposited film thickness acquiring unit 113.

The estimated film formation rate acquisition unit 115 acquires the estimated film formation rate R ₀ stored in the estimated film formation rate storage unit 109.

The deposition time calculation unit 116 includes the second variable film thickness T _A1 calculated by the second variable film thickness calculation unit 112, the estimated film formation rate R ₀ acquired by the estimated film formation rate acquisition unit 115, and the target deposition film. The optimum deposition time t _target for the second lot product wafer is calculated using the target deposition film thickness T _target accumulated in the thickness accumulation unit 114. Specifically, the deposition time calculation unit 116 calculates the deposition time t _target by adding the second variable film thickness T _A1 to the target deposition film thickness T _target and dividing by the estimated film formation rate R _0. To do. That is, t _target = (T _target + T _A1 ) / R ₀ . Here, the second variable film thickness T _A1 is larger as the second wafer surface area L ₁ is larger. Accordingly, the larger the second wafer surface area L ₁ is, the longer the deposition time t _target is.

The deposition time accumulation unit 117 accumulates the deposition time t _target calculated by the deposition time calculation unit 116.

The deposition time output unit 118 outputs the deposition time t _target accumulated in the deposition time accumulation unit 117 to the film forming apparatus 30.

  The functions of the processing units included in the manufacturing control device 20 shown in FIG. 6 are typically stored in a memory (ROM, RAM, HDD, nonvolatile memory, or the like) by a processor included in the manufacturing control device 20. This is realized by executing the programmed program. Further, the function of each storage unit included in the production control device 20 is realized by a memory (RAM, HDD, nonvolatile memory, or the like) included in the production control device 20. Note that some or all of the plurality of processing units included in the manufacturing control apparatus 20 may be realized by a dedicated circuit (hardware).

Further, the manufacturing control apparatus 20 may obtain the first wafer surface area L ₀ , the second wafer surface area L ₁ , the processing time t _0, and the target deposition film thickness T _target from other apparatuses other than the film forming apparatus 30. Then, it may be input to the manufacturing control apparatus 20 by a user operation. Further, the manufacturing control apparatus 20 may acquire the measured film thickness T ₀ directly from the measuring apparatus 40 instead of the other apparatus, or the measured film thickness T ₀ may be manufactured by a user operation. It may be input to the control device 20.

  The first processing unit 21 and the second processing unit 22 may be provided in different devices. Moreover, the manufacturing control apparatus 20 according to the present invention may include only one of the first processing unit 21 and the second processing unit 22.

  Next, the operation flow of the manufacturing control apparatus 20 will be described.

First, the flow of the estimated film formation rate R ₀ calculation process (step S13 in FIG. 5) by the first processing unit 21 will be described.

FIG. 7 is a flowchart showing a flow of processing for calculating the estimated film formation rate R ₀ by the first processing unit 21.

As shown in FIG. 7, first, the first wafer surface area acquisition unit 101 acquires the first wafer surface area L ₀ of the first lot wafer, and stores it in the first wafer surface area storage unit 102 (S111).

Next, the first variable film thickness calculation unit 103 calculates the first variable film thickness T _A0 by multiplying the first wafer surface area L ₀ by the variable film thickness dependency coefficient A ₀ (S112).

Next, in the first lot, the processing time acquisition unit 104 acquires a processing time t ₀ that is a period during which the film formation apparatus 30 deposits an insulating film, and stores the processing time t ₀ in the processing time storage unit 105 (S113).

Next, the measured film thickness acquisition unit 106 acquires the measured film thickness T ₀ from the measurement device 40 and stores it in the measured film thickness storage unit 107 (S114).

Next, the estimated film formation rate calculation unit 108 calculates the estimated film formation rate R ₀ by dividing the film thickness obtained by subtracting the first variable film thickness T _A0 from the measured film thickness T ₀ by the processing time t _0. Then, it is stored in the estimated film formation rate storage unit 109 (S115).

Thus, the estimated film formation rate R ₀ is calculated.

  Note that the order of steps S111, S113, and S114 shown in FIG. 7 is arbitrary. Moreover, step S112 may be performed at an arbitrary timing after step S111 and before step S115. Moreover, you may perform a part of process of step S111-S114 simultaneously.

Next, the flow of the deposition time t _target calculation process (step S14 in FIG. 5) by the second processing unit 22 will be described.

FIG. 8 is a flowchart showing the flow of processing for calculating the deposition time t _target by the second processing unit 22.

As shown in FIG. 8, first, the second wafer surface area acquisition unit 110 acquires the second wafer surface area L ₁ of the second lot wafer and stores it in the second wafer surface area storage unit 111 (S121).

Next, the second variable film thickness calculation unit 112 calculates the second variable film thickness T _A1 by multiplying the second wafer surface area L ₁ by the variable film thickness dependency coefficient A ₀ (S122).

Next, the target deposited film thickness acquisition unit 113 acquires the target deposited film thickness T _target and accumulates it in the target deposited film thickness accumulation unit 114 (S123).

Next, the estimated film formation rate acquisition unit 115 acquires the estimated film formation rate R ₀ stored in the estimated film formation rate storage unit 109 (S124).

Next, the deposition time calculation unit 116 calculates the deposition time t _target by adding the second variable film thickness T _A1 to the target deposition film thickness T _target and dividing by the estimated film formation rate R ₀ . It accumulates in the accumulation time accumulation unit 117 (S125).

Next, the deposition time output unit 118 outputs the deposition time t _target accumulated in the deposition time accumulation unit 117 to the film forming apparatus 30 (S126).

Thus, the second lot deposition time t _target is output to the film forming apparatus 30.

  Note that the order of steps S121, S123, and S124 shown in FIG. 8 is arbitrary. Further, step S122 may be performed at an arbitrary timing as long as it is after step S121 and before step S125. Moreover, you may perform a part of process of step S121-S124 simultaneously.

As described above, the production control apparatus 20 according to the first embodiment of the present invention increases the deposition time t _target as the second wafer surface area L ₁ of the second lot increases. Thereby, since the manufacturing control apparatus 20 can suppress the variation in the deposited film thickness (the first film thickness variation) depending on the wafer surface area, the variation in transistor characteristics can be reduced.

Further, the production control apparatus 20 calculates the estimated film formation rate R ₀ from the measured film thickness T ₀ of the insulating film formed in the same lot by the same film formation apparatus 30. Thereby, the manufacturing control apparatus 20 can reduce the dispersion | variation (the said 3rd film thickness fluctuation | variation) between apparatuses.

In the above description, the wafer surface area is described as a general term, but the manufacturing control apparatus 20 uses the pattern area ratio, the pattern area, and the pattern aperture ratio as the first wafer surface area L ₀ and the second wafer surface area L _1. Alternatively, the pattern opening area may be used. Here, the pattern area ratio is the ratio of the area of the gate electrode pattern formed per unit area. The pattern area is the total area of the gate electrode pattern. The pattern aperture ratio is the ratio of the area where the gate electrode pattern is not formed per unit area. The pattern opening area is the total area where the gate electrode pattern is not formed. Further, the larger the pattern ratio and pattern area, the larger the wafer surface area. The larger the pattern opening ratio and pattern opening area, the smaller the wafer surface area.

Further, the manufacturing control apparatus 20 may use the pattern unit peripheral length (pattern peripheral length ratio) or the pattern peripheral length of the gate electrode as the first wafer surface area L ₀ and the second wafer surface area L ₁ . Here, the pattern unit peripheral length is the peripheral length of the gate electrode formed per unit area. The pattern peripheral length is the sum of the peripheral lengths of the gate electrode pattern formed on the wafer. Further, the larger the pattern unit peripheral length and the pattern peripheral length, the larger the wafer surface area.

  Specifically, when the gate electrode pattern is formed, the area of the wafer surface is expressed as follows: unit peripheral length of gate electrode × wafer area (150 mm × 150 mm × π) × gate electrode height + wafer surface area (150 mm × 150 mm × π). Further, the area of the wafer back surface is the wafer area (150 mm × 150 mm × π). The wafer surface area is a value obtained by adding the area of the front surface of the wafer and the area of the back surface of the wafer.

The manufacturing control apparatus 20 calculates the wafer surface area from these pattern area ratio, pattern area, pattern opening ratio, pattern opening area, pattern unit peripheral length, or pattern peripheral length, and then performs the above-described processing. _{Alternatively} , the first variable film thickness T _A0 and the second variable film thickness T _A1 may be calculated directly from these.

In addition, the manufacturing control apparatus 20 may further calculate a deposition time t _target that corrects differences between apparatuses and a natural oxide film thickness formed before deposition.

That is, the manufacturing control apparatus 20 may calculate the theoretical deposition time t _target using the following formula (1).

t _target = (T _target + L ₁ × A ₀ + B) / [(T ₀ −L ₀ × A ₀ + B) / t ₀ ] + C
... Formula (1)

  In the above equation (1), the correction value B is a coefficient for correcting, for example, a difference between apparatuses, and the correction value C is, for example, for correcting a natural oxide film thickness formed before deposition. Is the coefficient.

In the above description, the manufacturing control apparatus 20 predicts the deposited film thickness. However, the manufacturing control apparatus 20 may make a correction after predicting not the deposited film thickness but the fluctuation of the film forming rate. Specifically, the manufacturing control apparatus 20 calculates a film formation rate variation dependency coefficient A ₁ instead of the above-described deposition film thickness variation dependency coefficient A ₀ . Next, the manufacturing control apparatus 20 calculates a predicted rate R _A in which the rate variation is corrected after predicting the rate variation using the variation dependency coefficient A ₁ . For example, R _A = A ₁ × L ₁ . Next, the manufacturing control apparatus 20 may calculate the deposition time t _target by dividing the target deposition film thickness T _target by the predicted rate. That is, t _target = T _target / (R ₀ + R _A ).

  Next, an example of manufacturing a semiconductor device manufactured by the manufacturing system 10 will be described. This semiconductor device includes a transistor. Further, this semiconductor device is manufactured by a semiconductor manufacturing apparatus including the film forming apparatus 30.

  9A to 11D are cross-sectional views illustrating the manufacturing process of the semiconductor device manufactured by the manufacturing system 10. A cross-sectional structure of an n-ch MIS transistor (hereinafter referred to as an nMIS transistor) is schematically shown on the left side of the drawing, and a cross-sectional structure of a p-ch MIS transistor (hereinafter referred to as a pMIS transistor) is schematically illustrated on the right side.

  First, in the cross-sectional structure shown in FIG. 9A, a trench type element isolation insulating film 1103 that partitions the nMIS transistor formation region 1001 and the pMIS transistor formation region 1002 is formed on the silicon substrate 1104.

  Thereafter, a gate insulating film 1102 made of, for example, a silicon oxide film and a polysilicon film are sequentially formed on the entire surface of the silicon substrate 1104. Next, the polysilicon film is patterned using a dry etching method or the like, thereby forming the gate electrode 1100 of the nMIS transistor and the gate electrode 1105 of the pMIS transistor.

  Next, in the step shown in FIG. 9B, a first sidewall insulating film 1101 made of a silicon oxide film is deposited on the entire surface of the silicon substrate 1104 by CVD. As a result, the entire nMIS transistor formation region 1001 and the pMIS transistor formation region 1002 including the gate electrode 1100 of the nMIS transistor and the gate electrode 1105 of the pMIS transistor are covered with the first sidewall insulating film 1101.

Next, in the step shown in FIG. 9C, the first sidewall insulating film 1101 is anisotropically dry-etched using a fluorocarbon gas such as CF ₄ / Ar gas. Thus, the first sidewall insulating film 1106 is selectively formed on the side surfaces of the gate electrodes 1100 and 1105. At this time, when dry etching is performed using CF ₄ / Ar gas, the etching rate with respect to the first sidewall insulating film 1101 is slow, so that the etching controllability can be improved.

Next, in a step shown in FIG. 9D, a resist mask 1110 having an opening on the nMIS transistor formation region 1001 and covering the pMIS transistor formation region 1002 is formed. Thereafter, using the gate electrode 1100, the first sidewall insulating film 1106, and the resist mask 1110 as a mask, arsenic (As +) ions 1111 that are n-type impurities are implanted at an energy of about 1.0 keV to 5 keV and a dose amount of 5 Ion implantation is performed under conditions of × 10 ^{13 to} 5 × 10 ¹⁵ / cm ² . As a result, an n-type extension region 1112 is formed in the nMIS transistor formation region 1001.

  Next, in the step shown in FIG. 10A, the resist mask 1110 is removed by ashing. Note that the resist mask 1110 may be removed by wet cleaning using an aqueous hydrogen peroxide solution (SPM) or an aqueous ammonia hydrogen peroxide solution (APM).

  Next, in a step shown in FIG. 10B, a resist mask 1113 having an opening on the pMIS transistor formation region 1002 and covering the nMIS transistor formation region 1001 is formed.

Thereafter, using the gate electrode 1105, the first sidewall insulating film 1106, and the resist mask 1113 as a mask, boron (B +) ions 1114 that are p-type impurities are implanted at an energy of about 0.3 keV to 2.0 keV and a dose amount. Is ion-implanted under the conditions of 5 × 10 ^{13 to} 5 × 10 ¹⁵ / cm ² . As a result, the p-type extension region 1115 of the pMIS transistor formation region 1002 is formed.

  Next, in a step shown in FIG. 10C, the resist mask 1113 is removed by ashing. Note that the resist mask 1113 may be removed by performing wet cleaning using an aqueous sulfuric acid hydrogen peroxide solution (SPM) or an aqueous ammonia hydrogen peroxide solution (APM).

  Next, in the step shown in FIG. 10D, a second sidewall insulating film 1116 made of a silicon nitride film is deposited on the entire surface of the silicon substrate 1104 by CVD. As a result, the entire nMIS transistor formation region 1001 and the pMIS transistor formation region 1002 including the gate electrode 1100 of the nMIS transistor, the gate electrode 1105 of the pMIS transistor, and the first sidewall insulating film 1106 form the second sidewall insulating film 1116. Covered by.

  Next, anisotropic etching is performed on the second sidewall insulating film 1116 in the step shown in FIG. 11A, so that the second electrodes are selectively formed on the side surfaces of the gate electrodes 1100 and 1105 and the first sidewall insulating film 1106. Sidewall insulating films 1117 are formed.

Next, in a step shown in FIG. 11B, a resist mask 1118 having an opening on the nMIS transistor formation region 1001 and covering the pMIS transistor formation region 1002 is formed. After that, using the gate electrode 1100, the first sidewall insulating film 1106, the second sidewall insulating film 1117, and the resist mask 1118 as a mask, arsenic (As +) ions 1119, which are n-type impurities, are implanted at an energy of about 5 keV. Ion implantation is performed under the conditions of 30 keV and a dose of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ² . As a result, n-type source / drain regions 1120 are formed in the nMIS transistor formation region 1001.

  Next, in the step shown in FIG. 11C, the resist mask 1118 is removed by ashing. Note that the resist mask 1118 may be removed by performing wet cleaning using a sulfuric acid hydrogen peroxide aqueous solution (SPM), an ammonia hydrogen peroxide aqueous solution (APM), or the like. Next, a resist mask 1121 having an opening on the pMIS transistor formation region 1002 and covering the nMIS transistor formation region 1001 is formed.

After that, using the gate electrode 1105, the first sidewall insulating film 1106, the second sidewall insulating film 1117, and the resist mask 1121 as a mask, boron (B +) ions 1122 that are p-type impurities are implanted at an energy of about 5 keV. Ion implantation is performed under the conditions of ²⁰ keV and a dose of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ² . As a result, the p-type source / drain region 1123 of the pMIS transistor formation region 1002 is formed.

  Next, in a step shown in FIG. 11D, the resist mask 1121 is removed by ashing. Note that the resist mask 1118 is removed by performing wet cleaning using an aqueous hydrogen peroxide solution (SPM) or an aqueous ammonia hydrogen peroxide solution (APM).

  Thus, a transistor structure in which an implantation process for determining transistor characteristics is performed is formed.

  Thereafter, a product (semiconductor device) is completed through an interlayer insulating film forming process, a contact forming process, a wiring forming process, and a PAD forming process.

The manufacturing control apparatus 20 described above calculates, for example, the deposition time t _target of the second sidewall insulating film 1116 in the above process. Note that the manufacturing control apparatus 20 may calculate the deposition time t _target of the first sidewall insulating film 1101 in the above process.

(Second Embodiment)
The manufacturing control apparatus 20A according to the second embodiment of the present invention increases the deposition time as the total surface area of the plurality of wafers put into each lot increases. As a result, the manufacturing control apparatus 20A according to the second embodiment of the present invention can suppress the variation in the deposited film thickness (the second film thickness variation) depending on the total surface area of the wafer. Can be reduced.

  In addition, description of the content similar to 1st Embodiment mentioned above is abbreviate | omitted, and only a different point is demonstrated below.

  FIG. 12 is a block diagram showing a configuration of a manufacturing control apparatus 20A according to the second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the element similar to FIG. 6, and the overlapping description is abbreviate | omitted. The manufacturing control apparatus 20A includes a first processing unit 21A and a second processing unit 22A.

  In addition to the configuration of the first processing unit 21 according to the first embodiment, the first processing unit 21A further includes a first wafer number acquisition unit 221, a first wafer number storage unit 222, and a first total surface area calculation unit. 223. Further, the configurations of the first wafer surface area acquisition unit 201, the first wafer surface area accumulation unit 202, and the first variable film thickness calculation unit 203 are different from those of the first embodiment.

The first wafer surface area acquisition unit 201 includes a first wafer surface area L _0n (n = 0 to the number of product types−) of each of a plurality of types of products included in the first lot wafer introduced into the support of the film forming apparatus 30. 1) is acquired from the film forming apparatus 30.

The first wafer surface area accumulating unit 202 accumulates the first wafer surface area L _0n acquired by the first wafer surface area acquiring unit 201.

The first wafer number acquisition unit 221 acquires the first wafer number N _0n (n = 0 to the product type−1) of each of the plurality of types of products in the first lot.

The first wafer number storage unit 222 stores the first wafer number N _0n acquired by the first wafer number acquisition unit 221.

The first total surface area calculation unit 223 uses the first wafer surface area L _0n accumulated in the first wafer surface area accumulation unit 202 and the first wafer number N _0n accumulated in the first wafer number accumulation unit 222. A first total surface area L _t0 that is the sum of the surface areas of the plurality of wafers introduced into the support is calculated. Specifically, the first total surface area calculation unit 223 calculates the product of the first wafer surface area L _0n and the first wafer number N _0n for each product, and adds the calculated products for each product, A first total surface area L _t0 is calculated. That is, L _t0 = Σ (L _0n × N _0n ).

The first variable film thickness calculator 203 uses the first total surface area L _t0 calculated by the first total surface area calculator 223 to calculate a first variable film thickness T _A0 for the first total surface area L _t0 . Here, the first variable film thickness T _A0 is specifically calculated by the first variable film thickness calculation unit 203 by multiplying the first total surface area L _t0 by the variable film thickness dependency coefficient D ₀ . 1 Fluctuating film thickness T _A0 is calculated. That is, the larger the first total surface area L _t0 , the thicker the first variable film thickness T _A0 .

  In addition to the configuration of the second processing unit 22 according to the first embodiment, the second processing unit 22A further includes a second wafer number acquisition unit 224, a second wafer number storage unit 225, and a second total surface area calculation unit. 226. The configurations of the second wafer surface area acquisition unit 210, the second wafer surface area accumulation unit 211, and the second variable film thickness calculation unit 212 are different from those of the first embodiment.

The second wafer surface area acquisition unit 210 has a second wafer surface area L _1n (n = 0 to the number of product types−) of each of a plurality of types of products included in the second lot wafer introduced into the support of the film forming apparatus 30. 1) is acquired from the film forming apparatus 30.

The second wafer surface area accumulation unit 211 accumulates the second wafer surface area L _1n acquired by the second wafer surface area acquisition unit 210.

The second wafer number acquisition unit 224 acquires the second wafer number N _1n (n = 0 to the product type−1) of each of the plurality of types of products of the second lot.

The second wafer number accumulation unit 225 accumulates the second wafer number N _1n acquired by the second wafer number acquisition unit 224.

The second total surface area calculation unit 226 uses the second wafer surface area L _1n accumulated in the second wafer surface area accumulation unit 211 and the second wafer number N _1n accumulated in the second wafer number accumulation unit 225, A second total surface area L _t1 that is the sum of the surface areas of the plurality of wafers introduced into the support is calculated. Specifically, the second total surface area calculation unit 226 calculates the product of the second wafer surface area L _1n and the second wafer number N _1n for each product, and adds the calculated products for each product, A second total surface area L _t1 is calculated. That is, L _t1 = Σ (L _1n × N _1n ).

The second variable film thickness calculator 212 uses the second total surface area L _t1 calculated by the second total surface area calculator 226 to calculate a second variable film thickness T _A1 for the second total surface area L _t1 . Here, specifically, the second variable film thickness T _A1 is calculated by multiplying the second total film surface area L _t1 by the variable film thickness dependency coefficient D ₀ . 2 Calculate the variable film thickness T _A1 . That is, as the second total surface area L _t1 increases, the second variable film thickness T _A1 increases.

With the above configuration, the manufacturing control apparatus 20A calculates the theoretical deposition time t _target using the following equation (2).

t _target = (T _target + L ₀₀ × N ₀₀ × D ₀ + L ₀₁ × N ₀₁ × D ₀ +... + L _0n × N _0n × D ₀ + E) / [(T ₀ −L ₁₀ × N ₁₀ × D0 + L ₁₁ × N ₁₁ × D ₀ +... + L _1n × N _1n × D ₀ + E) / t ₀ ] + F Equation (2)

  In the above equation (2), the correction value E is, for example, a coefficient for correcting a difference between apparatuses, and the correction value F is, for example, for correcting a natural oxide film thickness formed before deposition. Is the coefficient.

  Further, as in the first embodiment described above, the manufacturing control device 20A may be modified.

As described above, the manufacturing control apparatus 20A according to the second embodiment of the present invention increases the deposition time t _target as the second total surface area L _t1 of the second lot wafer increases. Thereby, since the manufacturing control apparatus 20 can suppress the variation in the deposited film thickness (the second film thickness variation) depending on the total surface area of the wafer, the variation in transistor characteristics can be reduced.

(Third embodiment)
A production control device 20B according to the third embodiment of the present invention is a modification of the production control device 20 according to the first embodiment. The manufacturing control apparatus 20B according to the third embodiment calculates control parameters of the film forming apparatus 30 such that the film deposition apparatus 30 deposits an insulating film thicker as the wafer surface area increases. Thereby, the manufacturing control apparatus 20B according to the third embodiment of the present invention can suppress the variation in the deposited film thickness depending on the wafer surface area (the first film thickness variation), and thus can reduce the variation in the transistor characteristics. .

  In addition, description of the content similar to 1st Embodiment mentioned above is abbreviate | omitted, and only a different point is demonstrated below.

  FIG. 13 is a block diagram showing a configuration of a production control apparatus 20B according to the third embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the element similar to FIG. 6, and the overlapping description is abbreviate | omitted. The manufacturing control apparatus 20B is different from the first embodiment in the configuration of the second processing unit 22B. Specifically, the second processing unit 22B includes a parameter calculation unit 216, a parameter storage unit 217, and a parameter output unit 218 instead of the deposition time calculation unit 116, the deposition time accumulation unit 117, and the deposition time output unit 118.

The second processing unit 22B is configured to calculate the estimated film formation rate R ₀ calculated by the first processing unit 21 and the second lot before the second lot film formation after the first lot film formation and before the second lot film formation. The control parameter P _target is calculated using the second wafer surface area L ₁ of the wafer and the target deposition film thickness T _target, and the calculated control parameter P _target is output to the film forming apparatus 30.

The parameter calculation unit 216 includes the second variable film thickness T _A1 calculated by the second variable film thickness calculation unit 112, the estimated film formation rate R ₀ acquired by the estimated film formation rate acquisition unit 115, and the target deposition film thickness. A control parameter P _target optimum for the second lot of product wafer is calculated using the target deposited film thickness T _target stored in the storage unit 114. Specifically, the parameter calculation unit 216 calculates a control parameter P _target that complements the second variable film thickness T _A1 with respect to the target deposition film thickness T _target . That is, the parameter calculation unit 216 calculates the control parameter P _target such that the film forming apparatus 30 deposits the insulating film thicker as the second variable film thickness T _A1 increases. In other words, the parameter calculation unit 216 calculates the control parameter P _target such that the film deposition apparatus 30 deposits the insulating film thicker as the second wafer surface area L ₁ is larger.

Here, the control parameter P _target is a parameter for controlling temperature, power, pressure, partial pressure, output, input, gas flow rate, exhaust pressure, and the like during film formation of the film forming apparatus 30.

The parameter storage unit 217 stores the control parameter P _target calculated by the parameter calculation unit 216.

The parameter output unit 218 outputs the control parameter P _target stored in the parameter storage unit 217 to the film forming apparatus 30.

With the above, manufacturing control device 20B according to a third embodiment of the present invention, as the second larger wafer surface area L ₁ is the 2Lot film forming apparatus 30 is deposited thick insulating film, the film forming apparatus 30 The control parameter P _target is calculated. Thereby, the manufacturing control apparatus 20B according to the third embodiment of the present invention can suppress the variation in the deposited film thickness depending on the wafer surface area (the first film thickness variation), and thus can reduce the variation in the transistor characteristics. .

  A similar modification may be applied to the manufacturing control apparatus 20A according to the second embodiment described above.

(Fourth embodiment)
A production control apparatus 20C according to the fourth embodiment of the present invention is a modification of the production control apparatus 20 according to the first embodiment. In addition to the function of the manufacturing control device 20, the manufacturing control device 20C according to the fourth embodiment further corrects the target deposited film thickness T _target in accordance with the gate electrode size generated in the previous process of the second lot. Thereby, the manufacturing control apparatus 20C according to the fourth embodiment of the present invention can reduce variations in transistor characteristics (the third film thickness fluctuation) between apparatuses and between lots.

  First, an overall processing flow in the manufacturing system 10 according to the fourth embodiment will be described.

  FIG. 14 is a flowchart showing a process flow of the manufacturing system 10 according to the fourth embodiment. Note that the processing in steps S11 to S13 is the same as in the first embodiment.

  As shown in FIG. 14, first, the film forming apparatus 30 deposits an insulating film on the first lot wafer (S11). Next, the measuring device 40 measures the film thickness of the insulating film deposited in step S11 (S12).

Next, the production control apparatus 20 calculates the estimated film formation rate R ₀ of the film formation apparatus 30 using the film thickness of the insulating film measured in step S12 (S13).

  Next, the semiconductor manufacturing apparatus including the film forming apparatus 30 performs the first process of the second lot (S24).

  Next, the measuring device 40 measures the shape of the structure generated in the first process of the second lot (S25).

Next, the manufacturing control apparatus 20 uses the estimated film formation rate R ₀ calculated in step S13 and the measurement value measured in step S25 to form the insulating film by the film formation apparatus 30 for the second process of the second lot. The deposition time t _target is calculated (S26).

Next, the film forming apparatus 30 deposits the insulating film in the second process of the second lot at the deposition time t _target calculated by the manufacturing control apparatus 20 (S27).

  Next, the configuration of a production control apparatus 20C according to the fourth embodiment of the present invention will be described.

  FIG. 15 is a block diagram showing a configuration of a production control apparatus 20C according to the fourth embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the element similar to FIG. 6, and the overlapping description is abbreviate | omitted. The manufacturing control device 20C is different from the first embodiment in the configuration of the second processing unit 22C. Specifically, the second processing unit 22C further includes a measurement value acquisition unit 231, a measurement value storage unit 232, and a target deposited film thickness correction unit 233.

  The measurement value acquisition unit 231 acquires, from the measurement device 40, the measurement value 234 that is measured by the measurement device 40 and indicates the shape of the structure formed on the wafer after the completion of the first process of the second lot.

  The measurement value accumulation unit 232 accumulates the measurement value 234 acquired by the measurement value acquisition unit 231.

The target deposited film thickness correcting unit 233 sets the target deposited film thickness T _target accumulated in the target deposited film thickness accumulating unit 114 according to the measured value 234 accumulated in the measured value accumulated unit 232 in the first step. The corrected target deposited film thickness T _target2 is generated by correcting the characteristics of the transistor so as to change in the direction opposite to the direction in which the characteristics have changed.

The deposition time calculation unit 116 includes the second variable film thickness T _A1 calculated by the second variable film thickness calculation unit 112, the estimated film formation rate R ₀ acquired by the estimated film formation rate acquisition unit 115, and the target deposition film. Using the corrected target deposition film thickness T _target2 generated by the thickness correction unit 233, the optimum deposition time t _target for the second step of the second lot is calculated. Specifically, the deposition time calculation unit 116 adds the second variable film thickness T _A1 to the corrected target deposition film thickness T _target2 , and then divides by the estimated film formation rate R ₀ to obtain the deposition time t _target. Is calculated. That is, t _target = (T _target2 + T _A1 ) / R ₀ .

Specifically, the first step is a step of forming up to the structure shown in FIG. 9A, and the second step is a step of forming a first sidewall insulating film 1101 shown in FIG. 9B. The measured value 234 is the gate electrode dimension 1124 of the nMIS transistor and the gate electrode dimension 1125 of the pMIS transistor shown in FIG. 9A. The target deposition film thickness T _target and the deposition time t _target are the target deposition film thickness and deposition time of the first sidewall insulating film 1101.

Here, transistor characteristics such as Vt (threshold voltage) of the transistor fluctuate due to fluctuation of the gate electrode dimension 1124 or 1125. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the first sidewall insulating film thickness 1128 in a direction to return the transistor characteristics changed in the first step. Compensate for fluctuations.

The target deposited film thickness correcting unit 233 sets the correction amount at this time as the correlation data between the gate electrode size 1124 or 1125 or the average value thereof and Vt, and the correlation data between the first sidewall insulating film thickness 1128 and Vt. And using Specifically, the target deposition film thickness correction unit 233 increases the corrected target deposition film thickness T _target2 as the gate electrode dimensions 1124 and 1125 are smaller.

Next, the flow of the deposition time t _target calculation process (step S26 in FIG. 14) by the second processing unit 22C will be described.

FIG. 16 is a flowchart showing a flow of a calculation process of the deposition time t _target by the second processing unit 22C.

As shown in FIG. 16, first, the second wafer surface area acquisition unit 110 acquires the second wafer surface area L ₁ of the second lot wafer, and stores it in the second wafer surface area storage unit 111 (S121).

Next, the second variable film thickness calculation unit 112 calculates the second variable film thickness T _A1 by multiplying the second wafer surface area L ₁ by the variable film thickness dependency coefficient A ₀ (S122).

Next, the target deposited film thickness acquisition unit 113 acquires the target deposited film thickness T _target and accumulates it in the target deposited film thickness accumulation unit 114 (S123).

  Next, the measurement value acquisition unit 231 acquires the measurement value 234 measured by the measurement device 40 and indicating the shape of the structure formed on the wafer after the completion of the first process of the second lot, and the measurement value storage unit 232. (S227).

Next, the target deposited film thickness correcting unit 233 corrects the target deposited film thickness T _target in a direction to return the transistor characteristics changed in the first step according to the measured value 234, thereby correcting the target deposited film thickness after correction. T _target2 is generated (S228).

Next, the estimated film formation rate acquisition unit 115 acquires the estimated film formation rate R ₀ stored in the estimated film formation rate storage unit 109 (S124).

Next, the deposition time calculation unit 116 calculates the deposition time t _target by adding the second variable film thickness T _A1 to the corrected target deposition film thickness T _target2 and dividing by the estimated film formation rate R _0. And accumulated in the deposition time accumulation unit 117 (S125).

Next, the deposition time output unit 118 outputs the deposition time t _target accumulated in the deposition time accumulation unit 117 to the film forming apparatus 30 (S126).

As described above, the deposition time t _target of the second process of the second lot is output to the film forming apparatus 30.

  Note that the order of steps S121, S123, S227, and S124 shown in FIG. 16 may be arbitrary. Further, step S122 may be performed at an arbitrary timing as long as it is after step S121 and before step S125. Further, step S228 may be performed at any timing as long as it is after steps S123 and S227 and before step S125. Moreover, you may perform a part of process of step S121-S124 simultaneously.

As described above, the manufacturing control apparatus 20C according to the fourth embodiment of the present invention sets the target deposition in a direction to return the transistor characteristics changed in the first step according to the gate electrode size generated in the first step of the second lot. The film thickness T _target is corrected. Thereby, the manufacturing control apparatus 20C according to the fourth embodiment of the present invention can reduce variations in transistor characteristics (the third film thickness variation) between apparatuses and between lots and between lots.

(Fifth embodiment)
The production control apparatus according to the fifth embodiment of the present invention is a modification of the production control apparatus 20C according to the fourth embodiment. The configuration of the manufacturing control apparatus 20C according to the fifth to twelfth embodiments is the same as the configuration shown in FIG.

The manufacturing control apparatus 20C according to the fifth embodiment of the present invention performs the first sidewall insulation shown in FIG. 9B according to the gate electrode angle 1126 of the nMIS transistor and the gate electrode angle 1127 of the pMIS transistor shown in FIG. 9A. The target deposited film thickness T _target of the film thickness 1128 is changed.

Here, when the gate electrode angles 1126 and 1127 are reduced to a taper angle (closer to 90 degrees), the first sidewall insulating film formed by anisotropic etching of the first sidewall insulating film 1101. The first side wall insulating film widths 1131 and 1132 of 1106 are narrowed. As a result, the Vt of the transistor varies. In contrast, when the gate electrode angles 1126 and 1127 are lowered, the target deposited film thickness correcting unit 233 sets the target deposited film thickness T _target of the first sidewall insulating film thickness 1128 in the previous step. By changing the changed transistor characteristics in the returning direction, the fluctuation of the transistor characteristics such as Vt is complemented.

The target deposited film thickness correcting unit 233 uses the gate electrode angle 1126 or 1127, or correlation data between the average value and Vt, and correlation data between the first sidewall insulating film thickness 1128 and Vt as the correction amount at this time. And using Specifically, the target deposited film thickness correcting unit 233 decreases the corrected target deposited film thickness T _target2 as the gate electrode angles 1126 and 1127 are larger (the taper angle is smaller).

(Sixth embodiment)
A production control apparatus 20C according to the sixth embodiment of the present invention is a modification of the production control apparatus 20C according to the fourth embodiment.

The manufacturing control apparatus 20C according to the sixth embodiment of the present invention performs the second sidewall insulation shown in FIG. 10D according to the gate electrode size 1124 of the nMIS transistor and the gate electrode size 1125 of the pMIS transistor shown in FIG. 9A. The target deposited film thickness T _target of the film thickness 1135 is changed.

Here, when the gate electrode dimensions 1124 and 1125 vary, transistor characteristics such as Vt of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the second sidewall insulating film thickness 1135 in a direction to return the transistor characteristics changed in the previous process, thereby changing the transistor such as Vt. Compensates for fluctuations in characteristics.

The target deposited film thickness correction unit 233 sets the correction amount at this time as the correlation data between the gate electrode size 1124 or 1125 or an average value thereof and Vt, and the correlation data between the second sidewall insulating film thickness 1135 and Vt. And using Specifically, the target deposition film thickness correction unit 233 increases the corrected target deposition film thickness T _target2 as the gate electrode dimensions 1124 and 1125 are smaller.

(Seventh embodiment)
A production control apparatus 20C according to the seventh embodiment of the present invention is a modification of the production control apparatus 20C according to the fourth embodiment.

The manufacturing control apparatus 20C according to the seventh embodiment of the present invention performs the second sidewall insulation shown in FIG. 10D according to the gate electrode angle 1126 of the nMIS transistor and the gate electrode angle 1127 of the pMIS transistor shown in FIG. 9A. The target deposited film thickness T _target of the film thickness 1135 is changed.

Here, when the gate electrode angles 1126 and 1127 are lowered, the second side wall insulation of the second side wall insulating film 1117 formed by anisotropic etching of the second side wall insulating film 1116 is performed. The film widths 1140 and 1141 are narrowed. As a result, the Vt of the transistor varies. On the other hand, when the gate electrode angles 1126 and 1127 are lowered, the target deposited film thickness correcting unit 233 sets the target deposited film thickness T _target of the second sidewall insulating film thickness 1135 in the previous step. By changing the changed transistor characteristics in the direction of returning, the fluctuation of the transistor characteristics such as Vt is complemented.

The target deposited film thickness correcting unit 233 sets the correction amount at this time as the correlation data between the gate electrode angle 1126 or 1127 or the average value thereof and Vt, and the correlation data between the second sidewall insulating film thickness 1135 and Vt. And using Specifically, the target deposited film thickness correcting unit 233 decreases the corrected target deposited film thickness T _target2 as the gate electrode angles 1126 and 1127 are larger (the taper angle is smaller).

(Eighth embodiment)
A production control apparatus 20C according to the eighth embodiment of the present invention is a modification of the production control apparatus 20C according to the fourth embodiment.

The manufacturing control apparatus 20C according to the eighth embodiment of the present invention performs the second sidewall insulation shown in FIG. 10D according to the gate electrode size 1129 of the nMIS transistor and the gate electrode size 1130 of the pMIS transistor shown in FIG. 9C. The target deposited film thickness T _target of the film thickness 1135 is changed. Here, the gate electrode dimension 1129 is the dimension of the gate electrode including the gate electrode 1100 of the nMIS transistor and the first sidewall insulating film 1106, and is the sum of the gate electrode dimension 1124 and the first sidewall insulating film width 1131. is there. The gate electrode dimension 1130 is the dimension of the gate electrode including the gate electrode 1105 and the first sidewall insulating film 1106 of the pMIS transistor, and is the sum of the gate electrode dimension 1125 and the first sidewall insulating film width 1132. .

Here, when the gate electrode dimensions 1129 and 1130 are narrowed, transistor characteristics such as Vt of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the second sidewall insulating film thickness 1135 in a direction to return the transistor characteristics changed in the previous process, thereby changing the transistor such as Vt. Compensates for fluctuations in characteristics.

The target deposited film thickness correction unit 233 sets the correction amount at this time as the correlation data between the gate electrode size 1129 or 1130 or the average value thereof and Vt, and the correlation data between the second sidewall insulating film thickness 1135 and Vt. And using Specifically, the target deposition film thickness correction unit 233 increases the corrected target deposition film thickness T _target2 as the gate electrode dimensions 1129 and 1130 are smaller.

(Ninth embodiment)
A production control apparatus 20C according to the ninth embodiment of the present invention is a modification of the production control apparatus 20C according to the fourth embodiment.

The manufacturing control apparatus 20C according to the ninth embodiment of the present invention corresponds to the first sidewall insulating film width 1131 of the nMIS transistor and the first sidewall insulating film width 1132 of the pMIS transistor shown in FIG. The target deposited film thickness T _target of the second sidewall insulating film thickness 1135 shown in FIG.

Here, when the first sidewall insulating film widths 1131 and 1132 become narrower, transistor characteristics such as Vt of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the second sidewall insulating film thickness 1135 in a direction to return the transistor characteristics changed in the previous process, thereby changing the transistor such as Vt. Compensates for fluctuations in characteristics.

The target deposited film thickness correction unit 233 sets the correction amount at this time as the first sidewall insulating film width 1131 or 1132, or the correlation data between the average value and Vt, the second sidewall insulating film thickness 1135 and Vt. And the correlation data. Specifically, the target deposited film thickness correcting unit 233 increases the corrected target deposited film thickness T _target2 as the first sidewall insulating film widths 1131 and 1132 are _decreased .

(Tenth embodiment)
A manufacturing control apparatus 20C according to the tenth embodiment of the present invention is a modification of the manufacturing control apparatus 20C according to the fourth embodiment.

The manufacturing control apparatus 20C according to the tenth embodiment of the present invention corresponds to the first sidewall insulating film angle 1133 of the nMIS transistor and the first sidewall insulating film angle 1134 of the pMIS transistor illustrated in FIG. The target deposited film thickness T _target of the second sidewall insulating film thickness 1135 shown in FIG.

Here, when the first sidewall insulating film angles 1133 and 1134 are reduced in taper angle, the second sidewall insulating film 1117 formed by anisotropic etching of the second sidewall insulating film 1116 is performed. 2 side wall insulating film widths 1140 and 1141 become narrower. As a result, the Vt of the transistor varies. In contrast, when the first sidewall insulating film angles 1133 and 1134 are lowered, the target deposited film thickness correcting unit 233 sets the target deposited film thickness T _{target of} the second sidewall insulating film thickness 1135. Is changed in a direction to return the transistor characteristics changed in the previous process, thereby compensating for the change in transistor characteristics such as Vt.

The target deposited film thickness correction unit 233 sets the correction amount at this time to the first sidewall insulating film angle 1133 or 1134, or the correlation data between the average value and Vt, the second sidewall insulating film thickness 1135 and Vt. And the correlation data. Specifically, the target deposited film thickness correcting unit 233 decreases the corrected target deposited film thickness T _target2 as the first sidewall insulating film angles 1133 and 1134 are increased.

(Eleventh embodiment)
A production control apparatus 20C according to the eleventh embodiment of the present invention is a modification of the production control apparatus 20C according to the fourth embodiment.

The manufacturing control apparatus 20C according to the eleventh embodiment of the present invention forms the n-type extension region 1112 of the nMIS transistor and then performs ashing or cleaning processing according to the gate electrode dimension 1136 of the pMIS transistor shown in FIG. 10A. The target deposited film thickness T _target of the second sidewall insulating film thickness 1135 shown in FIG. 10D is changed. Here, the gate electrode dimension 1136 is the dimension of the gate electrode including the gate electrode 1105 and the first sidewall insulating film 1106 of the pMIS transistor, and is the sum of the gate electrode dimension 1125 and the first sidewall insulating film width 1132. is there.

Here, when the gate electrode dimension 1136 of the pMIS transistor becomes thin, transistor characteristics such as Vt of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the second sidewall insulating film thickness 1135 in a direction to return the transistor characteristics changed in the previous process, thereby changing the transistor such as Vt. Compensates for fluctuations in characteristics.

The target deposited film thickness correction unit 233 uses the correlation data between the gate electrode size 1136 and Vt and the correlation data between the second sidewall insulating film thickness 1135 and the pMIS transistor Vt as the correction amount at this time. calculate. Specifically, the target deposited film thickness correcting unit 233 increases the corrected target deposited film thickness T _target2 as the gate electrode size 1136 is smaller.

(Twelfth embodiment)
A manufacturing control apparatus 20C according to the twelfth embodiment of the present invention is a modification of the manufacturing control apparatus 20C according to the fourth embodiment.

The manufacturing control apparatus 20C according to the twelfth embodiment of the present invention forms the n-type extension region 1112 of the nMIS transistor and then undergoes ashing or cleaning treatment, and then the first sidewall insulating film angle of the pMIS transistor shown in FIG. 10A depending on 1137, changing the target deposition thickness T _target of the second side-wall insulating film thickness 1135 shown in FIG. 10D.

Here, when the first sidewall insulating film angle 1137 of the pMIS transistor is lowered, the transistor characteristics such as Vt of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the second sidewall insulating film thickness 1135 in a direction to return the transistor characteristics changed in the previous process, thereby changing the transistor such as Vt. Compensates for fluctuations in characteristics.

The target deposited film thickness correcting unit 233 uses the correlation data between the first sidewall insulating film angle 1137 and Vt, and the correlation data between the second sidewall insulating film thickness 1135 and the pMIS transistor Vt. And using Specifically, the target deposited film thickness correcting unit 233 decreases the corrected target deposited film thickness T _target2 as the first side wall insulating film angle 1137 is larger.

From the above, the manufacturing control apparatus 20C according to the fourth to twelfth embodiments returns the target deposited film thickness in a direction to return the transistor characteristics changed in the previous process in accordance with the dimension, inclination, and film thickness data of the previous process. Change T _target . Thereby, the manufacturing control apparatus 20C according to the fourth to twelfth embodiments can reduce transistor characteristic variation (third film thickness variation) for each process and each product.

In the above description, the manufacturing control apparatus 20C according to the fourth to twelfth embodiments corrects the target deposition thickness T _target of one insulating film based on one measured value 234, respectively. As described above, based on the two or more kinds of measured values 234 described above, the target deposition thickness T _target of one insulating film thickness may be corrected, or the target deposition film of two or more insulating film thicknesses may be corrected. The thickness T _target may be corrected. That is, the manufacturing control apparatus 20C includes the gate electrode dimensions 1124, 1125, 1129, 1130, 1136, the gate electrode angles 1126, 1127, the first sidewall insulating film widths 1131, 1132, the first sidewall insulating film angles 1133, 1134, and One or more of the first sidewall insulating film thickness 1128 and the second sidewall insulating film thickness 1135 may be corrected based on two or more of 1137.

(13th Embodiment)
In the following thirteenth to thirty-seventh embodiments, modifications of the manufacturing control apparatus 20C according to the fourth embodiment will be described.

  In the thirteenth to thirty-seventh embodiments, the case where a semiconductor device is manufactured by a process different from the above-described first to twelfth embodiments will be described.

  First, a method for manufacturing a semiconductor device in the thirteenth to thirty-seventh embodiments will be described.

  FIGS. 17A to 19C are cross-sectional views illustrating the manufacturing steps of the semiconductor device manufactured by the manufacturing system 10 in the thirteenth to thirty-seventh embodiments. In addition, the same code | symbol is attached | subjected to the element similar to FIG. 9A-FIG. 11D, and the overlapping description is abbreviate | omitted.

  In the thirteenth to thirty-seventh embodiments, the manufactured semiconductor device further includes a third sidewall insulating film 1216 and a contact etch stop layer 1226.

  The third sidewall insulating film 1216 is formed between the first sidewall insulating film 1106 and the second sidewall insulating film 1117.

  The contact etch stop layer 1226 is an insulating film formed on the gate electrodes 1100 and 1105. The contact etch stop layer 1226 has a function of applying stress to the channel portion in order to improve the driving capability of the transistor.

  Note that the steps up to the step of removing the resist mask 1113 (FIGS. 9A to 10C) are the same as those in the first to twelfth embodiments, and a description thereof is omitted.

  After removing the resist mask 1113, in the step shown in FIG. 17A, a third sidewall insulating film 1216 made of a silicon oxide film is deposited on the entire surface of the substrate by CVD.

  Next, in the step shown in FIG. 17B, a second sidewall insulating film 1116 made of a silicon nitride film is formed on the entire surface of the substrate by CVD. As a result, the entire nMIS transistor formation region 1001 and the pMIS transistor formation region 1002 including the gate electrode 1100 of the nMIS transistor, the gate electrode 1105 of the pMIS transistor, and the first sidewall insulating film 1106 constitute the third sidewall insulating film 1216 and Covered by the second sidewall insulating film 1116.

  Next, in the step shown in FIG. 18A, the third sidewall insulating film 1216 is subjected to anisotropic dry etching. At that time, the second sidewall insulating film 1116 is used as an etch stop to suppress the substrate damage of the silicon substrate 1104. After that, the second sidewall insulating film 1116 is anisotropically dry etched to selectively form the third sidewall insulating film 1218 on the side surfaces of the gate electrodes 1100 and 1105 and the first sidewall insulating film 1106. At the same time, a second sidewall insulating film 1117 is formed on the side and upper surfaces of the third sidewall insulating film 1218.

Next, in a step shown in FIG. 18B, a resist mask 1118 having an opening on the nMIS transistor formation region 1001 and covering the pMIS transistor formation region 1002 is formed. After that, using the gate electrode 1100, the first sidewall insulating film 1106, the third sidewall insulating film 1218, the second sidewall insulating film 1117, and the resist mask 1118 as a mask, arsenic (As +) ions 1119 that are n-type impurities are used. the implantation energy is about 5KeV～30keV, the dose amount under the conditions of ^{1 × 10 14 ~1 × 10 16} / cm 2. As a result, n-type source / drain regions 1120 are formed in the nMIS transistor formation region 1001.

  Next, in the step shown in FIG. 18C, the resist mask 1118 is removed by ashing. Note that the resist mask 1118 may be removed by performing wet cleaning using a sulfuric acid hydrogen peroxide aqueous solution (SPM), an ammonia hydrogen peroxide aqueous solution (APM), or the like.

  Next, in a step shown in FIG. 19A, a resist mask 1121 having an opening on the pMIS transistor formation region 1002 and covering the nMIS transistor formation region 1001 is formed.

Thereafter, boron (B +) ions 1122 which are p-type impurities are formed using the gate electrode 1105, the first sidewall insulating film 1106, the third sidewall insulating film 1218, the second sidewall insulating film 1117, and the resist mask 1121 as a mask. Are implanted under conditions of an implantation energy of about 5 keV to 20 keV and a dose of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ² . Thereby, the p-type source / drain region 1123 of the pMIS transistor formation region 1002 is formed.

  Next, in a step shown in FIG. 19B, the resist mask 1121 is removed by ashing. Note that the resist mask 1121 may be removed by performing wet cleaning using an aqueous hydrogen peroxide solution (SPM) or an aqueous ammonia hydrogen peroxide solution (APM).

  Next, in a step shown in FIG. 19C, a contact etch stop layer 1226 (insulating film) having a function of applying stress to the channel portion is improved by using the CVD method in order to improve the driving capability of the transistor.

  Thus, a transistor structure in which an implantation process for determining transistor characteristics is performed is formed.

  Thereafter, a product (semiconductor device) is completed through an interlayer insulating film forming process, a contact forming process, a wiring forming process, and a PAD forming process.

  A manufacturing control apparatus 20C according to the thirteenth embodiment that controls film formation of this semiconductor device will be described below. Note that the configuration of the manufacturing control apparatus 20C according to the thirteenth to thirty-seventh embodiments is the same as the configuration illustrated in FIG.

The manufacturing control apparatus 20C according to the thirteenth embodiment of the present invention provides a third sidewall insulating film shown in FIG. 17B according to the gate electrode size 1124 of the nMIS transistor and the gate electrode size 1125 of the pMIS transistor shown in FIG. 9A. The target deposited film thickness T _target of the thickness 1239 is changed.

Here, when the gate electrode dimensions 1124 and 1125 are narrowed, transistor characteristics such as Vt of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the third sidewall insulating film thickness 1239 so as to return the transistor characteristics changed in the previous process, thereby changing the transistor such as Vt. Compensates for fluctuations in characteristics.

The target deposited film thickness correcting unit 233 sets the correction amount at this time as the correlation data between the gate electrode size 1124 or 1125 or the average value thereof and Vt, and the correlation data between the third sidewall insulating film thickness 1239 and Vt. And using Specifically, the target deposition film thickness correction unit 233 increases the corrected target deposition film thickness T _target2 as the gate electrode dimensions 1124 and 1125 are smaller.

(Fourteenth embodiment)
The manufacturing control apparatus 20C according to the fourteenth embodiment of the present invention performs the third sidewall insulation shown in FIG. 17B according to the gate electrode angle 1126 of the nMIS transistor and the gate electrode angle 1127 of the pMIS transistor shown in FIG. 9A. to change the target deposited film thickness T _target with a thickness of 1239.

Here, when the gate electrode angles 1126 and 1127 are lowered, the third sidewall insulating film 1216 and the second sidewall insulating film 1116 are formed by anisotropic etching. The sidewall insulating film widths 1243 and 1244 of the sidewall insulating film 1218 and the second sidewall insulating film 1117 are narrowed. As a result, the Vt of the transistor varies. In contrast, a target deposition thickness correcting unit 233, when the gate electrode angle 1126 and 1127 are low angle reduction is a target deposition thickness T _target of the third side-wall insulating film thickness 1239 in the previous step By changing the changed transistor characteristics in the returning direction, the fluctuation of the transistor characteristics such as Vt is complemented.

The target deposited film thickness correction unit 233 sets the correction amount at this time as the correlation data between the gate electrode angle 1126 or 1127 or the average value thereof and Vt, and the correlation data between the third sidewall insulating film thickness 1239 and Vt. And using Specifically, the target deposited film thickness correcting unit 233 decreases the corrected target deposited film thickness T _target2 as the gate electrode angles 1126 and 1127 are larger (the taper angle is smaller).

(Fifteenth embodiment)
The manufacturing control apparatus 20C according to the fifteenth embodiment of the present invention performs the third sidewall insulation shown in FIG. 17B according to the gate electrode size 1129 of the nMIS transistor and the gate electrode size 1130 of the pMIS transistor shown in FIG. 9C. The target deposited film thickness T _target of the film thickness 1239 is changed.

Here, when the gate electrode dimensions 1129 and 1130 are narrowed, transistor characteristics such as Vt of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the third sidewall insulating film thickness 1239 so as to return the transistor characteristics changed in the previous process to Vt or the like. Compensates for variations in transistor characteristics.

The target deposited film thickness correction unit 233 sets the correction amount at this time as the correlation data between the gate electrode size 1129 or 1130 or the average value thereof and Vt, and the correlation data between the third sidewall insulating film thickness 1239 and Vt. And using Specifically, the target deposition film thickness correction unit 233 increases the corrected target deposition film thickness T _target2 as the gate electrode dimensions 1129 and 1130 are smaller.

(Sixteenth embodiment)
The manufacturing control apparatus 20C according to the sixteenth embodiment of the present invention corresponds to the first sidewall insulating film width 1131 of the nMIS transistor and the first sidewall insulating film width 1132 of the pMIS transistor shown in FIG. The target deposited film thickness T _target of the third sidewall insulating film thickness 1239 shown in FIG.

Here, when the first sidewall insulating film widths 1131 and 1132 become narrower, transistor characteristics such as Vt of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the third sidewall insulating film thickness 1239 so as to return the transistor characteristics changed in the previous process to Vt or the like. Compensates for variations in transistor characteristics.

The target deposited film thickness correcting unit 233 sets the correction amount at this time as the first sidewall insulating film width 1131 or 1132, or the correlation data between the average value and Vt, the third sidewall insulating film thickness 1239, and Vt. And the correlation data. Specifically, the target deposited film thickness correcting unit 233 increases the corrected target deposited film thickness T _target2 as the first sidewall insulating film widths 1131 and 1132 are _decreased .

(Seventeenth embodiment)
The manufacturing control apparatus 20C according to the seventeenth embodiment of the present invention corresponds to the first sidewall insulating film angle 1133 of the nMIS transistor shown in FIG. 9C and the first sidewall insulating film angle 1134 of the pMIS transistor shown in FIG. The target deposited film thickness T _target of the third sidewall insulating film thickness 1239 shown in FIG.

Here, when the first sidewall insulating film angles 1133 and 1134 are lowered, the third sidewall insulating film 1216 and the second sidewall insulating film 1116 are formed by anisotropic etching. The sidewall insulating film widths 1243 and 1244 of the third sidewall insulating film 1218 and the second sidewall insulating film 1117 are narrowed. As a result, the Vt of the transistor varies. On the other hand, when the first sidewall insulating film angles 1133 and 1134 are lowered, the target deposited film thickness correcting unit 233 sets the target deposited film thickness T _{target of} the third sidewall insulating film thickness 1239. Is changed in a direction to return the transistor characteristics changed in the previous process to compensate for the change in transistor characteristics such as Vt.

The target deposited film thickness correcting unit 233 sets the correction amount at this time as the first sidewall insulating film angle 1133 or 1134, or correlation data between the average value and Vt, and the third sidewall insulating film thickness 1239 and Vt. And the correlation data. Specifically, the target deposited film thickness correcting unit 233 decreases the corrected target deposited film thickness T _target2 as the first sidewall insulating film angles 1133 and 1134 are increased.

(Eighteenth embodiment)
The manufacturing control apparatus 20C according to the eighteenth embodiment of the present invention forms the n-type extension region 1112 of the nMIS transistor and then performs an ashing or cleaning process according to the gate electrode dimension 1136 of the pMIS transistor shown in FIG. 10A. Then, the target deposited film thickness T _target of the third sidewall insulating film thickness 1239 shown in FIG. 17B is changed.

Here, when the gate electrode dimension 1136 of the pMIS transistor becomes thin, transistor characteristics such as Vt of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the third sidewall insulating film thickness 1239 so as to return the transistor characteristics changed in the previous process to Vt or the like. Compensates for variations in transistor characteristics.

The target deposited film thickness correction unit 233 sets the correction amount at this time to the correlation data between the gate electrode dimension 1136 including the first sidewall insulating film 1106 of pMIS and Vt, the third sidewall insulating film thickness 1239, and pMIS. Calculation is performed using correlation data with Vt of the transistor. Specifically, the target deposited film thickness correcting unit 233 increases the corrected target deposited film thickness T _target2 as the gate electrode size 1136 is smaller.

(Nineteenth embodiment)
The manufacturing control apparatus 20C according to the nineteenth embodiment of the present invention forms the n-type extension region 1112 of the nMIS transistor and then undergoes ashing or cleaning treatment, and then the first sidewall insulating film angle of the pMIS transistor shown in FIG. 10A In accordance with 1137, the target deposition thickness T _target of the third sidewall insulating film thickness 1239 shown in FIG. 17B is changed.

Here, when the first sidewall insulating film angle 1137 of the pMIS transistor becomes a low taper angle, transistor characteristics such as Vt of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the third sidewall insulating film thickness 1239 so as to return the transistor characteristics changed in the previous process to Vt or the like. Compensates for variations in transistor characteristics.

The target deposited film thickness correcting unit 233 uses the correlation data between the first sidewall insulating film angle 1137 and Vt and the correlation data between the third sidewall insulating film thickness 1239 and the pMIS transistor Vt. And using Specifically, the target deposited film thickness correcting unit 233 decreases the corrected target deposited film thickness T _target2 as the first side wall insulating film angle 1137 is larger.

(20th embodiment)
The manufacturing control apparatus 20C according to the twentieth embodiment of the present invention performs the second sidewall insulation shown in FIG. 10D according to the gate electrode size 1124 of the nMIS transistor and the gate electrode size 1125 of the pMIS transistor shown in FIG. 9A. The target deposited film thickness T _target of the film thickness 1135 is changed.

Here, when the gate electrode dimensions 1124 and 1125 are narrowed, transistor characteristics such as Vt of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the second sidewall insulating film thickness 1135 to a direction in which the transistor characteristics changed in the previous process are returned, such as Vt. Compensates for variations in transistor characteristics.

The target deposited film thickness correction unit 233 sets the correction amount at this time as the correlation data between the gate electrode size 1124 or 1125 or an average value thereof and Vt, and the correlation data between the second sidewall insulating film thickness 1135 and Vt. And using Specifically, the target deposition film thickness correction unit 233 increases the corrected target deposition film thickness T _target2 as the gate electrode dimensions 1124 and 1125 are smaller.

(21st Embodiment)
The manufacturing control apparatus 20C according to the twenty-first embodiment of the present invention performs the second sidewall insulation shown in FIG. 10D according to the gate electrode angle 1126 of the nMIS transistor and the gate electrode angle 1127 of the pMIS transistor shown in FIG. 9A. to change the target deposited film thickness T _target with a thickness of 1135.

Here, when the gate electrode angles 1126 and 1127 are lowered, the third sidewall insulating film 1216 and the second sidewall insulating film 1116 are formed by anisotropic etching. The sidewall insulating film widths 1243 and 1244 of the sidewall insulating film 1218 and the second sidewall insulating film 1117 are narrowed. As a result, the Vt of the transistor varies. In contrast, when the gate electrode angles 1126 and 1127 are lowered, the target deposited film thickness correcting unit 233 sets the target deposited film thickness T _target of the second sidewall insulating film thickness 1135 to the previous process. The change in the transistor characteristics such as Vt is complemented by changing the direction in which the transistor characteristics changed in step 1 are restored.

The target deposited film thickness correcting unit 233 sets the correction amount at this time as the correlation data between the gate electrode angle 1126 or 1127 or the average value thereof and Vt, and the correlation data between the second sidewall insulating film thickness 1135 and Vt. And using Specifically, the target deposited film thickness correcting unit 233 decreases the corrected target deposited film thickness T _target2 as the gate electrode angles 1126 and 1127 are increased.

(Twenty-second embodiment)
The manufacturing control apparatus 20C according to the twenty-second embodiment of the present invention performs the second sidewall insulation shown in FIG. 10D according to the gate electrode size 1129 of the nMIS transistor and the gate electrode size 1130 of the pMIS transistor shown in FIG. 9C. The target deposited film thickness T _target of the film thickness 1135 is changed.

Here, when the gate electrode dimensions 1129 and 1130 are narrowed, transistor characteristics such as Vt of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the second sidewall insulating film thickness 1135 to a direction in which the transistor characteristics changed in the previous process are returned, such as Vt. Compensates for variations in transistor characteristics.

The target deposited film thickness correction unit 233 sets the correction amount at this time as the correlation data between the gate electrode size 1129 or 1130 or the average value thereof and Vt, and the correlation data between the second sidewall insulating film thickness 1135 and Vt. And using Specifically, the target deposition film thickness correction unit 233 increases the corrected target deposition film thickness T _target2 as the gate electrode dimensions 1129 and 1130 are smaller.

(23rd embodiment)
The manufacturing control apparatus 20C according to the twenty-third embodiment of the present invention corresponds to the first sidewall insulating film width 1131 of the nMIS transistor and the first sidewall insulating film width 1132 of the pMIS transistor shown in FIG. The target deposited film thickness T _target of the second sidewall insulating film thickness 1135 shown in FIG.

Here, when the first sidewall insulating film widths 1131 and 1132 become narrower, transistor characteristics such as Vt of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the second sidewall insulating film thickness 1135 to a direction in which the transistor characteristics changed in the previous process are returned, such as Vt. Compensates for variations in transistor characteristics.

The target deposited film thickness correction unit 233 sets the correction amount at this time as the first sidewall insulating film width 1131 or 1132, or the correlation data between the average value and Vt, the second sidewall insulating film thickness 1135 and Vt. And the correlation data. Specifically, the target deposition thickness correcting unit 233, as the first sidewall insulating film width 1131 and 1132 is small, to increase the corrected target deposition thickness T _target2.

(24th Embodiment)
The manufacturing control apparatus 20C according to the twenty-fourth embodiment of the present invention corresponds to the first sidewall insulating film angle 1133 of the nMIS transistor and the first sidewall insulating film angle 1134 of the pMIS transistor illustrated in FIG. The target deposited film thickness T _target of the second sidewall insulating film thickness 1135 shown in FIG.

Here, when the first sidewall insulating film angles 1133 and 1134 are lowered, the third sidewall insulating film 1216 and the second sidewall insulating film 1116 are formed by anisotropic etching. The sidewall insulating film widths 1243 and 1244 of the third sidewall insulating film 1218 and the second sidewall insulating film 1117 are narrowed. As a result, the Vt of the transistor varies. In contrast, when the first sidewall insulating film angles 1133 and 1134 are lowered, the target deposited film thickness correcting unit 233 sets the target deposited film thickness T _{target of} the second sidewall insulating film thickness 1135. Is changed in a direction to return the transistor characteristics changed in the previous process to compensate for the change in transistor characteristics such as Vt.

The target deposited film thickness correction unit 233 sets the correction amount at this time to the first sidewall insulating film angle 1133 or 1134, or the correlation data between the average value and Vt, the second sidewall insulating film thickness 1135 and Vt. And the correlation data. Specifically, the target deposited film thickness correcting unit 233 decreases the corrected target deposited film thickness T _target2 as the first sidewall insulating film angles 1133 and 1134 are increased.

(25th Embodiment)
The manufacturing control apparatus 20C according to the twenty-fifth embodiment of the present invention forms the n-type extension region 1112 of the nMIS transistor, and then undergoes ashing or cleaning processing in accordance with the gate electrode dimension 1136 of the pMIS transistor shown in FIG. 10A. The target deposited film thickness T _target of the second sidewall insulating film thickness 1135 shown in FIG. 10D is changed.

Here, when the gate electrode dimension 1136 of the pMIS transistor becomes thin, transistor characteristics such as Vt of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the second sidewall insulating film thickness 1135 to a direction in which the transistor characteristics changed in the previous process are returned, such as Vt. Compensates for variations in transistor characteristics.

The target deposited film thickness correction unit 233 sets the correction amount at this time to the correlation data between the gate electrode dimension 1136 including the first sidewall insulating film 1106 of pMIS and Vt, the second sidewall insulating film thickness 1135 and the pMIS. Calculation is performed using correlation data with Vt of the transistor. Specifically, the target deposited film thickness correcting unit 233 increases the corrected target deposited film thickness T _target2 as the gate electrode size 1136 is smaller.

(26th Embodiment)
The manufacturing control apparatus 20C according to the twenty-sixth embodiment of the present invention performs the ashing or cleaning process after forming the n-type extension region 1112 of the nMIS transistor and the first sidewall insulating film angle of the pMIS transistor shown in FIG. 10A. depending on 1137, changing the target deposition thickness T _target of the second side-wall insulating film thickness 1135 shown in FIG. 10D.

Here, when the first sidewall insulating film angle 1137 of the pMIS transistor becomes a low taper angle, transistor characteristics such as Vt of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the second sidewall insulating film thickness 1135 to a direction in which the transistor characteristics changed in the previous process are returned, such as Vt. Compensates for variations in transistor characteristics.

The target deposited film thickness correcting unit 233 uses the correlation data between the first sidewall insulating film angle 1137 and Vt, and the correlation data between the second sidewall insulating film thickness 1135 and the pMIS transistor Vt. And using Specifically, the target deposited film thickness correcting unit 233 decreases the corrected target deposited film thickness T _target2 as the first side wall insulating film angle 1137 is larger.

(Twenty-seventh embodiment)
The manufacturing control apparatus 20C according to the twenty-seventh embodiment of the present invention provides a target deposition film having the second sidewall insulating film thickness 1135 shown in FIG. 10D according to the third sidewall insulating film thickness 1239 shown in FIG. 17B. Change the thickness T _target .

Here, when the third sidewall insulating film thickness 1239 is reduced, transistor characteristics such as Vt of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the second sidewall insulating film thickness 1135 to a direction in which the transistor characteristics changed in the previous process are returned, such as Vt. Compensates for variations in transistor characteristics.

The target deposited film thickness correction unit 233 uses the correlation data between the third sidewall insulating film thickness 1239 and Vt and the correlation data between the second sidewall insulating film thickness 1135 and Vt as the correction amount at this time. Use to calculate. Specifically, the target deposition thickness correcting unit 233, as the third sidewall insulation film thickness 1239 is small, to increase the corrected target deposition thickness T _target2.

(Twenty-eighth embodiment)
The manufacturing control apparatus 20C according to the twenty-eighth embodiment of the present invention has a deposited film thickness of the contact etch stop layer 1226 according to the gate electrode dimension 1124 of the nMIS transistor and the gate electrode dimension 1125 of the pMIS transistor shown in FIG. 9A. The target deposited film thickness T _target of a certain contact etch stop film thickness 1245 is changed.

Here, when the gate electrode dimensions 1124 and 1125 are narrowed, transistor characteristics such as transistor drive capability vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the contact etch stop film thickness 1245 in a direction to return the transistor characteristics that have been changed in the previous process, so that the transistor characteristics such as the driving capability. To compensate for fluctuations in

  The target deposited film thickness correction unit 233 uses the gate electrode size 1124 or 1125 or correlation data between the average value and the driving capability and correlation data between the contact etch stop film thickness 1245 and the driving capability as the correction amount at this time. calculate.

  Here, depending on the direction of internal stress (compressive stress or tensile stress) generated by the contact etch stop layer 1226 and whether the transistor is an nMIS transistor or a pMIS transistor, the effect on the driving ability is reversed. Specifically, the target deposited film thickness correcting unit 233 has a contact etch stop film thickness so that the tensile stress is increased (the compressive stress is decreased) in the channel portion for the nMIS transistor when the driving capability is reduced. 1245 is changed. Further, if the contact etch stop layer 1226 gives a compressive stress to the channel portion, the target deposited film thickness correction unit 233 decreases the contact etch stop film thickness 1245.

(Twenty-ninth embodiment)
The manufacturing control apparatus 20C according to the twenty-ninth embodiment of the present invention has a contact etch stop film thickness 1245 shown in FIG. 19C according to the gate electrode angle 1126 of the nMIS transistor and the gate electrode angle 1127 of the pMIS transistor shown in FIG. 9A. The target deposited film thickness T _target is changed.

Here, when the gate electrode angles 1126 and 1127 are lowered, the third sidewall insulating film 1218 formed by anisotropically etching the third sidewall insulating film 1216 and the contact etch stop layer 1226. The sidewall insulating film widths 1243 and 1244 of the second sidewall insulating film 1117 are narrowed. As a result, the driving capability of the transistor varies. On the other hand, when the gate electrode angles 1126 and 1127 are lowered, the target deposited film thickness correction unit 233 changes the target deposited film thickness T _target of the contact etch stop film thickness 1245 in the previous process. By changing the direction to return the transistor characteristics, the fluctuation of the transistor characteristics such as driving ability is compensated.

  The target deposited film thickness correction unit 233 uses the gate electrode angle 1126 or 1127, or the correlation data between the average value and the driving capability, and the correlation data between the contact etch stop film thickness 1245 and the driving capability as the correction amount at this time. Calculate using.

(Thirty embodiment)
The manufacturing control apparatus 20C according to the thirtieth embodiment of the present invention has a contact etch stop film thickness 1245 shown in FIG. 19C according to the gate electrode size 1129 of the nMIS transistor and the gate electrode size 1130 of the pMIS transistor shown in FIG. 9C. The target deposited film thickness T _target is changed.

Here, when the gate electrode dimensions 1129 and 1130 are narrowed, transistor characteristics such as transistor drive capability vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the contact etch stop film thickness 1245 in a direction to return the transistor characteristics that have been changed in the previous process, so that the transistor characteristics such as the driving capability. To compensate for fluctuations in

  The target deposited film thickness correction unit 233 determines the correction amount at this time from the correlation data between the gate electrode size 1129 or 1130 or the average value thereof and the driving capability, and the correlation data between the contact etch stop film thickness 1245 and the driving capability. calculate.

(Thirty-first embodiment)
The manufacturing control apparatus 20C according to the thirty-first embodiment of the present invention corresponds to the first sidewall insulating film width 1131 of the nMIS transistor and the first sidewall insulating film width 1132 of the pMIS transistor shown in FIG. The target deposited film thickness T _target of the contact etch stop film thickness 1245 shown in FIG.

Here, when the first sidewall insulating film widths 1131 and 1132 are narrowed, transistor characteristics such as transistor driving capability vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the contact etch stop film thickness 1245 in a direction to return the transistor characteristics that have been changed in the previous process, so that the transistor characteristics such as the driving capability. To compensate for fluctuations in

  The target deposited film thickness correction unit 233 sets the correction amount at this time as the first sidewall insulating film width 1131 or 1132, or the correlation data between the average value and the drive capability, the contact etch stop film thickness 1245, and the drive capability. And the correlation data.

(Thirty-second embodiment)
The manufacturing control apparatus 20C according to the thirty-second embodiment of the present invention operates in accordance with the first sidewall insulating film angle 1133 of the nMIS transistor and the first sidewall insulating film angle 1134 of the pMIS transistor shown in FIG. The target deposited film thickness T _target of the contact etch stop film thickness 1245 shown in FIG.

Here, when the first sidewall insulating film angles 1133 and 1134 are lowered, the third sidewall insulating film 1216 and the second sidewall insulating film 1116 are formed by anisotropic etching. The sidewall insulating film widths 1243 and 1244 of the third sidewall insulating film 1218 and the second sidewall insulating film 1117 are narrowed. As a result, the driving capability of the transistor varies. On the other hand, when the first sidewall insulating film angles 1133 and 1134 are lowered, the target deposited film thickness correcting unit 233 sets the target deposited film thickness T _target of the contact etch stop film thickness 1245 as the previous deposited film thickness T _target . Changes in transistor characteristics such as drive capability are complemented by changing the transistor characteristics changed in the process to return.

  The target deposited film thickness correcting unit 233 sets the correction amount at this time as the first sidewall insulating film angle 1133 or 1134, or the correlation data between the average value and the driving ability, the contact etch stop film thickness 1245, and the driving ability. And the correlation data.

(Thirty-third embodiment)
The manufacturing control apparatus 20C according to the thirty-third embodiment of the present invention forms the n-type extension region 1112 of the nMIS transistor and then undergoes ashing or cleaning treatment, according to the gate electrode dimension 1136 of the pMIS transistor shown in FIG. 10A. 19C, the target deposited film thickness T _target of the contact etch stop film thickness 1245 shown in FIG. 19C is changed.

Here, when the gate electrode dimension 1136 of the pMIS transistor becomes thin, transistor characteristics such as the driving capability of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the contact etch stop film thickness 1245 in a direction to return the transistor characteristics that have been changed in the previous process, so that the transistor characteristics such as the driving capability. To compensate for fluctuations in

  The target deposited film thickness correction unit 233 sets the correction amount at this time to the correlation data between the gate electrode size 1136 including the first sidewall insulating film 1106 of the pMIS and the driving capability, the contact etch stop film thickness 1245 and the pMIS transistor. Calculation is performed using correlation data with driving ability.

(Thirty-fourth embodiment)
The manufacturing control apparatus 20C according to the thirty-fourth embodiment of the present invention performs the ashing or cleaning process after forming the n-type extension region 1112 of the nMIS transistor, and the first sidewall insulating film angle of the pMIS transistor shown in FIG. 10A In response to 1137, the target deposited film thickness T _target of the contact etch stop film thickness 1245 shown in FIG. 19C is changed.

Here, when the first sidewall insulating film angle 1137 of the pMIS transistor becomes a low taper angle, transistor characteristics such as the driving capability of the transistor vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the contact etch stop film thickness 1245 in a direction to return the transistor characteristics that have been changed in the previous process, so that the transistor characteristics such as the driving capability. To compensate for fluctuations in

  The target deposited film thickness correction unit 233 sets the correction amount at this time to correlation data between the first sidewall insulating film angle 1137 and the driving capability, and correlation data between the contact etch stop film thickness 1245 and the driving capability of the pMIS transistor. Calculate using.

(Thirty-fifth embodiment)
In accordance with the third sidewall insulating film thickness 1239 shown in FIG. 17B, the manufacturing control apparatus 20C according to the thirty-fifth embodiment of the present invention has a target deposited film thickness T _target of the contact etch stop film thickness 1245 shown in FIG. 19C. To change.

Here, when the third sidewall insulating film thickness 1239 is reduced, transistor characteristics such as transistor drive capability vary. In contrast, a target deposition thickness correction section 233, the transistor characteristics such as driving capability by changing a target deposition thickness T _target contact etch stop film thickness 1245, the direction of returning the transistor characteristics vary in the previous step To compensate for fluctuations in

  The target deposited film thickness correcting unit 233 uses the correlation data between the third sidewall insulating film thickness 1239 and the driving capability and the correlation data between the contact etch stop film thickness 1245 and the driving capability as the correction amount at this time. To calculate.

(Thirty-sixth embodiment)
The manufacturing control apparatus 20C according to the thirty-sixth embodiment of the present invention includes the first sidewall insulating film 1106, the third sidewall insulating film 1218, and the second sidewall insulating film 1117, and the gate electrode dimension 1241 shown in FIG. 18A. And 1242, the target deposited film thickness T _target of the contact etch stop film thickness 1245 shown in FIG. 19C is changed.

Here, when the gate electrode dimensions 1241 and 1242 are narrowed, transistor characteristics such as transistor drive capability vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the contact etch stop film thickness 1245 in a direction to return the transistor characteristics that have been changed in the previous process, so that the transistor characteristics such as the driving capability. To compensate for fluctuations in

  The target deposited film thickness correction unit 233 sets the correction amount at this time to the correlation data between the gate electrode dimension 1241 or 1242 or the average value thereof and the driving capability, and the correlation data between the contact etch stop film thickness 1245 and the driving capability. Calculate using.

(Thirty-seventh embodiment)
The manufacturing control apparatus 20C according to the thirty-seventh embodiment of the present invention includes the third sidewall insulating film 1216 and the second sidewall insulating film 1116, according to the sidewall insulating film widths 1243 and 1244 shown in FIG. 18A. 19C, the target deposited film thickness T _target of the contact etch stop film thickness 1245 shown in FIG. 19C is changed.

Here, when the sidewall insulating film widths 1243 and 1244 are narrowed, transistor characteristics such as transistor drive capability vary. On the other hand, the target deposited film thickness correcting unit 233 changes the target deposited film thickness T _target of the contact etch stop film thickness 1245 in a direction to return the transistor characteristics that have been changed in the previous process, so that the transistor characteristics such as the driving capability. To compensate for fluctuations in

  The target deposited film thickness correction unit 233 sets the correction amount at this time as the correlation data between the sidewall insulating film width 1243 or 1244 or the average value thereof and the driving ability, and the correlation data between the contact etch stop film thickness 1245 and the driving ability. Calculate from

(Thirty-eighth embodiment)
A manufacturing control apparatus 20C according to the thirty-eighth embodiment is a modification of the thirteenth to thirty-seventh embodiments described above. In the thirty-eighth embodiment, the case where a semiconductor device is manufactured by a process different from the thirteenth to thirty-seventh embodiments described above will be described.

  In the method for manufacturing a semiconductor device according to the thirty-eighth embodiment, the second sidewall insulating film 1117 is removed, and then the contact etch stop layer 1226 is formed.

  Note that the steps up to the step shown in FIG.

  20A and 20B are cross-sectional views showing a manufacturing process of a semiconductor device manufactured by the manufacturing system 10 in the thirty-eighth embodiment.

  After the step of FIG. 19B, as shown in FIG. 20A, the second sidewall insulating film 1117 is removed by wet etching in order to further improve the transistor capability.

  Next, as shown in FIG. 20B, a contact etch stop layer 1226 is formed.

  Even in such a process, the same manufacturing control apparatus 20C as in the thirteenth to thirty-seventh embodiments described above can be realized.

As described above, in the manufacturing control apparatus 20C according to the thirteenth to thirty-eighth embodiments, the target deposited film thickness T _target is changed in the previous process in accordance with the dimension, inclination, and film thickness data of the previous process. The target deposited film thickness T _target is changed in the direction of returning. Thereby, the manufacturing control apparatus 20C according to the thirteenth to thirty-eighth embodiments can reduce transistor characteristic variation (third film thickness variation) for each process and each product.

In the above description, manufacturing control device 20C according to a thirteenth 38 embodiment of, based on one measurement 234, respectively, an example of correcting a target deposition thickness T _target thickness of one insulating layer As described above, based on the two or more kinds of measured values 234 described above, the target deposition thickness T _target of one insulating film thickness may be corrected, or the target deposition film of two or more insulating film thicknesses may be corrected. The thickness T _target may be corrected.

(39th Embodiment)
In the following 39th to 44th embodiments of the present invention, modified examples of the production control device 20 according to the first embodiment will be described.

  In the thirty-ninth to forty-fourth embodiments, a case where a semiconductor device is manufactured by a process different from that of the first embodiment described above will be described.

  First, a method for manufacturing a semiconductor device in the thirty-ninth to forty-fourth embodiments will be described.

  In the method for manufacturing a semiconductor device according to the thirty-ninth to forty-fourth embodiments, after removing the gate electrodes 1100 and 1105 formed of polysilicon or the like, a gate electrode is formed using a metal material.

  21A to 23C are cross-sectional views illustrating the manufacturing process of the semiconductor device manufactured by the manufacturing system 10 in the thirty-ninth to forty-fourth embodiments. In addition, the same code | symbol is attached | subjected to the element similar to FIG. 9A-FIG. 10C and FIG. 17A-FIG. 19C, and the overlapping description is abbreviate | omitted.

  The manufacturing method of the semiconductor device in the thirty-ninth to forty-fourth embodiments further includes a process after the process of FIG. 19C described above.

  Note that the steps up to the step of FIG.

  After the step shown in FIG. 19C, in the next step shown in FIG. 21A, an interlayer insulating film 1327 is deposited using the CVD method.

  Next, in the step shown in FIG. 21B, planarization is performed by performing mechanical chemical polishing (CMP) to expose the polysilicon layers (gate electrodes 1100 and 1105).

  Next, in the step shown in FIG. 22A, the exposed gate electrodes 1100 and 1105 are removed using a chemical solution containing a low-concentration aqueous ammonia solution.

  Next, in a step shown in FIG. 22B, a gate electrode material 1328 having a low work function such as Al, Ta, Mo, Ti, Hf, TaN, Nb, or TiN is embedded in the removed portion by a CVD method.

  Next, in the step shown in FIG. 22C, excess gate electrode material 1328 is removed by polishing using CMP.

  Next, in a step shown in FIG. 23A, a resist mask 1329 having an opening on the pMIS transistor formation region 1002 and covering the nMIS transistor formation region 1001 is formed.

  Thereafter, the gate electrode material 1328 embedded in the pMIS transistor formation region 1002 is removed by wet etching. After that, the resist mask 1329 is removed by wet cleaning or the like.

Next, in a step shown in FIG. 23B, a gate electrode material 1330 having a high work function such as RuO ₂ , Ir, Pt, WN, Mo ₂ N, TaN, Au, or Ni is embedded in the removed portion by a CVD method.

  Next, in the step shown in FIG. 23C, excess gate electrode material 1330 is polished by CMP until the surface of the gate electrode material 1328 in the nMIS transistor formation region 1001 is exposed.

  Thus, a transistor structure in which an implantation process for determining transistor characteristics is performed is formed.

  Thereafter, a product (semiconductor device) is completed through an interlayer insulating film forming process, a contact forming process, a wiring forming process, and a PAD forming process.

  Next, the configuration of the manufacturing control apparatus 20D according to the 39th to 44th embodiments of the present invention will be described.

  The manufacturing control apparatus 20D according to the thirty-nineth to fourty-fourth embodiments of the present invention changes the work function of the gate electrode materials 1328 and 1330 according to the size, inclination, and film thickness data of the previous process, and thereby processes and products Each transistor characteristic variation (third film thickness variation) is reduced.

  FIG. 24 is a block diagram showing a configuration of a production control apparatus 20D according to the 39th to 44th embodiments of the present invention. In addition, the same code | symbol is attached | subjected to the element similar to FIG. 6, and the overlapping description is abbreviate | omitted. The manufacturing control apparatus 20D further includes a third processing unit 23.

  The third processing unit 23 includes a measurement value acquisition unit 241, a measurement value storage unit 242, a gate electrode characteristic determination unit 243, a gate electrode characteristic storage unit 244, and a gate electrode characteristic output unit 245.

  The measurement value acquisition unit 241 acquires, from the measurement device 40, a measurement value 251 that is measured by the measurement device 40 and indicates the shape of the structure formed on the wafer after the first process of the second lot.

  The measurement value accumulation unit 242 accumulates the measurement value 251 acquired by the measurement value acquisition unit 241.

  The gate electrode characteristic determination unit 243 determines the gate electrode characteristic 252 according to the measurement value 251 stored in the measurement value storage unit 242. Here, the gate electrode characteristics 252 are, for example, characteristics of the nMIS gate electrode material 1328 or the pMIS gate electrode material 1330, and specifically, the film type, film quality, or film thickness (1349 or 1350). In addition, the gate electrode characteristic determining unit 243 determines the gate electrode characteristic 252 so as to return the transistor characteristics such as the changed Vt in the first step of the second lot.

  The gate electrode characteristic accumulation unit 244 accumulates the gate electrode characteristic 252 determined by the gate electrode characteristic determination unit 243.

  The gate electrode characteristic output unit 245 outputs the gate electrode characteristic 252 accumulated by the gate electrode characteristic accumulation unit 244 to the film forming apparatus 30.

  In addition, the film forming apparatus 30 generates the gate electrode material 1328 or 1330 with the gate electrode characteristic 252 output by the gate electrode characteristic output unit 245 in the second step of the second lot.

  Here, a case where the manufacturing control apparatus 20D changes the film type (gate electrode characteristic 252) of the nMIS gate electrode material 1328 according to the gate electrode dimension 1124 (measured value 251) of the nMIS transistor shown in FIG. 9A will be described. .

  Here, when the gate electrode dimension 1124 is reduced, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the work function of the nMIS gate electrode material 1328 so as to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determining unit 243 complements the variation in transistor characteristics such as Vt by changing the film type of the nMIS gate electrode material 1328 so as to have a desired work function. For example, the gate electrode characteristic determining unit 243 changes the nMIS gate electrode material 1328 to another metal having a necessary work function, or changes the N amount of TaN. Specifically, Vt can be reduced by reducing the work function.

  The gate electrode characteristic determining unit 243 calculates the correction amount at this time using the correlation data between the gate electrode size 1124 and Vt and the correlation data between the film type of the nMIS gate electrode material 1328 and Vt. Specifically, the gate electrode characteristic determination unit 243 decreases the work function of the nMIS gate electrode material 1328 as the gate electrode size 1124 decreases.

(40th embodiment)
The manufacturing control apparatus 20D according to the fortieth embodiment changes the film quality of the nMIS gate electrode material 1328 according to the gate electrode dimension 1124 of the nMIS transistor shown in FIG. 9A.

  Here, when the gate electrode dimension 1124 is reduced, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the work function of the nMIS gate electrode material 1328 so as to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determining unit 243 changes the transistor characteristics such as Vt by changing the film quality of the nMIS gate electrode material 1328 (for example, the crystal structure of TaN) to a desired work function. Complement minutes.

  The gate electrode characteristic determining unit 243 calculates the correction amount at this time using the correlation data between the gate electrode size 1124 and Vt and the correlation data between the film quality of the nMIS gate electrode material and Vt.

(41st embodiment)
The manufacturing control apparatus 20D according to the forty-first embodiment changes the nMIS gate electrode film thickness 1349, which is the film thickness of the nMIS gate electrode material 1328 shown in FIG. 23C, according to the gate electrode dimension 1124 of the nMIS transistor shown in FIG. 9A. To do.

  Here, when the gate electrode dimension 1124 is reduced, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the work function of the nMIS gate electrode material 1328 so as to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determining unit 243 changes the nMIS gate electrode film thickness 1349 to a film thickness that provides a desired work function by changing the polishing thickness during CMP. This compensates for variations in transistor characteristics such as Vt.

  The gate electrode characteristic determination unit 243 calculates the correction amount at this time using correlation data between the gate electrode size 1124 and Vt and correlation data between the nMIS gate electrode film thickness 1349 and Vt. Specifically, the gate electrode characteristic determining unit 243 decreases the nMIS gate electrode film thickness 1349 as the gate electrode dimension 1124 is smaller.

(Forty-second embodiment)
The manufacturing control apparatus 20D according to the forty-second embodiment changes the film type of the pMIS gate electrode material 1330 according to the gate electrode dimension 1125 of the pMIS transistor shown in FIG. 9A.

  Here, when the gate electrode dimension 1125 is narrowed, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the work function of the pMIS gate electrode material 1330 to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determining unit 243 compensates for the variation in transistor characteristics such as Vt by changing the film type of the pMIS gate electrode material 1330 to have a desired work function. For example, the gate electrode characteristic determining unit 243 changes the pMIS gate electrode material 1330 to another metal having a necessary work function, or changes the N amount of TaN.

  The gate electrode characteristic determination unit 243 calculates the correction amount at this time using the correlation data between the gate electrode dimension 1125 and Vt and the correlation data between the film type of the pMIS gate electrode material and Vt. Specifically, the gate electrode characteristic determination unit 243 decreases the work function of the pMIS gate electrode material 1330 as the gate electrode size 1125 is smaller.

(43rd embodiment)
The manufacturing control apparatus 20D according to the forty-third embodiment changes the film quality of the pMIS gate electrode material 1330 according to the gate electrode size 1125 of the pMIS transistor shown in FIG. 9A.

  Here, when the gate electrode dimension 1125 is narrowed, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the work function of the pMIS gate electrode material 1330 to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determining unit 243 changes the transistor characteristics such as Vt by changing the film quality of the pMIS gate electrode material 1330 (for example, the crystal structure of TaN) to have a desired work function. To complement.

  The gate electrode characteristic determining unit 243 calculates the correction amount at this time using the correlation data between the gate electrode size 1125 and Vt and the correlation data between the film quality of the pMIS gate electrode material and Vt.

(44th Embodiment)
The manufacturing control apparatus 20D according to the forty-fourth embodiment changes the pMIS gate electrode film thickness 1350 shown in FIG. 23C according to the gate electrode size 1125 of the pMIS transistor shown in FIG. 9A.

  Here, when the gate electrode dimension 1125 is narrowed, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the work function of the pMIS gate electrode material 1330 to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determination unit 243 changes the thickness of the pMIS gate electrode 1350 after CMP to a thickness that provides a desired work function by changing the polishing thickness at the time of CMP. This compensates for variations in transistor characteristics such as Vt.

  The gate electrode characteristic determination unit 243 calculates the correction amount at this time using correlation data between the gate electrode size 1125 and Vt and correlation data between the pMIS gate electrode film thickness 1350 and Vt. Specifically, the gate electrode characteristic determining unit 243 decreases the pMIS gate electrode film thickness 1350 as the gate electrode dimension 1125 is smaller.

  In the thirty-ninth to forty-fourth embodiments, the case where the film type, film quality, or film thickness (1349 or 1350) of the gate electrode materials 1328 and 1330 is corrected according to the gate electrode size 1124 or 1125 has been described. , NMIS gate electrode angle 1126, pMIS gate electrode angle 1127, first sidewall insulating film thickness 1128, nMIS gate electrode dimension 1129, pMIS gate electrode dimension 1130, nMIS first sidewall insulating film angle 1133, pMIS first sidewall Insulating film angle 1134, nMIS gate electrode first sidewall insulating film width 1131, pMIS gate electrode first sidewall insulating film width 1132, third sidewall insulating film thickness 1239, second sidewall insulating film thickness 1135 , NMIS gate electrode dimension 1241, pMIS gate electrode dimension 1242, nMIS sidewall insulating film width 12 3, pMIS sidewall insulating film width 1244, or in accordance with the contact etch stop film thickness 1245, film type of the gate electrode material 1328,1330, may be corrected quality or thickness (1349 or 1350).

The manufacturing control device 20C, based on the measured value 234 of the two or more compounds as described above, to the target deposited film thickness T _target thickness of one insulating film may be corrected, the thickness of the two or more insulating films The target deposited film thickness T _target may be corrected.

  As described above, the manufacturing control apparatus 20D according to the thirty-ninth to the forty-fourth embodiments changes the work function of the gate electrode materials 1328 and 1330 in accordance with the dimensions, inclination, and film thickness data of the previous process. It is possible to reduce transistor characteristic variation (third film thickness variation) for each product.

  Here, although the example in which the production control device 20 according to the first embodiment further includes the third processing unit 23 has been described, the production control devices 20A to 20C according to other embodiments further include the third processing unit 23. Three processing units 23 may be provided.

  Further, the manufacturing control apparatus 20D may include only the third processing unit 23 without including the first processing unit 21 and the second processing unit 22.

(Forty-fifth embodiment)
Hereinafter, in 45th to 52nd embodiments of the present invention, modified examples of the manufacturing control apparatus 20D according to the 39th to 44th embodiments will be described.

  In the 45th to 52nd embodiments, the case where a semiconductor device is manufactured by a process different from the 39th to 44th embodiments will be described.

  First, a method for manufacturing a semiconductor device in the 45th to 52nd embodiments will be described.

  In the semiconductor device manufacturing method according to the 45th to 52nd embodiments, in addition to the gate electrodes 1100 and 1105, the gate insulating film 1102 is removed, and then a high dielectric film 1401 to be a gate insulating film is formed, and then The gate electrode materials 1328 and 1330 are embedded.

  Note that the processing up to FIG. 22A is the same as in the thirty-ninth to forty-fourth embodiments, and a description thereof is omitted.

  FIG. 25A to FIG. 26 are cross-sectional views showing a manufacturing process of a semiconductor device manufactured by the manufacturing system 10 in the 45th to 52nd embodiments.

  After the step of FIG. 22A, in the step shown in FIG. 25A, the underlying gate insulating film 1102 is removed by wet etching.

  Next, in a step shown in FIG. 25B, a high dielectric film 1401 such as an insulating film containing Hf is deposited on the removed portion by CVD. Thereafter, a gate electrode material 1328 having a low work function such as Al, Ta, Mo, Ti, Hf, TaN, Nb, or TiN is embedded by CVD.

  Subsequently, the excess gate electrode material 1328 and the high dielectric film 1401 are removed by polishing using CMP.

  Next, in a step shown in FIG. 25C, a resist mask 1329 having an opening in the pMIS transistor formation region 1002 and covering the nMIS transistor formation region 1001 is formed. Thereafter, the gate electrode material 1328 embedded in the pMIS transistor formation region 1002 is removed by wet etching. After that, the resist mask 1329 is removed by wet cleaning or the like.

Next, in the step shown in FIG. 25D, a gate electrode material 1330 having a high work function such as RuO ₂ , Ir, Pt, WN, Mo ₂ N, TaN, Au, or Ni is embedded in the removed portion by CVD.

  Next, in the step shown in FIG. 26, the pMIS gate electrode is formed by polishing the surplus gate electrode material 1330 until the surface of the gate electrode material 1330 in the nMIS transistor formation region 1001 is exposed using CMP.

  Thus, a transistor structure in which an implantation process for determining transistor characteristics is performed is formed.

  Thereafter, a product (semiconductor device) is completed through an interlayer insulating film forming process, a contact forming process, a wiring forming process, and a PAD forming process.

  A manufacturing control apparatus 20D according to the forty-fifth embodiment for controlling the manufacture of this semiconductor device will be described below. The configuration of the manufacturing control apparatus 20D according to the 45th to 52nd embodiments is the same as the configuration shown in FIG.

  The manufacturing control apparatus 20D according to the forty-fifth embodiment changes the film type of the high dielectric film 1401 serving as the nMIS gate insulating film according to the gate electrode dimension 1124 of the nMIS transistor shown in FIG. 9A.

  Here, when the gate electrode dimension 1124 is reduced, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the work function of the high dielectric film 1401 to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determining unit 243 compensates for the variation in transistor characteristics such as Vt by changing the film type of the high dielectric film 1401 to have a desired work function. For example, the gate electrode characteristic determining unit 243 changes the composition of Hf and Si or adds an additive so that the high dielectric film 1401 has a necessary work function.

  The gate electrode characteristic determination unit 243 calculates the correction amount at this time using the correlation data between the gate electrode dimension 1124 and Vt and the correlation data between the film type of the high dielectric film 1401 and Vt. Specifically, the gate electrode characteristic determining unit 243 decreases the work function of the high dielectric film 1401 as the gate electrode dimension 1124 is smaller.

(Forty-sixth embodiment)
The manufacturing control apparatus 20D according to the forty-sixth embodiment changes the film quality of the high dielectric film 1401 according to the gate electrode size 1124 of the nMIS transistor shown in FIG. 9A.

Here, when the gate electrode dimension 1124 is reduced, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the work function of the high dielectric film 1401 to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determining unit 243 changes the transistor characteristics such as Vt by changing the film quality (for example, the crystal structure of HfO ₂ ) of the high dielectric film 1401 so as to have a desired work function. Complement minutes.

  The gate electrode characteristic determination unit 243 calculates the correction amount at this time using correlation data between the gate electrode dimension 1124 and Vt and correlation data between the film quality of the high dielectric film 1401 and Vt.

(47th embodiment)
The manufacturing control apparatus 20D according to the forty-seventh embodiment changes the high dielectric film thickness 1405 shown in FIG. 25A according to the gate electrode size 1124 of the nMIS transistor shown in FIG. 9A.

  Here, when the gate electrode dimension 1124 is reduced, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the gate electrode dimension 1408 to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determining unit 243 changes the deposited film thickness of the high dielectric film 1401 deposited by using the CVD method so that the high dielectric material has a desired gate electrode size 1408. The film thickness 1405 is changed. This compensates for variations in transistor characteristics such as Vt.

  The gate electrode characteristic determining unit 243 calculates the correction amount at this time using the correlation data between the gate electrode dimension 1124 and Vt and the correlation data between the high dielectric film thickness 1405, the nMIS gate electrode dimension 1408, and Vt. To do. Specifically, the gate electrode characteristic determining unit 243 decreases the high dielectric film thickness 1405 as the gate electrode size 1124 is smaller.

(Forty-eighth embodiment)
The manufacturing control apparatus 20D according to the forty-eighth embodiment changes the nMIS gate electrode film thickness 1349 shown in FIG. 26 according to the gate electrode size 1124 of the nMIS transistor shown in FIG. 9A.

  Here, when the gate electrode dimension 1124 is reduced, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the nMIS gate electrode film thickness 1349 in a direction to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determining unit 243 changes the nMIS gate electrode film thickness 1349 so as to obtain a desired nMIS gate electrode film thickness 1349 by changing the polishing thickness at the time of CMP. This compensates for variations in transistor characteristics such as Vt.

  The gate electrode characteristic determination unit 243 calculates the correction amount at this time using correlation data between the gate electrode size 1124 and Vt and correlation data between the nMIS gate electrode film thickness 1349 and Vt. Specifically, the gate electrode characteristic determining unit 243 decreases the nMIS gate electrode film thickness 1349 as the gate electrode dimension 1124 is smaller.

(49th Embodiment)
The manufacturing control apparatus 20D according to the forty-ninth embodiment changes the film type of the high dielectric film 1401 according to the gate electrode size 1125 of the pMIS transistor shown in FIG. 9A.

  Here, when the gate electrode dimension 1125 is narrowed, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the work function of the high dielectric film 1401 to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determining unit 243 compensates for the variation in transistor characteristics such as Vt by changing the film type of the high dielectric film 1401 to have a desired work function. For example, the gate electrode characteristic determining unit 243 changes the composition of Hf and Si or adds an additive so that the high dielectric film 1401 has a necessary work function.

  The gate electrode characteristic determination unit 243 calculates the correction amount at this time using correlation data between the gate electrode size 1125 and Vt and correlation data between the film type of the high dielectric film 1401 and Vt. Specifically, the gate electrode characteristic determining unit 243 decreases the work function of the high dielectric film 1401 as the gate electrode size 1125 is smaller.

(50th Embodiment)
The manufacturing control apparatus 20D according to the 50th embodiment changes the film quality of the high dielectric film 1401 in accordance with the gate electrode size 1125 of the pMIS transistor shown in FIG. 9A.

Here, when the gate electrode dimension 1124 is reduced, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the work function of the high dielectric film 1401 to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determining unit 243 changes the transistor characteristics such as Vt by changing the film quality (for example, the crystal structure of HfO ₂ ) of the high dielectric film 1401 so as to have a desired work function. Complement minutes.

  The gate electrode characteristic determination unit 243 calculates the correction amount at this time using correlation data between the gate electrode size 1125 and Vt and correlation data between the film type of the high dielectric film 1401 and Vt.

(51st Embodiment)
The manufacturing control apparatus 20D according to the fifty-first embodiment changes the high dielectric film thickness 1405 according to the gate electrode dimension 1125 of the pMIS transistor shown in FIG. 9A.

  Here, when the gate electrode dimension 1125 is narrowed, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the gate electrode size 1409 to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determining unit 243 changes the deposited film thickness of the high dielectric film 1401 deposited by the CVD method, so that the high dielectric film thickness is obtained so that the desired gate electrode dimension 1409 is obtained. 1405 is changed. This compensates for variations in transistor characteristics such as Vt.

  The gate electrode characteristic determination unit 243 calculates the correction amount at this time using correlation data between the gate electrode dimension 1125 and Vt, and correlation data between the high dielectric film thickness 1405, the pMIS gate electrode dimension 1409, and Vt. To do. Specifically, the gate electrode characteristic determination unit 243 decreases the high dielectric film thickness 1405 as the gate electrode size 1125 is smaller.

(52nd embodiment)
The manufacturing control apparatus 20D according to the 52nd embodiment changes the pMIS gate electrode film thickness 1350 shown in FIG. 26 according to the gate electrode size 1125 of the pMIS transistor shown in FIG. 9A.

  Here, when the gate electrode dimension 1125 is narrowed, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determining unit 243 changes the pMIS gate electrode film thickness 1350 in a direction to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determining unit 243 changes the gate electrode film thickness 1350 so as to obtain a desired gate electrode film thickness 1350 by changing the polishing thickness at the time of CMP. This compensates for variations in transistor characteristics such as Vt.

  The gate electrode characteristic determination unit 243 calculates the correction amount at this time using correlation data between the gate electrode size 1125 and Vt and correlation data between the pMIS gate electrode film thickness 1350 and Vt. Specifically, the gate electrode characteristic determining unit 243 decreases the pMIS gate electrode film thickness 1350 as the gate electrode dimension 1125 is smaller.

  In the 45th to 52nd embodiments, the film type, film quality, high dielectric film thickness 1405, and gate electrode film thickness 1349 or 1350 of the high dielectric film 1401 are corrected according to the gate electrode size 1124 or 1125. As described above, the nMIS gate electrode angle 1126, the pMIS gate electrode angle 1127, the first sidewall insulating film thickness 1128, the nMIS gate electrode dimension 1129, the pMIS gate electrode dimension 1130, and the nMIS first sidewall insulating film angle 1133 are described. , PMIS first sidewall insulating film angle 1134, nMIS gate electrode first sidewall insulating film width 1131, pMIS gate electrode first sidewall insulating film width 1132, third sidewall insulating film thickness 1239, second Side wall insulation film thickness 1135, nMIS gate electrode size 1241, pMIS gate electrode size 1242, nMIS side wall The film type, film quality, high dielectric film thickness 1405, and gate electrode film thickness 1349 or 1350 of the high dielectric film 1401 are corrected according to the edge film width 1243, the pMIS sidewall insulating film width 1244, or the contact etch stop film thickness 1245. May be.

  Further, the manufacturing control apparatus 20D determines one or more of the film type, the film quality, the high dielectric film thickness 1405, and the gate electrode film thicknesses 1349 and 1350 of the high dielectric film 1401 based on the two or more kinds of measured values 251 described above. It may be corrected.

  As described above, the manufacturing control apparatus 20D according to the forty-fifth to fifty-second embodiments determines the film type, film quality, high dielectric film thickness 1405, and gate electrode film thickness 1349 or 1350 of the high dielectric film 1401 in the previous step. By changing according to the dimension, inclination, or film thickness data, transistor characteristic variation (third film thickness variation) for each process and product can be reduced.

(53rd Embodiment)
In the following 53rd to 58th embodiments of the present invention, modified examples of the production control apparatus 20D according to the 45th to 52nd embodiments will be described.

  In the 53rd to 58th embodiments, a case where a semiconductor device is manufactured by a process different from that of the above 45th to 52nd embodiments will be described.

  The semiconductor devices according to the 53rd to 58th embodiments have a gate electrode structure in which two layers of metal materials are stacked.

  FIGS. 27A to 28 are cross-sectional views illustrating the manufacturing steps of the semiconductor device manufactured by the manufacturing system 10 in the 53rd to 58th embodiments.

  Note that the steps up to the step in FIG. 25A are the same as those in the 45th to 52nd embodiments, and a description thereof will be omitted.

  After the step shown in FIG. 25A, in the next step shown in FIG. 27A, a high dielectric film 1401 such as an insulating film containing Hf is deposited on the removed portion by CVD. Thereafter, a first gate electrode material 1501 having a low work function, such as La, Mo, Al, Ta, Mo, Ti, Hf, TaN, Nb, or TiN, is embedded using a CVD method.

  Thereafter, a second gate electrode having a low work function, such as La, Mo, Al, Ta, Mo, Ti, Hf, TaN, Nb, or TiN, is further formed on the first gate electrode material 1501 using a CVD method. The material 1502 is embedded.

  Subsequently, the excessive high dielectric film 1401, the first gate electrode material 1501, and the second gate electrode material 1502 are removed by polishing using CMP.

  Next, in a step shown in FIG. 27B, a resist mask 1329 having an opening in the pMIS transistor formation region 1002 and covering the nMIS transistor formation region 1001 is formed. After that, the first gate electrode material 1501 and the second gate electrode material 1502 embedded in the pMIS transistor formation region 1002 are removed by performing wet etching, and then the resist mask 1329 is removed by performing wet cleaning or the like. To do.

Next, in the step shown in FIG. 27C, a third high work function such as RuO ₂ , Ir, Pt, WN, Mo ₂ N, TaN, Au, Ni, or Al ₂ O ₃ is used for the removed portion by CVD. A gate electrode material 1504 is embedded. Subsequently, a fourth gate electrode material 1505 having a high work function including RuO ₂ , Ir, Pt, WN, Mo ₂ N, TaN, Au, Ni, or TiN is embedded.

  Next, in the step shown in FIG. 28, an excess of the third gate electrode material 1504 and the surface of the first gate electrode material 1501 and the second gate electrode material 1502 in the nMIS transistor formation region 1001 are exposed using CMP. A pMIS gate electrode is formed by polishing the fourth gate electrode material 1505.

  Thus, a transistor structure in which an implantation process for determining transistor characteristics is performed is formed.

  Thereafter, a product (semiconductor device) is completed through an interlayer insulating film forming process, a contact forming process, a wiring forming process, and a PAD forming process.

  A manufacturing control apparatus 20D according to the 53rd embodiment for controlling the manufacture of this semiconductor device will be described below. The configuration of the manufacturing control apparatus 20D according to the 53rd to 58th embodiments is the same as the configuration shown in FIG.

  The manufacturing control apparatus 20D according to the 53rd embodiment changes the film type of the first gate electrode material 1501 in accordance with the gate electrode size 1124 of the nMIS transistor shown in FIG. 9A.

  Here, when the gate electrode dimension 1124 is reduced, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the work function of the first gate electrode material 1501 to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determining unit 243 compensates for a variation in transistor characteristics such as Vt by changing the film type of the first gate electrode material 1501 so as to have a desired work function. For example, the gate electrode characteristic determination unit 243 adopts another metal so as to have a necessary work function as the first gate electrode material 1501, or adds an additive to the first gate electrode material 1501. The film type of the first gate electrode material 1501 is changed.

  The gate electrode characteristic determination unit 243 calculates the correction amount at this time using the correlation data between the gate electrode dimension 1124 and Vt and the correlation data between the film type of the first gate electrode material 1501 and Vt. Specifically, the gate electrode characteristic determining unit 243 decreases the work function of the first gate electrode material 1501 as the gate electrode size 1124 is smaller.

(Fifth embodiment)
The manufacturing control apparatus 20D according to the 54th embodiment changes the first gate electrode film thickness 1506 shown in FIG. 27A according to the gate electrode size 1124 of the nMIS transistor shown in FIG. 9A.

  Here, when the gate electrode dimension 1124 is reduced, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the first gate electrode film thickness 1506 deposited by using the CVD method in a direction to return the transistor characteristic changed in the previous process, thereby changing the transistor such as Vt. Compensates for fluctuations in characteristics.

  The gate electrode characteristic determination unit 243 calculates the correction amount at this time using correlation data between the gate electrode dimension 1124 and Vt and correlation data between the first gate electrode film thickness 1506 and Vt.

(55th Embodiment)
The manufacturing control apparatus 20D according to the 55th embodiment changes the film type of the second gate electrode material 1502 in accordance with the first gate electrode film thickness 1506 of the nMIS transistor shown in FIG. 27A.

  Here, when the first gate electrode film thickness 1506 is reduced, transistor characteristics such as Vt of the transistor change. On the other hand, the gate electrode characteristic determination unit 243 compensates for the variation in transistor characteristics such as Vt by changing the film type of the second gate electrode material 1502 in a direction to return the transistor characteristics that have been varied in the previous process. To do.

  The gate electrode characteristic determining unit 243 uses the correlation data between the first gate electrode film thickness 1506 and Vt and the correlation data between the film type of the second gate electrode material 1502 and Vt as the correction amount at this time. To calculate.

(56th Embodiment)
The manufacturing control apparatus 20D according to the 56th embodiment changes the film type of the third gate electrode material 1504 according to the gate electrode size 1125 of the pMIS transistor shown in FIG. 9A.

  Here, when the gate electrode dimension 1125 is narrowed, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the work function of the third gate electrode material 1504 to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determining unit 243 compensates for a variation in transistor characteristics such as Vt by changing the film type of the third gate electrode material 1504 to have a desired work function. For example, the gate electrode characteristic determining unit 243 adopts another metal as the third gate electrode material 1504 so as to have a necessary work function, or adds an additive to the third gate electrode material 1504. The film type of the third gate electrode material 1504 is changed.

  The gate electrode characteristic determination unit 243 calculates the correction amount at this time using correlation data between the gate electrode size 1125 and Vt and correlation data between the film type of the third gate electrode material 1504 and Vt. Specifically, the gate electrode characteristic determining unit 243 decreases the work function of the third gate electrode material 1504 as the gate electrode size 1125 is smaller.

(57th Embodiment)
The manufacturing control apparatus 20D according to the 57th embodiment changes the third gate electrode film thickness 1507 shown in FIG. 27C according to the gate electrode size 1125 of the pMIS transistor shown in FIG. 9A.

  Here, when the gate electrode dimension 1125 is narrowed, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the third gate electrode film thickness 1507 deposited using the CVD method in a direction to return the transistor characteristic changed in the previous process, thereby changing the transistor such as Vt. Compensates for fluctuations in characteristics.

  The gate electrode characteristic determination unit 243 calculates the correction amount at this time using correlation data between the gate electrode dimension 1125 and Vt and correlation data between the third gate electrode film thickness 1507 and Vt.

(58th Embodiment)
The manufacturing control apparatus 20D according to the 58th embodiment changes the film type of the fourth gate electrode material 1505 according to the third gate electrode film thickness 1507 of the pMIS transistor shown in FIG. 27C.

  Here, when the third gate electrode film thickness 1507 is reduced, transistor characteristics such as Vt of the transistor are changed. On the other hand, the gate electrode characteristic determining unit 243 compensates for the variation in transistor characteristics such as Vt by changing the film type of the fourth gate electrode material 1505 in the direction to return the transistor characteristics that have been varied in the previous process. To do.

  The gate electrode characteristic determining unit 243 uses the correlation data between the third gate electrode film thickness 1507 and Vt and the correlation data between the film type of the fourth gate electrode material 1505 and Vt as the correction amount at this time. To calculate.

  In the 53rd to 58th embodiments, the first gate electrode material 1501 is formed in accordance with the gate electrode dimensions 1124, 1125, the first gate electrode film thickness 1506, or the third gate electrode film thickness 1507. Film type, first gate electrode film thickness 1506, film type of second gate electrode material 1502, film type of third gate electrode material 1504, third gate electrode film thickness 1507, or fourth gate electrode material 1505 Are corrected, but nMIS gate electrode angle 1126, pMIS gate electrode angle 1127, first sidewall insulating film thickness 1128, nMIS gate electrode dimension 1129, pMIS gate electrode dimension 1130, nMIS first sidewall insulation Film angle 1133, pMIS first sidewall insulating film angle 1134, nMIS gate electrode first sidewall insulating film width 1131, pMIS gate electrode First sidewall insulating film width 1132, third sidewall insulating film thickness 1239, second sidewall insulating film thickness 1135, nMIS gate electrode dimension 1241, pMIS gate electrode dimension 1242, nMIS sidewall insulating film width 1243, pMIS According to the sidewall insulating film width 1244 or the contact etch stop film thickness 1245, the first gate electrode material 1501 film type, the first gate electrode film thickness 1506, the second gate electrode material 1502 film type, the third The film type of the gate electrode material 1504, the third gate electrode film thickness 1507, or the film type of the fourth gate electrode material 1505 may be corrected.

  Further, the manufacturing control apparatus 20 </ b> D determines the film type of the first gate electrode material 1501, the first gate electrode film thickness 1506, and the film type of the second gate electrode material 1502 based on the two or more types of measurement values 251 described above. One or more of the film types of the third gate electrode material 1504, the third gate electrode film thickness 1507, and the fourth gate electrode material 1505 may be corrected.

  As described above, the manufacturing control apparatus 20D according to the 53rd to 58th embodiments described above includes the film type of the first gate electrode material 1501, the film thickness of the first gate electrode 1506, and the film of the second gate electrode material 1502. The seed, the film type of the third gate electrode material 1504, the third gate electrode film thickness 1507, or the film type of the fourth gate electrode material 1505 are changed in accordance with the size, inclination, or film thickness data of the previous process. Thus, transistor characteristic variation (third film thickness variation) for each process and product can be reduced.

(59th embodiment)
In the following 59th to 61st embodiments of the present invention, modified examples of the production control apparatus 20D according to the 53rd to 58th embodiments will be described.

  In the fifty-sixth to sixty-first embodiments, the case where a semiconductor device is manufactured by a process different from the fifty-fifth to fifty-eighth embodiments will be described.

  The semiconductor devices according to the 59th to 61st embodiments have different gate insulating films for nMIS and pMIS.

  FIGS. 29A to 30 are cross-sectional views showing the manufacturing steps of the semiconductor device manufactured by the manufacturing system 10 in the 59th to 61st embodiments.

  Note that the steps up to the step in FIG. 27A are the same as those in the 53rd to 58th embodiments, and a description thereof will be omitted.

  After the process of FIG. 27A, in the process shown in FIG. 29A, a resist mask 1329 having an opening in the pMIS transistor formation region 1002 and covering the nMIS transistor formation region 1001 is formed. Thereafter, the high dielectric film 1401, the first gate electrode material 1501, and the second gate electrode material 1502 buried in the pMIS transistor formation region 1002 are removed by wet etching. After that, the resist mask 1329 is removed by wet cleaning or the like.

Next, in a step shown in FIG. 29B, a high dielectric film 1604 such as an insulating film containing Hf is deposited on the removed portion by CVD. RuO _2, Ir followed by CVD, Pt, embedded _{WN, Mo 2 N, TaN,} Au, Ni, or Al ₂ O high work function, such as ₃ third gate electrode material 1504.

Subsequently, a fourth gate electrode material 1505 having a high work function including RuO ₂ , Ir, Pt, WN, Mo ₂ N, TaN, Au, Ni, TiN and the like is embedded.

  Next, in the step shown in FIG. 30, an extra third gate electrode material 1504 is used until the surfaces of the first gate electrode material 1501 and the second gate electrode material 1502 in the nMIS transistor formation region 1001 are exposed using CMP. By polishing the fourth gate electrode material 1505 and the high dielectric film 1604, a pMIS gate electrode is formed.

  Thus, a transistor structure in which an implantation process for determining transistor characteristics is performed is formed.

  Thereafter, a product (semiconductor device) is completed through an interlayer insulating film forming process, a contact forming process, a wiring forming process, and a PAD forming process.

  A manufacturing control apparatus 20D according to the 59th embodiment for controlling the manufacture of this semiconductor device will be described below. The configuration of the manufacturing control apparatus 20D according to the 59th to 61st embodiments is the same as the configuration shown in FIG.

  The manufacturing control apparatus 20D according to the 59th embodiment changes the film type of the third gate electrode material 1504 according to the gate electrode dimension 1125 of the pMIS transistor shown in FIG. 9A.

  Here, when the gate electrode dimension 1125 is narrowed, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the work function of the third gate electrode material 1504 to return the transistor characteristic changed in the previous process. Specifically, the gate electrode characteristic determining unit 243 compensates for a variation in transistor characteristics such as Vt by changing the film type of the third gate electrode material 1504 to have a desired work function. For example, the gate electrode characteristic determining unit 243 adopts another metal as the third gate electrode material 1504 so as to have a necessary work function, or adds an additive to the third gate electrode material 1504. The film type of the third gate electrode material 1504 is changed.

  The gate electrode characteristic determination unit 243 calculates the correction amount at this time using correlation data between the gate electrode size 1125 and Vt and correlation data between the film type of the third gate electrode material 1504 and Vt. Specifically, the gate electrode characteristic determining unit 243 decreases the work function of the first gate electrode material 1501 as the gate electrode size 1125 is smaller.

(60th Embodiment)
The manufacturing control apparatus 20D according to the sixtyth embodiment changes the third gate electrode film thickness 1507 shown in FIG. 27C according to the gate electrode size 1125 of the pMIS transistor shown in FIG. 9A.

  Here, when the gate electrode dimension 1125 is narrowed, transistor characteristics such as Vt of the transistor vary. On the other hand, the gate electrode characteristic determination unit 243 changes the third gate electrode film thickness 1507 deposited using the CVD method in a direction to return the transistor characteristic changed in the previous process, thereby changing the transistor such as Vt. Compensates for fluctuations in characteristics.

  The gate electrode characteristic determination unit 243 calculates the correction amount at this time using correlation data between the gate electrode dimension 1125 and Vt and correlation data between the third gate electrode film thickness 1507 and Vt.

(61st Embodiment)
The manufacturing control apparatus 20D according to the sixteenth embodiment changes the film type of the fourth gate electrode material 1505 according to the third gate electrode film thickness 1507 of the pMIS transistor shown in FIG. 29B.

  Here, when the third gate electrode film thickness 1507 is reduced, transistor characteristics such as Vt of the transistor are changed. On the other hand, the gate electrode characteristic determining unit 243 compensates for the variation in transistor characteristics such as Vt by changing the film type of the fourth gate electrode material 1505 in the direction to return the transistor characteristics that have been varied in the previous process. To do.

  The gate electrode characteristic determining unit 243 uses the correlation data between the third gate electrode film thickness 1507 and Vt and the correlation data between the film type of the fourth gate electrode material 1505 and Vt as the correction amount at this time. To calculate.

  In the 59th to 61st embodiments, the film type of the third gate electrode material 1504 and the third gate electrode film thickness 1507 according to the gate electrode size 1125 or the third gate electrode film thickness 1507. Alternatively, although the film type of the fourth gate electrode material 1505 is corrected, the pMIS gate electrode angle 1127, the first sidewall insulating film thickness 1128, the pMIS gate electrode dimension 1130, the pMIS first sidewall insulating film angle 1134, pMIS gate electrode first sidewall insulation film width 1132, third sidewall insulation film thickness 1239, second sidewall insulation film thickness 1135, pMIS gate electrode dimension 1242, pMIS sidewall insulation film width 1244, or contact etch stop Depending on the film thickness 1245, the film type of the third gate electrode material 1504, the third gate electrode film thickness 1507, or the fourth gate electrode material 505 kinds of films may be corrected.

  In addition, the manufacturing control apparatus 20D uses one or more of the film type of the third gate electrode material 1504, the third gate electrode film thickness 1507, and the fourth gate electrode material 1505 based on the two or more kinds of measured values 251 described above. May be corrected.

  As described above, the manufacturing control apparatus 20D according to the 59th to 61st embodiments described above has the film type of the third gate electrode material 1504, the film thickness of the third gate electrode 1507, or the film type of the fourth gate electrode material 1505. Is changed according to the dimension, inclination, or film thickness data of the previous process, so that transistor characteristic variation (third film thickness variation) for each process and product can be reduced.

  Each processing unit included in the manufacturing control apparatus according to the first to 61st embodiments is typically realized by a processor such as a CPU executing a program.

  Further, the present invention may be the above program or a recording medium on which the above program is recorded. Needless to say, the program can be distributed via a transmission medium such as the Internet.

  A part or all of the functions of the production control apparatus according to the first to 61st embodiments of the present invention are realized as an LSI which is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them.

  The name used here is LSI, but it may also be called IC, system LSI, super LSI, or ultra LSI depending on the degree of integration.

  Further, the circuit integration is not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor. An FPGA (Field Programmable Gate Array) that can be programmed after manufacturing the LSI or a reconfigurable processor that can reconfigure the connection and setting of circuit cells inside the LSI may be used.

  Moreover, although the corner | angular part and edge | side of each component of a semiconductor device are described linearly in the said figure, the thing with a rounded corner | angular part and edge | side is also included in this invention for the reason on manufacture.

  Moreover, you may combine at least one part among the functions of the manufacturing control apparatus which concerns on the said 1st-61st embodiment, and its modification.

  Furthermore, various modifications in which the present embodiment is modified within the scope conceived by those skilled in the art are also included in the present invention without departing from the gist of the present invention.

  The present invention can be applied to a manufacturing control apparatus that controls a semiconductor manufacturing apparatus. Further, the present invention can be applied to a manufacturing system for manufacturing a semiconductor device.

DESCRIPTION OF SYMBOLS 10 Manufacturing system 20, 20A, 20B, 20C, 20D Manufacturing control apparatus 21, 21A 1st process part 22, 22A, 22B, 22C 2nd process part 30 Film-forming apparatus 40 Measuring apparatus 101, 201 1st wafer surface area acquisition part 102 , 202 First wafer surface area accumulating unit 103, 203 First variable film thickness calculating unit 104 Processing time acquiring unit 105 Processing time accumulating unit 106 Measured film thickness acquiring unit 107 Measured film thickness accumulating unit 108 Estimated film forming rate calculating unit 109 Estimating composition Film rate accumulation unit 110, 210 Second wafer surface area acquisition unit 111, 211 Second wafer surface area accumulation unit 112, 212 Second variable film thickness calculation unit 113 Target deposition thickness acquisition unit 114 Target deposition thickness accumulation unit 115 Estimated film formation Rate acquisition unit 116 Deposition time calculation unit 117 Deposition time accumulation unit 118 Deposition time output unit 216 Parameter Data calculation unit 217 parameter storage unit 218 parameter output unit 221 first wafer number acquisition unit 222 first wafer number storage unit 223 first total surface area calculation unit 224 second wafer number acquisition unit 225 second wafer number storage unit 226 second Total surface area calculation unit 231, 241 Measurement value acquisition unit 232, 242 Measurement value accumulation unit 233 Target deposition film thickness correction unit 234, 251 Measurement value 243 Gate electrode characteristic determination unit 244 Gate electrode characteristic accumulation unit 245 Gate electrode characteristic output unit 252 Gate Electrode characteristics 301, 1104 Silicon substrate 302, 1102 Gate insulating film 303, 1100, 1105 Gate electrode 304, 1103 Element isolation insulating film 305 Side wall insulating film 306 Side wall insulating film 307, 310, 1110, 1113, 1118, 1121, 1329 Resist Mask 08,311,1111,1114,1119,1122 ion 309,1112 n-type extension regions 312,1115 p-type extension regions 1001, R _TN nMIS transistor forming region 1002, R _TP pMIS transistor forming region 1101 first sidewall insulating film DESCRIPTION OF SYMBOLS 1106 1st side wall insulating film 1116 2nd side wall insulating film 1117 2nd side wall insulating film 1120 n-type source / drain region 1123 p-type source / drain region 1124, 1125, 1129, 1130, 1136, 1241, 1242, 1408, 1409 Gate electrode dimensions 1126, 1127 Gate electrode angle 1128 First sidewall insulating film thickness 1131, 1132 First sidewall insulating film width 1133, 1134, 1137 First sidewall insulating film angle 1135 Second 1140, 1141 Second sidewall insulating film width 1216 Third sidewall insulating film 1218 Third sidewall insulating film 1226 Contact etch stop layer 1239 Third sidewall insulating film 1243, 1244 Side wall insulation Film width 1245 Contact etch stop film thickness 1327 Interlayer insulation film 1328, 1330 Gate electrode material 1349, 1350 Gate electrode film thickness 1401, 1604 High dielectric film 1405 High dielectric film thickness 1501 First gate electrode material 1502 Second gate Electrode material 1504 third gate electrode material 1505 fourth gate electrode material 1506 first gate electrode film thickness 1507 third gate electrode film thickness L ₀ , L _0n first wafer surface area L ₁ , L _1n second wafer surface area L _t0 first total surface area L _t1 second total surface area N _0n number of first wafers N _1n Number of second wafers P _target control parameter R ₀ estimated film formation rate T ₀ measured film thickness T _A0 first variable film thickness T _A1 second variable film thickness T _target target deposition film thickness T _target2 corrected target deposition film thickness t ₀ Processing time t _target deposition time

Claims (20)

A manufacturing control apparatus for calculating a control parameter for controlling a film forming apparatus for depositing an insulating film on a first semiconductor wafer,
The manufacturing control device that calculates the control parameter for depositing the insulating film thicker on the film forming device as the first surface area of the first semiconductor wafer is larger. The manufacturing control device includes:
As the control parameter, the deposition apparatus includes a deposition time calculation unit that calculates a first deposition time for depositing the insulating film on the first semiconductor wafer,
The manufacturing control apparatus according to claim 1, wherein the deposition time calculation unit calculates the first deposition time such that the first deposition time becomes longer as the first surface area is larger. The manufacturing control device further includes:
A target deposited film thickness obtaining unit for obtaining a target deposited film thickness;
A film formation rate acquisition unit that acquires a film formation rate that is a thickness of the insulating film deposited per unit time by the film formation apparatus;
By multiplying the first surface area by a first coefficient, a first variable film thickness that is a film thickness depending on the first surface area out of the film thickness of the insulating film deposited by the film forming apparatus is calculated. 1 fluctuation film thickness calculation part,
The deposition time calculation unit calculates a first estimated film thickness by adding the target deposition film thickness and the first variable film thickness, and divides the first estimated film thickness by the film formation rate. The manufacturing control apparatus according to claim 2, wherein the first deposition time is calculated. The manufacturing control device further includes:
A second surface area acquisition unit for acquiring a second surface area of the second semiconductor wafer;
A processing time acquisition unit that acquires a processing time that is a deposition time when an insulating film is deposited on the second semiconductor wafer by the film forming apparatus;
A measurement film thickness acquisition unit that acquires a measurement film thickness that is a film thickness of the insulating film when the insulating film is deposited on the second semiconductor wafer by the film forming apparatus;
By multiplying the second surface area by the first coefficient, a second variable film thickness that is a film thickness depending on the second surface area is calculated out of the film thickness of the insulating film deposited by the film forming apparatus. A second variable thickness calculator,
A second estimated film thickness is calculated by subtracting the second variable film thickness from the measured film thickness, and the film formation rate is calculated by dividing the calculated second estimated film thickness by the processing time. A film rate calculator,
The manufacturing control apparatus according to claim 3, wherein the film formation rate acquisition unit acquires the film formation rate calculated by the film formation rate calculation unit. The film deposition apparatus deposits the insulating film on a plurality of first semiconductor wafers including the first semiconductor wafer,
The plurality of first semiconductor wafers include a plurality of types of wafers on which different patterns are formed,
The production control apparatus according to claim 1, wherein the surface area is an average value of a maximum surface area and a minimum surface area among the surface areas of the plurality of types of wafers. The film deposition apparatus deposits the insulating film on a plurality of first semiconductor wafers including the first semiconductor wafer,
The plurality of first semiconductor wafers include a plurality of types of wafers on which different patterns are formed,
The manufacturing control apparatus according to claim 1, wherein the surface area is a total surface area of the plurality of semiconductor wafers. The semiconductor control device including the film forming apparatus manufactures a semiconductor device including a transistor in the first semiconductor wafer,
The manufacturing process of the semiconductor device by the semiconductor control device includes a first step of forming a gate electrode pattern of the transistor, and a second step of depositing the insulating film by the film forming device after the first step. ,
The manufacturing control apparatus according to claim 1, wherein the first surface area is a ratio of an area of the gate electrode pattern formed per unit area after the first step. The semiconductor control device including the film forming apparatus manufactures a semiconductor device including a transistor in the first semiconductor wafer,
The manufacturing process of the semiconductor device by the semiconductor control device includes a first step of forming a gate electrode pattern of the transistor, and a second step of depositing the insulating film by the film forming device after the first step. ,
The manufacturing control apparatus according to claim 1, wherein the first surface area is a ratio of an area where the gate electrode pattern per unit area is not formed after the first step. The semiconductor control device including the film forming apparatus manufactures a semiconductor device including a transistor in the first semiconductor wafer,
The manufacturing process of the semiconductor device by the semiconductor control device includes a first step of forming a gate electrode pattern of the transistor, and a second step of depositing the insulating film by the film forming device after the first step. ,
The manufacturing control apparatus according to claim 1, wherein the first surface area is a peripheral length of the gate electrode pattern formed per unit area after the first step. The semiconductor control device including the film forming apparatus manufactures a semiconductor device including a transistor in the first semiconductor wafer,
The manufacturing process of the semiconductor device by the semiconductor control device includes a first step of forming a gate electrode pattern of the transistor, and a second step of depositing the insulating film by the film forming device after the first step. ,
The manufacturing control apparatus according to claim 1, wherein the first surface area is a total sum of peripheral lengths of the gate electrode pattern formed in the first step. The semiconductor control device including the film forming apparatus manufactures a semiconductor device including a transistor in the first semiconductor wafer,
The manufacturing process of the semiconductor device by the semiconductor control device includes: a first step of forming a gate electrode of the transistor; and the insulating film used by the film forming device as a sidewall insulating film of the gate electrode after the first step. A second step of depositing,
The manufacturing control device further includes:
A first measurement value acquisition unit for acquiring a first measurement value indicating a shape of a structure of the transistor formed on the first semiconductor wafer after the first step and before the second step;
In accordance with the first measurement value, the corrected target deposition is performed by correcting the target deposition film thickness so as to change the transistor characteristics in the direction opposite to the direction in which the transistor characteristics have changed in the first step. A target deposited film thickness correction unit for generating a film thickness is provided.
The deposition time calculation unit calculates a first estimated film thickness by adding the target deposition film thickness and the first variable film thickness, and divides the first estimated film thickness by the film formation rate. The manufacturing control apparatus according to claim 3, wherein the first deposition time is calculated. The first measurement value acquisition unit acquires the dimension or angle of the gate electrode as the first measurement value,
The manufacturing control apparatus according to claim 11, wherein the target deposited film thickness correcting unit increases the target deposited film thickness as the size of the gate electrode is smaller or the angle of the gate electrode is larger. In the first step, a first sidewall insulating film of the gate electrode is further formed,
In the second step, the film deposition apparatus deposits the insulating film used for the second sidewall insulating film of the gate electrode, which is formed on a side surface of the first sidewall insulating film,
The first measurement value acquisition unit acquires a width or an angle of the first sidewall insulating film as the first measurement value,
The manufacturing control apparatus according to claim 11, wherein the target deposited film thickness correcting unit increases the target deposited film thickness as the width of the first sidewall insulating film is smaller or as the first sidewall insulating film is larger. The target deposited film thickness correcting unit varies the threshold voltage in a direction opposite to a direction in which the threshold voltage of the transistor varies in the first step according to the first measured value. The manufacturing control apparatus according to claim 11. The semiconductor control device including the film forming apparatus manufactures a semiconductor device including a transistor in the first semiconductor wafer,
The manufacturing process of the semiconductor device by the semiconductor control device includes a first step of forming a gate electrode of the transistor, and a contact etch stop layer as the insulating film on the gate electrode after the first step. And a second step of depositing
The manufacturing control device further includes:
A measurement value acquisition unit for acquiring a measurement value indicating the shape of the structure of the transistor formed on the first semiconductor wafer after the first step and before the second step;
In accordance with the first measurement value, the target deposition after correction is performed by correcting the target deposition film thickness so that the driving capability is changed in the direction opposite to the direction in which the driving capability of the transistor is changed in the first step. A target deposited film thickness correction unit for generating a film thickness is provided.
The deposition time calculation unit calculates a first estimated film thickness by adding the target deposition film thickness and the first variable film thickness, and divides the first estimated film thickness by the film formation rate. The manufacturing control apparatus according to claim 3, wherein the first deposition time is calculated. The semiconductor control device including the film forming apparatus manufactures a semiconductor device including a transistor in the first semiconductor wafer,
The manufacturing process of the semiconductor device by the semiconductor control device is as follows:
A first step of forming a first gate electrode of the transistor and depositing the insulating film used by the film forming apparatus as a sidewall insulating film of the gate electrode;
A second step of removing the first gate electrode and embedding a gate electrode material in a region where the first gate electrode is removed after the first step;
The manufacturing control device further includes:
A second measurement value acquisition unit for acquiring a second measurement value indicating the shape of the structure of the transistor formed on the first semiconductor wafer after the first step and before the second step;
A gate electrode characteristic that determines a characteristic of the gate electrode that varies the characteristic of the transistor in the second step in a direction opposite to the direction in which the characteristic of the transistor fluctuated in the first process according to the second measurement value. The manufacturing control apparatus according to claim 1, further comprising a determination unit. The manufacturing control apparatus according to claim 16, wherein the gate electrode characteristic determination unit determines a film type, a film quality, or a film thickness of the gate electrode material as the characteristic of the gate electrode. The gate electrode characteristic determination unit determines a characteristic of the gate electrode having a work function that varies the threshold voltage in the second step in a direction opposite to a direction in which the threshold voltage of the transistor varies in the first step. Item 18. A manufacturing control apparatus according to Item 17. In the second step, a high dielectric film serving as a gate insulating film of the transistor is formed in a region where the first gate electrode is removed, and the gate electrode material is formed on the formed high dielectric film. embedded,
The manufacturing control apparatus according to claim 16, wherein the gate electrode characteristic determination unit determines a film type, a film quality, or a film thickness of the high dielectric film as the characteristic of the gate electrode. A manufacturing control method for controlling a film forming apparatus for depositing an insulating film on a first semiconductor wafer, comprising:
The manufacturing control method, wherein the insulating film is deposited thicker on the deposition apparatus as the first surface area of the first semiconductor wafer is larger.

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