JP2010258155A - TDI image sensor and method for driving the image sensor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a TDI image sensor for performing TDI operation, wherein a horizontal OFD is formed without sacrificing the aperture ratio. <P>SOLUTION: A vertical CCD has a VPCCD structure having four or more phases. Horizontal OFDs are formed in transfer gates 7a, 7b, and 7d other than a virtual electrode 8c. The potential barrier of an overflow barrier in the OFDs formed in the transfer electrodes 7b and 7d adjacent to the virtual electrode and the potential barrier of an overflow barrier in the OFDs formed in the transfer electrode 7a not adjacent to the virtual electrode are set to different values. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a TDI image sensor used in the field of remote sensing and the like, and a method for driving the image sensor.

  A large number of image sensors have been developed in which a large number of photodetectors are arranged in an array on a semiconductor substrate, and a signal charge readout circuit and an output amplifier are provided on the same substrate. In remote sensing, a linear image sensor with photodetectors arranged in a one-dimensional array is mounted on an artificial satellite, etc., and a two-dimensional image of the ground surface is taken by matching the direction perpendicular to the array with the direction of travel of the satellite. Is done. In order to improve the image resolution, it is desirable to reduce the pixel pitch as much as possible. However, there is a problem that the incident light amount is reduced by the reduction in the area of the photodetector and the S / N is deteriorated.

  As a clever means for improving S / N, a TDI (Time Delay and Integration) type image sensor has been developed. The TDI method uses an FFT (full frame transfer) CCD (Charge Coupled Devices), which is a two-dimensional image sensor, and synchronizes the charge transfer timing with the movement timing of the subject image, thereby improving the S / N. It is a method. In the case of remote sensing, TDI operation can be realized by adjusting the charge transfer in the vertical direction to the moving speed of the satellite. When an M-stage TDI operation is performed with a vertical CCD, the accumulation time is effectively M times, so that the sensitivity is improved M times and the S / N is improved to √M times.

  In many cases, the visible image sensor performs imaging by making light incident from the surface side of the chip. Incident light is photoelectrically converted inside the Si substrate to generate signal charges. In the FFT type CCD, since light enters the photodetector through the polysilicon electrode that controls the vertical charge transfer, there is a problem that light in a short wavelength region is absorbed by the polysilicon electrode, and sensitivity is lowered. . As a countermeasure, an image sensor with improved sensitivity by using a so-called VPCCD (virtual phase CCD) structure in which light absorption at the electrode portion is suppressed by replacing some vertical transfer electrodes, for example, polysilicon electrodes with virtual electrodes. Has been proposed.

  For example, Patent Document 1 discloses an example of an image sensor having the VPCCD structure. The image sensor of Patent Document 1 has a two-phase drive VPCCD structure, and the potential under the transfer electrode is graded. For this reason, the vertical transfer direction of the signal charge is limited to one direction from the shallowest potential to the deepest potential.

  On the other hand, a so-called bidirectional TDI in which vertical transfer can be performed bidirectionally is desirable for a satellite-mounted TDI sensor. The VPCCD in this case can realize bidirectional TDI by driving with three or more phases instead of providing a potential gradient under the transfer electrode.

  In addition, an image sensor having a function of discharging excessive charges generated when an excessive amount of light is incident on the photodetector, that is, an anti-blooming function has been proposed. In the sensor, the excess charge is discharged to an overflow drain (OFD) region through a potential barrier adjacent to the photodetector. The overflow drain structure includes a horizontal overflow drain structure in which an OFD is arranged in the horizontal direction of the photodetector and a vertical overflow drain structure in which an OFD is arranged in the vertical direction of the detector. For a CCD used for remote sensing, a horizontal overflow drain structure capable of detecting light in the visible to near infrared region is often suitable.

  Furthermore, for example, Patent Document 2 discloses an example of an image sensor in which a lateral overflow drain is formed in an FFT CCD as shown in FIG.

Japanese Examined Patent Publication No. 6-91659 Japanese Patent Laid-Open No. 10-229183

However, in the conventional technology, even if an attempt is made to manufacture an image sensor that performs a TDI operation by forming a horizontal OFD in a VPCCD structure, the anti-blooming function does not function correctly, or the aperture ratio decreases and the sensitivity decreases. was there.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a TDI type image sensor capable of executing a TDI operation by forming a horizontal OFD without sacrificing an aperture ratio in a VPCCD structure, and a driving method of the image sensor. .

In order to achieve the above object, the present invention is configured as follows.
That is, the TDI image sensor according to one embodiment of the present invention includes a photoelectric conversion unit that forms pixels and transfers a signal charge in a vertical direction, and transfers the signal charge to the photoelectric conversion unit by a time delay integration operation. In the TDI type image sensor, the photoelectric conversion unit includes four or more transfer electrodes extending in the horizontal direction and arranged in parallel in the vertical direction, and one of the transfer electrodes includes: A virtual phase type transfer electrode formed of a virtual electrode, and a horizontal overflow drain structure is provided only on the transfer electrode other than the virtual phase type transfer electrode adjacent to the vertical transfer channel portion in the corresponding photoelectric conversion unit. It is characterized by that.

  According to the TDI type image sensor of one embodiment of the present invention, the photoelectric conversion unit has four or more transfer electrodes, one of which is a virtual phase (VP) type configured by virtual electrodes, and further a virtual A horizontal overflow drain (OFD) structure is provided adjacent to the vertical transfer channel portion corresponding to other than the electrode (virtual phase transfer electrode), and the horizontal overflow is provided in the vertical transfer channel portion corresponding to the virtual electrode (virtual phase transfer electrode). The drain structure is not provided. In such a configuration, the sensitivity of the image sensor is improved by adopting the VP structure, and further, blooming can be suppressed by forming the horizontal OFD.

It is an element top view of TDI-CCD by Embodiment 1 of this invention. It is an enlarged plan view of the photoelectric conversion part which comprises TDI-CCD shown in FIG. It is sectional drawing in the A section shown in FIG. It is sectional drawing in the B section and D section shown in FIG. It is sectional drawing in the C section shown in FIG. FIG. 2 is an enlarged plan view of a light shielding pixel constituting the TDI-CCD shown in FIG. 1. It is sectional drawing in the E section and G section shown in FIG. It is sectional drawing in the F section and H section shown in FIG. FIG. 5 is a timing diagram of a vertical transfer clock in the TDI-CCD driving method according to the first and second embodiments of the present invention. It is a potential diagram for demonstrating operation | movement in the transfer part which comprises TDI-CCD shown in FIG. It is a potential diagram for demonstrating the drive method of TDI-CCD shown in FIG. It is an enlarged plan view of the photoelectric conversion part which comprises TDI-CCD by Embodiment 2 of this invention. It is sectional drawing in the J section shown in FIG. It is sectional drawing in the K section and M section shown in FIG. It is sectional drawing in the L section shown in FIG. FIG. 10 is a potential diagram for explaining a method of driving the TDI-CCD shown in FIG. 9.

  A TDI image sensor according to an embodiment of the present invention and a driving method of the image sensor will be described below with reference to the drawings. In each figure, the same or similar components are denoted by the same reference numerals.

Embodiment 1 FIG.
First, based on the above-described prior art, when considering a configuration in which a horizontal OFD is formed in a conventional VPCCD and a TDI operation is executed, anti-blooming does not function correctly as described below. Challenges are expected.
With respect to this anticipated problem, in an FFT type CCD in which the bidirectional TDI can be realized and the vertical transfer is a three-phase drive, one of the three transfer electrodes providing the vertical transfer clocks φ1, φ2, and φ3 is virtually set. An example of a VPCCD composed of electrodes will be described below.

  In other words, when a P-type Si substrate is used, the overflow barrier in the lateral OFD is obtained by providing a P-type impurity region between the CCD transfer channel of the N-type impurity region and the OFD of the N-type impurity region, and sandwiching the oxide film. Thus, a MOS transistor is constituted by a polysilicon gate (overflow gate; hereinafter referred to as OFG) formed thereabove.

  At this time, the height of the potential barrier is changed by the voltage applied to the OFG, and the discharge of charges is controlled. As shown in FIG. 4 of Patent Document 2, in the FFT type CCD, the vertical CCD transfer electrode and OFG can be formed by a common polysilicon gate. With such a layout, it is not necessary to prepare a separate wiring to the OFG, and a decrease in aperture ratio is suppressed.

  On the other hand, the virtual electrode of VPCCD is obtained by forming a high-concentration P-type impurity layer on the substrate surface by ion implantation, and there is no polysilicon gate above it. Therefore, when a lateral OFD is formed adjacent to the virtual electrode of the VPCCD, it is necessary to prepare a separate polysilicon gate and form the lateral OFD. However, the aperture ratio is sacrificed and the sensitivity is deteriorated. It will be. Therefore, when forming the horizontal OFD in the VPCCD structure, the horizontal OFD is not formed in the virtual electrode portion, but the horizontal OFD is formed only in the polysilicon transfer gate portion forming the transfer electrode other than the virtual electrode.

In the transfer operation of the vertical CCD having such a configuration, when the vertical transfer clock φ1 is a high voltage, the MOS transistor including the gate corresponding to the transfer electrode to which the vertical transfer clock φ1 is supplied functions, and excess charge is transferred to the OFD. And discharged. Similarly, when the vertical transfer clock φ2 is at a high voltage, the MOS transistor including the gate corresponding to the transfer electrode to which the vertical transfer clock φ2 is supplied functions and excess charge is discharged.
However, when the vertical transfer clock φ3 is a high voltage (the vertical transfer clock φ1 and the vertical transfer clock φ2 are low voltages), the vertical transfer clock φ3 is supplied in the VPCCD using the transfer electrode to which the vertical transfer clock φ3 is supplied as a virtual electrode. There is no MOS transistor including a gate corresponding to the transferred electrode. For this reason, the horizontal OFD does not function at this timing. That is, excess charge is not discharged.

  In the case of still image shooting, if the vertical transfer clock φ1 or the vertical transfer clock φ2 is used as a high voltage and the image is taken and the vertical transfer and signal reading are performed after the mechanical shutter is closed, the excess charge is Anti-blooming functions correctly by discharging to the horizontal OFD formed at the gate of the vertical transfer clock φ1 or the gate of the vertical transfer clock φ2.

  However, in the case of TDI operation, the transfer clocks φ1, φ2, and φ3 are given so that the movement of the potential well of the CCD coincides with the movement of the subject image. Therefore, there is always a fixed period during which only the transfer clock φ3 is at the high voltage. To do. Therefore, if an excessive amount of light is incident on the photodetector during this period, the generated excess charge overflows to adjacent pixels in the vertical transfer direction and blooming occurs.

  As described above, in the conventional VPCCD, when the horizontal OFD is simply formed to execute the TDI operation, a problem that anti-blooming does not function correctly is expected.

  Therefore, the TDI type image sensor and the driving method of the image sensor in the embodiments of the present invention described below are configured to solve the above-described problems.

  In the following embodiments, a CCD (charge coupled device) is taken as an example of the photoelectric conversion unit, but the photoelectric conversion unit is not limited to the CCD.

FIG. 1 is an element plan view showing a circuit configuration of a TDI-CCD 101 as a TDI image sensor according to Embodiment 1 of the present invention. The TDI-CCD 101 includes a photoelectric conversion unit 1 that forms pixels and transfers signal charges in the vertical direction 191 in an array, and transfers the signal charges to the photoelectric conversion unit 1 by a time delay integration (TDI) operation. This is an image sensor that is a TDI system, is a virtual phase (VP) type, and further has a lateral overflow drain (OFD) structure. In the present embodiment, the drive unit 71 that supplies a vertical transfer clock for causing the photoelectric conversion unit 1 to transfer the signal charge in the TDI operation is formed on the same Si substrate as the TDI-CCD 101. . However, the driving unit 71 can be provided on a different substrate separately from the TDI-CCD 101.
The configuration of the TDI-CCD 101 will be specifically described below.

  On the surface of the Si substrate, a photoelectric conversion unit 1 having pixels and having a VPCCD structure is arranged in a two-dimensional array (vertical 6 pixels × horizontal 10 pixels in the example of FIG. 1) and a VPCCD structure. A transfer unit 82 in which light-shielding pixels 2 that are not taken are arranged in a two-dimensional array (in the example of FIG. 1, vertical 2 pixels × horizontal 10 pixels) is formed.

  Each photoelectric conversion unit 1 has four transfer electrodes 7a, 7b, 8c, and 7d extending in the horizontal direction 192 and arranged in parallel in the vertical direction 191 in the present embodiment, and these transfer electrodes 7a, 7b, One of 8c and 7d is constituted by a virtual electrode to adopt a VPCCD structure. In the present embodiment, among the four transfer electrodes 7a, 7b, 8c and 7d, the third transfer electrode 8c is a virtual electrode 8c, and the remaining three transfer electrodes 7a, 7b and 7d are gate electrodes made of polysilicon or the like. It consists of. As will be described in detail later, vertical transfer clocks φ1, φ2, and φ4 are respectively supplied from the drive unit 71 to the transfer electrodes 7a, 7b, and 7d, and the TDI-CCD 101 transfers signal charges in the vertical direction 191 by the TDI operation. The

The drive unit 71 is electrically connected to the input pin 15 (15a to 15d), and the input pin 15 includes the wiring 14 (14a to 14d), the contact 13 (13a to 13d), and the wiring 12 (12a to 12d). And are electrically connected.
The transfer electrodes 7a, 7b, 7d are electrically connected to the wirings 14a, 14b, 14d via the wirings 12a, 12b, 12d. On the other hand, the virtual electrode 8c is not electrically connected to the wiring 14c.

  FIG. 2 is an element plan view showing the enlarged planar structure of the photoelectric conversion unit 1 in the TDI-CCD 101 shown in FIG. 3A to 3C are element cross-sectional views schematically showing the structure of each cross section in the parts A to D shown in FIG.

  As shown in FIG. 2, there is a pixel separation between the vertical transfer channel 19 of each photoelectric conversion unit 1 in the vertical direction 191 and another vertical transfer channel 19 (not shown) adjacent thereto in the horizontal direction 192. A region 11 is formed, and a horizontal OFD (overflow drain) is formed in the pixel isolation region 11 as described below.

  As shown in the cross section A of FIG. 3A, the first transfer electrode (gate electrode) 7a to which the vertical transfer clock φ1 is supplied is formed of the first layer polysilicon 22, and the N-type is formed on the surface side of the P-type Si substrate 20. A vertical transfer channel 19 made of an impurity region 25 is formed. As a pixel isolation region 11, a channel stop 17 made of a high-concentration P-type impurity region, a charge discharge drain 16 made of a high-concentration N-type impurity region, and a P-type impurity region 18 are formed. Is formed. The P-type impurity region 18 and the polysilicon 22 formed above the oxide film 21 constitute an OFG (overflow gate), and the potential barrier height is changed by the voltage applied to the OFG. Then, the discharge of excess charges to the charge discharging unit 5 is controlled.

  Next, as shown in section B and section D of FIG. 3B, the second transfer electrode (gate electrode) 7b to which the vertical transfer clock φ2 is supplied and the fourth transfer electrode (gate electrode) to which the vertical transfer clock φ4 is supplied. ) 7d is formed of the second-layer polysilicon 23, and as the pixel isolation region 11 as in the configuration in the cross section A, the vertical transfer channel 19 including the N-type impurity region 25 on the surface side of the P-type Si substrate 20, A channel stop 17 made of a concentration P-type impurity region, a charge discharge drain 16 made of a high-concentration N-type impurity region, and a P-type impurity region 18 are formed. The P-type impurity region 18 and the polysilicon 23 formed above the oxide film 21 constitute an OFG, and the potential barrier height changes depending on the voltage applied to the OFG. Emission is controlled.

On the other hand, the third transfer electrode (gate electrode), that is, the virtual electrode 8c is configured as follows. That is, as shown in the cross section C of FIG. 3C, the high-concentration P-type impurity region 24 formed on the outermost surface side of the P-type Si substrate 20 becomes the virtual electrode 8c. A vertical transfer channel 19 composed of an N-type impurity region 25 is formed below the high-concentration P-type impurity region 24. Adjacent to this, as a pixel isolation region 11, a channel stop 17 composed of a high concentration P-type impurity region and a charge discharge drain 16 composed of a high concentration N-type impurity region sandwiched between the channel stops 17 are formed.
Thus, in the virtual electrode 8c, an electrode (polysilicon) is not formed above the oxide film 21, and a horizontal OFD is not formed in the virtual electrode 8c.

Next, the light shielding pixel 2 will be described.
The light-shielding pixel 2 is a four-phase drive vertical CCD, and in this embodiment, four transfer electrodes 7a, 7b, 7c and 7d extending in the horizontal direction 192 and arranged in the vertical direction 191 are gates made of polysilicon or the like. It consists of electrodes. Although not shown, a light shielding film is provided above the light shielding pixels 2 so that light from the subject does not enter. The transfer electrodes 7a, 7b, 7c, and 7d are electrically connected to the wirings 14a to 14d via the wirings 12a to 12d, respectively, and the vertical transfer clocks φ1 to φ4 from the driving unit 71 to the light-shielding pixel 2 are connected. Supply is performed via the input pins 15a to 15d via the wirings 14a to 14d, the contacts 13a to 13d, and the wirings 12a to 12d.

FIG. 4 is an element plan view showing a planar structure of the light-shielding pixel 2 shown in FIG. 5A and 5B are element cross-sectional views schematically showing the structures of the respective cross sections E to H in FIG.
As shown in FIG. 4, also in the light-shielded pixel 2, between the vertical transfer channel 19 of each pixel column in the vertical direction 191 and the vertical transfer channel 19 (not shown) adjacent thereto in the horizontal direction 192, A pixel isolation region 11 is formed. On the other hand, the horizontal OFD is not formed with respect to the light shielding pixel 2.

  As shown in section E and section G of FIG. 5A, the transfer electrodes 7a and 7c to which the vertical transfer clocks φ1 and φ3 are supplied are formed of the first layer polysilicon 22 and N on the surface side of the P-type Si substrate 20. A vertical transfer channel 19 made of a type impurity region 25 is formed, and a channel stop 17 made of a high concentration P type impurity region is formed as the pixel isolation region 11. 5B, the transfer electrodes 7b and 7d to which the vertical transfer clocks φ2 and φ4 are supplied are formed of the second-layer polysilicon 23 and are on the surface side of the P-type Si substrate 20. A vertical transfer channel 19 made of an N-type impurity region 25 is formed in the channel, and a channel stop 17 made of a high-concentration P-type impurity region is formed as the pixel isolation region 11.

  Furthermore, as shown in FIG. 1, a charge discharging unit 5 for discharging excess charges is formed at the opposite end of the photoelectric conversion unit 1 array from the horizontal CCD 3.

  The signal charges that have been time-delay-integrated by the photoelectric conversion unit 1 are transferred downward in the drawing toward the charge storage unit 4 through the transfer unit 82 including the light-shielded pixel 2 array by the vertical transfer clocks φ1 to φ4. The signal charge once stored in the charge storage unit 4 is transferred to the horizontal CCD 3 every horizontal period, and then transferred in the horizontal CCD 3 in the horizontal direction 192 (right side of the drawing) from the output amplifier 6. Read out.

Next, the vertical transfer clocks φ1 to φ4 will be described.
FIG. 6 shows timings of vertical transfer clocks φ1 to φ4 supplied to the TDI-CCD 101 in the driving method of the TDI-CCD 101 of the first embodiment. In the driving method of the TDI-CCD 101 according to the first embodiment, the vertical transfer clock has four phases as described above, and the transfer potential for transferring the signal charges to the photoelectric conversion unit 1 and the light-shielding pixel 2 is as follows. In the form, it has a voltage of “H” level. The drive unit 71 supplies the vertical transfer clocks φ1 to φ4 to the transfer electrodes 7a to 7d by setting two transfer electrodes adjacent to each other in the vertical direction 191 to the transfer potential, that is, the “H” level at the same time. Thus, the TDI-CCD 101 is driven by the drive unit 71 with a double clock. Here, the double clock represents a clock group having a clock phase relationship of φ1 to φ4 shown in FIG.
The drive unit 71 sends out the vertical transfer clocks φ1 to φ4 at the timing described above, but the vertical transfer clock φ3 is not supplied to the virtual electrode 8c of the photoelectric conversion unit 1 as described above.

Next, the vertical CCD transfer operation when the vertical transfer clocks φ1 to φ4 shown in FIG. 6 are supplied to the TDI-CCD 101 shown in FIG. 1 will be described.
FIG. 7 is a diagram showing the potential pattern of the vertical transfer channel 19 in time series for the transfer unit 82 formed of an array of light-shielding pixels 2. A potential well is formed under the gate where the clock voltage applied to the transfer gate 26 (corresponding to the transfer electrodes 7a to 7d described above) is the “H” voltage. The signal charge 27 accumulated in the potential well is CCD-transferred in the right direction in FIG. 7 as the potential well moves according to the vertical transfer clocks φ1 to φ4.

Next, FIG. 8 is a diagram showing the potential pattern of the vertical transfer channel 19 in time series with respect to the light receiving unit 81 including the array of the photoelectric conversion units 1.
A dotted line 28 shown in FIG. 8 indicates the potential level of the vertical transfer channel 19 under the virtual electrode 8c having the VPCCD structure.
8 corresponds to the transfer electrodes 7a, 7b, and 7d when the “H” voltage in the vertical transfer clock is applied to the transfer electrode 7a, the transfer electrode 7b, or the transfer electrode 7d. The potential level of the OFG formed adjacent to the vertical transfer channel 19 is shown.

  In the VPCCD structure, when the “H” voltage of the vertical transfer clock is applied to the transfer electrode 7a, transfer electrode 7b, or transfer electrode 7d, the potential level in the vertical transfer channel 19 below these electrodes is the virtual electrode 8c. The impurity concentration of the channel stop 17 that is an impurity region and the drive voltage, that is, the “H” level voltage are set so as to be deeper than the potential level 28 of the lower vertical transfer channel 19.

  In the VPCCD structure, when a voltage of “L” level of the vertical transfer clock is applied to the transfer electrode 7a, the transfer electrode 7b, or the transfer electrode 7d, the potential level in the vertical transfer channel 19 below these electrodes is The impurity concentration of the channel stop 17 that is an impurity region and the drive voltage, that is, the “L” level voltage are set so as to be shallower than the potential level 28 of the vertical transfer channel 19 under the virtual electrode 8c.

  Under such conditions, when the vertical transfer clocks φ1, φ2, and φ4 shown in FIG. 6 are given to the transfer electrode 7a, the transfer electrode 7b, and the transfer electrode 7d, the vertical transfer channel 19 under these electrodes The potential distribution is as shown in FIG. Therefore, the signal charge 27 accumulated in the potential well is transferred in the right direction of FIG. 8 as the potential well moves in accordance with the vertical transfer clocks φ1, φ2, and φ4.

  The potential level 29 of OFG is set to be deeper than the potential level 28 of the vertical transfer channel 19 below the virtual electrode 8c. With this setting, even when an excessive amount of light is incident during the transfer operation and the amount of the signal charge 27 in the potential well increases, the excess charge exceeds the potential barrier of the OFG before overflowing to the adjacent pixel. Excess charge is discharged to the charge discharge drain 16.

  Further, according to the above setting, a part of the signal charge is left in the potential well during the transfer operation and merges with the signal charge in the potential well on the rear side (left in the figure) with respect to the transfer direction. It does not occur. Therefore, the effect that the transfer efficiency is improved is also obtained.

  As described above, according to the TDI-CCD 101 according to the first embodiment, the VPCCD structure improves the sensitivity of the detector, that is, the image sensor, and suppresses blooming because the horizontal OFD is formed.

  Further, according to the driving method of the TDI-CCD 101 according to the first embodiment, the OFD is formed corresponding to the transfer electrodes 7a, 7b, and 7d other than the virtual electrode 8c, and two adjacent to each other in the vertical direction 191. Since the transfer electrode is configured to give a vertical transfer clock so as to be at the “H” level at the same time, there is no timing at which the OFD does not function, and even when an excessive amount of light is incident at any timing, Anti-blooming can function correctly.

  In the first embodiment described above, the case where the vertical CCD is driven by four phases has been described. However, the same configuration as described above can be adopted when driving the vertical CCD by five phases or more. The effect of can be obtained.

Embodiment 2. FIG.
In the TDI-CCD as the TDI image sensor in the second embodiment, a part of the configuration of the photoelectric conversion unit 1 in the TDI-CCD 101 in the first embodiment described above is changed. The configuration other than the photoelectric conversion unit in the TDI-CCD of the second embodiment is the same as the configuration of the TDI-CCD 101 of the first embodiment described above, and a description thereof is omitted here.

The changes in the photoelectric conversion unit of the TDI-CCD of the second embodiment are as follows. That is, in the photoelectric conversion unit 61 in the TDI-CCD 102 of the second embodiment shown in FIG. 9, the vertical conversion channel 19 is provided adjacent to the vertical transfer channel 19 corresponding to the transfer electrodes 7b and 7d adjacent to the virtual electrode 8c. The potential level of the overflow gate (OFG) constituting the horizontal overflow drain (OFD) structure is set shallower than the potential level of the vertical transfer channel 19 corresponding to the virtual electrode 8c, and is adjacent to the virtual electrode 8c in the vertical direction 191. The potential level of OFG constituting the horizontal OFD structure provided adjacent to the vertical transfer channel 19 corresponding to the non-transfer electrode 7a is set deeper than the potential level of the vertical transfer channel 19 corresponding to the virtual electrode 8c.
The other configuration in the photoelectric conversion unit 61 is the same as the configuration of the photoelectric conversion unit 1 in the TDI-CCD 101 of the first embodiment.

The above-described configuration of the photoelectric conversion unit 61 will be described in more detail with reference to FIGS. 10A to 10C.
9 and 10A to 10C, the photoelectric conversion unit 61 is a vertical CCD driven by four phases, has a VPCCD structure in which the third transfer electrode is configured by the virtual electrode 8c, and the remaining three transfer electrodes (transfer gates). ) 7a, 7b, 7d are formed of gate electrodes made of polysilicon or the like. A pixel isolation region 11 is formed between the vertical transfer channel 19 of each of the 61 photoelectric conversion units 61 columns in the vertical direction 191 and the vertical transfer channel 19 (not shown) adjacent thereto in the horizontal direction 192. A horizontal OFD is formed on the surface.

  10A is the same as the structure of the section A described with reference to FIG. 3A for the TDI-CCD 101 of the first embodiment. 10C is the same as the structure of the cross section C described with reference to FIG. 3C for the TDI-CCD 101 of the first embodiment. Therefore, these descriptions are omitted.

  On the other hand, in the region related to the second transfer electrode (gate electrode) 7b supplied with the vertical transfer clock φ2 and the region related to the fourth transfer electrode (gate electrode) 7d supplied with the vertical transfer clock φ4, adjacent to the virtual electrode 8c. The configuration is partially different from the configuration of the TDI-CCD 101 of the first embodiment.

That is, as shown in the cross section K and cross section M of FIG. 10B, the transfer electrode 7b and the transfer electrode 7d are formed of the second layer polysilicon 23, and the pixel isolation region 11 is formed on the surface side of the P-type Si substrate 20 with N. A vertical transfer channel 19 made of a type impurity region 25, a channel stop 17 made of a high concentration P type impurity region, a charge drain 16 made of a high concentration N type impurity region, and a P type impurity region 30 are formed.
The P-type impurity region 30 and the polysilicon electrode 23 formed above the oxide film 21 constitute an OFG, and the potential barrier height changes depending on the voltage applied to the OFG, and the charge Emission is controlled.

  In the above-described pixel structure, in the TDI-CCD 102 according to the second embodiment, the P-type impurity region 18 under the transfer electrode 7a not adjacent to the virtual electrode 8c, and the transfer electrode 7b and transfer electrode 7d adjacent to the virtual electrode 8c. The impurity concentration of the lower P-type impurity region 30 is set to a different value.

  That is, as described above, in the photoelectric conversion unit 61 in the TDI-CCD 102 of the second embodiment, the potential level 31 (FIG. 11) of the OFG formed by the P-type impurity region 30 and the polysilicon electrode 23 is the virtual electrode. The potential level 29 (FIG. 11) of the OFG composed of the P-type impurity region 18 and the polysilicon electrode 22 is shallower than the potential level 28 (FIG. 11) of the vertical transfer channel 19 below 8c. Also set deeply.

  In the TDI-CCD 102 according to the second embodiment configured as described above, the vertical transfer clock has four phases as in the method of driving the TDI-CCD 101 according to the first embodiment, and the vertical transfer clock described in the first embodiment. φ1 to φ4 are supplied to the transfer electrodes 7a to 7d by setting two transfer electrodes adjacent to each other in the vertical direction 191 to the H level at the same time, and are driven by a double clock.

Next, the transfer operation of the vertical CCD when the drive clock shown in FIG. 6 is applied to the TDI-CCD according to the second embodiment of the present invention will be described.
FIG. 11 is a diagram showing the potential pattern of the vertical transfer channel 19 in time series for the light receiving unit 81 formed of an array of photoelectric conversion units 61. A dotted line 28 shown in FIG. 11 indicates the potential level of the vertical transfer channel 19 below the virtual electrode 8c having the VPCCD structure. In addition, the one-dot chain line 29 shown in FIG. 11 is an OFG formed in the region related to the transfer electrode 7a when the “H” level voltage as the transfer potential is applied to the transfer electrode 7a not adjacent to the virtual electrode 8c as described above. Indicates the potential level. In addition, the two-dot chain line 31 shown in FIG. 11 is a case where the “H” level voltage as the transfer potential is applied to the transfer electrode 7b or the transfer electrode 7d adjacent to the virtual electrode 8c as described above, and the transfer electrode 7b and Both potential levels of OFG formed in the region related to the transfer electrode 7d are shown.

  In the VPCCD structure, when the “H” level voltage of the vertical transfer clock is applied to the transfer electrode 7a, transfer electrode 7b, or transfer electrode 7d, the potential level in the vertical transfer channel 19 below these electrodes is the virtual electrode. The concentration of the impurity region and the drive voltage, that is, the “H” level voltage are set so as to be deeper than the potential level 28 of the vertical transfer channel 19 below 8c. Further, when the “L” level voltage of the vertical transfer clock is applied to the transfer electrode 7 a, the transfer electrode 7 b, or the transfer electrode 7 d, the potential level in the vertical transfer channel 19 below these electrodes is higher than the potential level 28. The concentration of the impurity region and the drive voltage, that is, the “L” level voltage are set so as to be shallower.

  Under these conditions, when the drive clocks φ1, φ2, and φ4 shown in FIG. 6 are applied to the transfer electrode 7a, the transfer electrode 7b, and the transfer electrode 7d, the potential distribution of the vertical transfer channel 19 under these electrodes is: As shown in FIG. Therefore, the signal charge 27 accumulated in the potential well is transferred in the right direction in FIG. 11 as the potential well moves in accordance with the vertical transfer clocks φ1, φ2, and φ4. The signal transfer operation so far is the same as that of the TDI-CCD 101 according to the first embodiment described above.

  As described above, the potential level 29 of the OFG formed in the region related to the transfer electrode 7a is set to be deeper than the potential level 28 of the vertical transfer channel 19 below the virtual electrode 8c. The potential level 31 of the OFG formed in the region related to the transfer electrode 7b and the transfer electrode 7d is shallower than the potential level 28 of the vertical transfer channel 19 below the virtual electrode 8c, and an “L” level voltage is applied to the transfer electrode 7a. Set it to be deeper than the potential level. In such a setting, when an excessive amount of light is incident, which OFD functions and excess charge is discharged varies depending on the clock timing of the vertical transfer.

  That is, at time t1, time t4, and time t5 shown in FIG. 11, excess charge is discharged to the OFD beyond the potential level 29 of the OFG formed in the region related to the transfer electrode 7a. At time t2, excess charge is discharged to OFD beyond the potential level 31 of OFG formed in the region related to the transfer electrode 7b. At time t3, excess charges are discharged to the OFD beyond the potential level 31 of the OFG formed in the region related to the transfer electrode 7d.

8 and 11, the saturation charge amount that can be transferred by the vertical CCD is proportional to the cross-sectional area of the well from the bottom surface of the potential well to the potential level 29 or potential level 31 of the OFG. In the case of FIG. 8, at the timing of time t2 and time t3, since the potential well is formed under only one gate of the transfer electrode 7b or the transfer electrode 7d, the saturation charge amount is relatively small.
On the other hand, in the case of the TDI-CCD 102 according to the second embodiment shown in FIG. 11, since the potential level 31 of the OFG that functions at the timings of the time t2 and the time t3 is set relatively shallow, the saturation charge amount at this timing is Increase. As a result, the dynamic range of the TDI-CCD 102 can be expanded.

  In the VPCCD, among the transfer electrode 7a, transfer electrode 7b, virtual electrode 8c, and transfer electrode 7d constituting one pixel, the virtual electrode 8c has a relatively long gate length, and other polysilicon gates, that is, transfer electrodes 7a, transfer electrodes. Since the light transmittance of the entire image sensor becomes higher when the length 7b and the transfer electrode 7d are relatively short, the sensitivity is improved. In this case, since the gate lengths of the transfer electrode 7b and the transfer electrode 7d adjacent to the virtual electrode 8c are shortened, the amount of saturation charge that can be accumulated under these gates is small.

  However, according to the second embodiment, as shown in FIG. 11, since the potential well at the timings of time t2 and time t3 can be extended and accumulated under the virtual electrode 8c, the sensitivity can be increased while maintaining the saturation charge amount. An excellent effect that it can be improved can be obtained.

  In the second embodiment, the case where the vertical CCD is driven in four phases has been described. However, the same configuration as described above can be applied to the case where the vertical CCD is driven in five phases or more. Obtainable.

1 photoelectric conversion unit, 2 pixels, 7a to 7d transfer electrode, 8c virtual electrode,
19 vertical transfer channels, 28 potential levels, 29 potential levels,
30 P-type impurity region, 31 potential level, 61 photoelectric conversion unit,
81 light receiving unit, 82 transfer unit,
101,102 TDI-CCD, 191 vertical direction, 192 horizontal direction.

Claims (5)

A TDI type image sensor that includes a photoelectric conversion unit that forms a pixel and transfers a signal charge in a vertical direction, and transfers the signal charge to the photoelectric conversion unit by a time delay integration operation,
The photoelectric conversion unit includes four or more transfer electrodes extending in the horizontal direction and arranged in parallel in the vertical direction, and one of the transfer electrodes is a virtual phase transfer electrode formed of a virtual electrode. And
A horizontal overflow drain structure is provided only on the transfer electrodes other than the virtual phase transfer electrodes, adjacent to the vertical transfer channel portions in the photoelectric conversion units corresponding to the transfer electrodes, respectively.
This is a TDI image sensor. A drive unit for supplying a vertical transfer clock for causing the photoelectric conversion unit to transfer the signal charge in the time delay integration operation;
The vertical transfer clock has a transfer potential for causing the photoelectric conversion unit to transfer the signal charge, and the drive unit transfers the two transfer electrodes adjacent to each other in the vertical direction at the same time. The TDI image sensor according to claim 1, wherein the vertical transfer clock is supplied to the transfer electrode as a potential.   The first potential level when a positive drive voltage is applied to the overflow gate constituting the horizontal overflow drain structure is deeper than the second potential level of the vertical transfer channel portion corresponding to the virtual phase transfer electrode. The TDI image sensor according to claim 1, wherein the image sensor is a TDI image sensor.   A third potential when a positive driving voltage is applied to the overflow gate constituting the lateral overflow drain structure provided in the transfer electrode adjacent to the virtual phase transfer electrode with respect to the second potential level. The fourth potential level when the positive potential is applied to the overflow gate constituting the lateral overflow drain structure provided in the transfer electrode not adjacent to the virtual phase transfer electrode is shallow. The TDI image sensor according to claim 1, wherein the image sensor is a TDI image sensor. In the driving method of the TDI type image sensor according to claim 1,
Supply the vertical transfer clock to transfer the signal charge by time delay integration operation to the photoelectric conversion unit,
Here, the vertical transfer clock has a transfer potential for causing the photoelectric conversion unit to transfer the signal charge, and the two transfer electrodes adjacent to each other in the vertical direction are used as the transfer potential at the same time. Supplied to the electrode,
A method of driving a TDI type image sensor.

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