JP2010245325A - Thin film transistor manufacturing method - Google Patents

Abstract

An object of the present invention is to simplify the etching process and form a thin semiconductor layer.
A gate electrode is formed. A gate insulating film 14 is formed so as to cover the gate electrode 12. A semiconductor layer 16 is formed on the gate insulating film 14 at least in a region overlapping with the gate electrode 12. Plasma treatment with a gas containing a dopant is performed on the semiconductor layer 16 to increase the impurity concentration of the surface layer 18 of the semiconductor layer 16. A conductive film 20 is formed on the surface layer 18 of the semiconductor layer 16 subjected to the plasma treatment. The conductive film 20 is etched to form the source electrode 22 and the drain electrode 24.
[Selection] Figure 6

Description

  The present invention relates to a method for manufacturing a thin film transistor.

  In a thin film transistor, it is known that a contact resistance is lowered by interposing a silicon layer having a high impurity concentration between a silicon layer and a source electrode or a drain electrode (Patent Document 1).

JP-A-11-87721

  Since a conventional thin film transistor forms two silicon layers, it is necessary to etch each of them. In addition, since the silicon layer itself having a high impurity concentration also has resistance, it is preferable to form the thin silicon layer. In order to prevent malfunction due to light absorption, it is preferable to form the two silicon layers thin. However, there was a limit to making it thinner.

  An object of the present invention is to simplify the etching process and form a thin semiconductor layer.

  (1) A method of manufacturing a thin film transistor according to the present invention includes a step of forming a gate electrode, a step of forming a gate insulating film so as to cover the gate electrode, and a region on the gate insulating film overlapping at least the gate electrode. Forming a semiconductor layer on the semiconductor layer, performing a plasma treatment on the semiconductor layer with a gas containing a dopant to increase an impurity concentration of a surface layer of the semiconductor layer, and the semiconductor on which the plasma treatment has been performed. A step of forming a conductive film on the surface layer of the layer; and a step of etching the conductive film to form a source electrode and a drain electrode. According to the present invention, the semiconductor layer is not formed on the semiconductor layer, but the impurity concentration of the surface layer of the semiconductor layer is increased, and a two-layer semiconductor layer can also be formed. Is not etched. Therefore, the etching process can be simplified and the entire semiconductor layer can be formed thin.

  (2) In the method of manufacturing a thin film transistor described in (1), the step of forming the semiconductor layer includes patterning the semiconductor layer, and performing the plasma treatment on the patterned semiconductor layer. The impurity concentration of the surface layer may be increased also on the side surface rising from the gate insulating film.

  (3) In the method for manufacturing a thin film transistor described in (1), the method further includes a step of patterning the semiconductor layer after performing the plasma treatment, and the step of patterning the semiconductor layer increases the impurity concentration. Further, it may be characterized by including etching of the surface layer.

  (4) In the method for manufacturing a thin film transistor described in any one of (1) to (3), the gas may include phosphine which is a compound of phosphorus as the dopant.

It is a figure explaining the manufacturing method of the thin-film transistor which concerns on embodiment of this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on embodiment of this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on embodiment of this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on embodiment of this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on embodiment of this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on embodiment of this invention. It is a perspective view which shows the outline of a liquid crystal display panel. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on the modification of embodiment of this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on the modification of embodiment of this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on the modification of embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. 1 to 6 are diagrams for explaining a method of manufacturing a thin film transistor according to an embodiment of the present invention.

  In the present embodiment, a thin film transistor (specifically, a field effect transistor including a thin film) is formed over the substrate 10. The board | substrate 10 may be comprised from glass and may be comprised from resin. The substrate 10 is light transmissive.

  A gate electrode 12 is formed on the substrate 10 (FIG. 1). The gate electrode 12 is formed from a single layer or a stacked layer of Al, Cr, Mo, Ta or the like. Then, a gate insulating film 14 is formed so as to cover the gate electrode 12. The gate insulating film 14 is made of silicon nitride or the like.

A semiconductor layer 16 is formed on the gate insulating film 14 at least in a region overlapping with the gate electrode 12. The semiconductor layer 16 is made of amorphous silicon, microcrystalline silicon, or polycrystalline silicon. For the formation of the semiconductor layer 16, PECVD (Plasma Enhanced Chemical Vapor Deposition) or sputtering can be applied. For example, the semiconductor layer 16 made of amorphous silicon can be formed by PECVD using monosilane (SiH ₄ ) as a source gas. The step of forming the semiconductor layer 16 includes patterning the semiconductor layer 16. For patterning, etching using an etching resist as a mask can be applied.

As shown in FIG. 2, the semiconductor layer 16 is subjected to plasma treatment with a gas containing a dopant. Examples of the dopant include phosphorus (P) for forming an n-type semiconductor and boron (B) for forming a p-type semiconductor. The gas does not contain monosilane (SiH ₄ ) or other raw materials for forming a film. Plasma is generated in an atmosphere in which such a gas is introduced, and the surface layer 18 of the semiconductor layer 16 is exposed to the plasma.

The impurity concentration of the surface layer 18 of the semiconductor layer 16 can be increased by the plasma treatment. For example, when a gas containing phosphine (PH ₃ ) which is a compound of phosphorus (P) is used, the surface layer 18 can be an n ⁺ layer, and when the gas contains boron (B), the surface layer 18 can be a p ⁺ layer.

  The contact resistance can be lowered by increasing the impurity concentration of the surface layer 18. Further, since the surface layer 18 is not a layer formed by CVD or the like, it can be formed very thin, and its own resistance value can also be lowered. Further, since the impurity concentration is increased by plasma treatment, a structure having a concentration gradient can be formed without an interface between a high concentration layer and a low concentration layer.

  It is possible to increase the impurity concentration of the surface layer 18 by implanting impurities into the semiconductor layer 16 and annealing, but the method is performed at about 500 ° C. On the other hand, the plasma treatment can be performed at a low temperature (about 300 ° C.). Further, in the case of a method of stacking the high-concentration semiconductor layer 16 by CVD or the like, it is required to perform patterning by etching, but in this embodiment, etching is unnecessary.

  In this embodiment, since the plasma treatment is performed on the patterned semiconductor layer 16, the impurity concentration of the surface layer 18 of the semiconductor layer 16 is increased even on the side surface rising from the gate insulating film 14.

  As shown in FIG. 3, a conductive film 20 is formed on the surface layer 18 of the semiconductor layer 16 that has been subjected to plasma treatment. The conductive film 20 is formed of Al, for example.

  As shown in FIG. 4, the conductive film 20 is etched to form the source electrode 22 and the drain electrode 24. Since the surface layer 18 has a high impurity concentration, the contact resistance with the source electrode 22 and the drain electrode 24 is low.

  As shown in FIG. 5, the surface layer 18 having a high impurity concentration (low resistance) in the semiconductor layer 16 is etched in a region between the source electrode 22 and the drain electrode 24. Thereby, the electrical conduction between the source electrode 22 and the drain electrode 24 by the surface layer 18 is cut off. Note that when the surface layer 18 is etched, the portion below the surface layer 18 (inside the semiconductor layer 16) is also slightly etched. A known thin film transistor manufacturing method can be applied to other processes.

  According to the present embodiment, a semiconductor layer is not further formed on the semiconductor layer 16, but the impurity concentration of the surface layer 18 of the semiconductor layer 16 is increased, so that a two-layer semiconductor layer is not formed. The two semiconductor layers are not etched. Therefore, the etching process can be simplified and the entire semiconductor layer 16 can be formed thin. Further, by forming the surface layer 18 thin, the resistance value can be lowered and the on-characteristic of the field effect transistor can be improved.

  In this embodiment mode, a thin film transistor is formed as a switching element for controlling a pixel of a liquid crystal display panel. Therefore, a corresponding process is further performed.

  As shown in FIG. 6, a protective film 26 is formed so as to cover the source electrode 22, the drain electrode 24, and the semiconductor layer 16. Then, a through hole 28 is formed in the protective film 26, and a pixel electrode 30 is formed so as to be electrically connected to one of the source electrode 22 and the drain electrode 24 (the source electrode 22 in FIG. 6). The pixel electrode 30 may be formed of a transparent conductive material such as ITO (indium tin oxide) when light transmission is required, and may be formed of a low resistance material such as Al when light transmission is not required. Good. The manufacturing method of a liquid crystal display panel includes a known process.

  FIG. 7 is a perspective view schematically showing a liquid crystal display panel. The liquid crystal display panel includes a substrate 10 on which the above-described thin film transistor 32 is formed and a color filter substrate 34, and a liquid crystal (not shown) is disposed between the two.

[Modification]
8-10 is a figure explaining the manufacturing method of the thin-film transistor which concerns on the modification of embodiment of this invention.

  In the present modification, as shown in FIG. 8, after the plasma treatment is performed on the semiconductor layer 116, the semiconductor layer 116 is patterned as shown in FIG. Accordingly, the step of patterning the semiconductor layer 116 includes etching of the surface layer 118 with an increased impurity concentration. Then, as shown in FIG. 10, a source electrode 122 and a drain electrode 124 are formed. The details correspond to the contents described in the above embodiment.

  In the present modification, as shown in FIG. 9, the patterned semiconductor layer 116 has a higher impurity concentration on the upper surface, but has a state before the plasma treatment on the side surface. Therefore, as illustrated in FIG. 10, the source electrode 122 and the drain electrode 124 are in contact with the surface layer 118 having a high impurity concentration (low resistance) on the upper surface of the semiconductor layer 116, but on the side surface of the semiconductor layer 116. It is in contact with a higher resistance layer. Other processes are as described in the above embodiment.

  The present invention is not limited to the embodiment described above, and various modifications are possible. For example, the configuration described in the embodiment can be replaced with a substantially the same configuration, a configuration that exhibits the same operational effects, or a configuration that can achieve the same purpose.

  10 substrate, 12 gate electrode, 14 gate insulating film, 16 semiconductor layer, 18 surface layer, 20 conductive film, 22 source electrode, 24 drain electrode, 26 protective film, 28 through hole, 30 pixel electrode, 32 thin film transistor, 34 color filter substrate , 116 semiconductor layer, 118 surface layer, 122 source electrode, 124 drain electrode.

Claims (4)

Forming a gate electrode;
Forming a gate insulating film so as to cover the gate electrode;
Forming a semiconductor layer in a region overlapping at least the gate electrode on the gate insulating film;
Performing a plasma treatment with a gas containing a dopant on the semiconductor layer to increase the impurity concentration of the surface layer of the semiconductor layer;
Forming a conductive film on the surface layer of the semiconductor layer subjected to the plasma treatment;
Etching the conductive film to form a source electrode and a drain electrode;
A method for producing a thin film transistor, comprising: In the manufacturing method of the thin-film transistor described in Claim 1,
Forming the semiconductor layer includes patterning the semiconductor layer;
A method of manufacturing a thin film transistor, wherein the plasma treatment is performed on the patterned semiconductor layer to increase the impurity concentration of the surface layer even on a side surface rising from the gate insulating film. In the manufacturing method of the thin-film transistor described in Claim 1,
Further comprising patterning the semiconductor layer after performing the plasma treatment;
The method of manufacturing a thin film transistor, wherein the step of patterning the semiconductor layer includes etching of the surface layer in which the impurity concentration is increased. In the manufacturing method of the thin-film transistor as described in any one of Claim 1 to 3,
The method for manufacturing a thin film transistor, wherein the gas contains phosphine which is a compound of phosphorus as the dopant.

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