JP2010135671A - Semiconductor equipment and method of manufacturing the same - Google Patents

Abstract

To secure a connection terminal height and to reduce a pitch in a stacked semiconductor device.
A semiconductor device is disposed between a semiconductor device, a semiconductor device, and between the semiconductor device and the semiconductor device, and has a tapered shape that extends from an upper surface formed in a central portion toward a lower surface. And a spacer 35 that is formed adjacent to the through hole 35 b and has a plurality of through holes 35 a for electrically connecting the semiconductor device 3 and the semiconductor device 5. At least one of the plurality of through holes 35a is inclined from the lower surface of the spacer 35 toward the upper surface toward the central portion.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device in which a plurality of semiconductor devices are stacked, and more particularly to a semiconductor device in which a spacer is provided between upper and lower semiconductor devices.

  2. Description of the Related Art In the semiconductor field, SiP (System in Package) and a plurality of semiconductor devices, in which different semiconductor chips are mounted on a semiconductor chip to form a single semiconductor device, are combined into different systems. There are two techniques of POP (Package On Package) that directly binds.

  SiP has the merit of low power consumption and fast circuit operation because the circuits are directly connected to each other. On the other hand, since the POP is manufactured from a semi-finished semiconductor device, it is possible to select a combination of products that have been found to be non-defective products by quality inspection, and the yield of finished products is not reduced. In addition, since the POP is completed in the final mounting process, there is an advantage that a device manufacturer can select by itself a combination of semiconductor devices that exhibits performance that suits the convenience of the product.

  In a POP type semiconductor device, in order to further increase the mounting density, it is required that the connection terminals of the semiconductor device have a narrow pitch and a large number of pins. In addition, at the time of stacking, it is necessary to maintain a distance that is equal to or higher than the height of the semiconductor chip mounted on the lower semiconductor device or the height of the resin covering the semiconductor chip between the upper and lower semiconductor devices.

  However, since the connection terminals are short-circuited when the connection terminals are narrowed, the connection terminals need to be small. For this reason, it is difficult to maintain the height of the connection terminal at a distance greater than the height of the semiconductor chip mounted on the lower semiconductor device or the height of the resin covering the semiconductor chip. On the other hand, there is a method of thinning the semiconductor chip, but the thinning of the chip causes a significant cost increase.

  As a connection method that can satisfy the securing of the height of the connection terminal and the narrowing of the pitch at the same time, for example, there is a conventional technique using a spacer described in Patent Document 1 between the substrates.

  FIG. 8 shows the structure of a conventional semiconductor device.

  As shown in FIG. 8, the conventional semiconductor device 100 has a structure in which a semiconductor device 300 and a semiconductor device 500 are stacked in order from the bottom, and the semiconductor device 300 and the semiconductor device 500 are provided in a spacer 305. The connection terminals (wiring connection portions) 306 are electrically and physically connected to each other.

  In a semiconductor device (upper semiconductor device) 500, a semiconductor chip 503 and a semiconductor chip 502 that are electrically connected to each other are sequentially mounted on a substrate 501, and each of the semiconductor chips 503 and 502 is connected to the substrate via a wire 504. The electrode 505 on the 501 is electrically connected. Further, these structures on the substrate 501 are covered with a resin 506. Note that the semiconductor chip 502 may be electrically connected to the substrate 501 by flip chip connection.

  On the other hand, in the semiconductor device (lower semiconductor device) 300, a semiconductor chip 302 is mounted on a substrate 301, and a spacer 305 is mounted. The spacer 305 is provided with a connection terminal 306 in the through hole, and connects the upper and lower substrates 301 and 501 through the electrode 307. A connection terminal 308 for connecting to another substrate such as a mother board is provided on the lower surface of the substrate 301 via an electrode 307. The semiconductor chip 302 is electrically connected to the substrate 301 by flip chip connection. The substrate 301 and the semiconductor chip 302 are electrically connected to each other through a connection terminal 303. Further, the substrate 301 and the semiconductor chip 302 are physically connected to each other by an adhesive layer 304. Note that the semiconductor chip 302 may be electrically connected to the substrate 301 by wire connection or may be covered with a resin.

Thus, according to the conventional semiconductor device 100, since the spacer 305 is provided between the lower semiconductor device and the upper semiconductor device, adjacent connection terminals even if the connection terminals 306 are narrow in pitch. The height of the connection terminal distance can be realized without causing a short circuit between 306.
International Publication Number WO2008 / 050723A1

  However, in the conventional POP type semiconductor device 100, since the semiconductor chip 302 is mounted on the upper surface of the lower semiconductor device 300, the electrode 7 on the lower substrate 301 is a region where the semiconductor chip 302 is mounted. Can only be placed in other areas.

  The arrangement of the electrodes 307 on the lower surface of the substrate 501 in the upper semiconductor device 500 is the same as the arrangement of the electrodes 307 on the lower substrate 301. For this reason, the number of the electrodes 307 in the POP type semiconductor device 100 is restricted by the area of the semiconductor chip 302 mounted on the lower semiconductor device 300, which is an adverse effect of increasing the number of pins.

  In addition, when both the electrode 307 in the upper semiconductor device 500 and the electrode 307 in the lower semiconductor device 300 have a narrow pitch, both the opening diameter of the upper through hole of the spacer 305 and the opening diameter of the lower through hole are both. Get smaller. For this reason, there is a concern that the mounting yield may decrease due to mounting defects due to non-wetting of the connection terminals 306 or short-circuits between the connection terminals 306.

  In view of the above, an object of the present invention is to provide a semiconductor device having a structure that realizes a narrow pitch while securing the height of a connection terminal. This provides a semiconductor device with high mounting density as well as improved mounting yield.

  A first semiconductor device of the present invention includes a first semiconductor device mounting a first semiconductor chip, and a second semiconductor device formed on the first semiconductor device and mounting a second semiconductor chip. A first through hole disposed between the first semiconductor device and the second semiconductor device and having a tapered shape extending from the upper surface toward the lower surface formed in the central portion; and the first through hole And a spacer having a plurality of second through holes for electrically connecting the first semiconductor device and the second semiconductor device, and a plurality of second through holes. At least one of the holes is inclined toward the center side or the outer side from the lower surface of the spacer toward the upper surface.

  According to the first semiconductor device, the connection terminal of the second semiconductor device can be arranged at a position overlapping the region on the first semiconductor chip mounted on the first semiconductor device, with the spacer interposed. And can be connected to the first semiconductor device. Further, the connection terminal of the second semiconductor device can be arranged at a position where it does not overlap with the region on the first semiconductor device, and can be connected to the first semiconductor device through a spacer. Therefore, securing of the connection terminal height and narrowing of the pitch can be realized.

  In the first semiconductor device of the present invention, it is preferable that at least two of the plurality of second through holes are inclined at different inclinations.

  In the first semiconductor device of the present invention, the upper opening diameter of the inclined second through hole is preferably larger than the lower opening diameter of the inclined second through hole.

  In the first semiconductor device of the present invention, the area of the spacer facing the second semiconductor device is preferably larger than the area of the spacer facing the first semiconductor device.

  In the first semiconductor device of the present invention, a thin film may be formed on the side wall of the second through hole, or on the electrode of the first semiconductor device formed in the second through hole, A metal post may be interposed, or a metal paste may be interposed on the electrode of the first semiconductor device formed in the second through hole.

  In this way, when the connection terminal melts, the wettability of the connection terminal is improved. Moreover, the gap with the electrode in the through hole can be filled with a metal post or a metal paste, which facilitates connection and improves the mounting yield.

  A second semiconductor device of the present invention includes a first semiconductor device mounting a first semiconductor chip, and a second semiconductor device formed on the first semiconductor device and mounting a second semiconductor chip. The groove portion is disposed between the first semiconductor device and the second semiconductor device, and is formed adjacent to the groove portion so as to accommodate the first semiconductor chip on the lower surface side in the central portion. And a spacer having a plurality of through holes for electrically connecting the first semiconductor device and the second semiconductor device, wherein at least one of the plurality of through holes is a lower surface of the spacer. It is inclined toward the center side from the top to the top.

  In the second semiconductor device of the present invention, it is preferable that at least two of the plurality of through holes are inclined at different inclinations.

  In the second semiconductor device of the present invention, it is preferable that the upper opening diameter in the inclined through hole is larger than the lower opening diameter in the inclined through hole.

  In the second semiconductor device of the present invention, a thin film may be formed on the side wall of the second through hole, or on the electrode of the first semiconductor device formed in the second through hole, A metal post may be interposed, or a metal paste may be interposed on the electrode of the first semiconductor device formed in the second through hole.

  In this way, when the connection terminal melts, the wettability of the connection terminal is improved. Moreover, the gap with the electrode in the through hole can be filled with a metal post or a metal paste, which facilitates connection and improves the mounting yield.

  According to the first method for manufacturing a semiconductor device of the present invention, the step (a) of forming an adhesive layer on the spacer and the spacer on the first semiconductor device on which the first semiconductor chip is mounted via the adhesive layer. A step (b) of bonding, a step (c) of mounting a second semiconductor device on which a second semiconductor chip is mounted on the opposite side of the surface of the spacer where the first semiconductor device is present, A step (d) of electrically connecting the first semiconductor device and the second semiconductor device with the connection terminals by heating and melting the connection terminals formed in the semiconductor device 2 in step (a). The spacer includes a first through hole having a tapered shape that extends from the upper surface toward the lower surface in the central portion, and a first semiconductor device and a second semiconductor device that are adjacent to the first through hole by connection terminals. Multiple second for electrical connection And through holes are formed.

  According to the second method of manufacturing a semiconductor device of the present invention, the step (a) of forming an adhesive layer on the spacer and the spacer on the first semiconductor device on which the first semiconductor chip is mounted via the adhesive layer. A step (b) of bonding, a step (c) of mounting a second semiconductor device on which a second semiconductor chip is mounted on the opposite side of the surface of the spacer where the first semiconductor device is present, A step (d) of electrically connecting the first semiconductor device and the second semiconductor device by heating and melting the connection terminals formed in the semiconductor device 2; And forming a groove portion for housing the first semiconductor chip on the lower surface side in the central portion, and a plurality of through holes for electrically connecting the first semiconductor device and the second semiconductor device adjacent to the groove portion. Has been.

  According to the semiconductor device of the present invention, in the POP type semiconductor device, the connection terminal height can be ensured and the pitch can be reduced. As a result, it is possible to provide a semiconductor device with high mounting density as well as improved mounting yield.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention. 2A is a cross-sectional view of a spacer used in the semiconductor device according to the first embodiment of the present invention, and FIG. 2B is a spacer used in the semiconductor device according to the first embodiment of the present invention. FIG.

  As shown in FIG. 1, the semiconductor device 1 of the present embodiment has a structure in which a semiconductor device 3 and a semiconductor device 5 are stacked in order from the bottom, and the semiconductor device 3 and the semiconductor device 5 include a spacer 35. Are electrically and physically connected to each other via a connection terminal (wiring connection portion) 36 provided in the circuit board.

  Here, as a base material layer used for the spacer 35, what is necessary is just a layer which has a dimensional stability, handling appropriateness, and processing appropriateness, and the function which hold | maintains thickness, and a thing with high mechanical strength is preferable. The thickness is appropriately selected according to a desired distance between the lower semiconductor device 3 and the upper semiconductor device 5.

  In a semiconductor device (upper semiconductor device) 5, a semiconductor chip 53 and a semiconductor chip 52 that are electrically connected to each other are sequentially mounted on a substrate 51, and each semiconductor chip 53 and 52 is connected to a substrate via a wire 54. The electrode 55 is electrically connected to the electrode 55. Further, these structures on the substrate 51 are covered with a resin 56. The semiconductor chip 52 may be electrically connected to the substrate 51 by flip chip connection.

  On the other hand, in the semiconductor device (lower semiconductor device) 3, the semiconductor chip 32 is mounted on the substrate 31, and the spacer 35 is mounted. In the spacer 35, a connection terminal (wiring connection part) 36 is provided in the through hole, and the upper and lower substrates 31 and 51 are connected via the electrode 37. A connection terminal 38 for connecting to another substrate such as a mother board is provided on the lower surface of the substrate 31 via an electrode 37. The semiconductor chip 32 is electrically connected to the substrate 31 by flip chip connection. The substrate 31 and the semiconductor chip 32 are electrically connected to each other by connection terminals 33. Further, the substrate 31 and the semiconductor chip 32 are physically connected to each other by an adhesive layer 34. The semiconductor chip 32 may be electrically connected to the substrate 31 by wire connection or may be covered with a resin.

  Thus, in the semiconductor device 1 according to the present embodiment, the upper semiconductor device 3 and the lower semiconductor device 5 are connected to the electrode 37 on the lower surface of the upper substrate 51 and the electrode 37 on the upper surface of the lower substrate 31. It has a structure of being stacked via connection terminals 36 to be connected.

  Here, as shown in FIGS. 2A and 2B, the spacer 35 in this embodiment includes a plurality of through holes 35 a for wiring connection and through holes 35 b for housing the semiconductor chip 32. . Specifically, the through hole 35 b is a through hole having a tapered shape that spreads from the upper surface to the lower surface of the spacer 35. At least one through hole 35a (two on the center side in the figure) among the plurality of through holes 35a is inclined toward the center of the substrate 31 from the lower side to the upper side of the spacer 35, and is open. The diameter is different between the upper side and the lower side of the spacer 35 (the upper side is larger than the lower side). Each of the inclined through holes 35a is inclined toward the central portion at a plurality of angles. In addition, the plurality of through holes 35a have at least portions having different pitches. One or more spacers 35 having such through holes 35 a and 35 b are disposed between the lower semiconductor device 3 and the upper semiconductor device 5.

  As described above, according to the semiconductor device of the present embodiment, the POP type semiconductor device 1 can be downsized by the laminated structure of the lower semiconductor device 3 and the upper semiconductor device 5. The following effects can be obtained.

  That is, since the spacer 35 is disposed between the lower semiconductor device 3 and the upper semiconductor device 5, the pitch of the connection terminals 36 between the lower semiconductor device 3 and the upper semiconductor device 5 is reduced. However, it is possible to maintain a gap between the lower semiconductor device 3 and the upper semiconductor device 5 without causing a short circuit between the connection terminals 36.

  In addition, the spacer 35 is formed so that at least one of the through holes 35a for wiring connection is inclined as described above by providing a tapered shape in the through hole 35b for housing the semiconductor chip 32. As a result, even if the electrodes 37 on the lower surface of the substrate 51 in the upper semiconductor device 5 are arranged so as to overlap the region for mounting the semiconductor chip 32 on the lower semiconductor device 3, the lower semiconductor The device 3 can be connected to the electrode 37 on the lower surface of the substrate 3, and a connection terminal 36 for wiring connection can be formed.

  Therefore, the number of connection terminals 36 can be increased without being restricted by the area of the semiconductor chip 32 mounted on the lower semiconductor device 3. Therefore, the lower semiconductor device 3 and the upper semiconductor device 5 can be stacked even if the terminal diameters and terminal pitches of the connection terminals 36 between the lower semiconductor device 3 and the upper semiconductor device 5 are different. Development costs can be reduced in a POP type semiconductor device.

-Modification 1-
FIG. 3 is a cross-sectional view of a semiconductor device according to the first modification of the present embodiment.

  As shown in FIG. 3, in the semiconductor device 1 according to the first modification, the through hole 35 b for accommodating the semiconductor chip 32 of the spacer 35 is not provided with a taper shape, but the taper shape is formed around the spacer 35. Provided. Compared with the structure of the semiconductor device 1 shown in FIG. 1, the spacer 35 in FIG. 1 has a tapered shape in the through hole 35 b for accommodating the semiconductor chip 32, while the shape around the spacer 35 has a tapered shape. It is different in that it is not provided. The structure of the semiconductor device 1 shown in FIG. 3 is the same as the corresponding structure portion of the semiconductor device 1 shown in FIG. 1 except for the difference in the structure associated with the structure of the spacer 35. In other words, at least one through hole 35a (two on the outside in the drawing) of the plurality of through holes 35a is different in that it is inclined outward from the lower side of the spacer 35 toward the upper side. Others are the same.

  In this way, the electrode 7 on the lower surface of the substrate 51 in the upper semiconductor device 5 is disposed at a position that does not overlap the region where the lower semiconductor device 3 is disposed, so that the upper semiconductor device 5 and the lower semiconductor are disposed. Since it can connect with the apparatus 3, the number of connection terminals can be increased.

(Second Embodiment)
FIG. 4 shows a cross-sectional view of a semiconductor device 1 according to the second embodiment of the present invention.

  As shown in FIG. 4, in the semiconductor device 1 according to the present embodiment, the spacer 35 is provided with a groove 35 c for accommodating the semiconductor chip 32, and no through hole penetrating the spacer 35 in the vertical direction is provided. Compared with the structure of the semiconductor device 1 shown in FIG. 1, the spacer 35 in FIG. 1 differs from the semiconductor chip 32 as a through hole 35 b for accommodating the semiconductor chip 32 in that it vertically penetrates the spacer 35 and has a tapered shape. ing. The structure of the semiconductor device 1 shown in FIG. 3 is the same as the corresponding structure portion of the semiconductor device 1 shown in FIG. 1 except for the difference in the structure associated with the structure of the spacer 35.

  FIG. 5A shows a cross-sectional view of the spacer 35 of the semiconductor device according to this embodiment, and FIG. 5B shows a perspective view of the spacer 35 of the semiconductor device according to this embodiment.

  As shown in FIGS. 5A and 5B, the spacer 35 in the present embodiment accommodates the semiconductor chip 32 and has a groove 35c that does not penetrate in the vertical direction and a plurality of through holes 35a for wiring connection. is doing.

  Thus, by providing the groove 35c for housing the semiconductor chip 32 and having a structure in which the upper portion of the spacer 35 is continuous without passing through, the case of FIG. 1 or FIG. The number of connection terminals can be increased by utilizing the area portion that has been penetrated.

(Third embodiment)
The method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described below.

  Here, as a method for manufacturing the semiconductor device according to the present embodiment, the method for manufacturing the semiconductor device shown in FIG. 1 will be described as an example, but this is the case of the semiconductor device having the structure of FIG. 3 or FIG. However, it can be assumed from the following description of the manufacturing method of the semiconductor device.

  6A to 6D are cross-sectional views for explaining a semiconductor device manufacturing method according to the third embodiment of the present invention in the order of steps, and specifically, the semiconductor device shown in FIG. The process of manufacturing is shown as an example. Note that the description of the structure of the semiconductor device shown in FIG. 1 is as described above.

  First, as shown in FIG. 6A, the through-hole 35b for housing a semiconductor chip provided with a taper shape by laser processing is different from the upper and lower sides in the opening diameter (the upper side is greatly lowered in the final arrangement). A spacer 35 having a plurality of through holes 35c having portions whose pitches are different from each other is formed. Thereafter, the adhesive layer 39 is applied to a predetermined position above the spacer 35. On the other hand, as a part of the structure of the lower semiconductor device 3 described above, the semiconductor chip 32 is mounted on one surface of the substrate 31 via the adhesive layer 34 and the connection terminal 33, and the other side of the substrate 31 is mounted. A structure in which connection terminals 38 are formed on the surface via electrodes 37 is prepared.

  Next, as shown in FIG. 6B, the semiconductor device 3 is pressure-bonded to the adhesive layer 39 of the spacer 35.

  Next, as shown in FIG. 6C, after the flux is applied to the connection terminal 36a before the connection terminal 36 later in the upper semiconductor device 5 having the above-described structure, the upper semiconductor device 5 is formed. The spacer 35 is mounted at a predetermined position.

  Next, as shown in FIG. 6 (d), the upper semiconductor device 5 is mounted on the lower semiconductor device 3 and heated with a reflow device or the like to melt the connection terminal 36a shown in FIG. 6 (c). Then, by connecting to the electrode 37 in the through hole 35a in the lower semiconductor device 3, the connection terminal 36 serving as a wiring connection portion as shown in FIG. 6D is formed.

  In this manner, a structure in which the upper semiconductor device 3 and the lower semiconductor device 5 are stacked via the connection terminals 36 can be manufactured.

-Modification 2-
FIGS. 7A to 7C show a modification of a connection terminal which is a wiring connection portion formed in the spacer 35 as a second modification of the semiconductor device and the manufacturing method thereof according to the first to third embodiments. It is sectional drawing explaining an example.

  7A, the thin film 40 is formed on the inner wall of the through hole 35a of the spacer 35 in the structure of the connection terminal which is the wiring connection portion shown in FIG. In this way, when the connection terminal 36a is melted, the melted connection terminal 36a is easily transmitted along the inner wall of the through hole 35a. For this reason, even if the through hole 35a has a high aspect, poor connection of the formed connection terminals 36 hardly occurs, and the mounting yield is improved.

  Further, in the structure of the connection terminal which is the connection portion for wiring shown in FIG. 7B, an adhesive paste (not shown) is interposed around the lower electrode 37 in the through hole 35a of the spacer 35. A metal post 41 is disposed. In this way, when the connection terminal 36a is melted, the metal post 41 fills the gap between the connection terminal 36a and the lower electrode 37 in the through hole 35a. For this reason, the connection terminal 36 to be formed and the lower electrode 37 in the through hole 35 a are easily connected via the metal post 41.

  Further, in the structure of the connection terminal which is the connection portion for wiring shown in FIG. 7C, a metal paste is formed by interposing an adhesive paste (not shown) around the lower electrode in the through hole 35a of the spacer 35. 41 is filled. In this way, when the connection terminal 36a is melted, the metal paste 42 fills the gap between the connection terminal 36a and the lower electrode 37 in the through hole 35a. For this reason, the connection between the connection terminal 36 to be formed and the lower electrode 37 in the through hole 35 a is easily performed via the metal paste 41.

  In addition, in the structure of the connection part for wiring shown in FIGS. 7A to 7C, the shape of the through hole 35a is as shown in FIGS. 1, 3, and 4 for convenience of explanation. Although the description has been made without using at least one of the plurality of through-holes 35a having a shape in which at least one through-hole 35a is inclined in the vertical direction, the structure of FIGS. 7A to 7C is inclined in the vertical direction. Of course, the present invention can be applied to the case of the through hole 35a.

  In each of the above embodiments, the number of connection terminals can be further increased by applying the structure of the semiconductor device shown in FIG. 1 or 4 to the structure of the semiconductor device shown in FIG.

  Each of the embodiments described above is a preferred specific example for carrying out the present invention, and thus various technical limitations are made. However, there is no specification that the present invention is particularly limited. However, the present invention is not limited to these forms, and covers all changes and modifications included in the scope of the technical idea of the present invention.

  The present invention is useful for POP type semiconductor devices, and is useful for securing the height of connection terminals, narrowing the pitch, improving the mounting yield, and improving the mounting density.

It is sectional drawing which shows the structure of the semiconductor device which concerns on the 1st Embodiment of this invention. (A) is sectional drawing of the spacer in the 1st Embodiment of this invention, (b) is a perspective view of the spacer in the 1st Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the modification 1 of the 1st Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A) is sectional drawing of the spacer in the 2nd Embodiment of this invention, (b) is a perspective view of the spacer in the 2nd Embodiment of this invention. (A)-(d) is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention in process order. (A)-(c) is sectional drawing explaining the modification of the connection terminal which is the connection part for wiring formed in a spacer as the modification 2 in the semiconductor device which concerns on each embodiment of this invention, and its manufacturing method. It is. It is sectional drawing which shows the structure of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 3 Lower semiconductor device 31 Substrate 32 Semiconductor chip 33 Connection terminal 34 Adhesive layer 35 Spacer 35a Through hole 35b Through hole 35c Groove part 36 Connection terminal (connection part for wiring)
36a connecting terminal 37 electrode 38 connecting terminal 5 upper semiconductor device 51 substrate 52, 53 semiconductor chip 54 wire 55 electrode 56 resin 40 thin film 41 metal post 42 metal paste

Claims (15)

A first semiconductor device on which a first semiconductor chip is mounted;
A second semiconductor device formed on the first semiconductor device and mounting a second semiconductor chip;
A first through hole disposed between the first semiconductor device and the second semiconductor device and having a tapered shape extending from an upper surface to a lower surface formed in a central portion; A spacer formed adjacent to a through hole and having a plurality of second through holes for electrically connecting the first semiconductor device and the second semiconductor device;
At least one of the plurality of second through holes is a semiconductor device that is inclined toward the center side or the outside from the lower surface of the spacer toward the upper surface. The semiconductor device according to claim 1,
A semiconductor device, wherein at least two of the plurality of second through holes are inclined at different inclinations. The semiconductor device according to claim 1 or 2,
A semiconductor device in which an upper opening diameter in the inclined second through hole is larger than a lower opening diameter in the inclined second through hole. The semiconductor device according to any one of claims 1 to 3,
A semiconductor device, wherein an area of the spacer facing the second semiconductor device is larger than an area of the spacer facing the first semiconductor device. The semiconductor device according to any one of claims 1 to 4,
A semiconductor device, wherein a thin film is formed on a side wall of the second through hole. The semiconductor device according to any one of claims 1 to 4,
A semiconductor device, wherein a metal post is interposed on an electrode of the first semiconductor device formed in the second through hole. The semiconductor device according to any one of claims 1 to 4,
A semiconductor device in which a metal paste is interposed on an electrode of the first semiconductor device formed in the second through hole. A first semiconductor device on which a first semiconductor chip is mounted;
A second semiconductor device formed on the first semiconductor device and mounting a second semiconductor chip;
A groove portion disposed between the first semiconductor device and the second semiconductor device and formed to receive the first semiconductor chip on a lower surface side in a central portion; and adjacent to the groove portion And a spacer having a plurality of through holes for electrically connecting the first semiconductor device and the second semiconductor device,
At least one of the plurality of through holes is a semiconductor device that is inclined toward the central portion from the lower surface to the upper surface of the spacer. The semiconductor device according to claim 8,
A semiconductor device, wherein at least two of the plurality of through holes are inclined at different inclinations. The semiconductor device according to claim 8 or 9,
A semiconductor device in which an upper opening diameter in the inclined through hole is larger than a lower opening diameter in the inclined through hole. The semiconductor device according to any one of claims 8 to 10, wherein
A semiconductor device, wherein a thin film is formed on a side wall of the through hole. The semiconductor device according to any one of claims 8 to 10, wherein
A semiconductor device, wherein a metal post is interposed on an electrode of the first semiconductor device formed in the through hole. The semiconductor device according to any one of claims 8 to 10, wherein
A semiconductor device in which a metal paste is interposed on an electrode of the first semiconductor device formed in the through hole. Forming an adhesive layer on the spacer (a);
A step (b) of adhering the spacer to the first semiconductor device on which the first semiconductor chip is mounted via the adhesive layer;
A step (c) of mounting a second semiconductor device on which a second semiconductor chip is mounted on the side of the spacer opposite to the surface side on which the first semiconductor device exists;
A step (d) of electrically connecting the first semiconductor device and the second semiconductor device by heating and melting a connection terminal formed in the second semiconductor device;
The spacer in the step (a) includes a first through hole having a tapered shape extending from an upper surface toward a lower surface in a central portion, the first semiconductor device adjacent to the first through hole, and the A method of manufacturing a semiconductor device, wherein a plurality of second through holes for electrically connecting a second semiconductor device via the connection terminals are formed. Forming an adhesive layer on the spacer (a);
A step (b) of adhering the spacer to the first semiconductor device on which the first semiconductor chip is mounted via the adhesive layer;
(C) mounting a second semiconductor device on which a second semiconductor chip is mounted on the side of the spacer opposite to the surface side on which the first semiconductor device exists;
(D) electrically connecting the first semiconductor device and the second semiconductor device via the connection terminal by heating and melting the connection terminal formed on the second semiconductor device; Prepared,
The spacer in the step (a) includes a groove portion that houses the first semiconductor chip on a lower surface side in a central portion, and the first semiconductor device and the second semiconductor device that are adjacent to the groove portion. A method for manufacturing a semiconductor device, wherein a plurality of through holes for electrical connection are formed.

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