JP2010135658A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device including a lateral field effect transistor with high alignment accuracy is obtained by a simple procedure.
A semiconductor device includes a step of forming a comb-shaped insulating film having comb teeth on at least one side in a gate length direction on a gate electrode, and a semiconductor substrate using the comb-shaped insulating film as a mask. The first conductivity type impurity diffusion regions and the second conductivity type impurity diffusion regions are alternately arranged with a constant width along the gate width direction of the gate electrode 110 by implanting first conductivity type impurity ions into the gate electrode 110. Forming a drift region 172 having a super junction structure, forming a sidewall 152 formed on both sides of the comb-shaped insulating film 150 and burying a region between the comb teeth of the comb-shaped insulating film 150, and the sidewall 152 And forming a source region 116a and a drain region 116b using the mask as a mask.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Conventionally, a lateral field effect transistor having a super junction structure is known (Patent Documents 1 to 3 (US Pat. No. 7,023,050, US Pat. No. 7,202,526, US Pat. No. 7,105,387)) Patent Document 1).

  FIG. 20 is a plan view showing the configuration of such a lateral field effect transistor. Here, the configuration of the surface of the semiconductor substrate 22 of the semiconductor device 10 and the gate electrode 24 are shown. The semiconductor device 10 includes a p-type channel region 12, a p-type impurity diffusion region 14, an n-type source region 16a and a drain region 16b, and a drift region provided between the channel region 12 and the drain region 16b. 18 and so on. The drift region 18 has a superjunction structure in which n-type pillars 20 a and p-type pillars 20 b are alternately repeated at regular intervals along the gate width direction of the gate electrode 24.

With such a superjunction structure, the n-type pillar 20a and the p-type pillar 20b are completely depleted with a constant electric field, so that the electric field is relaxed compared to a transistor without a superjunction structure. For this reason, even if the impurity concentration on the substrate surface is increased, a high breakdown voltage can be achieved.
US Pat. No. 7,022,050 US Pat. No. 7,202,526 US Pat. No. 7,105,387 S. Iwamoto, K. Takahashi, H. Kuribayashi, S. Wakimoto, K. Mochizuki, and H. Nakazawa, “Above 500V class Superjunction MOSFETs fabricated by deep trench etching and epitaxial growth“, Proceedings of the 17th International Symposium on Power Semiconductor Devices &IC's May 23-26, 2005

  However, as described in Non-Patent Document 1, for example, conventionally, when forming a superjunction structure of the drift region 18, for example, a groove is formed in a substrate of one conductivity type, and an opposite conductivity type pillar is formed by epitaxial growth. There is a problem that the process becomes complicated.

  Further, when impurity ions are implanted using, for example, a photoresist in order to form the source region 16a and the drain region 16b, an alignment error in the photolithography process must be taken into consideration, which is indicated by an arrow in FIG. As described above, it is necessary to take a margin (p-type impurity diffusion region 14) between the drift region 18 and the drain region 16b, resulting in a problem that the device area increases. In addition, such alignment errors may cause variations in characteristics such as withstand voltage and resistance during operation.

According to the present invention,
Forming a gate electrode on a channel region of a substrate having a second conductivity type region formed on the surface;
Forming a comb-shaped first insulating film on the gate electrode, covering the gate electrode and having comb teeth on at least one side in the gate length direction;
Using the first insulating film as a mask, first conductivity type impurity ions are implanted into the substrate, and a first conductivity type impurity diffusion region is formed in a region between the comb teeth of the first insulating film. And forming a drift region of a superjunction structure in which the first conductivity type impurity diffusion regions and the second conductivity type impurity diffusion regions are alternately arranged with a constant width along the gate width direction of the gate electrode. And a process of
Forming a second insulating film on the entire surface of the substrate, and embedding the first insulating film in the second insulating film;
The second insulating film is etched back by dry etching, formed on both sides of the first insulating film in the gate length direction, and the first conductive type impurity diffusion region on the first conductivity type in the drift region. Forming a sidewall for embedding a region between the comb teeth of the insulating film;
Implanting first conductivity type impurity ions using the sidewall as a mask, and forming a first conductivity type drain region on the one side in the gate length direction and a first conductivity type source region on the other side; ,
Provides a method of manufacturing a semiconductor device including a step of forming a field effect transistor.

According to the present invention,
A substrate,
A gate electrode formed on a channel region of the substrate;
A source region and a drain region of a first conductivity type respectively formed on both sides of the channel region on the substrate surface;
The first conductivity type impurity diffusion region and the second conductivity type impurity diffusion region are alternately provided with a constant width along the gate width direction of the gate electrode provided between the channel region and the drain region. A drift region of the arranged superjunction structure;
A first insulating film formed on the gate electrode so as to cover the gate electrode;
Sidewalls formed on both sides of the first insulating film in the gate length direction on the substrate;
Including
The first insulating film is formed in a comb-shaped structure having comb teeth covering the impurity diffusion region of the second conductivity type in the drift region in plan view,
There is provided a semiconductor device including a field effect transistor in which the sidewall is formed by burying a region between the comb teeth of the first insulating film on the impurity diffusion region of the first conductivity type in the drift region. The

  With this configuration, the field-effect transistor has the comb-shaped first insulating film, and the region between the comb teeth of the first insulating film is buried with the second insulating film, and on both sides of the first insulating film. A sidewall constituted by the second insulating film is formed. Therefore, the distance between the gate electrode and the drain region can be defined by the sidewall. Therefore, it is not necessary to take a margin in consideration of the alignment error as in the case of using a photoresist, and the device area can be prevented from becoming unnecessarily large. In addition, since the field effect transistor has the comb-shaped first insulating film, the drift region can be formed in a self-aligned manner using the gate electrode as a mask, so that a semiconductor device can be formed by a simple method. it can.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between methods, apparatuses, and the like are also effective as an aspect of the present invention.

  According to the present invention, a semiconductor device including a lateral field effect transistor with high alignment accuracy can be obtained by a simple procedure.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a perspective view showing a configuration of a semiconductor device in the present embodiment. FIG. 2 is a plan view showing the surface configuration of the semiconductor substrate of the semiconductor device.
In the present embodiment, the semiconductor device 100 includes a high breakdown voltage transistor 128 that is a lateral field effect transistor. The semiconductor device 100 includes a semiconductor substrate (substrate) 101, a gate electrode 110 formed on a p-type (second conductivity type) channel region 170 in a P well 102 on the semiconductor substrate 101, and a gate electrode 110. It includes a comb-shaped insulating film 150 formed and sidewalls 152 formed on both sides of the comb-shaped insulating film 150.

  The semiconductor device 100 includes an n-type (first conductivity type) source region 116a and a drain region 116b formed on both sides of the channel region 170 on the surface of the semiconductor substrate 101, and between the channel region 170 and the drain region 116b. , A n-type extension region 174 provided between the channel region 170 and the source region 116a, and an n-type extension region provided between the drift region 172 and the drain region 116b. 176.

  Here, the drift region 172 has a superjunction structure in which n-type impurity diffusion regions 180 and p-type impurity diffusion regions 182 are alternately arranged with a constant width along the gate width direction of the gate electrode 110. .

  In the present embodiment, comb-shaped insulating film 150 is formed in a comb-shaped structure having comb teeth that cover p-type impurity diffusion region 182 of drift region 172 in plan view. In the present embodiment, comb-shaped insulating film 150 has a shape overlapping channel region 170 and p-type impurity diffusion region 182 of drift region 172. In the present embodiment, n-type impurity diffusion region 180 of drift region 172 is formed in a self-aligned manner using comb teeth of comb-shaped insulating film 150 as a mask. Here, as will be described later, the n-type impurity diffusion region 180 is formed by implanting an n-type impurity exceeding its concentration into a region (p-type impurity diffusion region 106) into which a p-type impurity has been previously introduced. It is formed. On the other hand, in the superjunction structure such as the drift region 172, it is preferable to make the space charges in the p / n regions equal. The width and interval of the comb teeth of the comb insulating film 150 are determined in consideration of these. By making the width of the comb teeth of the comb-shaped insulating film 150 larger than the interval between the comb teeth, the space charge can be well balanced.

  Sidewall 152 embeds a region between comb teeth of comb-shaped insulating film 150 on p-type impurity diffusion region 182 of drift region 172. In this embodiment, the source region 116a and the drain region 116b are formed in a self-aligning manner using the sidewall 152 as a mask. Therefore, the distance between the channel region 170 and the source region 116 a and the distance between the drift region 172 and the drain region 116 b are defined by the width of the sidewall 152.

  In the present embodiment, the first conductivity type is n-type, the second conductivity type is p-type, and an n-type field effect transistor (n-FET) is described as an example. However, the first conductivity type is p-type. The p-type field effect transistor (p-FET) can be formed in the same configuration, with the n-type and the second conductivity type.

  In the present embodiment, the high breakdown voltage transistor 128 can be configured to have a breakdown voltage of about 10 to 20 V, for example.

Next, a manufacturing procedure of the semiconductor device 100 in the present embodiment will be described.
3 to 9 are diagrams showing a manufacturing procedure of the semiconductor device 100 according to the present embodiment. 3 to 9, FIGS. 3A to 9A are plan views showing the configuration of the semiconductor device 100. FIGS. 3B to 9B are cross-sectional views taken along line aa in FIGS. 3A to 9A, respectively. FIGS. 4C to 7C are cross-sectional views taken along line bb of FIGS. 4A to 7A, respectively. 10 and 11 are cc cross-sectional views of FIGS. 5A and 7A, respectively.

First, the element isolation insulating film 104 is formed on the surface of the semiconductor substrate 101. Subsequently, a P well 102 is formed in a predetermined region on the surface of the semiconductor substrate 101. Next, p-type impurity ions (for example, conditions of 15 keV and 6E12 cm ⁻² ) are implanted into a region that will later become the drift region 172 in the P well of the semiconductor substrate 101 to form a p-type impurity diffusion region 106 (FIG. 3 (a), FIG. 3 (b)).

  Thereafter, an insulating film for forming the gate insulating film 108 and a conductive film for forming the gate electrode 110 are stacked in this order on the entire surface of the semiconductor substrate 101. In the present embodiment, the gate insulating film 108 can be composed of, for example, a silicon oxide film, a high dielectric constant film, or a laminated film thereof. In the present embodiment, the conductive film for forming gate electrode 110 can be made of, for example, polycrystalline silicon. Next, the conductive film and the insulating film are patterned into a predetermined shape. Thereby, the gate insulating film 108 and the gate electrode 110 are formed on the semiconductor substrate 101 (FIGS. 4A, 4B, and 4C).

Subsequently, an insulating film is formed on the entire surface of the semiconductor substrate 101. Here, the insulating film can be composed of, for example, a silicon oxide (SiO ₂ ) film deposited by chemical vapor deposition (CVD). Next, using a resist film (not shown), the insulating film is patterned into a predetermined shape to form a comb-shaped insulating film 150. In the present embodiment, the comb-shaped insulating film 150 is formed in a comb shape in plan view, and comb-shaped comb teeth are disposed on a region that later becomes the drift region 172. The comb-teeth of the comb-shaped insulating film 150 are such that the portion where the n-type impurity diffusion region 180 that will later become the drift region 172 is opened and the portion where the p-type impurity diffusion region 182 is formed is covered. (FIG. 5A, FIG. 5B, FIG. 5C, FIG. 10).

Subsequently, n-type impurity ions (for example, conditions of 10 keV and 1E13 cm ⁻² ) are implanted into the semiconductor substrate 101 using the comb-shaped insulating film 150 as a mask to form an n-type impurity diffusion region 112 (FIG. 6A). FIG. 6B and FIG. 6C. Here, the concentration of the n-type impurity ions can be higher than the concentration of the p-type impurity ions in the p-type impurity diffusion region 106. In this embodiment, since the comb-shaped insulating film 150 is formed in a comb shape in plan view, n-type impurity ions are implanted into the region between the comb teeth of the comb-shaped insulating film 150 as shown in FIG. As a result, a superjunction structure as shown in FIG. 2 is formed.

  In the present embodiment, the n-type impurity diffusion region 112 is formed using the comb-shaped insulating film 150 as a mask. Therefore, by appropriately controlling the film thickness of the comb-shaped insulating film 150 and increasing the thickness to some extent, the n-type impurity diffusion region 112 is formed. Therefore, the concentration of n-type impurity ions to be implanted can be increased. Therefore, the concentration of p-type impurity ions in p-type impurity diffusion region 106 can also be increased, and the concentration of drift region 172 can be increased.

Next, an insulating film is formed on the entire surface of the semiconductor substrate 101. Here, the insulating film can be constituted by, for example, a silicon oxide (SiO ₂ ) film deposited by CVD or a laminated structure of a silicon oxide film and a silicon nitride (Si ₃ N ₄ ) film. The thickness of the insulating film to be deposited is at least a half of the interval between comb teeth of the comb-shaped insulating film 150. Thereby, the space between the comb-shaped insulating films 150 is filled with the insulating film. Thereafter, anisotropic etching is performed to expose the semiconductor substrate 101 where the source region 116a and the drain region 116b are to be formed, and the comb-shaped insulating film 150 on the gate electrode 110 and the comb-tooth portion, and on both sides of the gate electrode 110. A sidewall 152 is formed on the side (FIGS. 7A, 7B, 7C, and 11).

  At this time, since the space between the comb teeth of the comb-shaped insulating film 150 is filled with the insulating film, the insulating film remains even if anisotropic etching is performed. Therefore, for example, the distance d from the tip of the comb insulating film 150 on the side where the drain region 116b is to be formed later to the end of the sidewall 152 is set to the end of the comb insulating film 150 on the side where the source region 116a is formed later. Can be made as narrow as the distance d ′ from the end of the side wall 152 (see FIG. 11).

  In this embodiment, by using the comb-shaped insulating film 150, the drift region 172 can be formed in a self-aligned manner, and the sidewall 152 is embedded in a region between the comb teeth of the comb-shaped insulating film 150. Side walls 152 having a predetermined width can be formed on both sides of the gate electrode 110, and the distance between the gate electrode 110 and the drain region 116 b can be defined by the side walls 152. Therefore, it is not necessary to take a margin in consideration of the alignment error as in the case of using a photoresist, and the device area can be prevented from becoming unnecessarily large.

Subsequently, using the sidewall 152 as a mask, n-type impurity ions (for example, conditions of 10 keV and 3E15 cm ⁻² ) are implanted into the semiconductor substrate 101 to form the source region 116a and the drain region 116b (FIG. 8A). 8 (b)). Thereafter, the implanted ions are electrically activated in the semiconductor substrate by, for example, heat treatment at 1000 ° C. for 30 seconds by an RTA (rapid thermal annealing) method or the like.

  Thereafter, an interlayer insulating film 122 (not shown in FIG. 9A) is formed on the entire surface of the semiconductor substrate 101, and contact holes for exposing the source region 116a, the drain region 116b, and the gate electrode 110 are formed. Subsequently, a conductive material is embedded in the contact hole to form the contact 124. Further, an interlayer insulating film (not shown) is formed on the interlayer insulating film 122, and a wiring groove is formed in the interlayer insulating film. Next, a conductive material is embedded in the wiring trench to form the wiring 126. Thus, the semiconductor device 100 is formed (FIGS. 9A and 9B).

  According to semiconductor device 100 in the present embodiment, high breakdown voltage transistor 128 has comb-shaped comb insulating film 150, and therefore drift region 172 can be formed in a self-aligned manner using comb-shaped insulating film 150 as a mask. . Further, the sidewall 152 can be embedded in a region between the comb teeth of the comb-shaped insulating film 150 so that sidewalls 152 having a predetermined width are formed on both sides of the comb-shaped insulating film 150. The gate electrode 110 and the drain region 116b can be formed. Can be defined by a sidewall 152. Therefore, it is not necessary to take a margin in consideration of the alignment error as in the case of using a photoresist, and the device area can be prevented from becoming unnecessarily large.

(Second Embodiment)
In this embodiment, the semiconductor device 100 can have a structure in which a low breakdown voltage transistor is formed in addition to the high breakdown voltage transistor 128 described in the first embodiment. A procedure for simultaneously forming the high breakdown voltage transistor 128 and the low breakdown voltage transistor will be described below.

  12, 18 and 19 are plan views of semiconductor device 100 in the present embodiment. 13 to 17 are process cross-sectional views illustrating the manufacturing procedure of the semiconductor device 100 according to the present embodiment. 13A corresponds to the aa sectional view of FIG. 12, FIG. 14B corresponds to the aa sectional view of FIG. 18, and FIG. 15B corresponds to the aa sectional view of FIG. . Also, in each of FIGS. 13 to 17, cross-sectional views corresponding to cross-sections aa in FIGS. 12, 18 and 19 are shown.

  The semiconductor device 100 is provided with a high breakdown voltage region 200 in which the high breakdown voltage transistor 128 is formed and a low breakdown voltage region 202 in which the low breakdown voltage transistor 142 is formed.

First, the element isolation insulating film 104 is formed on the surface of the semiconductor substrate 101. Subsequently, a P well 102 is formed in a predetermined region on the surface of the semiconductor substrate 101. Also in the present embodiment, as in the first embodiment, the P well 102 is formed on the surface of the semiconductor substrate 101, but the description of the semiconductor substrate 101 is omitted. Next, p-type impurity ions (for example, conditions of 15 keV and 6E12 cm ⁻² ) are implanted into a region that will later become the drift region 172 in the P well of the semiconductor substrate 101 in the high breakdown voltage region 200, and the p-type impurity diffusion region 106. (FIGS. 12 and 13A).

  Thereafter, a gate insulating film 108 is formed on the entire surface of the semiconductor substrate 101. Here, the gate insulating film 108 can be, for example, a silicon oxide film formed by oxidizing the surface of the semiconductor substrate 101. Next, a resist film 130 that selectively covers the high withstand voltage region 200 and is opened in the low withstand voltage region 202 is formed (FIG. 13B). Subsequently, the gate insulating film 108 exposed in the low breakdown voltage region 202 is removed by etching with, for example, hydrogen fluoride (HF). Next, a gate insulating film 132 having a thickness smaller than that of the gate insulating film 108 is formed in the low withstand voltage region 202 (FIG. 14A). The gate insulating film 132 can be, for example, a silicon oxide film formed by oxidizing the surface of the semiconductor substrate 101. Thereafter, the resist film 130 is removed.

  Thereafter, a conductive film for forming the gate electrode 110 is formed on the entire surface of the semiconductor substrate 101. Next, the conductive film and the insulating film are patterned into a predetermined shape. Thereby, the gate electrode 110a and the gate electrode 110b are formed in the high breakdown voltage region 200 and the low breakdown voltage region 202 on the semiconductor substrate 101, respectively. Here, the gate electrode 110a has the same configuration as the gate electrode 110 described in the first embodiment (FIG. 14B). The gate insulating film 108 and the gate insulating film 132 are also patterned together with the gate electrode 110a and the gate electrode 110b, respectively, and have the same shape as the gate electrode 110a and the gate electrode 110b.

Subsequently, a resist film 136 is formed on the semiconductor substrate 101 so as to selectively cover the high breakdown voltage region 200 and open in the low breakdown voltage region 202. Next, in the low breakdown voltage region 202, n-type impurity ions (for example, conditions of 20 keV and 1E14 cm ⁻² ) are implanted into the semiconductor substrate 101 using the gate electrode 110 b as a mask, and an n-type extension region 138 is formed in the low breakdown voltage region 202. (FIG. 15A).

Subsequently, an insulating film is formed on the entire surface of the semiconductor substrate 101. Here, the insulating film can be composed of, for example, a silicon oxide (SiO ₂ ) film deposited by CVD. Next, the insulating film is patterned into a predetermined shape using a resist film (not shown), and the comb-shaped insulating film 150a is formed on the side of the gate electrode 110a in the high breakdown voltage region 200, and the gate electrode 110b is formed on the side of the low breakdown voltage region 202. Side walls 150b are respectively formed on the substrate. Here, the comb-shaped insulating film 150a has the same configuration as the comb-shaped insulating film 150 described in the first embodiment (FIG. 15B).

  Subsequently, a resist film 139 that selectively covers the low withstand voltage region 202 and is opened in the high withstand voltage region 200 is formed (FIG. 16A). Next, in the high breakdown voltage region 200, n-type impurity ions are implanted into the semiconductor substrate 101 using the comb insulating film 150 a as a mask, and an n-type impurity diffusion region 112 is formed in the high breakdown voltage region 200. Here, the concentration of the n-type impurity ions can be the same as in the first embodiment.

Next, an insulating film is formed on the entire surface of the semiconductor substrate 101. Here, the insulating film can be constituted by, for example, a silicon oxide (SiO ₂ ) film deposited by CVD or a laminated structure of a silicon oxide film and a silicon nitride film (Si ₃ N ₄ ) film. The thickness of the insulating film to be deposited is at least a half or more of the interval between the comb teeth of the comb-shaped insulating film 150a. Thereby, the space between the comb teeth of the comb-shaped insulating film 150a is filled with the insulating film.

  Thereafter, anisotropic etching is performed to form the source region 116a and the drain region 116b of the high breakdown voltage region 200 and the semiconductor substrate 101 where the source region 140a and the drain region 140b of the low breakdown voltage region 202 are formed, and the gate electrode 110a and The gate electrode 110b is exposed. Thus, the sidewall 152a and the sidewall 152b are formed on both sides of the comb-shaped insulating film 150a of the gate electrode 110a and the sidewall 150b of the gate electrode 110b, respectively (FIG. 16B).

Subsequently, n-type impurity ions (for example, conditions of 10 keV and 3E15 cm ⁻² ) are implanted into the semiconductor substrate 101 using the comb-shaped insulating film 150 a and the sidewalls 152 a, and the sidewalls 150 b and the sidewalls 152 b as masks. The source region 116a and the drain region 116b are formed in the low breakdown voltage region 202, and the source region 140a and the drain region 140b are formed in the low breakdown voltage region 202, respectively (FIG. 17A). Thereafter, the implanted ions are electrically activated in the semiconductor substrate by, for example, heat treatment at 1000 ° C. for 30 seconds by an RTA (rapid thermal annealing) method or the like.

  Thereafter, an interlayer insulating film 122 is formed on the entire surface of the semiconductor substrate 101, and contact holes are formed to expose the source region 116a and the drain region 116b, the source region 140a and the drain region 140b, and the gate electrode 110a and the gate electrode 110b. Subsequently, a conductive material is embedded in the contact hole to form the contact 124. Further, an interlayer insulating film (not shown) is formed on the interlayer insulating film 122, and a wiring groove is formed in the interlayer insulating film. Next, a conductive material is embedded in the wiring trench to form the wiring 126. Thus, the semiconductor device 100 in which the high breakdown voltage transistor 128 is formed in the high breakdown voltage region 200 and the low breakdown voltage transistor 142 is formed in the low breakdown voltage region 202 is formed (FIG. 17B).

  Also in this embodiment, the same effect as that of the first embodiment can be obtained. Further, the low breakdown voltage transistor 142 and the high breakdown voltage transistor 128 can be formed in the same process and with a simple procedure.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

  In the above embodiment, the case where the gate electrode is made of polycrystalline silicon has been described as an example. However, the gate electrode can be made of a material having a lower resistance than that of polycrystalline silicon, such as polysilicide. . Thereby, the resistance of the gate electrode can be lowered.

  After forming the source region 116a and the drain region 116b, a metal layer such as Ni or Co is formed on the entire surface of the semiconductor substrate 101, and the exposed source region 116a and drain region 116b on the surface of the semiconductor substrate 101 are selectively selected. It can also be silicided (self-aligned silicidation). Thus, silicide layers can be formed on the surfaces of the source region 116a and the drain region 116b, and the contact resistance of the source region 116a and the drain region 116b can be reduced. At this time, in the low breakdown voltage transistor 142 described in the second embodiment, a silicide layer can also be formed on the surface of the gate electrode 110b.

  In the above embodiment, the example in which the drift region 172 is formed between the channel region 170 and the drain region 116b of the high breakdown voltage transistor 128 is shown. However, the channel region 170 may be provided between the channel region 170 and the source region 116a. The high breakdown voltage transistor 128 having such a structure is formed by providing the comb-shaped insulating film 150 on the source region 116a side and forming the n-type impurity diffusion region 112 using the comb-shaped insulating film 150 as a mask. Can do. FIG. 21 is a plan view showing the surface configuration of the semiconductor substrate 101 of the semiconductor device 100 having such a configuration. With such a configuration, the high breakdown voltage transistor 128 can have a high breakdown voltage even when the source and drain are inverted.

  In the above embodiment, the example in which the p-type impurity diffusion region 106 is selectively provided only in the region where the drift region 172 is to be formed later is described. However, as the p-type impurity diffusion region 106, the P well 102 is used. Can be used. That is, the p-type impurity diffusion region 182 of the drift region 172 and the channel region 170 can have the same concentration profile.

It is a perspective view which shows the structure of the semiconductor device in embodiment of this invention. It is a top view which shows the surface structure of the semiconductor substrate of the semiconductor device in embodiment of this invention. It is a figure which shows the manufacture procedure of the semiconductor device in embodiment of this invention. It is a figure which shows the manufacture procedure of the semiconductor device in embodiment of this invention. It is a figure which shows the manufacture procedure of the semiconductor device in embodiment of this invention. It is a figure which shows the manufacture procedure of the semiconductor device in embodiment of this invention. It is a figure which shows the manufacture procedure of the semiconductor device in embodiment of this invention. It is a figure which shows the manufacture procedure of the semiconductor device in embodiment of this invention. It is a figure which shows the manufacture procedure of the semiconductor device in embodiment of this invention. It is cc sectional drawing of Fig.5 (a). It is cc sectional drawing of Fig.7 (a). It is a top view of the semiconductor device in an embodiment of the invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is a top view of the semiconductor device in an embodiment of the invention. It is a top view of the semiconductor device in an embodiment of the invention. It is a top view which shows the structure of the semiconductor device for demonstrating the problem of the conventional horizontal field effect transistor. It is a top view which shows the other example of the surface structure of the semiconductor substrate of the semiconductor device in embodiment of this invention.

Explanation of symbols

10 semiconductor device 12 p-type channel region 14 p-type impurity diffusion layer region 16a n-type source region 16b n-type drain region 18 drift region 20a n-type pillar 20b p-type pillar 22 semiconductor substrate 24 gate electrode 100 semiconductor Device 101 Semiconductor substrate 102 P well 104 Element isolation insulating film 106 P-type impurity diffusion region 108 Gate insulating film 110 Gate electrode 110a Gate electrode 110b Gate electrode 112 n-type impurity diffusion region 116a Source region 116b Drain region 122 Interlayer insulating film 124 Contact 126 Wiring 128 High breakdown voltage transistor 130 Resist film 132 Gate insulating film 136 Resist film 138 Extension region 139 Resist film 140a Source region 140b Drain region 142 Low breakdown voltage transistor 150 Comb Insulating film 150a Comb insulating film 150b Side wall 152 Side wall 152a Side wall 152b Side wall 170 Channel region 172 Drift region 174 n-type extension region 176 n-type extension region 180 n-type impurity diffusion region 182 p-type impurity diffusion region 200 High breakdown voltage region 202 Low breakdown voltage region

Claims (7)

Forming a gate electrode on a channel region of a substrate having a second conductivity type region formed on the surface;
Forming a comb-shaped first insulating film on the gate electrode, covering the gate electrode and having comb teeth on at least one side in the gate length direction;
Using the first insulating film as a mask, first conductivity type impurity ions are implanted into the substrate, and a first conductivity type impurity diffusion region is formed in a region between the comb teeth of the first insulating film. And forming a drift region of a superjunction structure in which the first conductivity type impurity diffusion regions and the second conductivity type impurity diffusion regions are alternately arranged with a constant width along the gate width direction of the gate electrode. And a process of
Forming a second insulating film on the entire surface of the substrate, and embedding the first insulating film in the second insulating film;
The second insulating film is etched back by dry etching, formed on both sides of the first insulating film in the gate length direction, and the first conductive type impurity diffusion region on the first conductivity type in the drift region. Forming a sidewall for embedding a region between the comb teeth of the insulating film;
Implanting first conductivity type impurity ions using the sidewall as a mask, and forming a first conductivity type drain region on the one side in the gate length direction and a first conductivity type source region on the other side; ,
The manufacturing method of the semiconductor device including the process of forming a field effect transistor by this. In the manufacturing method of the semiconductor device according to claim 1,
The semiconductor device includes a high breakdown voltage region in which the field effect transistor is formed and a low breakdown voltage region in which a second field effect transistor having a lower breakdown voltage than the field effect transistor is formed,
In the step of forming the gate electrode, the gate electrode is formed in the high breakdown voltage region, a second gate electrode is formed in the low breakdown voltage region, and then the high breakdown voltage region is selectively covered. In a state where the high breakdown voltage region is protected by a first resist film having an opening in the low breakdown voltage region, the second gate electrode of the low breakdown voltage region is formed in the low breakdown voltage region using the second gate electrode as a mask. Including the step of forming extension regions on both sides,
In the step of forming the comb-shaped first insulating film, the comb-shaped first insulating film is formed in the high-breakdown-voltage region, and in the low-breakdown-voltage region, on both sides of the second gate electrode, 1 side wall,
In the step of forming the drift region, in the state where the low breakdown voltage region is protected by a first resist film that selectively covers the low breakdown voltage region and opens the high breakdown voltage region, the drift region is formed in the high breakdown voltage region. Form the
In the step of embedding the first insulating film in the second insulating film, the first sidewall is also embedded with the second insulating film,
In the step of forming the sidewall, the second insulating film is etched back by dry etching, and the second insulating film is formed on the first sidewall of the second gate electrode in the low breakdown voltage region. Forming a second sidewall composed of a film;
In the step of forming the drain region and the source region, also in the low breakdown voltage region, first conductivity type impurity ions are implanted using the first sidewall and the second sidewall as a mask, and the first conductivity Method of manufacturing a semiconductor device for forming a drain region and a source region of a mold A substrate,
A gate electrode formed on a channel region of the substrate;
A source region and a drain region of a first conductivity type respectively formed on both sides of the channel region on the substrate surface;
The first conductivity type impurity diffusion region and the second conductivity type impurity diffusion region are alternately provided with a constant width along the gate width direction of the gate electrode provided between the channel region and the drain region. A drift region of the arranged superjunction structure;
A first insulating film formed on the gate electrode so as to cover the gate electrode;
Sidewalls formed on both sides of the first insulating film in the gate length direction on the substrate;
Including
The first insulating film is formed in a comb-shaped structure having comb teeth covering the impurity diffusion region of the second conductivity type in the drift region in plan view,
The semiconductor device includes a field effect transistor formed by burying a region between the comb teeth of the first insulating film on the impurity diffusion region of the first conductivity type in the drift region. The semiconductor device according to claim 3.
The first conductivity type impurity diffusion region of the drift region is a semiconductor device formed in a self-aligned manner using the comb teeth of the insulating film as a mask. The semiconductor device according to claim 3 or 4,
The semiconductor device in which the source region and the drain region are formed in a self-aligned manner using the sidewall as a mask. The semiconductor device according to claim 3.
The drift region is also provided between the channel region and the source region,
The semiconductor device in which the comb teeth of the first insulating film are also provided on the drift region between the channel region and the source region. The semiconductor device according to claim 3.
A second field effect transistor provided on the same layer as the field effect transistor and having a lower withstand voltage than the field effect transistor is further provided on the substrate.
The second field effect transistor is:
A second gate electrode formed on the second channel region of the substrate;
A second source region and a second drain region of the first conductivity type respectively formed on both sides of the second channel region on the substrate surface;
An extension region of a first conductivity type provided between the second channel region and the second source region and the second drain region,
A semiconductor device including:

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