JP2010129104A - Nonvolatile semiconductor memory device - Google Patents

Abstract

Provided is a nonvolatile semiconductor memory device that minimizes an increase in the number of signal lines of a memory block configured to perform a write operation and a verify operation in parallel and a circuit amount of a selection circuit in the block. .
First and second blocks each having a cell array, a row decoder, and a local bit line selection gate, a plurality of sectors each having a first and a second block, and a bank having a plurality of sectors are included. , A plurality of common global bit lines GBL are arranged in the plurality of sectors of the bank, and the local bit line selection gates of the first and second blocks are connected to the plurality of common global bit lines GBL. Each global bit line GBL is connected to a sense amplifier and a write driver via a global bit line selection gate, and the global bit line selection gate connected to the sense amplifier and the global bit line selection gate connected to the write driver are selected by different addresses. Is done.
[Selection] Figure 1

Description

  The present invention relates to writing of a nonvolatile semiconductor memory device, and more particularly, to reduce the size of signal lines and circuits of a memory block configured to execute a memory cell write operation and a verify operation in parallel. The present invention relates to a nonvolatile semiconductor memory device capable of performing the above.

  In the data write operation to the memory cell of the nonvolatile semiconductor memory device, a verify operation for verifying whether data is correctly written is performed following the write operation. Conventionally, when data is continuously written to a plurality of memory cells of a nonvolatile semiconductor memory device, a write process and a verify are repeatedly performed. FIG. 3 is a timing chart in conventional continuous writing. After the write voltage is supplied to the memory cell at address 0 and the write process is performed, the memory cell at address 0 is verified, and then the address is incremented, and then the write voltage is applied to the memory cell at address 1 And the write process is performed, and the memory cell at address 1 is verified. However, this method requires both a write processing period and a verify period for each memory cell, leading to an increase in write time in continuous writing.

  In order to solve this problem, in Japanese Patent Application No. 2008-278520, when the memory cells of the first and second blocks are alternately written, and writing is performed on the memory cells of one block, the other Method for nonvolatile semiconductor memory device capable of shortening overall write time in continuous write by performing verify on memory cells of block and performing write operation and verify operation in parallel And a writing device. FIG. 4 is a timing chart showing the write sequence and address timing. In FIG. 4, the entire write time in continuous writing is shortened by executing the write sequence and the verify sequence in parallel.

  FIG. 5 is a block diagram showing a configuration of a nonvolatile semiconductor memory device that operates at the timing of FIG. In FIG. 5, since the write selection address and the verify selection address enter each block, the number of signal lines and the circuit amount of the selection circuit in the block increase. As described above, in this method, although the writing time is shortened, there arises a problem that the number of signal lines and the circuit amount of the selection circuit in the block increase.

  The present invention has been made to solve such a problem, and its object is to provide the number of signal lines and the number of signal lines of a memory block configured to perform a write operation and a verify operation in parallel. An object of the present invention is to provide a nonvolatile semiconductor memory device that minimizes an increase in the circuit amount of a selection circuit.

  A nonvolatile semiconductor memory device of the present invention includes a cell array, a row decoder, and a local bit line in a nonvolatile semiconductor memory device having a block having a cell array configured to execute a memory cell write operation and a verify operation in parallel. A plurality of sectors each having first and second blocks each having a selection gate; and a bank having a plurality of sectors. The global bit lines are arranged, and the local bit line selection gates of the first and second blocks are connected to the plurality of common global bit lines, and the plurality of global bit lines are respectively connected via the global bit line selection gates. Connected to sense amplifier and write driver, sense amplifier The global bit line selection gate connected to the global bit line select gate and a write driver connected to, characterized by being selected by different address. As a result, the increase in the number of signal lines in the memory block and the circuit amount of the selection circuit in the block can be minimized.

  An address for selecting a global bit line selection gate that connects a global bit line and a write driver of the nonvolatile semiconductor memory device of the present invention and a global bit line selection gate that connects the global bit line and a sense amplifier is written The address that selects the global bit line selection gate connected to the write driver in the sequence is switched to become the address that selects the global bit line selection gate connected to the sense amplifier in the next verify sequence, and the address Switching is performed by the least significant bit of the address. As a result, it is possible to minimize the increase in the signal line and circuit amount of the global bit line selection gate.

  The local bit line selection gates of the first and second blocks connected to the even-numbered global bit lines of the plurality of common global bit lines of the nonvolatile semiconductor memory device of the present invention and the odd-numbered global bit lines The first and second block local bit line selection gates connected to the even-numbered global bit lines and the first block local bit line selection gates connected to the odd-numbered global bit lines. Two blocks of local bit line select gates are simultaneously selected and the second block local bit line select gate connected to the even numbered global bit line and the first block local connected to the odd numbered global bit line. Bit line select gate is selected at the same time It is characterized in. As a result, it is possible to minimize the increase in signal lines and circuit amount of the local bit line selection gate.

  According to the present invention, it is possible to minimize the increase in the number of signal lines of a memory block configured to perform the memory cell write operation and the verify operation in parallel and the circuit amount of the selection circuit in the block. It is possible to provide a non-volatile semiconductor memory device that can be used.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the nonvolatile semiconductor memory device of the present invention. In FIG. 1, the nonvolatile semiconductor memory device 100 includes a first block 40 (block 0, block 1), a block 0, and a block 1 each having a cell array 10, a row decoder 30, and a local bit line selection gate 20. And a bank 60 having a plurality of sectors 50.

  A plurality of common global bit lines 80 are arranged in the plurality of sectors 50 of the bank 60, and the local bit line selection gates 20 of the first and second blocks 40 are connected to the plurality of common global bit lines 80. ing. The plurality of global bit lines 80 are connected to the sense amplifier 90 and the write driver 95 via the global bit line selection gate 70, respectively.

  In the write operation to the memory cell, the row decoder 30 of the block 1 selects the word line WL2 of the cell array 10 by a predetermined address. The global bit line selection gate 70 is selected by the write address YGW1, and the global bit line GBL1 rises. At this time, the local bit line selection gate 20 of the block 1 is selected by the address YL0, and the selected local bit line is thereby selected. A memory cell at the intersection of LBL and word line WL2 is selected and writing is performed.

  At this time, the row decoder 30 of the block 0 selects the word line WL1 of the cell array 10 with the same address as the row decoder 30 of the block 1. Similarly, the global bit line selection gate 70 is selected by the verify read address YGR0, and the global bit line GBL0 rises. At this time, the local bit line selection gate 20 of the block 0 is selected by the address YL0. The memory cell at the intersection of the local bit line LBL and the word line WL1 selected by the above is selected, read out, and verified.

  By the way, when writing to the same memory cell that has been read, the row decoder 30 of the block 0 selects the word line WL1 of the cell array 10 with the same predetermined address as described above. Further, the global bit line selection gate 70 is selected by the write address YGW0, and the global bit line GBL0 rises. At this time, the local bit line selection gate 20 of the block 0 is selected by the address YL0, thereby selecting the memory cell. Writing is performed.

  At this time, the row decoder 30 of the block 1 similarly selects the word line WL2 of the cell array 10 with the same address. The global bit line selection gate 70 is selected by the verify read address YGR1, and the global bit line GBL1 rises. At this time, the local bit line selection gate 20 of the block 1 is selected by the address YL0, and the memory cell information Are read and verified.

  As described above, the local bit lines LBL connected to the local bit line selection gates 20 of the first and second blocks 40 (block 0 and block 1) selected by the same address YL0 are paired with each other, During a write operation, the other always operates in parallel so that the other performs a verify operation. This operation is the same for the local bit lines LBL connected to the local bit line selection gates 20 of the block 0 and the block 1 selected by the same address YL1 to YL3, respectively, and always operates in parallel. To do.

  This operation will be described with reference to the time sequence of FIG. First, the address for selecting the global bit line selection gate 70 for connecting the global bit line GBL1 and the write driver 95 and the global bit line selection gate 70 for connecting the global bit line GBL1 and the sense amplifier 90 are basically as follows. The read address YGW1 for selecting the global bit line selection gate 70 connected to the write driver 95 in the write sequence selects the global bit line selection gate 70 connected to the sense amplifier 90 in the next verification sequence. Switch to address YGR1.

  The address for selecting the global bit line selection gate 70 that connects the global bit line GBL0 and the write driver 95 and the global bit line selection gate 70 that connects the global bit line GBL0 and the sense amplifier 90 is the write sequence. The write address YGW0 for selecting the global bit line selection gate 70 connected to the write driver 95 in FIG. 5A is a verify read address YGR0 for selecting the global bit line selection gate 70 connected to the sense amplifier 90 in the next verify sequence. It switches to become.

  Then, as shown in the sequence of FIG. 4, when the write address YGW1 rises in the block 1, the series of operations starts in the block 0 and the read address YGR0 for verification rises, and in the block 1 the verify address When the read address YGR1 rises, the block 0 switches so that the write address YGW0 rises. As a result, the memory cell write operation and the verify operation are executed in parallel. At this time, the address switching is performed by the least significant bit of the address. For this reason, it is possible to minimize the increase in the selection circuit of the global bit line selection gate.

  Next, in order to explain the operation of the local bit line selection gate corresponding to the selection conditions of the plurality of global bit lines 80, the local bit line selection gates of the blocks 0 and 1 connected to the even-numbered global bit line GBL0; The connection operation of the local bit line selection gates of blocks 0 and 1 connected to the odd-numbered global bit line GBL01 will be described.

  The global bit lines GBL0 and GBL1 and GBL0 and GBL1 and GBL0 and GBL0 and GBL0 and GBL0, GBL0 and GBL0, GBL0 and GBL0, respectively. At this time, since the local bit lines LBL of the blocks 0 and 1 are always selected in a pair relationship, when the local bit line selection gate of the block 0 connected to the global bit line GBL0 is selected by the address YL0, the global bit line LBL is selected. The local bit line selection gate of the block 1 connected to the line GBL1 is also selected by the address YL0.

  When the local bit line selection gate of block 0 connected to global bit line GBL0 is selected by address YL1, the local bit line selection gate of block 1 connected to global bit line GBL1 is also selected by address YL1. . Thus, the local bit lines LBL in the blocks 0 and 1 are always selected in a pair. Therefore, the row decoders 30 in the blocks 0 and 1 select the word lines WL0 and WL1 of each cell array 10 with the same address. As a result, the selection of the word line of the cell array and the selection of the local bit line are selected by the same address, so that the increase of the decode circuit of the cell array can be minimized.

  FIG. 2 is an address sequence chart showing the progress of each selected address. In FIG. 2, first, in block 0 of bank 0, addresses YL0 and YGW0 are input, and the memory cell of block 0 is written. Next, the addresses YL0 and YGW1 are input to the block 1 of the bank 0, and the memory cells of the block 1 are written. In parallel, the addresses YL0 and YGR0 are input to the block 0 of the bank 0 and the block 0 is written. The read memory cell is read and verified. Next, in block 0 of bank 0, addresses YL2 and YGW2 are input, memory cells of block 0 (not shown) are written, and in parallel in block 0 of bank 0, addresses YL0 and YGR1 are input. The written memory cell is read and verified. In this way, the selection operation is performed by shifting the addresses YGR and YGW for selecting the sense amplifier 90 and the write driver 95 by one.

  As described above, according to the present invention, since the selection switching between the sense amplifier and the write driver is performed by the least significant bit of the address, it is possible to minimize the increase in the selection circuit of the global bit line selection gate. Become. Further, since the selection of the word line of the cell array and the selection of the local bit line are selected by the same address, it is possible to minimize the increase in the decoding circuit of the cell array. Thus, a nonvolatile semiconductor memory device that minimizes the increase in the number of signal lines of a memory block configured to perform a write operation and a verify operation in parallel and the circuit amount of a selection circuit in the block is provided. It becomes possible.

The block diagram which shows the structure of the non-volatile semiconductor memory device of this invention. An address sequence chart showing the progress of each selected address of the storage device of the present invention. The timing chart in the conventional continuous writing. 6 is a timing chart showing a write sequence and address timing. FIG. 5 is a block diagram showing a configuration of a semiconductor memory device that operates at the timing of FIG. 4.

Explanation of symbols

10 cell array 20 local bit line selection gate 30 row decoder 40 first and second block 50 sector 60 bank 70 global bit line selection gate 80 multiple global bit lines 90 sense amplifier 95 write driver 100 nonvolatile semiconductor memory device WL word line LBL local Bit line GBL Global bit line YL0-3 Selection address for local bitline selection gate YGR0-3 Read address for verification YGW0-3 Write address

Claims (3)

In a nonvolatile semiconductor memory device having a block having a cell array configured to perform a write operation and a verify operation of a memory cell in parallel,
A first block and a second block each having a cell array, a row decoder, and a local bit line selection gate; a plurality of sectors each having the first and second blocks; and a bank having the plurality of sectors.
A plurality of common global bit lines are provided in the plurality of sectors of the bank,
The common global bit lines are connected to the local bit line selection gates of the first and second blocks,
The plurality of global bit lines are connected to a sense amplifier and a write driver through global bit line selection gates, respectively.
The nonvolatile semiconductor memory device, wherein the global bit line selection gate connected to the sense amplifier and the global bit line selection gate connected to the write driver are selected by different addresses. An address for selecting the global bit line selection gate that connects the global bit line and the write driver, and the global bit line selection gate that connects the global bit line and the sense amplifier,
The address that selects the global bit line selection gate connected to the write driver in the write sequence is switched to the address that selects the global bit line selection gate connected to the sense amplifier in the next verify sequence. ,
2. The nonvolatile semiconductor memory device according to claim 1, wherein the address switching is performed by a least significant bit of the address. The local bit line selection gates of the first and second blocks connected to the even numbered global bit lines of the plurality of common global bit lines and the first number connected to the odd numbered global bit lines. And the local bit line selection gate of the second block,
The local bit line selection gate of the first block connected to the even-numbered global bit line and the local bit line selection gate of the second block connected to the odd-numbered global bit line are simultaneously selected. And
The local bit line selection gate of the second block connected to the even-numbered global bit line and the local bit line selection gate of the first block connected to the odd-numbered global bit line are simultaneously selected. The nonvolatile semiconductor memory device according to claim 1, wherein:

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