JP2010128192A - Manufacturing method of wiring board and display device - Google Patents

Abstract

A method of manufacturing a wiring board and a display device capable of reducing wiring resistance while suppressing an increase in the number of processes.
A method of manufacturing a wiring board comprising wiring on a substrate, the manufacturing method comprising: forming the wiring on the substrate and projecting the wiring from the substrate in a convex shape; and conductive particles And a step of disposing ink droplets continuously spreading over the entire width of the upper surface of the wiring on the wiring, and a step of firing the ink droplet and forming a conductive layer on the wiring. It is a manufacturing method of a wiring board containing.
[Selection] Figure 5

Description

The present invention relates to a method for manufacturing a wiring board and a display device. More specifically, the present invention relates to a method of manufacturing a wiring board suitable for a large and high-definition display device and the display device.

As the display device is increased in size and definition, the wiring used in the display device tends to be thinner and longer. In recent years, signal delay due to an increase in wiring resistance accompanying the above trend has been regarded as a problem, and a technique for reducing the wiring resistance is desired.

As a wiring formation method, a photolithography method and an ink jet method are generally known.

The photolithography method is a method of forming a wiring pattern by forming a conductive layer by a CVD method or the like, then forming a resist pattern on the conductive layer, and removing unnecessary portions of the conductive layer along the resist pattern. is there. According to the photolithography method, a high-definition wiring pattern can be formed. However, the photolithography method requires a step of removing unnecessary portions of the conductive layer, and there is room for improvement in that the utilization efficiency of the material of the conductive layer is low.

In contrast, the ink jet method is a method in which a conductive layer is formed by applying a solution (ink) in which conductive particles such as metal are dispersed on the surface of a substrate or the like and then removing a solvent component in the ink. According to the inkjet method, a conductive layer can be easily formed only in a necessary portion, and thus a wiring pattern can be formed without providing a step of removing an unnecessary portion of the conductive layer. Therefore, it can be said that the inkjet method is superior in that resource saving can be realized as compared with the photolithography method.

As a method for forming a wiring using an inkjet method, Patent Document 1 discloses a mode in which a thin film is formed by applying ink to a region partitioned by a bank and then removing a solvent component in the ink by heat treatment. Has been.
JP 2006-78859 A

Incidentally, the wiring resistance tends to be inversely proportional to the cross-sectional area of the wiring. Therefore, by forming a conductive layer on the original wiring and using the conductive layer as a part of the wiring, the cross-sectional area of the wiring can be increased and the wiring resistance can be reduced. That is, it is preferable to form a thick conductive layer from the viewpoint of sufficiently reducing the wiring resistance.

When the ink jet method is used, the thickness of the conductive layer is proportional to the thickness (ink amount) of the ink droplet disposed on the wiring. Therefore, in order to form a thick conductive layer using the inkjet method, it is necessary to dispose thick ink droplets on the wiring.

Here, the behavior of the ink droplet when the ink droplet is arranged on the wiring by the conventional method will be described with reference to the drawings. FIG. 7 is a schematic plan view showing a state in which ink droplets are arranged on the wiring by a conventional method. 8A is a schematic cross-sectional view corresponding to the line B1-B2 in FIG. 7, and FIG. 8B is an enlarged view of a region surrounded by a broken line in FIG. 7 and 8, a laminated wiring 110 in which wiring layers 110a, 110b, and 110c are laminated in this order from the insulating substrate 122 side is arranged on the insulating substrate 122, and the laminated wiring 110 (on the wiring layer 110c) is arranged. ) Is provided with ink droplets 121a.

As shown in FIGS. 7 and 8, when the ink droplet 121a is arranged on the wiring layer 110c by the conventional method, the ink droplet 121a spreads in the direction of the white arrow in FIG. At this time, the thickness of the ink droplet 121a is determined by the contact angle of the ink droplet 121a with respect to the upper surface of the wiring layer 110c. When the wiring layer 110c and the ink droplet 121a are formed using a general material, the contact angle of the ink droplet 121a with respect to the upper surface of the wiring layer 110c is less than 6 °. Even if the ink droplet 121a is baked in this state to form the conductive layer, the conductive layer having a sufficient thickness cannot be formed. Therefore, in the conventional method, in order to form a thick conductive layer on the wiring layer 110c, the outer edge of the upper surface of the wiring layer 110c is subjected to a liquid repellency treatment such as a fluorine plasma treatment, and the ink on the upper surface of the wiring layer 110c. There is room for improvement in that the contact angle of the droplet 121a needs to be increased and the number of steps increases.

Further, the contact angle of the ink droplet 121a with respect to the upper surface of the wiring layer 110c can also be increased by forming the wiring layer 110c using a special material having liquid repellency. However, this method is difficult in that it is difficult to arrange the ink droplets 121a in a line by a single drawing on the upper surface of the wiring layer 110c, so that a plurality of drawing and drying steps are required. There was room.

Furthermore, as in Patent Document 1, a thick conductive layer can be formed by disposing ink droplets in a region surrounded by banks (region having a concave cross section). However, this method requires a process for forming a bank, and there is room for improvement in that the number of processes increases.

The present invention has been made in view of the above situation, and an object of the present invention is to provide a method of manufacturing a wiring board and a display device that can reduce the wiring resistance while suppressing an increase in the number of processes. .

The inventors of the present invention have made various studies on a method of manufacturing a wiring board that can reduce the wiring resistance while suppressing an increase in the number of processes. As a result, the width of ink droplets arranged on the wiring and the ink on the upper surface of the wiring We focused on the relationship with the contact angle of the drops. And by arranging ink droplets continuously over the entire width of the upper surface of the wiring, it is found that the ink droplets are held (pinned) by the surface tension acting on the end in the width direction of the wiring, and the above surface By using the tension, the contact angle of the ink droplet with respect to the wiring is increased, and it has been found that the ink droplet can be thickly stacked on the wiring, and the inventors have conceived that the above problems can be solved brilliantly, thereby reaching the present invention. It is a thing.

That is, the present invention is a method for manufacturing a wiring board comprising wiring on a substrate, the manufacturing method includes forming the wiring on the substrate and projecting the wiring from the substrate in a convex shape, A step of ejecting ink containing conductive particles and disposing ink droplets continuously spreading over the entire width of the upper surface of the wiring on the wiring; and firing the ink droplets to form a conductive layer on the wiring A method for manufacturing a wiring board including:
The present invention is described in detail below.

The state in which the wiring is protruded from the substrate is a state in which no partition walls such as banks are formed around the wiring arranged on the substrate (the cross section of the wiring substrate along the width direction of the wiring is concave). For example, the state shown in FIG. 2 described later. When ink droplets are arranged on the wiring in this state, if the width of the ink droplets arranged on the upper surface of the wiring is made smaller than the width of the upper surface of the wiring, as shown in FIG. 7 and FIG. 110c), the ink droplet (ink droplet 121a) spreads, and the ink droplet cannot be thickly stacked on the wiring. On the other hand, according to the method for manufacturing a wiring board of the present invention, the ink ejection area is adjusted and the ink droplets are arranged so as to spread continuously over the entire width of the upper surface of the wiring. Therefore, it is not necessary to form a bank for holding the ink droplet around the wiring. Thereby, wiring resistance can be reduced, suppressing the increase in the number of processes.

Further, according to the method for manufacturing a wiring board of the present invention, the ink droplets disposed on the wiring can be thickened without the bank performing the liquid repellency treatment on the outer edge of the upper surface of the wiring. The wiring resistance can be reduced while suppressing the increase in the resistance. Thus, the present invention is particularly suitable for an aspect that does not include a step of performing a liquid repellent treatment on the upper surface of the wiring and / or a step of forming a bank around the wiring.

The ink is a solution in which conductive particles and a solvent are mixed. The conductive particles may be particles that can form a conductive layer by fusing or the like in the step of firing ink droplets. For example, metal particles made of a single metal such as Ag and Cu, Alloy particles made of an alloy containing Ag, Ag, Cu and the like can be suitably used. Moreover, the said solvent should just be a solvent removed easily at the process of baking an ink drop, for example, should use tetradecane which has a viscosity of 0.005-0.015 Pa.s (5-15 cP) suitably. Can do.

The conductive particles are preferably nanoparticles (average particle diameter of less than 1 μm). Thereby, a conductive layer having a low resistance can be formed on the wiring, and the wiring resistance can be further reduced. Further, the dispersion stability of the conductive particles in the ink is improved, and the generation of precipitates due to the aggregation of the conductive particles can be suppressed. Furthermore, since the melting point of the conductive particles is lowered, ink droplets for forming the conductive layer can be fired at a low temperature.

Note that in this specification, the width of the wiring means the length of the wiring in a direction orthogonal to the extending direction of the wiring. In the present specification, “upper” means a side farther from the substrate, and “lower” means a side closer to the substrate.

The method for producing a wiring board of the present invention is not particularly limited by other steps as long as it has the above-described steps, but a step of performing a liquid repellency treatment on the upper surface of the wiring and / or the periphery of the wiring An embodiment that does not include a step of forming a bank is preferable.
The preferable aspect in the manufacturing method of the wiring board of this invention is demonstrated in detail below. In addition, the various aspects shown below may be combined as appropriate.

The cross section in the vicinity of the upper surface of the wiring preferably has an inversely tapered shape. Thereby, the amount of ink droplets arranged on the wiring can be increased and a thicker conductive layer can be formed. As a result, the wiring resistance can be further reduced. Note that the vicinity of the upper surface of the wiring preferably includes a region from the upper surface of the wiring to 50 nm, for example, a region from the upper surface to 400 nm. The vicinity of the upper surface of the wiring is more preferably a region from the upper surface to the bottom surface of the wiring. When the wiring is a laminated wiring formed by laminating a plurality of wiring layers, the wiring layer arranged at the top of the plurality of wiring layers, that is, a wiring layer (ink) that is in direct contact with ink droplets. The cross section in the vicinity of the upper surface of the wiring layer located immediately below the droplets only needs to be reversely tapered.

In this specification, the reverse tapered shape refers to a shape in which the side surface angle (taper angle) with respect to the substrate surface exceeds 90 °, while the forward tapered shape refers to a side surface angle with respect to the substrate surface of less than 90 °. The shape.

The ink droplet preferably has a contact angle of 6 ° or more with respect to the upper surface of the wiring. Thereby, the thickness of the conductive layer on the wiring can be ensured more reliably, and the wiring resistance can be more reliably reduced. If the contact angle of the ink droplet with respect to the wiring exceeds 10 °, there is a possibility that the ink droplet cannot be held on the wiring. Therefore, the ink droplet preferably has a contact angle with respect to the upper surface of the wiring of 10 ° or less. That is, the contact angle of the ink droplet with respect to the upper surface of the wiring is more preferably 6 to 10 °. In addition, the method for measuring the contact angle of the ink droplet with respect to the wiring is not particularly limited, and for example, a method of measuring the shape of the ink droplet arranged on the wiring on the screen from the cross-sectional direction of the wiring can be mentioned.

The ink is preferably ejected from a direction perpendicular to the upper surface of the wiring. Thereby, ink droplets can be uniformly arranged on the wiring, and a conductive layer with less surface irregularities can be formed on the wiring.

This invention is also a display apparatus provided with the wiring board manufactured using the manufacturing method of the wiring board of this invention. A wiring board manufactured by using the method for manufacturing a wiring board according to the present invention has a feature of low wiring resistance. Therefore, for example, a thin film transistor substrate with low wiring resistance can be manufactured by applying the method for manufacturing a wiring substrate of the present invention to a thin film transistor substrate for a display device including wiring such as gate bus lines. Thus, the occurrence of signal delay in a high-definition display device can be suppressed.

According to the wiring board manufacturing method and display device of the present invention, it is possible to provide a wiring board manufacturing method and display device capable of reducing the wiring resistance while suppressing an increase in the number of processes.

Embodiments will be described below, and the present invention will be described in more detail with reference to the drawings. However, the present invention is not limited only to these embodiments.

(Embodiment 1)
The display device of this embodiment is a liquid crystal display device including a liquid crystal display panel and a backlight unit provided on the back side of the liquid crystal display panel. The liquid crystal display panel includes a thin film transistor (TFT) substrate, a color filter (CF) substrate, and a liquid crystal layer sandwiched between the two substrates.

Next, mainly focusing on one picture element, the configuration of this embodiment will be described in detail with reference to the drawings. FIG. 1 is a schematic plan view showing a picture element of a TFT substrate in the display device of this embodiment. As shown in FIG. 1, the TFT substrate includes a gate bus line 10 extending in parallel in the left-right direction when the liquid crystal display panel is viewed from the front, and a direction orthogonal to each gate bus line 10, that is, the liquid crystal display panel. When viewed from the front, the source bus lines 11 extending in parallel with each other in the vertical direction and the Cs bus extending in parallel with each gate bus line 10, that is, extending in the left-right direction when the liquid crystal display panel is viewed from the front. Line (holding capacity wiring) 12. Thus, the gate bus lines 10 and the Cs bus lines 12 are alternately arranged in parallel with each other. In the present embodiment, each picture element region is roughly defined as a region surrounded by each gate bus line 10 and each source bus line 11 and is arranged in a matrix. A TFT 13 is provided near the intersection of the gate bus line 10 and the source bus line 11. The TFT 13 includes a semiconductor layer 16 formed so as to overlap the gate wiring 18, and a source wiring 17 and a drain wiring 14 formed so as to partially overlap the semiconductor layer 16 in plan view. The drain wiring 14 has a storage capacitor portion 19 having a substantially rectangular shape in plan view at the end opposite to the TFT 13, and the storage capacitor portion 19 is electrically connected to the pixel electrode 15 through the contact hole 20. Yes.

The gate bus line 10 is a laminated wiring in which three wiring layers are laminated, and a conductive layer 21 is disposed on the gate bus line 10. FIG. 2 is a schematic cross-sectional view corresponding to line A1-A2 in FIG. As shown in FIG. 2, the gate bus line 10 includes a wiring layer 10a, 10b having a forward taper shape and a wiring layer 10c having a reverse taper shape on a colorless and transparent insulating substrate 22 from the insulating substrate 22 side. They are stacked in this order. Furthermore, a conductive layer 21 formed using metal nanoparticles is disposed on the gate bus line 10 (on the wiring layer 10c). The conductive layer 21 functions as a part of the gate bus line 10.

Hereinafter, a method for manufacturing the display device of this embodiment will be described. Here, only the manufacturing method of the gate bus line 10 in which the conductive layer 21 is disposed will be described, but the manufacturing method of other members is not particularly limited, and may be manufactured using a general method.

3A to 3C are schematic cross-sectional views illustrating the manufacturing process of the gate bus line according to the first embodiment.
First, the substrate 22 is prepared. The material of the substrate 22 is not particularly limited, and a glass substrate, a quartz substrate, a silicon substrate, a metal plate, a plastic substrate, a flexible organic substrate, a substrate having an insulating film formed on the surface of a stainless plate, or the like can be used. In this embodiment, a glass substrate which is a colorless and transparent insulating substrate is used as the substrate 22.

Next, the wiring layers 10a, 10b, and 10c are formed in this order from the substrate 22 side by sputtering (FIG. 3A). As a material of the wiring layers 10a, 10b, and 10c, low resistance metals such as aluminum (Al), titanium (Ti), molybdenum (Mo), copper (Cu), silver (Ag), or these low resistance metals are mainly used. An alloy material or a compound material as a component can be preferably used. In this embodiment, Ti is used as the material of the wiring layers 10a and 10c, and Al is used as the material of the wiring layer 10b. Thus, by arranging the wiring layer 10b using Al between the wiring layers 10a and 10c using Ti, generation of hillocks can be prevented.

Next, the wiring layers 10a, 10b, and 10c are patterned by photolithography (FIG. 3B). Thereby, the gate bus line 10 can be formed. The width of the upper surface of the wiring layer 10c on which the ink droplets 21a are arranged in a later step may be several tens to several hundreds of μm. Further, the taper angle of the wiring layer 10c exceeds 90 °. That is, the cross section of the wiring layer 10c has an inversely tapered shape.

Next, the ink droplet 21a is arranged on the gate bus line 10 (on the wiring layer 10c) using the ink jet device (FIG. 3C). More specifically, ink containing conductive particles is dropped from the ink head and discharged onto the upper surface of the wiring layer 10c. A plurality of liquid droplets (droplet ink) landed on the upper surface of the wiring layer 10c spread on the wiring layer 10c, and the liquid droplets gather to form an ink droplet 21a having a continuous shape. In this manner, the ink droplets 21a that continuously spread over the entire width of the upper surface of the wiring layer 10c can be disposed on the wiring layer 10c. The thickness of the ink droplet 21a may be about several μm. In this embodiment, 3 to 10 pl / droplet droplets are ejected at a flying speed of 5 to 10 m / s from a direction perpendicular to the landing surface (the upper surface of the wiring layer 10c). Moreover, the ink head which discharges a droplet should just have a nozzle diameter of 30 micrometers-20 mm (20 (phi)). As the conductive particles contained in the ink, metal particles made of a single metal such as Ag or Cu, or alloy particles made of an alloy containing Ag, Cu or the like can be suitably used, and the particle diameter is 3 to 7 nm. Preferably there is. Thus, the conductive particles are preferably metal nanoparticles. As the solvent contained in the ink, tetradecane having a viscosity of 0.005 to 0.015 Pa · s (5 to 15 cP) can be preferably used. The specific gravity of the ink may be about 1.62 g / ml.

Thereafter, the ink droplet 21a is baked to remove the solvent component in the ink droplet 21a and to fuse the conductive particles. Thereby, the conductive layer 21 is formed on the gate bus line 10 (on the wiring layer 10c). Firing is preferably performed at 200 to 400 ° C. for 10 to 60 minutes in an air or nitrogen atmosphere. Through such steps, the conductive layer 21 can be formed on the gate bus line 10 as shown in FIG. The film thickness of the conductive layer 21 may be several hundred nm. Through the above steps, the conductive layer 21 can be formed on the gate bus line 10 (on the wiring layer 10c) as shown in FIG.

Here, the reason why the conductive layer 21 having a sufficient thickness can be formed on the gate bus line 10 in the present embodiment will be described in more detail with reference to the drawings. FIG. 4 is a schematic plan view illustrating a state in which ink droplets are arranged on the gate bus line in the manufacturing process of the display device according to the first embodiment. 5A is a schematic cross-sectional view corresponding to the line A3-A4 in FIG. 4, and FIG. 5B is an enlarged view of a region surrounded by a broken line in FIG. Further, FIG. 6 is a plan photograph showing the gate bus line in a state where ink droplets are arranged.

As shown in FIGS. 4-6, in this embodiment, the ink droplet 21a which spreads continuously over the whole width | variety of the upper surface of the wiring layer 10c is arrange | positioned. That is, the width of the upper surface of the wiring layer 10c is equal to the width of the bottom surface of the ink droplet 21a. Thereby, the effect that the ink droplet 21a is held by the surface tension is generated on the end portion in the width direction of the wiring layer 10c. Therefore, the ink droplet 21a is disposed on the wiring layer 10c in a shape that swells in the thickness direction without spreading beyond the width of the upper surface of the wiring layer 10c. As a result, it is possible to dispose thick ink droplets 21a on the wiring layer 10c as compared with the conventional mode shown in FIG. 7, and the conductive layer 21 having a sufficient thickness can be formed. In the present embodiment, by arranging the conductive layer 21 having a thickness of several hundred nm on the gate bus line 10, the wiring resistance of the gate bus line 10 is reduced to ½ or less. In this way, the wiring resistance of the gate bus line 10 can be reduced and the occurrence of signal delay can be suppressed.

In the present embodiment, the ink droplet 21a can be thickened by adjusting the region where ink is ejected and arranging the ink droplet 21a so as to spread over the entire width of the upper surface of the wiring layer 10c. There is no need to form a bank so as to surround 10c or to perform a liquid repellency treatment on the outer edge of the upper surface of the wiring layer 10c. Accordingly, it is possible to reduce the wiring resistance while suppressing an increase in the number of processes.

In the present embodiment, the cross section of the wiring layer 10c has an inversely tapered shape. As a result, the amount of ink droplets 21a held on the wiring layer 10c can be increased, and thicker ink droplets 21a can be disposed on the wiring layer 10c. As a result, the conductive layer 21 can be formed thicker, and the wiring resistance of the gate bus line 10 can be further reduced.

Furthermore, in the present embodiment, the contact angle of the ink droplet 21a with respect to the wiring layer 10c is 6 ° or more. Thereby, the thickness of the conductive layer 21 on the wiring layer 10c can be ensured more reliably, and the wiring resistance of the gate bus line 10 can be more reliably reduced.

In this embodiment, ink is ejected from a direction perpendicular to the upper surface of the wiring layer 10c. Thereby, the ink droplets 21a can be uniformly arranged on the wiring layer 10c, and the conductive layer 21 with less surface unevenness can be formed.

As described above, in the present embodiment, the occurrence of signal delay can be suppressed by reducing the wiring resistance of the gate bus line 10. Therefore, the display device of the present embodiment can be particularly suitably used for a large and high-definition display device in which signal delay is regarded as a problem.

In the present embodiment, the case where the conductive layer 21 is disposed with respect to the gate bus line 10 has been described as an example. However, the conductive layer 21 may be disposed on a wiring other than the gate bus line 10. For example, when the conductive layer 21 is disposed on the Cs wiring 12 disposed in the same layer as the gate bus line 10, the ink droplet 21 a may be disposed continuously over the entire width of the upper surface of the Cs wiring 12.

It is a plane schematic diagram which shows the pixel of the TFT substrate in the display apparatus of this embodiment. It is a cross-sectional schematic diagram corresponding to the A1-A2 line in FIG. (A)-(c) is a cross-sectional schematic diagram which shows the manufacturing process of the gate bus line of Embodiment 1. FIG. FIG. 6 is a schematic plan view illustrating a state in which ink droplets are arranged on the gate bus line in the manufacturing process of the display device according to the first embodiment. (A) is the cross-sectional schematic diagram corresponding to the A3-A4 line in FIG. 4, (b) is the figure which expanded the area | region enclosed with the broken line in (a). It is a top view photograph which shows a gate bus line in the state where an ink drop was arranged. It is a plane schematic diagram which shows the state by which the ink droplet was arrange | positioned on wiring by the conventional method. (A) is the cross-sectional schematic diagram corresponding to the B1-B2 line in FIG. 7, (b) is the figure which expanded the area | region enclosed with the broken line in (a).

Explanation of symbols

10: Gate bus lines 10a, 10b, 10c, 110a, 110b, 110c: Wiring layer 11: Source bus line 12: Cs bus line (retention capacitor wiring)
13: TFT
14: drain wiring 15: pixel electrode 16: semiconductor layer 17: source wiring 18: gate wiring 19: storage capacitor 20: contact hole 21: conductive layer 21a, 121a: ink droplet 22, 122: insulating substrate 110: laminated wiring

Claims (5)

A method of manufacturing a wiring board comprising wiring on a board,
The manufacturing method is as follows:
Forming the wiring on the substrate and projecting the wiring in a convex shape from the substrate;
A step of ejecting ink containing conductive particles and disposing ink droplets that continuously spread over the entire width of the upper surface of the wiring on the wiring;
And a step of firing the ink droplets to form a conductive layer on the wiring. 2. The method of manufacturing a wiring board according to claim 1, wherein a cross section in the vicinity of the upper surface of the wiring has an inversely tapered shape. The method for manufacturing a wiring board according to claim 1, wherein the ink droplet has a contact angle with respect to the upper surface of the wiring of 6 ° or more. The method for manufacturing a wiring board according to claim 1, wherein the ink is ejected from a direction perpendicular to an upper surface of the wiring. A display device comprising a wiring board manufactured using the method for manufacturing a wiring board according to claim 1.

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