JP2010118578A - Power module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power module in which high reliability semiconductor chips are mounted. <P>SOLUTION: The power module 10 includes a base plate 11 for dissipating heat generated in the semiconductor chip 20 to a heat exchanging medium. A die pad 12 is disposed between the base plate 11 and semiconductor substrate 20. A plurality of semiconductor chips 20 are mounted on the base plate 11. Partial elements that function as one MOSFET are mounted in the plurality of the semiconductor chips 20. The temperature of a backside (heat dissipating surface) of the base plate 11 is made uniform by dividing a semiconductor device into the plurality of the semiconductor chips 20. The temperature of each of the semiconductor chips 20 is lowered and thus the reliability is improved by allowing the temperature of the heat dissipating surface to be uniform. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a power module on which a semiconductor chip is mounted.

  In recent years, power modules equipped with high-power switching elements have been used in electric vehicles and hybrid vehicles. Examples of switching elements include IGBTs and FETs. In particular, in-vehicle power modules are required to have a cooling structure with a small area and a large heat dissipation function in order to reduce the size.

  In the power module of Patent Document 1, a module substrate (heat sink) on which a semiconductor chip is mounted is directly exposed to a cooling liquid. Thereby, the thermal resistance is reduced and the cooling performance is improved.

JP 2001-503409 A

  However, the cooling capacity of the cooling water changes as the environment and the performance of the cooling liquid change. Therefore, in order to prevent the performance deterioration due to the temperature rise of the semiconductor element, it is necessary to secure a cooling capacity with a margin as much as possible.

  However, the technique of Patent Document 1 does not devise heat radiation as uniformly as possible from the back surface (heat radiation surface) of the heat sink. Therefore, when the power module is incorporated in a hybrid vehicle or the like, the chip temperature may be excessively increased depending on the driving condition of the vehicle. For this reason, it has been difficult to ensure sufficient reliability.

  An object of the present invention is to provide a highly reliable power module by making the temperature distribution on the heat radiation surface of the power module uniform.

  The power module of the present invention includes a base plate whose rear surface is a heat radiating surface, and a semiconductor element mounted on the upper surface. Here, the semi-semiconductor element is divided into a plurality of partial elements, and each partial element is arranged separately on a separate semiconductor chip. That is, each semiconductor chip contains a plurality of partial elements that function as a single semiconductor element.

In the conventional power module, a plurality of semiconductor elements are built in one semiconductor chip, or a single semiconductor element is constituted by the whole chip.
However, in any of the above cases, only the temperature near the center of the semiconductor chip on the back surface (heat dissipating surface) of the base plate becomes high.
On the other hand, in the present invention, since the semiconductor element is divided and arranged as a partial element on a plurality of semiconductor chips, the heat generated by each partial element is transferred from the plurality of semiconductor chips spaced apart from each other to the back surface of the base plate ( Heat is transferred to the heat dissipation surface. Therefore, the temperature on the back surface of the heat radiating surface is made uniform. As a result, the temperature of the semiconductor chip incorporating each partial element is lower than the temperature when a single semiconductor chip is arranged. Therefore, a highly reliable power module can be obtained by the present invention.

It has been confirmed that the chip temperature is more significantly lowered by dividing the common semiconductor element into four or more semiconductor chips.
However, the temperature of each partial element decreases as the number of divisions increases. However, the degree of decrease decreases even if the number of divisional elements exceeds four.

  The distance between the semiconductor chip located at the end on the base plate and the end of the base plate is preferably equal to or greater than the thickness of the base plate. Moreover, it is preferable that the space | interval of each semiconductor chip is 1/2 or more of the thickness of a baseplate.

  In principle, the chip temperature decreases as the chip interval increases and the interval between the end chip and the side edge of the base plate increases. However, the size of the base plate is limited due to the demand for miniaturization of the power module. Therefore, an appropriate range that satisfies the above two conditions is determined depending on the size of the base plate. By satisfying this appropriate range, the chip temperature can be effectively reduced while reducing the size of the power module.

  According to the power module of the present invention, the reliability can be improved by making the temperature of the heat radiation surface of the power module uniform.

-Power module structure-
FIG. 1 is a cross-sectional view of a power module 10 according to an embodiment. The power module 10 of this embodiment includes a die pad 12 on which a semiconductor chip 20 is mounted, and a base plate 11 disposed below the die pad 12. The semiconductor chip 20 incorporates a MOSFET that is a semiconductor element. The base plate 11 functions as a heat sink, and its back surface is a heat radiating surface. However, a finned plate or the like may be provided below the base plate 11.
In the present embodiment, it is assumed that only the MOSFET is built in the semiconductor chip 20. However, the present invention includes those in which elements other than MOSFETs are incorporated in each semiconductor chip.

  The back electrode 26 of each semiconductor chip 20 is bonded to the die pad 12. The die pad 12 is connected to an external electrode terminal layer (not shown) via a bonding wire 18. A control electrode 13 and a power supply electrode 15 are provided on the upper surface of each semiconductor chip 11. The control electrode 13 is connected to a gate electrode of a MOSFET described later. The power supply electrode 15 is connected to the source electrode of the MOSFET. The control electrode 13 and the power supply electrode 15 are connected to an external electrode terminal layer (not shown) via bonding wires 14 and 16, respectively.

  FIG. 2 is a cross-sectional view showing a unit structure of the vertical MOSFET partial element 30 built in the semiconductor chip 20. The vertical MOSFET subelement 30 includes a buffer layer 24 and a drift layer 23 formed on a semiconductor substrate 25.

  The main body portion of the semiconductor substrate 25 contains a relatively high concentration of n-type dopant. The drift layer 23 includes a low concentration n-type (first conductivity type) dopant. A region between the drift layer 23 and the semiconductor substrate 25 is a buffer layer 24, and the buffer layer 24 includes an n-type dopant having an intermediate concentration between the semiconductor substrate 25 and the drift layer 23.

  In the drift layer 23, a well 28 containing a p-type dopant is formed. In the well 28, a source region 27 containing a high concentration n-type dopant is formed.

  A gate insulating film 21 made of a silicon oxide film is formed on the drift layer 23 and the surrounding well 28. A gate electrode 22 made of Al / Ni / Ti is formed on the gate insulating film 21. A source electrode 29 made of a Ti / Al / Ti / Au film is formed across the source region 27 and the well 28. On the back surface of the semiconductor substrate 25, a back electrode 26 that is an ohmic electrode made of Ti / Al / Ti / Au is formed. The semiconductor substrate 25 functions as a drain region, and the back electrode 26 functions as a drain electrode.

  The vertical MOSFET partial element 30 is formed by forming a large number of unit structures shown in FIG. 1 on the entire surface of the substrate. The vertical MOSFET is configured by electrically connecting the unit structures of the partial elements 30 provided on the semiconductor chips 20 in parallel. The gate electrode 22 of each unit structure in the partial element 30 is connected to the control electrode 13 shown in FIG. The source electrode 29 of each unit structure in the subelement 30 is connected to the power supply electrode 15 shown in FIG.

  Therefore, according to the control signal supplied to the control electrode 13, the current between the source electrode 29 and the back electrode 26 in each unit structure of each subelement 30 is simultaneously turned on / off. As a result, the vertical MOSFET functions as a switching element that switches the supply of high power.

As described above, the plurality of semiconductor chips 20 incorporate the partial elements 30 that function as a single semiconductor element (power transistor). That is, a single semiconductor element is divided into a plurality of partial elements 30, and each partial element 30 is arranged separately in a plurality of semiconductor chips 20.
Here, in the present embodiment, no element other than the partial element 30 is arranged in each semiconductor chip 20. Therefore, in the present embodiment, for convenience, the semiconductor chip 20 and the partial element 30 are treated synonymously, and a single semiconductor element is expressed as being divided into a plurality of semiconductor chips 20. Therefore, in the following description, this structure, which is the basic structure of the present invention, is referred to as a “divided chip”.

FIG. 3 is a cross-sectional view showing another example of the unit structure of the partial element 30 of the vertical MOSFET. 3, members having the same functions as those shown in FIG. 2 are given the same reference numerals as those in FIG.
In this example, the gate electrode 22 is embedded in the drift layer 23 and faces the well 28 on the side surface. The gate insulating film 21 is interposed between the gate electrode 22 and the drift layer 23 and the well 28. In this other example, the structure of the other part is as shown in FIG.

Examples of the material constituting the base plate 11 include aluminum, aluminum alloy, Cu, Cu alloy, AlN, Mo, W, and Cu / Mo / Cu structure.
Examples of the material constituting the die pad 12 include Cu. Examples include CuMo, CuW, Kovar, and sintered Al alloy.
Examples of the substrate material of the semiconductor chip 20 include wide band gap semiconductor materials such as SiC and GaN, Si, and GaAs.

-Effect of the invention-
4A and 4B are cross-sectional views for explaining the difference in heat dissipation path between a conventional single chip and a four-divided chip. FIGS. 5A and 5B are plan views for explaining the difference in temperature distribution on the heat radiation surface between the conventional single chip and the four-divided chip.

  As shown in FIGS. 4A and 4B, the heat generated by the power device is radiated with a spread of about 45 ° through the die pad 12 to the back surface of the base plate 11. At this time, a temperature distribution as shown in FIG. 5A occurs on the back surface (heat radiating surface) of the base plate 11. That is, the temperature Ra is the highest in the region Ra1 immediately below the center of the semiconductor chip 20, and the temperature decreases toward the peripheral regions Rb1, Rc1, and Rd2.

On the other hand, in the case of the four-divided chip, the heat radiation from each chip overlaps at the center of the heat radiation surface. Therefore, as shown in FIG. 5B, the temperature Ra is substantially uniform in the region Ra2 having a large heat radiation surface. In the regions Rb2, Rc2, and Rd2 outside each semiconductor chip 20, the temperature is further lowered.
As a result, the temperature of the central region Ra2 of the four-divided chip on the heat dissipation surface is lowered to the average temperature of the single-chip regions Ra1, Rb1, Rc1, and Rd1. That is, heat is effectively radiated by the four-divided chip. Hereinafter, this effect will be verified based on the simulation result.

FIG. 9 is a diagram showing a simulation result of the surface temperature distribution of the semiconductor chip and the base plate in a single chip. FIG. 10 is a diagram illustrating a simulation result of the surface temperature distribution of the semiconductor chip and the base plate in the four-divided chip. However, these data indicate that the size of the base plate 11 is 16 × 32 × t2 (mm), the size of the die pad 12 is 16 × 30 × t0.3 (mm), and the size of the semiconductor chip 20 is 8 × 8 × t0. 4 (mm). Further, the heat generation amount of the semiconductor chip 20 is 160 W, the heat transfer coefficient of the back surface (heat dissipating surface) of the base plate 11 is 20 W / m ² K, and the ambient temperature is 25 ° C.

  In the case of the single chip shown in FIG. 9, the temperature of the central portion R11 is 320 ° C. to 350 ° C. The temperature of the region R12 adjacent to the central portion R11 is 290 ° C to 320 ° C. The temperature of the region R13 is 270 ° C to 290 ° C, the temperature of the region R14 is 250 ° C to 270 ° C, the temperature of the region R15 is 220 ° C to 250 ° C, and the temperature of the region R15 is 220 ° C or less.

  In the case of the four-divided chip shown in FIG. 10, the temperature of the central portion R21 is 88 ° C. to 95 ° C. The temperature of the region R22 adjacent to the central portion R21 is 85 ° C to 88 ° C. The temperature of the region R23 is 83 ° C to 85 ° C, the temperature of the region R24 is 79 ° C to 83 ° C, and the temperature of the region R25 is 79 ° C or less.

  From the above results, it can be seen that the temperature of the semiconductor chip 20 is greatly reduced by the divided chip of the present invention. That is, the divided chip of the present invention performs uniform heat radiation on the entire heat radiation surface, and as a result, the chip temperature decreases. Therefore, it is possible to effectively prevent the chip temperature from excessively rising due to heat generated by the power device.

  In the following, an appropriate division number and layout of the semiconductor chip 20 will be described from the measurement result of the chip temperature.

-Number of chip divisions and chip temperature-
FIG. 6 is a graph showing the dependence of the chip surface temperature on the number of chip divisions. In the figure, the horizontal axis indicates the number of chip divisions, and the vertical axis indicates the chip surface temperature (° C.). FIGS. 11A to 11E are perspective views showing the arrangement state of the semiconductor chips used to obtain the data of FIG. As shown in FIGS. 11A to 11E, the temperature distribution when one, two, four, eight and sixteen semiconductor chips 20 are arranged is calculated by simulation.

  As shown in FIG. 6, the chip temperature reaches 350 ° C. for a single chip, whereas the chip temperature decreases to about 170 ° C. for a two-chip chip. Therefore, it can be seen that even if the semiconductor chip 20 is divided into two, a sufficient effect is obtained in a normal use state.

  Further, in the four-divided chip, the chip temperature is lowered to about 90 ° C., which is 100 ° C. or less. Therefore, even when the semiconductor device falls into an overload state that is not a normal use state, it is possible to prevent an excessive increase in the chip temperature with a margin.

−Chip layout and chip temperature−
FIG. 7 is a graph showing the dependence of the chip temperature on the chip interval. In the figure, the horizontal axis indicates the chip interval normalized with the thickness of the base plate 11 as 1. The vertical axis represents the chip surface temperature normalized with the chip surface temperature being 1 when the chip interval is 0. The number of semiconductor chips 20 is four.

  FIG. 8 is a graph showing changes in the chip temperature with respect to the distance from the base plate end of the semiconductor chip. In the figure, the horizontal axis indicates the chip interval normalized with the thickness of the base plate 11 as 1. The vertical axis represents the chip surface temperature normalized with the chip surface temperature being 1 when the distance from the end of the base plate is 0. The number of semiconductor chips 20 is four.

  FIGS. 12A to 12E are perspective views showing the arrangement state of the semiconductor chips used for obtaining the data of FIGS. Here, the size of the base plate 11 is fixed to the above value (16 × 32 × t2 (mm)). Then, as shown in FIGS. 12A to 12E, the temperature distribution when the arrangement state of the semiconductor chip 20 is changed to five types is calculated by simulation.

As shown in FIG. 7, when the chip interval becomes 1/2 or more of the base plate thickness, the chip temperature becomes 0.3 or less in the case of a single chip (interval 0). Therefore, the chip interval is preferably 1/2 or more of the base plate thickness.
In FIG. 7, when the chip interval is 4 or more of the base plate thickness, the chip temperature rises conversely. This is considered to be caused by the semiconductor chip 20 being too close to the end of the base plate. When the base plate 11 is sufficiently large, the chip temperature should decrease even if the chip interval is 4 or more of the base plate thickness.

As shown in FIG. 8, when the distance from the end of the base plate of the semiconductor chip 20 is equal to or greater than the thickness of the base plate, the chip temperature becomes 0.87 or less when the distance is zero. Therefore, the distance from the end of the base plate of the semiconductor chip 20 is preferably equal to or greater than the thickness of the base plate.
In FIG. 8, when this distance becomes 3 or more of the base plate thickness, the chip temperature rises conversely. This is considered due to the fact that the chip interval is too close. When the base plate 11 is sufficiently large, the chip temperature should decrease even if the distance from the end of the base plate of the semiconductor chip 20 is 3 or more of the base plate thickness.

  In the above embodiment, the semiconductor chip 20 is divided into the same size. However, the size of the divided semiconductor chip may be changed depending on the location. For example, the chip size may be increased as the semiconductor chip 20 is located outward.

  Moreover, in the said embodiment, although the semiconductor chip 20 was divided | segmented into the rectangular shape, another shape may be sufficient. For example, the semiconductor chip 20 may be divided into regular hexagons.

  Although the case where the vertical MOSFET is formed in the semiconductor chip 20 has been described in the above embodiment, the present invention is not limited to this. A lateral MOSFET, IGBT, diode, JFET or the like may be formed on the semiconductor chip 20 of the present invention.

(Other embodiments)
The structure of the embodiment of the present invention disclosed above is merely an example, and the scope of the present invention is not limited to the scope of these descriptions. The scope of the present invention is indicated by the description of the scope of claims, and further includes meanings equivalent to the description of the scope of claims and all modifications within the scope.

  The power module of the present invention can be used for various devices equipped with MOSFET, IGBT, diode, JFET and the like.

It is sectional drawing of the power module in embodiment. It is sectional drawing which shows the unit structure of the partial element of the vertical MOSFET incorporated in the semiconductor chip. It is sectional drawing which shows another example of the unit structure of the partial element of vertical type MOSFET. (A), (b) is sectional drawing for demonstrating the difference in the thermal radiation path | route of the conventional single chip | tip and a 4-part dividing chip | tip. (A), (b) is a top view for demonstrating the difference in the temperature distribution in the thermal radiation surface of the conventional single chip | tip and a 4-part dividing chip | tip. It is a figure which shows the chip | tip division number dependence of the chip | tip surface temperature with a graph. It is a figure which shows the chip | tip interval dependence of chip | tip temperature with a graph. It is a figure which shows the change of the chip temperature with respect to the distance from the baseplate edge of a semiconductor chip with a graph. It is a figure which shows the simulation result of the surface temperature distribution of the semiconductor chip and base plate in a single chip. It is a figure which shows the simulation result of the surface temperature distribution of the semiconductor chip and base plate in a 4-part dividing chip. (A)-(e) is a perspective view which shows the arrangement | positioning state of the semiconductor chip used in order to obtain the data of FIG. (A)-(e) is a perspective view which shows the arrangement | positioning state of the semiconductor chip used in order to acquire the data of FIG. 7, FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Power module 11 Base plate 12 Die pad 13 Control electrode 14 Bonding wire 15 Power supply electrode 16 Bonding wire 18 Bonding wire 20 Semiconductor chip 21 Gate insulating film 22 Gate electrode 23 Drift layer 24 Buffer layer 25 Semiconductor substrate 26 Back surface electrode 27 Source region 28 well 29 source electrode

Claims (4)

A power module comprising a base plate whose back surface is a heat dissipation surface, and a semiconductor element mounted on the top surface of the base plate,
The power module, wherein the semiconductor element is divided into a plurality of partial elements, and each partial element is separately arranged on a separate semiconductor chip. The power module according to claim 1,
A power module in which the semiconductor element is divided into four or more partial elements. The power module according to claim 1 or 2,
The power module, wherein a distance between an end of the plurality of semiconductor chips located on the base plate and a base plate end is equal to or greater than a thickness of the base plate. In the power module according to any one of claims 1 to 3,
The power module, wherein an interval between the semiconductor chips is at least ½ times the thickness of the base plate.

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