JP2010117219A - High-frequency characteristics evaluation jig and method for manufacturing semiconductor - Google Patents

Abstract

A high-frequency characteristic evaluation jig capable of improving the measurement accuracy when measuring a high-frequency characteristic by holding a semiconductor device and positioning it without affecting the high-frequency characteristic is provided.
A jig base 12 on which a high-frequency substrate 30 is placed, a first block unit 33 disposed on the high-frequency substrate 30, and a lead 102 of a semiconductor device 100 are brought into contact with transmission lines 21 and 22 of the high-frequency substrate 30. A package guide 32 having a positioning hole 60 for fitting the package 101 of the semiconductor device and aligning in the in-plane direction parallel to the surface of the high-frequency substrate 30, and the package guide 32 together with the first block unit 33 on the package guide 32. A second block unit 31 that is sandwiched and fixed to the jig base 12 and a package retainer that pushes the package 101 by entering from the opening of the first block unit 33 in a direction perpendicular to the in-plane direction parallel to the surface of the high-frequency substrate. A member 150 is provided.
[Selection] Figure 5

Description

  The present invention relates to a high-frequency characteristic evaluation jig and a semiconductor device manufacturing method, and more particularly to a high-frequency characteristic evaluation jig and a semiconductor device manufacturing method for evaluating high-frequency characteristics of a semiconductor device such as a low noise transistor over a wide band.

  In general, when evaluating high frequency characteristics of an electronic component of a resin mold package as an example of a semiconductor device, for example, a low noise transistor, an evaluation type high frequency characteristic evaluation jig 200 shown in FIG. 13 is used.

  For example, when evaluating the high-frequency characteristics of a Si-based transistor or a SiGe-based transistor, the matching circuit is not connected to a single transistor, and oscillation is likely to occur. For this reason, a single transistor is evaluated for high frequency characteristics using a high frequency characteristic evaluation jig. Moreover, it is desirable from the viewpoints of cost reduction and work efficiency that various high-frequency transistors can be evaluated for high-frequency characteristics using one high-frequency characteristic evaluation jig.

  A high frequency characteristic evaluation jig 200 shown in FIG. 13 includes a jig base 201 on which a transistor 210 package is mounted, two 50 ohm transmission lines 202, and two high frequency connectors 203. The transistor 210 is placed on the high frequency substrate on the jig base 201. The two high-frequency connectors 203 are each connected to a bias T. One bias T is connected to the high-frequency input side of the measuring instrument, and the other bias T is connected to the high-frequency output side of the measuring instrument.

  14 and 15 show the shape of a conventional high-frequency characteristic evaluation jig 200. FIG. A plurality of tabs 205 are provided on the high frequency substrate 220 of the high frequency characteristic evaluation jig 200. The corners of the mold package of the transistor 210 are fixed by these tabs 205 so as to be positioned in the X-axis direction and the Y-axis direction orthogonal to the X-axis direction.

  In addition, each lead 206 of the transistor 210 is directly pushed along the Z-axis direction (perpendicular to the X-axis direction and the Y-axis direction) by the lead presser 207, so that the 50 ohm transmission line 202 on the high-frequency substrate 220 is applied to the lead 210. On the other hand, it is fixed in electrical contact.

Thus, in a state where the mold package of the transistor 210 is fixed to the high-frequency substrate 220 side, the periphery of the mold package of the transistor 210 is not surrounded by the metal member and is in an open state in terms of high frequency. A high-frequency wave propagating on the 50 ohm transmission line 202 of the evaluation jig 200 is radiated into the air.
In addition, as shown in FIG. 16, the center conductor 212 of the high frequency connector 202 is electrically connected to the 50 ohm transmission line 225 of the high frequency substrate 220 via the coaxial-50 ohm transmission line converter 211 of the high frequency characteristic evaluation jig. It is connected. The jig base 250 includes a member 251 and a member 252. The coaxial-50 ohm transmission line converter 211 has a through hole 227 formed in the member 251, and an insulator 213 made of Teflon (registered trademark) having an outer diameter of 2.2 mm is disposed in the through hole 227. Yes. This insulator 213 holds a center conductor 212 having an outer diameter of 0.65 mm. As the high frequency substrate 220, an expensive alumina ceramic substrate having a large thickness is used.

Further, as an example of this type of evaluation jig, Patent Document 1 discloses an IC evaluation jig for evaluating electric characteristics of an IC (integrated circuit) chip. This IC evaluation jig has a pedestal on which the IC chip is mounted, and a pressing portion for electrically contacting the IC lead wire of the IC chip and the tip of the transmission line.
Japanese Patent Laid-Open No. 10-82827

  However, in the package 210 fixing structure shown in FIGS. 14 and 15, the periphery of the package 210 is in an open state, and the high frequency characteristics are affected when the frequency for evaluating the high frequency characteristics of the semiconductor device exceeds 6 GHz. It becomes noticeable and the measurement accuracy deteriorates. In addition, generation of unnecessary radio waves and isolation between high frequency input and output are deteriorated, and resonance phenomenon and oscillation occur. In addition, since the lead 206 of the transistor 210 is directly pressed by the lead holder 207 and is fixed so as to be in electrical contact with the 50 ohm transmission line 202 on the high-frequency substrate 220, the characteristic impedance changes.

  Further, in the structure of the coaxial-50 ohm transmission line converter 211 shown in FIG. 16, since the outer diameter of the insulator 213 is 2.2 mm, the cut-off cannot be secured sufficiently and unnecessary radio waves are generated. There have been problems such as an increase in insertion loss, deterioration in reflection characteristics, and ripple in transmission characteristics. For this reason, in order to create a high frequency characteristic evaluation jig for evaluating a high frequency band of 6 GHz or more, it is necessary to give structural considerations.

  As described above, when a high frequency characteristic is evaluated when manufacturing a semiconductor device such as a low noise transistor over a wide band (100 MHz to 12 GHz), for example, the conventional high frequency characteristic evaluation jig uses an increase in insertion loss and reflection. As a result, deterioration of characteristics and ripple of pass characteristics occur, generation of unnecessary radio waves and isolation between high-frequency input and output may deteriorate, and a resonance phenomenon and oscillation may occur, and measurement accuracy cannot be ensured.

  Further, in the IC evaluation jig disclosed in Patent Document 1, the periphery of the IC chip is in an open state, so that the influence on the high-frequency characteristics becomes significant and the measurement accuracy is deteriorated. Generation of unnecessary radio waves and isolation between high frequency input and output are deteriorated, and resonance phenomenon and oscillation occur. Moreover, although the connector is connected to the transmission line in the pedestal, there is no suggestion about this connection structure.

  SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to measure the high frequency characteristics by measuring the high frequency characteristics by holding the semiconductor device so as not to affect the high frequency characteristics. It is to provide a method for manufacturing a semiconductor device and a high-frequency characteristic evaluation jig capable of improving the above.

  The high-frequency characteristic evaluation jig of the present invention is arranged on a jig base on which a high-frequency substrate having a transmission line is mounted, a metal first block unit disposed on the high-frequency substrate, and the first block unit. A package guide having a positioning hole for fitting the package of the semiconductor device and aligning the lead of the semiconductor device with the transmission line of the high-frequency substrate by aligning in the in-plane direction parallel to the surface of the high-frequency substrate. The second block unit is formed on the package guide, and the second block unit is made of metal and sandwiches the package guide together with the first block unit and fixes the package guide to the jig base. From the opening, enter in a direction perpendicular to the in-plane direction parallel to the surface of the high-frequency substrate and enter the front of the semiconductor device. Characterized in that it comprises a package pressing member pushes the package to the high frequency substrate side.

  The manufacturing method of a semiconductor device according to the present invention includes a semiconductor device creation process for creating a semiconductor device by electrically connecting a semiconductor element to a lead and sealing with a sealing resin, and a transmission line arranged on a jig base A first block unit made of metal is disposed on a high-frequency substrate including: a package of the semiconductor device is fitted, and the lead of the semiconductor device is aligned in an in-plane direction parallel to the surface of the high-frequency substrate. A package guide having a positioning hole to be brought into contact with the transmission line is disposed on the first block unit, and a second block unit made of metal is disposed on the package guide together with the first block unit. The guide is sandwiched and fixed to the jig base, and the package is pushed from the opening formed by the second block unit. Measurement of a semiconductor device that measures a high frequency characteristic of the semiconductor device by entering a member in a direction perpendicular to the in-plane direction parallel to the surface of the high frequency substrate and pushing the package of the semiconductor device to the high frequency substrate side And a semiconductor device evaluation step for evaluating a result of the measured high frequency characteristics of the semiconductor device.

  ADVANTAGE OF THE INVENTION According to this invention, manufacture of the high frequency characteristic evaluation jig | tool and semiconductor device which can improve the measurement precision at the time of measuring a high frequency characteristic by pressing and positioning a semiconductor device so that a high frequency characteristic is not affected A method can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows an evaluation system provided with a preferred embodiment of the high-frequency characteristic evaluation jig of the present invention.

  The evaluation system shown in FIG. 1 includes a high-frequency characteristic evaluation jig 10, two biases T, and a measuring instrument 11. The measuring instrument 11 has a noise generator 11B and a noise figure meter 11C.

  A high frequency characteristic evaluation jig 10 shown in FIG. 1 includes a jig base 12, 50 ohm transmission lines 21 and 22, and high frequency connectors 25 and 26. The package of the transistor 100 is placed on a high-frequency substrate on the jig base 12.

  The 50 ohm transmission lines 21 and 22 can be electrically connected to the base terminal and the collector terminal of the transistor 100, respectively. The 50 ohm transmission lines 21 and 22 are electrically connected to the high frequency connectors 25 and 26, respectively. The high frequency connectors 25 and 26 are connected to one and the other bias T, respectively, and one bias T is electrically connected to the noise generating unit 11B on the high frequency input side of the measuring instrument 11, and the other bias T is measured. It is electrically connected to a noise figure meter 11C on the high frequency output side of the device 11. One and the other bias T supply bias voltages Vbe and Vce to the high-frequency connectors 25 and 26, respectively.

  FIG. 2 is a perspective view showing a structural example of the high-frequency characteristic evaluation jig 10 shown in FIG. FIG. 3 is a perspective view showing a state where the two upper units 31, 31 of the upper block unit are removed from the high-frequency characteristic evaluation jig 10 shown in FIG. FIG. 4 is a plan view showing a state where the high frequency substrate is exposed by removing the upper blocks 31B and 31C, the package guide 32, and the lower blocks 33B and 33C from the high frequency characteristic evaluation jig 10 shown in FIG. FIG. 5 is a view showing the structure of the high-frequency characteristic evaluation jig 10 shown in FIG.

  2 and 3, the high frequency characteristic evaluation jig 10 includes a jig base 12, high frequency connectors 25 and 26, a high frequency substrate 30, an upper block unit 31, a package guide 32, and a lower block unit 33. is doing. The jig base 12 has side wall portions (flanges) 34 and 35.

  As shown in FIGS. 2 and 3, the side walls 34 and 35 protrude from the base 12 </ b> B of the jig base 12 in the Z direction and are formed in parallel along the X direction. The high frequency connectors 25 and 26 are fixed so as to protrude along the Y direction using screws to the outside of the side wall portions 34 and 35, respectively. The X direction, the Y direction, and the Z direction in FIGS. 2 and 3 are orthogonal to each other. The jig base 12, the upper block unit 31, and the lower block unit 33 are made of metal, for example, aluminum. The lower block unit 33 corresponds to a first block unit, and the upper block unit 31 corresponds to a second block unit.

  The upper block unit 31 includes one upper block 31B and the other upper block 31C. The lower block unit 33 includes one upper block 31B and the other upper block 31C. The lower block unit 33 includes one lower block 33B and the other lower block 33C. The package guide 32 is made of an electrically insulating plastic, for example, a Delrin material having a relative dielectric constant εr = 3.6.

  As shown in FIG. 4, the high-frequency substrate 30 is mounted on the mounting surface 12 </ b> C of the base 12 </ b> B of the jig base 12. The high-frequency substrate 30 includes linear 50 ohm transmission lines 21 and 22, conductor portions 41 and 42, and conductor portions 43, 44, 45, and 46. As shown in FIG. 5, a solid earth 47 is formed on the back surface of the high-frequency substrate 30.

  As shown in FIG. 4, the 50 ohm transmission lines 21 and 22 are formed along the Y direction, and one 50 ohm transmission line 21 is electrically connected to the central conductor 74 of the coaxial high frequency connector 25, and the other The 50 ohm transmission line 22 is electrically connected to the central conductor 74 of the coaxial high frequency connector 26. Through holes 41H, 42H, 43H, 44H, 45H, and 46H are formed in the conductor portions 41, 42, 43, 44, 45, and 46, respectively. The conductor portions 41 and 42 and the conductor portions 43, 44, 45, and 46 are electrically connected to the solid ground 47 through these through holes, respectively.

  Here, a low noise transistor 100 as an example of a semiconductor device evaluated by the high frequency characteristic evaluation jig 10 will be described with reference to FIGS. 4 and 5.

  The transistor 100 illustrated in FIGS. 4 and 5 includes a package 101 and four leads 102. The transistor 100 is, for example, a GaAs or SiGe transistor. As shown in FIG. 5, for example, SiGe pellets 103 as semiconductor elements are arranged on the leads 102, and the pellets 103 are electrically connected to the leads 102 using bonding wires 104. Then, a part of the leads 102, the pellet 103, and the bonding wire 104 are sealed with a sealing resin, whereby a cubic package 101 is formed.

  Then, as shown in FIG. 4, when the transistor 100 is disposed at the predetermined position P, the four leads 102 of the transistor 100 are electrically connected to the conductor portions 45 and 46 and the 50 ohm transmission lines 21 and 22, respectively. Can be connected.

  Next, the structures of the upper block unit 31, the package guide 32, and the lower block unit 33 will be described with reference to FIGS.

  FIG. 5 shows a state where the upper block unit 31, the package guide 32, and the lower block unit 33 are being assembled. FIG. 6 shows the upper block unit 31, the package guide 32, and the lower block unit 33 being assembled. FIG. 6 is a view showing a state in which the package 101 of the transistor 100 is pressed along the Z direction by a package pressing member 150.

  7 is a perspective view showing an example of the shape of the upper block unit 31 and the lower block unit 33, FIG. 8 shows an example of the shape of the package guide 32, and FIG. 8B is a side view of the package guide 32. Further, FIG. 8C shows the package 101 of the transistor 100 in the positioning hole 60 in the central portion M of the package guide 32 shown in FIG. 8A. It is a top view which shows the example arrange | positioned by being inserted and positioned.

  First, with reference to FIG. 7, an example of the shape of the upper block unit 31 and the lower block unit 33 will be described.

  The upper blocks 31B and 31C of the upper block unit 31 shown in FIG. 7 are plate-like members and have two screw holes 31D and one alignment pin hole 31G. On the lower side of the upper block 31, a groove portion 31T for fitting and holding the package guide 32 shown in FIG. 8 is formed in the X direction.

  The lower blocks 33B and 33C of the lower block unit 33 shown in FIG. 7 are plate-like members that are thinner than the upper block 31, and have two screw holes 33D and one alignment pin hole 33G. The two screw holes 33D and one alignment pin hole 33G are formed at positions corresponding to the two screw holes 31D and one alignment pin hole 31G, respectively. The length C1 in the Y direction of the upper blocks 31B and 31C and the length C1 in the Y direction of the lower blocks 33B and 33C are the same, and the length C2 in the X direction of the upper blocks 31B and 31C and the lower blocks 33B and 33C. The length C2 in the X direction is the same.

  Next, an example of the shape of the package guide 32 will be described with reference to FIG.

  The package guide 32 shown in FIG. 8 has a first portion 51, a second portion 52, and a central portion M. A central portion M is formed between the first portion 51 and the second portion 52. The first portion 51 is formed with two guide grooves 51D for passing screws and one alignment pin guide groove 51G. Similarly, in the second portion 52, two guide grooves 52D for passing a screw and one alignment pin guide groove 52G are formed. The two guide grooves 51D and the guide groove 51G of one alignment pin are formed at positions corresponding to the screw holes 31D and 33D and the alignment pin hole 31G shown in FIG. Two guide grooves 52D and one alignment pin guide groove 52G are formed at positions corresponding to the screw holes 33D and 33D and the alignment pin hole 33G shown in FIG. The upper surface of the central portion M of the package guide 32 is formed at a position lower than the upper surfaces of the first portion 51 and the second portion 52.

  A positioning hole 60 for fitting and positioning the package 101 of the transistor 100 is formed in the central portion M of the package guide 32 shown in FIG. The positioning hole 60 has a rectangular main body hole 61 into which the package 101 is fitted, and six lead holes 62 into which the leads 102 formed extending from the main body hole 61 are fitted. In the example of FIG. 8, the four leads 102 are fitted into the corresponding four holes 62, but when the package is different from the package 101, for example, the leads can be fitted into the six holes 62. Yes.

  Next, referring to FIGS. 5 and 6, the high-frequency substrate 30 is mounted on the base 12 </ b> B of the jig pedestal 12, and the upper block 31, the package guide 32, and the lower are placed on the base 12 </ b> B of the jig pedestal 12. By assembling the side block 33, the package 101 of the transistor 100 can be positioned and held. The high-frequency substrate 30 is a rectangular substrate disposed between the left and right partition walls 34 and 35 as shown in FIG.

  First, as shown in FIGS. 4 and 5, two alignment pins 70 are attached in advance in the Z direction to the hole 12H of the base 12B of the jig base 12 and the through hole 42H of the high-frequency substrate 30. Yes. On the high-frequency substrate 30, two lower blocks 33 </ b> B and 33 </ b> C shown in FIG. 7 are arranged apart from each other by the opening dimension W <b> 2. At this time, each alignment pin 70 is positioned at the lower block 33. It passes through the alignment pin hole 33G.

  Next, as shown in FIG. 5, the package guide 32 is disposed on the lower blocks 33B and 33C. At this time, one alignment pin 70 passes through the guide groove 51G of the first portion 51 of the package guide 32, and the other alignment pin 70 passes through the guide groove 52G of the second portion 52 of the package guide 32. . Thereby, the package guide 32 and the two lower blocks 33 and 33 are positioned relative to the base portion 12 </ b> B of the jig base 12 in the X direction and the Y direction. The central portion M of the package guide 32 is positioned between the lower blocks 33B and 33C.

  Further, as shown in FIG. 5, the two upper blocks 31 </ b> B and 31 </ b> C are respectively disposed on the first portion 51 and the second portion 52 of the package guide 32. At this time, one alignment pin 70 passes through the alignment pin hole 31G of one upper block 31, and the other alignment pin 70 passes through the alignment pin hole 31G of the other upper block 31. The two upper blocks 31B and 31C, the package guide 32, and the two lower blocks 33B and 33C are positioned relative to the base 12B of the jig base 12 with respect to the X direction and the Y direction.

  After that, as shown in FIGS. 4 and 5, the four screws 75 are screw holes 31D of the upper blocks 31B and 31C, guide grooves 51D and 52D of the package guide 32, and screw holes of the lower blocks 33B and 33C. The assembly unit of the upper blocks 31B and 31C and the lower blocks 33B and 33C sandwiches the package guide 32 as shown in FIG. 6 by being screwed into the female screw 12M of the base 12B of the jig base 12 through 33D. Thus, positioning with respect to the high-frequency substrate 30 on the jig base 12 can be performed with respect to the X direction, the Y direction, and the Z direction.

  Thereafter, the transistor 100 is positioned by being fitted into the positioning hole 60 of the package guide 32 as shown in FIG. 8C, and when the transistor 100 is arranged at a predetermined arrangement position P as shown in FIG. The four leads 102 of the transistor 100 can be electrically connected to the conductor portions 45 and 46 and the 50 ohm transmission lines 21 and 22, respectively.

  Next, with reference to FIG. 9, an example of a preferable structure of the coaxial-50 ohm transmission line conversion unit 79 for connecting and converting the high frequency connectors 25, 26 shown in FIG. 1 and the 50 ohm transmission lines 21, 22 will be described. To do. The coaxial-50 ohm transmission line converter 79 positions the center of the center conductor 74 of the high frequency connector 25 (26) and electrically connects the high frequency connector 25 (26) and the 50 ohm transmission line 21 (22). . The diameter of the center conductor 74 is, for example, 0.65 mm.

  On the jig base 12, a high frequency substrate 30 is fixed by screws 30N, and the thickness of the high frequency substrate 30 is, for example, 0.4 mm. A solid pattern 47 is formed on the back surface of the high-frequency substrate 30. The solid pattern 47 is, for example, a copper foil having a thickness of 35 μm. A first through hole 71 and a second through hole 72 are continuously formed in the side wall portions 34 and 35 of the jig base 12, respectively.

  In the embodiment of the present invention, the axial length K1 of the first through hole 71 shown in FIG. 9 is, for example, 0.9 mm, and the axial length K2 of the second through hole 72 is, for example, 1.6 mm. . The inner diameter of the second through hole 72 is set smaller than the inner diameter of the first through hole 71. For example, the inner diameter of the first through hole 71 is 2.2 mm, and the inner diameter of the second through hole 72 is 1.5 mm. It is. An insulator 73 of Teflon (registered trademark), which is an insulating material, is disposed in the first through hole 71, but the inside of the second through hole 72 becomes an air layer as an insulator continuously with the insulator 73. ing. The Teflon (registered trademark) insulator 73 having an outer diameter of 2.2 mm has an impedance of 50 ohms. This insulator 73 holds the center conductor 74.

  On the other hand, in the conventional example shown in FIG. 16, the high frequency connector 202 has a center conductor 212 having an outer diameter of 0.65 mm and an outer diameter with respect to the coaxial-50 ohm transmission line converter 211 of the high frequency characteristic evaluation jig Is connected using an insulator 213 made of Teflon (registered trademark) of 2.2 mm, thereby connecting the high frequency substrate 220 inside the high frequency characteristic evaluation jig and the external high frequency connector 202. As the high-frequency substrate 220, an expensive alumina ceramic substrate having a thickness of 0.635 mm is used. In addition, as shown in FIG. 16, the jig base 250 is constituted by a member 251 and a member 252.

  In the embodiment of the present invention, as shown in FIG. 9, the coaxial-50 ohm transmission line converter 79 includes a first through hole 71 filled with a Teflon (registered trademark) insulator 73 and a second air layer. The through hole 72 is formed in two stages, and the thickness FD of the high-frequency substrate 30 is made smaller than the thickness of the expensive alumina high-frequency substrate 220 shown in FIG. As the high-frequency board 30, a Teflon (registered trademark) board with low loss and low thickness is adopted to improve high-frequency characteristics, and the high-frequency board 30 is fixed to the base 12B of the jig base 12 with screws 30N. Yes. The distance between the input / output coaxial-50 ohm transmission line converter 79, that is, the distance between the side wall portions (flanges) 34, 35 is set to the shortest (12 mm).

  Accordingly, the high-frequency current path from the coaxial ground conductor part a1 to the high-frequency board installation part b1 shown in FIG. 9 is compared with the high-frequency current path from the coaxial ground conductor part a to the high-frequency board installation part b shown in the conventional example of FIG. Because the inner diameter of the second through hole 72 (the outer conductor diameter of the air insulation portion) is as small as 1.5 mm, the generation of unnecessary radio waves can be suppressed by the cut-off, and high-frequency low reflection, low loss, and measurement accuracy can be reduced. Improvement can be realized. The base 12B of the jig base 12 shown in FIG. 9 is not a combination of a plurality of members, but is an integral part. For this reason, compared with the case where it comprises by 2 members like before, an electrical connection resistance can be made small.

  Next, the width W1 of the package guide 32 shown in FIG. 3 and the opening dimension W2 of the metal block assembly composed of the upper blocks 31B and 31C and the lower blocks 33B and 33C shown in FIGS. 2 and 3 will be described.

  The width W1 along the Y direction of the package guide 32 shown in FIG. 3 is a half wavelength of the wavelength of the high-frequency signal when a high-frequency signal is transmitted using a Delrin material having a relative dielectric constant εr = 3.6 as a medium (however, It is desirable that the value is set to a value narrower than, for example, 4 mm, which is 0 to 8 times as large as 12 GHz (after wavelength reduction). A lateral width W1 along the Y direction of the package guide 32 shown in FIG. 3 is a width along the 50 ohm transmission lines 21 and 22 arranged in the Y direction between the high frequency connectors 25 and 26. Since the dielectric constant of the dielectric of the package guide 32 is 3.6, the package guide 32 functions as a dielectric resonator. Therefore, the lateral width W1 along the Y direction of the package guide 32 is, for example, 4 mm or less as described above. It is said.

Furthermore, the opening dimension W2 along the X direction of the metal block assembly composed of the upper blocks 31, 31 and the lower blocks 33, 33 shown in FIGS. 2 and 3 is 1 of the wavelength of the high frequency signal when the high frequency is transmitted. It is desirable to set a value narrower than a dimension obtained by multiplying a / 2 wavelength (however, after shortening the wavelength in the case of 12 GHz) 0,8, for example, 4 mm. That is, 50 ohm transmission lines 21 and 22 surrounded by a metal block assembly including side blocks 31 and 31 and lower blocks 33 and 33 are opened at intervals of 4 mm. When the high frequency passes through the package guide 32 that is a dielectric, the wavelength of the high frequency is shortened. The wavelength shortening rate on the high frequency substrate at this time can be expressed by 1 / (εr) ^1/2. it can.

  In this way, a structure is adopted in which the width W1 along the Y direction of the package guide 32 and the opening dimension W2 along the X direction of the metal block assembly composed of the upper blocks 31, 31 and the lower blocks 33, 33 are adopted. As a result, it is possible to prevent unnecessary high-frequency radio waves from flying through the air from the transistor 100 disposed on the high-frequency substrate 30 and transmitted to the 50 ohm transmission lines 21 and 22. For this reason, it is possible to prevent the unnecessary high-frequency radio waves flying from the transistor 100 in the air and the high-frequency radio waves passing through the transistor 100 from resonating, and to ensure the cutoff of the unnecessary radio waves and the isolation of input and output. Resonance can be avoided and ripple and undulation of high-frequency transmission characteristics can be suppressed.

  Further, the interval W3 along the Y direction of the input / output coaxial-50 ohm transmission line converter 79 shown in FIG. 3 is preferably set to 12 mm. The 50 ohm transmission lines 21 and 22 are preferably as short as possible, but such a distance W3 is the smallest dimension that can be applied to various semiconductor device packages.

  Next, the high frequency characteristic evaluation of the transistor 100 that is the object of characteristic evaluation using the above-described high frequency characteristic evaluation jig 10 will be described.

  First, as shown in FIG. 4, the high-frequency substrate 30 is mounted on the mounting surface 12 </ b> C of the base portion 12 </ b> B of the jig base 12. The 50 ohm transmission lines 21 and 22 of the high frequency substrate 30 are arranged in parallel to the Y direction, and the 50 ohm transmission lines 21 and 22 are respectively coaxial to 50 ohm transmission line converters with respect to the corresponding high frequency connectors 25 and 26. Electrical connection is made through 79 central conductors 74.

  Next, as shown in FIGS. 3 and 5, two lower blocks 33B and 33C are arranged on the high-frequency substrate 30 with an opening dimension W2. In this case, as shown in FIG. Thus, each alignment pin 70 passes through the alignment pin hole 33G of the lower block 33. Thus, the two lower blocks 33B and 33C can be reliably positioned with the opening dimension W2 using the alignment pin 70 and the alignment pin hole 33G.

  As shown in FIG. 5, the package guide 32 is disposed on the lower blocks 33B and 33C. At this time, one alignment pin 70 passes through the guide groove 51G of the first portion 51 of the package guide 32, and the other alignment pin 70 passes through the guide groove 52G of the second portion 52 of the package guide 32. . Thereby, the package guide 32 and the two lower blocks 33B and 33C are relatively reliably positioned. The center portion M of the package guide 32 is positioned so as to be fitted into the opening indicated by the opening dimension W2 of the lower blocks 33B and 33C.

  Further, as shown in FIG. 5, the two upper blocks 31 </ b> B and 31 </ b> C are respectively disposed on the first portion 51 and the second portion 52 of the package guide 32. At this time, one alignment pin 70 passes through the alignment pin hole 31G of one upper block 31B, and the other alignment pin 70 passes through the alignment pin hole 31G of the other upper block 31C. Thus, the two upper blocks 31B and 31C, the package guide 32, and the two lower blocks 33B and 33C are relatively reliably positioned.

  Thereafter, the four screws 75 pass through the screw holes 31D of the upper blocks 31B and 31C, the guide grooves 52D of the package guide 32, and the screw holes 33D of the lower blocks 33B and 33C, and the base 12B of the jig base 12 As shown in FIG. 6, the assembly unit 80 of the upper block unit 31, the package guide 32, and the lower block unit 33 causes the package guide 32 to be mounted on the high frequency substrate 30 on the jig base 12 by being screwed into the female screw 12 </ b> M. Relative to the X, Y, and Z directions.

  Thereafter, the package 101 of the transistor 100 is positioned by being dropped into the positioning hole 60 of the package guide 32 as shown in FIG. 8C, so that the package guide 32 is parallel to the high-frequency substrate 30. It can be positioned in the plane formed by the X direction and the Y direction. At this time, the package 101 itself of the transistor 100 is positioned in the positioning hole 60 in a state of being lifted by 0.3 mm from, for example, 50 ohm transmission lines 21 and 22.

  The package guide 32 is held so as to be parallel to the high-frequency substrate 30 while being sandwiched between the upper book unit 31 and the lower block unit 33. The transistor 100 is positioned by being inserted into the positioning hole 60 of the package guide 32 as shown in FIG. 8C, and the transistor 100 is arranged at a predetermined arrangement position P as shown in FIG. Since the package guide 32 of the transistor 100 can be pressed along the Z direction by the package pressing member 150, the four leads 102 of the transistor 100 are connected to the conductor portions 45 and 46 and the 50 ohm transmission lines 21 and 22. Can be electrically connected to each other.

  Thus, since the package 101 of the transistor 100 can be pressed along the Z direction by the package pressing member 150, the high frequency impedance does not change as compared with the conventional case where the pressing member directly presses the lead. There is. Moreover, the upper surface of the package 101 can be pressed at a constant pressure by the package pressing member 150, and the lead 102 of the transistor 100 can be brought into electrical contact with the corresponding 50 ohm transmission lines 21 and 22 reliably. Does not affect high frequency characteristics. As a result, the package pressing member 150 is not directly in contact with the lead 102, and the influence on the high frequency characteristics can be minimized. For example, the measurement accuracy is improved when the bandwidth is 100 MHz to 12 GHz.

  The upper block unit 31, the package guide 32, the lower block unit 33, and the high frequency substrate 30 can be easily and reliably aligned with each other with respect to the jig base 12 with reference to the two alignment pins 70, 70. it can. Thus, the package guide 32 is sandwiched between the upper block unit 31 and the lower block unit 33, and the upper block unit 31 and the lower block unit 33 connect the 50 ohm transmission lines 21 and 22 with a certain opening dimension W2. Other than opening, it can be enclosed from the outside.

  Thus, as shown in FIG. 6, when the transistor 100 is placed at the placement position P of the high-frequency substrate 30 by the assembly unit 80, the one and the other bias T shown in FIG. By applying a high frequency signal from the measuring instrument 11 to the transistor 100 through the transmission lines 21 and 22, the high frequency characteristics of the transistor 100 can be evaluated with good workability. The high frequency characteristics of various low noise transistors in a wide band (for example, 100 MHz to 12 GHz) can be evaluated using one high frequency characteristic evaluation jig 10.

  Conventionally, when evaluating the high-frequency characteristics of a transistor having a lead, the influence of the clamp that holds the lead increases as the frequency increases, the measurement error increases, and the reflection at the high-frequency connector-50 ohm transmission line converter increases. As a result, the insertion loss increases and the measurement accuracy decreases. Further, the transistor cannot secure a good high frequency characteristic over a wide band due to an abnormal resonance phenomenon.

  Here, FIG. 10 shows the reflection loss S11 and the insertion loss S21 in the high frequency characteristic evaluation jig 10 of the evaluation system shown in FIG. 11 and 12 show a comparison of high-frequency characteristics between the embodiment of the present invention and the conventional example.

  FIG. 11 is a graph showing the reflection loss S11-1 in the embodiment of the present invention and the reflection loss S11-2 in the conventional example, and FIG. 12 shows the insertion loss S21-1 in the embodiment of the present invention and the conventional example. It is a graph which shows insertion loss S21-2.

  As shown in FIG. 11, when the reflection loss S11-1 in the embodiment of the present invention is compared with the reflection loss S11-2 in the conventional example, the reflection loss S11-1 in the embodiment of the present invention decreases over a wide band. I understand that. In the embodiment of the present invention, the reflection loss is as low as -20 dB.

  As shown in FIG. 12, when the insertion loss S21-1 in the embodiment of the present invention is compared with the insertion loss S21-2 in the conventional example, the insertion loss S11-1 in the embodiment of the present invention is improved over a wide band. I understand that In the example of the present invention, the insertion loss was as low as -0.38 dB.

  Next, a preferred embodiment of the method for manufacturing a semiconductor device of the present invention will be described.

  First, in the manufacturing process of the semiconductor device, the transistor 100 as the semiconductor device shown in FIG. 5 is formed. For example, SiGe pellets 103 are arranged on the leads 102, and the pellets 103 are electrically connected to the leads 102 using bonding wires 104. Then, a part of the lead 102, the pellet 103, and the bonding wire 104 are sealed with a sealing resin, whereby the rectangular parallelepiped package 101 is formed.

  In the next measurement process of the semiconductor device, the transistor 100 produced as described above is positioned at the arrangement position P on the high frequency substrate 30 of the jig base 12 of the evaluation type high frequency characteristic evaluation jig 10 shown in FIG. Is done. The lower block unit 33, the package guide 32, and the upper block unit 31 of the high frequency characteristic evaluation jig 10 are assembled in advance on the high frequency substrate 30 of the jig base 12 to constitute an assembly unit 80.

  As shown in FIGS. 5 and 6, the transistor 100 is positioned in the X direction and the Y direction by being fitted into the positioning hole 60 of the package guide 32. In addition, as shown in FIG. 6, the package guide 101 of the transistor 100 is pressed by the package pressing member 150 and positioned in the Z direction. The frequency of the high-frequency signal passed through the 50 ohm transmission lines 21 and 22 is determined, and the high-frequency signal is supplied to the transistor 100 through the high-frequency connectors 25 and 26 and the 50 ohm transmission lines 21 and 22.

  Next, in the evaluation process of the semiconductor device, for example, the reflection loss shown in FIG. 11 and the insertion loss shown in FIG. 12 are measured, and the result of the high frequency characteristics of the semiconductor device is evaluated. The transistor 100, which is an example of a semiconductor device, can evaluate the result of high-frequency characteristics measured after fabrication.

  Note that when the evaluation of the transistor 100 is completed and the next semiconductor device is manufactured, the package pressing member 150 is separated from the package 101 of the transistor 100, and the transistor 100 is removed from the positioning hole 60 of the package guide 32. A new semiconductor device may be inserted into the positioning hole 60 of the package guide 32. The semiconductor device is a low noise amplifier used in, for example, a terrestrial digital television, a high sensitivity wireless LAN, a mobile phone, a wireless circuit, and the like.

The high-frequency characteristic evaluation jig of the present invention is a jig base on which a high-frequency substrate having a transmission line is mounted, a metal first block unit disposed on the high-frequency substrate, and a first block unit. A package guide having a positioning hole portion for fitting the semiconductor device package into an in-plane direction parallel to the surface of the high-frequency substrate and contacting the lead of the semiconductor device with the transmission line of the high-frequency substrate, and disposed on the package guide A metal second block unit that sandwiches the package guide together with the first block unit and is fixed to the jig base, and a plane parallel to the surface of the high-frequency substrate from the opening formed by the second block unit A package pressing member that enters in a direction perpendicular to the inward direction and pushes the package of the semiconductor device toward the high-frequency substrate side. And wherein the door. Accordingly, the first block unit and the second block unit can surround the periphery of the package of the semiconductor device positioned in the positioning hole. For this reason, the periphery of the package of the semiconductor device is in a closed state, and even when the frequency at which the high frequency characteristic of the semiconductor device is evaluated exceeds 6 GHz, the influence on the high frequency characteristic is reduced and the measurement accuracy is not deteriorated. Furthermore, generation of unnecessary radio waves can be suppressed and isolation between high frequency input and output can be obtained, thereby preventing resonance and oscillation. Since the lead of the semiconductor device is fixed so that the lead is in electrical contact with the transmission line on the high-frequency substrate in a state where the package is pushed without being pushed directly, the characteristic impedance can be prevented from changing. Therefore, the semiconductor device can be pressed and positioned so as not to affect the high frequency characteristics, and the measurement accuracy when measuring the high frequency characteristics can be improved. In the high frequency characteristic evaluation jig of the present invention, the first block unit Has one first block arranged on one side of the positioning hole and the other first block arranged on the other side of the positioning hole, and the second block unit has one first block It has one 2nd block arrange | positioned corresponding to 1 block, and the other 1st block arrange | positioned corresponding to the other 1st block, It is characterized by the above-mentioned. Thereby, one and the other first block of the first block unit and one and the other second block of the second block unit can easily surround the package of the semiconductor device positioned in the positioning hole.

  In the high-frequency characteristic evaluation jig of the present invention, the jig base has alignment pins for positioning the first block unit, the package guide, and the second block unit along the vertical direction, and the first block unit and the package guide The second block unit is detachably fixed to the jig base. Accordingly, the first block unit, the package guide, and the second block unit can be reliably positioned and fixed with respect to the jig base, and can be removed from the jig base as necessary.

  In the high-frequency characteristic evaluation jig of the present invention, a coaxial high-frequency connector attached to the flange of the jig pedestal, and a coaxial-to-line converter that electrically connects the center conductor of the high-frequency connector to the transmission line of the high-frequency substrate. And an opening through which the center conductor of the high-frequency connector passes is formed. The opening is formed continuously with the first through hole and the first through hole and has a smaller diameter than the first through hole. The second through hole is formed, an insulator for holding the central conductor is disposed in the first through hole, and an air layer is formed in the second through hole. Thereby, if the plate thickness of the high frequency substrate is reduced, the high frequency current path from the coaxial ground conductor portion to the high frequency substrate ground portion is not short. The diameter of the air layer in the second through hole is the diameter of the insulator in the first through hole. Therefore, generation of unnecessary radio waves can be suppressed.

  The manufacturing method of a semiconductor device according to the present invention includes a semiconductor device creation process for creating a semiconductor device by electrically connecting a semiconductor element to a lead and sealing with a sealing resin, and a transmission line arranged on a jig base The first block unit made of metal is disposed on the high-frequency substrate having the structure, the semiconductor device package is fitted, and the lead of the semiconductor device is aligned with the in-plane direction parallel to the surface of the high-frequency substrate. A package guide having a positioning hole portion to be contacted is arranged on the first block unit, a second block unit made of metal is arranged on the package guide, and the package guide is sandwiched with the first block unit to the jig base. From the opening formed by the second block unit, the package pressing member is placed in the in-plane direction parallel to the surface of the high-frequency substrate. The semiconductor device measurement process for measuring the high frequency characteristics of the semiconductor device by pushing the semiconductor device package toward the high frequency substrate side by entering the vertical direction, and the semiconductor device evaluation process for evaluating the result of the measured high frequency characteristics of the semiconductor device It is characterized by including these. Thereby, the periphery of the package of the semiconductor device is in a closed state, and the influence on the high frequency characteristic is reduced even when the frequency at which the high frequency characteristic of the semiconductor device is evaluated exceeds 6 GHz, and the measurement accuracy does not deteriorate. Furthermore, generation of unnecessary radio waves can be suppressed and isolation between high frequency input and output can be obtained, thereby preventing resonance and oscillation. The lead of the semiconductor device is fixed so that the lead is in electrical contact with the transmission line on the high-frequency substrate in a state where the package is pushed without being pushed directly, so that the characteristic impedance can be prevented from changing. It is possible to perform evaluation while improving the measurement accuracy when measuring the high frequency characteristics by holding the semiconductor device and positioning so as not to affect the frequency.

  Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage.

  Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine the component covering different embodiment suitably.

It is a figure which shows an evaluation system provided with preferable embodiment of the high frequency characteristic evaluation jig | tool of this invention. It is a perspective view which shows the structural example of the high frequency characteristic evaluation jig | tool shown in FIG. It is a perspective view which shows the state which removed the upper block from the high frequency characteristic evaluation jig | tool shown in FIG. It is a top view which shows the state which removed the upper block, the package guide, and the lower block from the high frequency characteristic evaluation jig | tool shown in FIG. 2, and exposed the high frequency board | substrate. It is a structure in the XX line of the high frequency characteristic evaluation jig | tool shown in FIG. 2, and is a figure which shows the state in the middle of assembling an upper block, a package guide, and a lower block. It is a figure which shows the state by which the upper block, the package guide, and the lower block are assembled and the package of the transistor is pressed by the package pressing member. It is a perspective view which shows the example of a shape of an upper block and a lower block. It is a figure which shows the example of a shape of a package guide. It is a figure which shows the high frequency connector and coaxial-50ohm line | wire conversion part in the frequency characteristic evaluation jig | tool of embodiment of this invention. It is a figure which shows the reflection loss S11 and the insertion loss S21 in the high frequency characteristic evaluation jig | tool of the evaluation type | system | group shown in FIG. It is a graph which shows the reflection loss S11-1 in the Example of this invention, and the reflection loss S11-2 in a prior art example. It is a graph which shows the insertion loss S21-1 in the Example of this invention, and the insertion loss S21-2 in a prior art example. It is a figure which shows the evaluation system containing the conventional high frequency characteristic evaluation jig | tool. It is a perspective view which shows the conventional high frequency characteristic evaluation jig | tool. It is a perspective view which shows the conventional high frequency board | substrate and a transistor. It is a figure which shows the high frequency connector and coaxial-50ohm line | wire conversion part in the conventional high frequency characteristic evaluation jig | tool.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... High frequency characteristic evaluation jig | tool, 11 ... Measuring device, 12 ... Jig base, 21, 22 ... 50 ohm transmission line, 25, 26 ... High frequency connector, 30 ... High frequency board, 31 ... Upper block unit (2nd block unit) , 32... Package unit, 33... Lower block unit (first block unit), 60. Positioning hole, 70. Positioning pin, 79. Coaxial-50 ohm transmission line converter, 100. One example), 101 ... package, 102 ... lead, 150 ... package holding member,

Claims (5)

A jig base on which a high-frequency substrate having a transmission line is mounted;
A first block unit made of metal disposed on the high-frequency substrate;
Arranged on the first block unit, the semiconductor device package is fitted and aligned in an in-plane direction parallel to the surface of the high-frequency substrate, and the lead of the semiconductor device contacts the transmission line of the high-frequency substrate. A package guide having a positioning hole to be
A metal second block unit disposed on the package guide and sandwiching the package guide together with the first block unit and fixed to the jig base;
A package presser that pushes the package of the semiconductor device toward the high-frequency substrate side through the opening formed by the second block unit in a direction perpendicular to the in-plane direction parallel to the surface of the high-frequency substrate. Members,
A high-frequency characteristic evaluation jig comprising: The first block unit has one first block disposed on one side of the positioning hole, and the other first block disposed on the other side of the positioning hole,
The second block unit has one second block arranged corresponding to the one first block and the other first block arranged corresponding to the other first block. The high-frequency characteristic evaluation jig according to claim 1, wherein The jig base includes an alignment pin that positions the first block unit, the package guide, and the second block unit along the vertical direction,
The high frequency characteristic evaluation unit according to claim 1 or 2, wherein the first block unit, the package guide, and the second block unit are detachably fixed to the jig base. Ingredients. A coaxial high-frequency connector attached to the flange of the jig base;
A coaxial-to-line converter that electrically connects a central conductor of the high-frequency connector to the transmission line of the high-frequency substrate; and
The flange is formed with an opening through which the center conductor of the high-frequency connector passes.
The opening is formed of a first through hole and a second through hole formed continuously from the first through hole and having a smaller diameter than the first through hole, and the central conductor is disposed in the first through hole. The high frequency characteristic evaluation jig according to any one of claims 1 to 3, wherein an insulator for holding the air is disposed, and the second through hole is an air layer. Creating a semiconductor device by electrically connecting a semiconductor element to the lead and encapsulating with a sealing resin to create a semiconductor device;
A metal first block unit is disposed on a high-frequency substrate having a transmission line disposed on a jig base, and the semiconductor device package is fitted and aligned in an in-plane direction parallel to the surface of the high-frequency substrate. A package guide having a positioning hole for bringing the lead of the semiconductor device into contact with the transmission line of the high-frequency substrate is disposed on the first block unit, and a metal second block unit is disposed on the package guide. The package guide is sandwiched together with the first block unit and fixed to the jig base, and the package pressing member is parallel to the surface of the high-frequency substrate from the opening formed by the second block unit. Enter the direction perpendicular to the in-plane direction and push the package of the semiconductor device to the high frequency substrate side. A measuring process of a semiconductor device for measuring the frequency characteristics of the semiconductor device,
A semiconductor device evaluation step for evaluating a result of the measured high-frequency characteristics of the semiconductor device;
A method for manufacturing a semiconductor device, comprising:

Images