JP2010113723A - Back-annotation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a back-annotation device capable of executing back-annotation efficiently. <P>SOLUTION: The back-annotation device executes pre-layout simulation, extracts a node (an active node) whose electric potential changes at the execution of simulation (S1), and performs layout pattern verification to layout pattern data (S2). A parasitic element is extracted from layout pattern data based on active node information extracted at the pre-layout simulation in S1, and a net list with a parasitic element including all devices of layout pattern data and extracted parasitic element information is generated(S3). Post-layout simulation is executed based on the generated net list (S4). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a back annotation device, and more particularly to a back annotation device that performs a simulation based on a result of an extracted parasitic element.

  With the progress of process technology and the increase in device speed, it has become important to reduce wiring delay. For this purpose, layout is performed once, and after the layout is completed, parasitic elements that cause wiring delay are extracted from the layout, and circuit simulation is performed using the circuit configuration of the layout and information on the parasitic elements. This is called back annotation.

  In the conventional back annotation flow, post-layout simulation is performed using a netlist with parasitic elements including parasitic element information of all devices present in the target layout pattern data and a designated node.

  However, in recent years, as semiconductor integrated circuits become larger, post-layout simulation for all devices in a semiconductor integrated circuit requires a lot of execution time for parasitic element extraction and post-layout simulation. It is often difficult to execute in a short time. In addition, it is difficult to manually select the target node for parasitic element extraction in the target layout pattern data, and post layout simulation becomes more difficult as the number of extraction target nodes increases. There's a problem.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a back annotation apparatus capable of efficiently executing back annotation.

  A back annotation apparatus according to an aspect of the present invention is connected to a pre-layout simulation execution unit that detects a node whose potential changes when a predetermined signal is applied to a logic circuit, and a pre-layout simulation execution unit. A parasitic element extraction unit that extracts parasitic elements from the nodes to be connected, and a netlist that is connected to the parasitic element extraction unit and includes all devices included in the layout pattern data of the logic circuit and the parasitic elements extracted by the parasitic element extraction unit. A net list generation unit to generate, and a post layout simulation execution unit that is connected to the net list generation unit and executes a post layout simulation using the net list.

  Preferably, the pre-layout simulation executing unit is configured to detect an active node detecting unit that detects a node whose potential changes when applying a predetermined signal to the logic circuit, and to detect a potential when applying the predetermined signal to the logic circuit. A non-active node detection unit that detects a node that does not change. The net list generation unit is connected to the parasitic element extraction unit and the layout pattern verification execution unit, and has a parasitic element for generating a net list including a parasitic element for the active node in the layout pattern data and a device connected to the active node. Includes a netlist generator. The post-layout simulation execution unit is connected to the net list generation unit and the non-active node detection unit, and fixes the potential of a node whose potential does not change to a predetermined potential, and executes the post-layout simulation using the net list including.

  More preferably, the back annotation apparatus is further connected to the layout pattern verification execution unit, on the layout pattern data or the logic circuit diagram in which serial connection devices that are degenerated based on a unique standard at the time of layout pattern verification are connected in parallel. Layout pattern data or logic circuit that is connected to a first internal node extraction unit for extracting a node and a layout pattern verification execution unit, and in which a serial connection element that is degenerated based on a unique standard at the time of layout pattern verification is made into a single element Connected to a second internal node extraction unit for extracting a node in the figure, a first internal node extraction unit, a second internal node extraction unit, an active node detection unit, and a non-active node detection unit; Based on the extraction results of the internal node extraction unit 2, the active node detection unit and Including a node information updating unit that updates the detection result of the non-active node detection unit is connected to the parasitic element with netlist and parasitic element information degenerating unit degenerating only parasitic element information contained in the net list.

  Using the pre-layout simulation result, the selection of the parasitic element extraction target node in the target layout pattern data is facilitated. Accordingly, the parasitic element extraction processing time is shortened. Further, since the post-layout simulation is executed using the parasitic element extraction result, the post-layout simulation processing time can be shortened and efficient back annotation can be performed.

  In addition, the selection of the parasitic element extraction target node in the layout pattern data using the pre-layout simulation result is facilitated. At the same time, it is possible to narrow down the post layout simulation target circuit, extract parasitic elements faithful to the layout pattern data, and degenerate parasitic element information while maintaining the extraction accuracy. Further, the parasitic element extraction processing time and the post-layout simulation processing time using the parasitic element extraction result can be shortened, and efficient back annotation can be performed.

1 is an external view of a back annotation apparatus according to Embodiments 1 and 2 of the present invention. It is a block diagram which shows the hardware constitutions of the back annotation apparatus by Embodiment 1 and 2 of this invention. 4 is a flowchart of back annotation processing according to the first embodiment. It is a figure for demonstrating the active node extraction method at the time of performing a pre-layout simulation on a logic circuit diagram. It is a figure for demonstrating the example which extracted the parasitic element from the layout pattern data. 10 is a flowchart of back annotation processing according to the second embodiment. It is a figure for demonstrating the active node / non-active node extraction method at the time of performing a pre-layout simulation on a logic circuit diagram. It is a figure for demonstrating in detail the process of S12 of FIG. It is a figure for demonstrating in detail the process of S12 of FIG. It is a figure for demonstrating in detail the process of S13 of FIG. It is a figure for demonstrating in detail the process of S13 of FIG. It is a figure for demonstrating the example of path selection type parasitic element extraction, and the degeneration example of parasitic element information.

[Embodiment 1]
Referring to FIG. 1, the back annotation apparatus includes a computer 1, a keyboard 5 and a mouse 6 for giving instructions to the computer 1, a display 2 for displaying results calculated by the computer 1, and the computer 1. Includes a magnetic tape device 3, a CD-ROM (Compact Disc-Read Only Memory) device 7, and a communication modem 9.

  The back annotation flow program is recorded on the magnetic tape 4 or CD-ROM 8 which is a recording medium readable by the computer 1, and is read by the magnetic tape device 3 and the CD-ROM device 7, respectively. Alternatively, the data is read by the communication modem 9 via the communication line.

  Referring to FIG. 2, computer 1 includes a CPU (Central Processing Unit) 10 for executing a program read via magnetic tape device 3, CD-ROM device 7 or communication modem 9, and the operation of computer 1. ROM (Read Only Memory) 11 for storing other programs and data necessary for the program, RAM (Random Access Memory) 12 for storing programs, parameters at the time of program execution, calculation results, etc., programs and data And a magnetic disk 13 for storing the.

  The program read by the magnetic tape device 3, the CD-ROM device 7, or the communication modem 9 is executed by the CPU 10, and the back annotation flow is executed.

  A back annotation flow according to the present embodiment will be described with reference to FIG.

  4A shows an inverter 42 connected to the input node B, a NAND gate 44 connected to the input node A and the output node C of the inverter 42, and an output of the NAND gate 44. And an inverter 46 connected to the node D.

  A pre-layout simulation is executed on the logic circuit diagram a1, and a node (hereinafter referred to as an “active node”) whose potential changes during the simulation is extracted (S1). FIG. 4B is a diagram in which a pre-layout simulation is performed on the logic circuit diagram a1 of FIG.

  Referring to FIG. 4B, when input signal aa1 is input to input node A and input signal aa2 (0V) is input to input node B, input / output node C receives signal aa3 (3.0V) during pre-layout simulation. , Output signal aa4 is output to input / output node D, and output signal aa5 is output to output node E. At the same time, nodes A, D, E, and F are extracted as active nodes whose potential changes during pre-layout simulation, and active node information aa6 shown in FIG. 4C is output.

  Next, layout pattern verification is performed on the layout pattern data a3 shown in FIG. 5A according to the same method as in the prior art (S2).

  Parasitic elements are extracted from the layout pattern data a3 based on the active node information aa6 extracted during the pre-layout simulation of S1, and a net with parasitic elements including all devices in the layout pattern data a3 and the extracted parasitic element information A list (FIG. 5B) is generated (S3).

  Thereafter, a post layout simulation is performed using the parasitic element-added netlist generated in S3 (S4).

  As described above, according to the first embodiment, selection of a parasitic element extraction target node in layout pattern data is facilitated using a pre-layout simulation result. Accordingly, the parasitic element extraction processing time is shortened. Further, since the post-layout simulation is executed using the parasitic element extraction result, the post-layout simulation processing time can be shortened and efficient back annotation can be performed.

[Embodiment 2]
The back annotation apparatus according to the present embodiment has the same hardware configuration as that of the first embodiment. Therefore, the description thereof will not be repeated here.

  The back annotation flow according to the present embodiment will be described with reference to FIG.

  A logic circuit diagram e1 shown in FIG. 7A includes an inverter 52 connected to the input node B, a NAND gate 54 connected to the input node A and the output node C of the inverter 52, and an output of the NAND gate 54. Resistor 56 connected to node D and an inverter 58 connected to input / output node G located on the opposite side of output node D of resistor 56 are included.

  A pre-layout simulation is executed on the logic circuit diagram e1 shown in FIG. 4A, and active nodes and nodes whose potentials do not change during the simulation (hereinafter referred to as “non-active nodes”) are extracted (S11).

  Referring to FIG. 7B, when input signal ea1 is input to input node A and input signal ea2 (0 V) is input to input node B, input / output node C receives signal ea3 (3.0 V) during pre-layout simulation. The output signal ea4 is output to the input / output node D, the output signal ea5 is output to the input / output node G, and the output signal ea6 is output to the output node E. At the same time, nodes A, D, E, F, and G are extracted as active nodes whose potentials change during the pre-layout simulation, and active node information ea7 shown in FIG. 7C is output. Further, node C and its fixed potential (3.0 V) are extracted as non-active nodes whose potential has not changed, and are output as non-active node information ea8 shown in FIG. 7D (S11).

  Next, layout pattern verification is performed on the layout pattern shown in FIG. 7B according to the same method as in the prior art (S2).

  A node on the layout pattern data corresponding to the active node / non-active node extracted during the pre-layout simulation is connected in parallel with a serial connection device that has been degenerated based on its own standard at the time of layout pattern verification (parallel connection element) In the case of an internal node of a single serial connection element, etc., all internal nodes (internal node before degeneration) on the degenerated layout pattern data are extracted (S12).

  At the same time, in S12, the nodes on the logical circuit diagram data corresponding to the active node / non-active node are the internal nodes of the serial connection devices connected in parallel at the time of the layout pattern verification. In the case, the internal node on the layout pattern data corresponding to the internal node on the logic circuit diagram is extracted.

  The process of S12 will be described in more detail. Referring to FIG. 8A, the node on the layout pattern data c1 corresponding to the active node / non-active node extracted during the pre-layout simulation is unique during the layout pattern verification. In the case of the internal node ca2 in which the serial connection devices reduced based on the above are connected in parallel, all the internal nodes (the internal nodes F and? 1 before the reduction) on the reduced layout pattern data c1 are extracted. (FIG. 8 (B)).

  In addition, referring to FIG. 9A, the nodes on the logic circuit diagram data corresponding to the active node / non-active node extracted at the time of the pre-layout simulation are degenerated based on the original standard at the time of layout pattern verification. When the device is an internal node of ca16 in which devices are connected in parallel, the internal node on the layout pattern data corresponding to the internal node on the degenerated logic circuit diagram data? 1 is extracted (FIG. 9B).

  After the process of S12, the nodes on the layout pattern data corresponding to the active nodes / non-active nodes extracted at the time of the pre-layout simulation are degenerated on the basis of the original criteria at the time of layout pattern verification. In the case of an internal node of a single element, etc., all internal nodes (internal nodes before degeneration) on the reduced layout pattern data are extracted (S13).

  At the same time, in S13, if the node on the logic circuit diagram data corresponding to the active node / non-active node is an internal node of a serial connection device that is degenerated based on a unique standard at the time of layout pattern verification, An internal node on the layout pattern data corresponding to the internal node is extracted.

  The process of S13 will be described in more detail. It is assumed that layout pattern data corresponding to the active node / non-active node extracted during the pre-layout simulation is shown in FIG. In the case where the node on the layout pattern data d3 shown in FIG. 10A is an internal node of the serial connection device da9 that has been degenerated based on its own criteria at the time of layout pattern verification, referring to FIG. Internal node (internal node before degeneration) D,? 2 and G are extracted.

  Further, it is assumed that the logic circuit diagram data corresponding to the active node / non-active node extracted during the pre-layout simulation is shown in FIG. When the node on the logic circuit diagram data d7 shown in FIG. 11 is an internal node of the serial connection device da21 that is degenerated based on its own reference when verifying the layout pattern, the internal node D on the degenerated logic circuit diagram data d7 and An internal node D on the layout pattern data corresponding to G is extracted.

  Summing up the processing of S12 and S13, as shown in FIG. 2, G, F and? 1 is extracted.

  The parasitic element-added netlist for the internal node extracted by the processing of S12 and S13 is converted into a parasitic element-added netlist in which only parasitic element information is degenerated while maintaining the parasitic element extraction accuracy (S14). In other words, the active node information ea7 in FIG. 1 and? 2 is added, and active node information ea11 is created.

  Using the result of the layout pattern verification in S2 and the active node information extracted in the pre-layout simulation in S11, the path selection type parasitic element extraction for the active node in the layout pattern data and the device portion connected to the active node (pre- A net list (FIG. 12C) of the partial circuit with parasitic elements of only the partial circuit that has been operated during the layout simulation is generated (S15).

  Referring to FIG. 12D, a netlist e6 in which only the parasitic element information included in the netlist of the partial circuit with parasitic elements created in the process of S15 is degenerated is created (S16).

  Thereafter, a post-layout simulation is performed using the net list with parasitic elements e6 generated in S16 (S17). When the post-layout simulation is executed, the potential of the node C is fixed to 3.0 V using the non-active node information ea8 shown in FIG.

  As described above, according to the present embodiment, selection of a parasitic element extraction target node in layout pattern data using a pre-layout simulation result is facilitated. At the same time, it is possible to narrow down the post layout simulation target circuit, extract parasitic elements faithful to the layout pattern data, and degenerate parasitic element information while maintaining the extraction accuracy. Further, the parasitic element extraction processing time and the post-layout simulation processing time using the parasitic element extraction result can be shortened, and efficient back annotation can be performed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 computer, 2 display, 3 magnetic tape device, 4 magnetic tape, 5 keyboard, 6 mouse, 7 CD-ROM device, 8 CD-ROM, 9 communication modem, 10 CPU, 11 ROM, 12 RAM, 13 magnetic disk, 42 , 46, 52, 58 Inverter, 44, 54 NAND gate, 56 resistor, a1, e1 logic circuit diagram, a3, c1, d3 layout pattern data, aa1, aa2, ea1, ea2 input signal, aa3, ea3 signal, aa4, aa5, ea5, ea6 output signal, aa6, ea11, ea7 active node information, d7 logic circuit diagram data, da21, da9 series connection device, e6 netlist, ea8 non-active node information.

Claims (1)

A pre-layout simulation execution unit that detects a node whose potential changes when a predetermined signal is applied to the logic circuit;
A parasitic element extraction unit connected to the pre-layout simulation execution unit and extracting a parasitic element from the node where the potential changes;
A netlist generating unit connected to the parasitic element extracting unit and generating a netlist including all devices included in the layout pattern data of the logic circuit and the parasitic elements extracted by the parasitic element extracting unit;
A back annotation apparatus including a post layout simulation execution unit that is connected to the net list generation unit and executes a post layout simulation using the net list.

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