JP2010109165A - Esd protection circuit and semiconductor integrated circuit including the same - Google Patents

Abstract

Provided is an ESD protection circuit that can cope with both positive and negative surge voltages as an ESD protection circuit and has a small element area.
An ESD protection circuit includes a collector 111 connected to a first terminal T1, an emitter 112 connected to a second terminal T2, and a base 113 connected to a second terminal T2 via a resistor 120. The nMOS transistor 100 has a bipolar transistor 110, a drain 101 connected to a base 113, a source 102, a gate 103, and a back gate 104 connected to a second terminal T2.
[Selection] Figure 1

Description

  The present invention relates to an ESD protection circuit and a semiconductor integrated circuit equipped with the ESD protection circuit, and more particularly to an ESD protection circuit capable of dealing with both positive and negative surge voltages due to ESD and a semiconductor integrated circuit equipped with the ESD protection circuit. Regarding the circuit.

  In order to increase the reliability of a semiconductor integrated circuit, it is important to increase the resistance against ESD (Electrostatic Discharge). Therefore, an ESD protection circuit is incorporated in a semiconductor integrated circuit.

  Here, ESD is a phenomenon in which a charge accumulated at a high potential in a device or human body existing outside a semiconductor integrated circuit is instantaneously discharged, and the discharged charge instantaneously flows into the semiconductor integrated circuit. Then, a high voltage and a high temperature are generated in the semiconductor integrated circuit, causing destruction. Therefore, the ESD protection circuit is designed to have a function of preventing this high potential charge from flowing into the semiconductor element.

  The ESD protection circuit is connected between the two terminals, and plays a role of inducing the charge flowing in by the ESD to the outside of the semiconductor integrated circuit without destroying the semiconductor element. At this time, even if the surge voltage generated between the two terminals is positive or negative, it must operate sufficiently as an ESD protection circuit. As a circuit that sufficiently operates as an ESD protection circuit against the positive and negative surge voltages, the ESD protection circuit of Patent Document 1 can be cited.

In Patent Document 1, when a surge voltage occurs in a positive direction, an ESD protection circuit that operates at a low voltage is realized by operating a transistor Q2 having a resistor R that plays a role of lowering a breakdown voltage. Yes. On the other hand, when the surge voltage is generated in a negative direction, the transistor Q1 operates to realize an ESD protection circuit that allows a sufficient collector current to flow and prevents element destruction. However, the ESD protection circuit composed of two bipolar transistors as in Patent Document 1 has a problem that the element area is large.
JP 2000-183288 A.

  An object of the present invention is to provide an ESD protection circuit that can cope with both positive and negative surge voltages as an ESD protection circuit and has a small element area.

  The ESD protection circuit according to the first aspect of the present invention includes a bipolar transistor having a collector connected to a first terminal, an emitter connected to a second terminal, and a base connected to the second terminal via a resistor. And an nMOS transistor having a drain connected to the base, a source, a gate, and a back gate connected to the second terminal.

  The ESD protection circuit according to the second aspect of the present invention is a bipolar circuit in which a collector is connected to a first terminal, an emitter is connected to a second terminal, and a base is connected to the second terminal via a resistor. A pMOS transistor having a transistor, a source, a gate, a back gate connected to the base, and a drain connected to the second terminal.

  In the ESD protection circuit according to the third aspect of the present invention, the collector is connected to the first terminal, the emitter is connected to the second terminal, and the base is connected to the second terminal via a resistor. A bipolar transistor and a diode connected in a forward direction from the second terminal are provided between the second terminal and the base.

  The semiconductor integrated circuit of one embodiment of the present invention is a semiconductor integrated circuit including a power supply terminal, an input terminal, and a ground terminal, and a main body integrated circuit to which the power supply terminal, the input terminal, and the ground terminal are connected, The power supply terminal and the input terminal, the input terminal and the ground terminal, or the power supply terminal and the ground terminal are connected between at least one of the terminals. 3 ESD protection circuits.

  According to another aspect of the present invention, there is provided a semiconductor integrated circuit including a power supply terminal, an output terminal, and a ground terminal, and a main body integrated circuit in which the power supply terminal, the output terminal, and the ground terminal are connected. And between the power supply terminal and the output terminal, between the output terminal and the ground terminal, or between at least one terminal between the power supply terminal and the ground terminal. It has the ESD protection circuit of Claim 3.

  According to the present invention, it is possible to provide an ESD protection circuit that can cope with both positive and negative surge voltages as an ESD protection circuit and has a small element area.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS.

(First embodiment)
As shown in FIG. 1, the ESD protection circuit according to the first embodiment of the present invention has a collector 111 connected to a first terminal T1, an emitter 112 connected to a second terminal T2, and a base 113 connected to a resistor. Bipolar transistor 110 connected to second terminal T2 via 120, nMOS transistor having drain 101 connected to base 113, source 102, gate 103, and back gate 104 connected to second terminal T2. 100.

  The ESD protection circuit according to the first embodiment has a configuration in which an nMOS transistor is connected between the base 113 of the bipolar transistor 110 and the terminal 20 of the ESD protection circuit 2 shown in FIG. Here, the merit of connecting the nMOS transistors will be described with reference to the ESD protection circuits 1 and 2 shown in FIGS.

  Each of the ESD protection circuits 1 and 2 includes a bipolar transistor having a collector 111 connected to the terminal 10 and an emitter 112 connected to the terminal 20. The base 113 of the bipolar transistor 110 of the ESD protection circuit 1 is directly connected to the terminal 20. Further, the base 113 of the bipolar transistor 110 of the ESD protection circuit 2 is connected to the terminal 20 via the resistor 120.

  When the voltage at the terminal 10 is V and the voltage at the terminal 20 is V ′, the voltage between the terminal 10 and the terminal 20 may be V> V ′ or V <V ′ due to a surge voltage generated by ESD. is there. In both cases, the ESD protection circuit must operate normally. In addition, the ESD protection circuit must operate at a voltage lower than the withstand voltage of the non-protection circuit (not shown).

  First, the operation of the ESD protection circuit 1 and the ESD protection circuit 2 when a surge voltage that satisfies V> V ′ occurs will be described. When V> V ′, a reverse bias is applied to the collector-base pn junction of the bipolar transistor 110 in the ESD protection circuits 1 and 2. When this reverse bias is sufficiently high, breakdown occurs in the collector-base junction region, and electron-hole pairs are generated. Of these electron-hole pairs, holes are injected from the base 113 into the emitter 112, and a collector current Ic that is hfe times the hole injected into the emitter 112 (hfe is the current amplification factor of the transistor) flows to the bipolar transistor 110. As a result, the collector-emitter becomes conductive, and the surge voltage generated between the terminal 10 and the terminal 20 is reduced. At this time, in the ESD protection circuit 1, a part of the holes of the electron hole pair generated by the breakdown flows out to the terminal 20 through the lead wire 109. Thereby, the injection efficiency into the emitter 112 is lowered, and the breakdown voltage is increased. On the other hand, in the ESD protection circuit 2, the resistor 120 suppresses holes from flowing out to the terminal 20 through the lead wire 109, so that the breakdown voltage can be lowered.

  Next, operations of the ESD protection circuit 1 and the ESD protection circuit 2 when a surge voltage satisfying V <V ′ occurs will be described. When V <V ′, a forward bias is applied between the collector and base of the bipolar transistor 110 in the ESD protection circuits 1 and 2. Due to this forward bias, the collector current Ic flows from the terminal 20 to the terminal 10 via the collector base and the surge voltage generated between the terminal 10 and the terminal 20 is reduced. At this time, it is known that the maximum collector current that can be passed through the bipolar transistor is smaller in the ESD protection circuit 2 than in the ESD protection circuit 1.

  The characteristics of the collector-emitter voltage Vce (= V−V ′) and the collector current Ic are shown in FIGS. 8A and 8B. FIG. 8A shows the characteristics when V> V ′, and FIG. 8B shows the characteristics when V <V ′.

  First, in the case of V> V ′, as shown in FIG. 8A, the ESD protection circuit 2 breaks down at a lower voltage than the ESD protection circuit 1 for the reason described above. Further, the ESD protection circuit 2 can change the breakdown voltage by changing the resistance value of the resistor 120. For this reason, when a surge voltage is generated so that V> V ′, the ESD protection circuit 2 is suitable as an ESD protection circuit.

  Next, in the case of V <V ′, as shown in FIG. 8B, the maximum collector current that flows when the voltage Vce is applied between the collector and the emitter by ESD is higher than that of the ESD protection circuit 1 as shown in FIG. The protection circuit 2 is smaller. That is, in the ESD protection circuit 1, the collector current flows even if the voltage applied between the collector and the emitter increases, but in the ESD protection circuit 2, no current exceeding the maximum collector current flows. If the maximum collector current is small, there is a high possibility of causing element destruction, so that it is not suitable as an ESD protection circuit. For this reason, when a surge voltage is generated such that V <V ′, the ESD protection circuit 1 capable of flowing a large collector current is suitable as an ESD protection circuit.

  As described above, as the ESD protection circuit, a circuit having the resistor 120 when V> V ′ and a circuit without the resistor 120 when V <V ′ are optimal. In the first embodiment, an nMOS transistor 100 is connected between the base 113 of the bipolar transistor 110 and the second terminal T2, thereby providing an optimum circuit in the case of V> V ′ and V <V ′. Can do.

  FIG. 2 is a cross-sectional view of the nMOS transistor 100 of the ESD protection circuit of FIG. 1, and the operation of the ESD protection circuit will be described in detail using this. As shown in FIG. 2, between the base 113 of the bipolar transistor 110 and the second terminal T2, the nMOS transistor 100 forms a pn junction of an n-type drain, a p-type substrate, and a p-type back gate. For this reason, when the base 113 side becomes a high voltage with respect to the second terminal T2, the pn junction is reverse-biased, and no current flows between the base 113 and the second terminal T2. On the other hand, when the second terminal T2 becomes a high voltage with respect to the base 113 side, the pn junction is forward biased, and a current flows from the second terminal T2 to the base 113 and becomes conductive. Therefore, the nMOS transistor 100 operates as a diode connected in the forward direction from the second terminal T2 between the second terminal T2 and the base 113. As described above, the nMOS transistor 100 is required to have a function of flowing a forward current at the time of forward bias, and thus can be configured with a smaller size than a normal nMOS transistor.

  In the following description of the operation of the ESD protection circuit, the voltage at the first terminal T1 is V, and the voltage at the second terminal T2 is V '.

  First, the operation of the ESD protection circuit when a surge voltage is generated so that V> V ′ will be described. When a surge voltage is generated by ESD so that V> V ′, a reverse bias is applied between the collector and base of the bipolar transistor 110, and breakdown occurs. As a result, the collector and the emitter become conductive, and the voltage at the first terminal T1 is lowered. At this time, the resistor 120 serves to lower the breakdown voltage as described above.

  At this time, since the base 113 has a high voltage with respect to the second terminal T2, the nMOS transistor 100 becomes a reverse bias of the diode and no current flows. For this reason, the ESD protection circuit operates with a low breakdown voltage due to the resistor 120.

  Next, the operation of the ESD protection circuit when a surge voltage is generated so that V <V ′ is described. When a surge voltage is generated by ESD so that V <V ′, a forward bias is applied between the collector and base of the bipolar transistor 110, and a collector current flows. At this time, in the nMOS transistor 100, since the second terminal T2 is at a high voltage with respect to the base 113, the nMOS transistor 100 becomes forward biased, and conducts current. An nMOS transistor can pass a current with a sufficiently small resistance value when conducting. Thus, the base 113 of the bipolar transistor 110 and the second terminal T2 are connected with a low resistance. For this reason, the maximum collector current can be increased and the ESD protection circuit can be prevented from being destroyed.

  As described above, in the ESD protection circuit according to the first embodiment of the present invention, when a surge voltage is generated by ESD so that the first terminal T1 has a higher voltage than the second terminal T2, The nMOS transistor 100 does not operate, and an ESD protection circuit that operates at a low voltage can be realized by the resistor 120 connected to the base 113 of the bipolar transistor 110. On the other hand, when a surge voltage is generated by ESD so that the second terminal T2 has a higher voltage than the first terminal T1, the nMOS transistor 100 becomes conductive and the base of the bipolar transistor 110 is connected to the second terminal T2. Since the terminal T2 is connected with a low resistance, the maximum collector current can be increased, and the ESD protection circuit can be prevented from being destroyed.

  In addition, the ESD protection circuit according to the first embodiment of the present invention can be configured only by inserting the nMOS transistor 100 between the base 113 of the bipolar transistor 110 and the second terminal T2, and the nMOS transistor 100 is substantially Therefore, since the operation corresponding to a diode through which forward current flows is performed, it can be configured in a small size, and the ESD protection circuit can be downsized.

(Second Embodiment)
As shown in FIG. 3, in the ESD protection circuit according to the second embodiment of the present invention, the collector 111 is connected to the first terminal T1, the emitter 112 is connected to the second terminal T2, and the base 113 is a resistor. Bipolar transistor 110, source 102, gate 103, back gate 104 connected to the base 113, and drain 101 connected to the second terminal T2 via the second terminal T2 via 120 100 ′.

  The difference between the ESD protection circuit according to the second embodiment and the ESD protection circuit according to the first embodiment is that, instead of the nMOS transistor 100 used in the ESD protection circuit according to the first embodiment, a pMOS transistor 100 ′. It is a point using. Since the pMOS transistor 100 ′ is used in the second embodiment, the source 102, the gate 103, and the back gate 104 are connected to the base 113 of the bipolar transistor 110 and the drain 101 is the second as shown in FIG. To the terminal T2.

  FIG. 4 shows a cross-sectional view of the pMOS transistor 100 ′ of the ESD protection circuit of the second embodiment. As shown in FIG. 4, between the base 113 of the bipolar transistor 110 and the second terminal T2, there is a pn junction of a p-type drain, an n-type well, and an n-type back gate. Therefore, similar to the nMOS transistor 100 of the first embodiment of the present invention, the pMOS transistor 100 ′ operates as a diode connected in the forward direction from the second terminal T2 between the second terminal T2 and the base 113. To do. For this reason, the operation of the ESD protection circuit according to the second embodiment is the same as the operation of the ESD protection circuit according to the first embodiment.

  As described above, in the ESD protection circuit according to the second embodiment of the present invention, when a surge voltage is generated by ESD so that the first terminal T1 has a higher voltage than the second terminal T2, The pMOS transistor 100 ′ does not operate, and an ESD protection circuit that operates at a low voltage can be realized by the resistor 120 connected to the base 113 of the bipolar transistor 110. On the other hand, when a surge voltage is generated by ESD so that the second terminal T2 has a higher voltage than the first terminal T1, the pMOS transistor 100 ′ becomes conductive and the base 113 of the bipolar transistor 110 is connected to the first terminal T1. 2 is connected to the terminal T2 with a low resistance, the maximum collector current can be increased, and the ESD protection circuit can be prevented from being destroyed.

  Further, the ESD protection circuit according to the second embodiment of the present invention can be configured by simply inserting the pMOS transistor 100 ′ between the base 113 of the bipolar transistor 110 and the second terminal T2, and the pMOS transistor 100 ′ Since the operation substantially corresponds to a diode for passing a forward current, it can be configured in a small size, and the element area of the ESD protection circuit can be reduced.

(Third embodiment)
As shown in FIG. 5, in the ESD protection circuit according to the third embodiment of the present invention, the collector 111 is connected to the first terminal T1, the emitter 112 is connected to the second terminal T2, and the base 113 is a resistor. The bipolar transistor 110 is connected to the second terminal T2 via 120, and the diode 130 is connected between the second terminal T2 and the base 113 in the forward direction from the second terminal T2.

  The difference between the ESD protection circuit according to the third embodiment and the ESD protection circuit according to the first and second embodiments is that the MOS transistor 100 used in the ESD protection circuit according to the first and second embodiments. , 100 ′ instead of the diode 130 in the third embodiment. As shown in FIG. 5, since the diode 130 is connected in the forward direction from the second terminal T2 between the second terminal T2 and the base 113, the ESD protection circuit according to the first and second embodiments. It operates in the same manner as the MOS transistors 100 and 100 ′. For this reason, the operation of the ESD protection circuit according to the third embodiment is the same as the operation of the ESD protection circuit according to the first and second embodiments.

  As described above, in the ESD protection circuit according to the third embodiment of the present invention, when a surge voltage is generated by ESD so that the first terminal T1 has a higher voltage than the second terminal T2, The diode 130 does not operate, and an ESD protection circuit that operates at a low voltage can be realized by the resistor 120 connected to the base 113 of the bipolar transistor 110. On the other hand, when a surge voltage is generated by ESD so that the second terminal T2 has a higher voltage than the first terminal T1, the diode 130 is turned on, and the base of the bipolar transistor 110 is connected to the second terminal. Since it is connected to T2 with a low resistance, the maximum collector current can be increased, and the ESD protection circuit can be prevented from being destroyed.

(Fourth embodiment)
As shown in FIG. 6, the semiconductor integrated circuit 300 according to the fourth embodiment of the present invention includes a power supply terminal 220, an input terminal 210, and a ground terminal 230. Output terminal 210, main body integrated circuit 240 to which ground terminal 230 is connected, power source terminal 220 and input terminal 210, input terminal 210 and ground terminal 230, or power source terminal 220 and ground terminal 230. The ESD protection circuits 200a, 200b, and 200c of the first embodiment, the second embodiment, or the third embodiment are connected between terminals.

  In the following description, the power supply terminal, input terminal, and ground terminal of the semiconductor integrated circuit will be described, but the same applies even if the input terminal replaces the output terminal. Therefore, description of the output terminal is omitted.

  6A, 6 </ b> B, and 6 </ b> C, a semiconductor integrated circuit including a main body integrated circuit 240 to which a power terminal 220, an input terminal 210, and a ground terminal 230 are connected, and ESD protection circuits 200 a, 200 b, and 200 c 300 is shown. The ESD protection circuit is for protecting the main body integrated circuit from a surge voltage generated between the terminals due to ESD.

  The ESD protection circuits 200a, 200b, and 200c shown in FIG. 6 are any of the ESD protection circuits shown in the first to third embodiments. The first terminal T1 and the second terminal T2 of the ESD protection circuits 200a, 200b, and 200c correspond to the first terminal T1 and the second terminal T2 of the ESD protection circuit shown in the first to third. .

  A semiconductor integrated circuit 300 shown in FIG. 6A includes a main body integrated circuit 240 to which a power supply terminal 220, an input terminal 210, and a ground terminal 230 are connected, and a power supply terminal 220 to which a first terminal T1 is connected. And an ESD protection circuit 200b in which the first terminal T1 is connected to the input terminal 210 and the second terminal T2 is connected to the ground terminal 230.

  When a surge voltage is generated by ESD between the power supply terminal 220 and the input terminal 210, the ESD protection circuit 200a operates as shown in the first to third embodiments to reduce the surge voltage. Similarly, when a surge voltage is generated by ESD between the input terminal 210 and the ground terminal 230, the ESD protection circuit 200b operates to reduce the surge voltage. Further, when a surge voltage is generated by ESD between the power supply terminal 220 and the ground terminal 230, the two ESD protection circuits of the ESD protection circuit 200a and the ESD protection circuit 200b operate to reduce the surge voltage.

  A semiconductor integrated circuit 300 shown in FIG. 6B includes a main body integrated circuit 240 to which a power supply terminal 220, an input terminal 210, and a ground terminal 230 are connected, and an ESD protection circuit 200a connected in the same manner as in FIG. It further includes an ESD protection circuit 200b, and further includes an ESD protection circuit 200c in which the first terminal T1 is connected to the power supply terminal 220 and the second terminal T2 is connected to the ground terminal 230. Accordingly, when a surge voltage is generated by ESD between the power supply terminal 220 and the ground terminal 230, the surge voltage is reduced by operating one ESD protection circuit 200c connected between the power supply terminal 220 and the ground terminal 230. Can be made.

  The semiconductor integrated circuit shown in FIG. 6C has a main body integrated circuit 240 to which a power supply terminal 220, an input terminal 210 and a ground terminal 230 are connected, a first terminal T 1 connected to the input terminal 210, and a ground terminal 230. An ESD protection circuit 200b connected to the second terminal T2 is provided.

  In the first to third ESD protection circuits, when the voltage of the second terminal T2 becomes higher than the voltage of the first terminal T1, a forward bias is applied between the base and collector of the bipolar transistor, and the collector current flows and operates. Therefore, it operates at a relatively low voltage. Therefore, in a semiconductor integrated circuit that operates so that the voltage at the input terminal 210 is higher than the power supply voltage 220, the first terminal T1 is connected to the power supply terminal 220 as in the ESD protection circuit 200a of FIG. When the second terminal T <b> 2 is connected to the input terminal 210, a voltage input as a signal to the input terminal 210 may be lost to the power supply terminal 220 through the ESD protection circuit 200. Therefore, in such a semiconductor integrated circuit, a configuration in which the ESD protection circuit 200a is not connected to the power supply terminal 220 and the input terminal 210 as shown in FIG. 6C is optimal.

The above-described embodiments are for facilitating understanding of the present invention, and are not intended to limit the present invention. The present invention can be changed / improved without departing from the spirit thereof, and the present invention includes equivalents thereof.

1 is a circuit diagram of an ESD protection circuit according to a first embodiment. It is sectional drawing of the nMOS transistor in the ESD protection circuit which concerns on 1st Embodiment. It is a circuit diagram of the ESD protection circuit which concerns on 2nd Embodiment. It is sectional drawing of the pMOS transistor in the ESD protection circuit which concerns on 2nd Embodiment. FIG. 6 is a circuit diagram of an ESD protection circuit according to a third embodiment. It is a block diagram of the semiconductor integrated circuit provided with the ESD protection circuit which concerns on 1st, 2nd or 3rd embodiment. It is a circuit diagram of an ESD protection circuit. It is a figure which shows the operating characteristic of an ESD protection circuit.

Explanation of symbols

1, 2 ESD protection circuit 10, 20 Terminal 100 nMOS transistor 100 ′ pMOS transistor 101 drain 102 source 103 gate 104 back gate 105 p-type substrate 106 n-type well 110 bipolar transistor 111 collector 112 emitter 113 base 120 resistor 130 diode T1 first Terminal T2 Second terminal 200a, 200b, 200c ESD protection circuit 210 Input terminal 220 Power supply terminal 230 Ground terminal 240 Main body integrated circuit 300 Integrated circuit

Claims (5)

A bipolar transistor having a collector connected to the first terminal, an emitter connected to the second terminal, and a base connected to the second terminal via a resistor;
An ESD protection circuit comprising: an nMOS transistor having a drain connected to the base, a source, a gate, and a back gate connected to the second terminal. A bipolar transistor having a collector connected to the first terminal, an emitter connected to the second terminal, and a base connected to the second terminal via a resistor;
An ESD protection circuit comprising: a source, a gate, and a pMOS transistor having a back gate connected to the base and a drain connected to the second terminal. A bipolar transistor having a collector connected to the first terminal, an emitter connected to the second terminal, and a base connected to the second terminal via a resistor;
An ESD protection circuit comprising: a diode connected in a forward direction from the second terminal between the second terminal and the base. In a semiconductor integrated circuit having a power supply terminal, an input terminal, and a ground terminal,
A main body integrated circuit to which a power supply terminal, an input terminal, and a ground terminal are connected;
The power supply terminal and the input terminal, the input terminal and the ground terminal, or the power supply terminal and the ground terminal are connected between at least one of the terminals. 3. A semiconductor integrated circuit comprising three ESD protection circuits. In a semiconductor integrated circuit having a power supply terminal, an output terminal, and a ground terminal,
A main body integrated circuit to which a power supply terminal, an output terminal, and a ground terminal are connected;
The power supply terminal and the output terminal, the output terminal and the ground terminal, or the power supply terminal and the ground terminal are connected between at least one of the terminals. 3. A semiconductor integrated circuit comprising three ESD protection circuits.

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