JP2010104014A - Imaging apparatus - Google Patents

Abstract

An imaging apparatus capable of suppressing deterioration of image quality and deterioration of output characteristics when the wafer thickness is reduced is provided.
An image pickup apparatus that processes luminance signals output from a plurality of light receiving elements and outputs image information, and impedance-converts at least one output circuit and an output signal at the last stage of the output circuit. And a buffer circuit for outputting image information. The last stage of the output circuit is a source follower circuit. The current source unit 5 of the source follower circuit is provided outside the solid-state imaging device 1 including a plurality of light receiving elements. Includes a resistance dividing circuit 7 and 8 that divides a predetermined constant voltage and outputs a divided voltage from a resistance dividing point, and the divided voltage is applied to the base electrode and the collector electrode is connected to the output line of the solid-state imaging device 1. A grounded-emitter transistor 9 and a capacitor 1 that is connected between a resistance dividing point and a predetermined potential and suppresses voltage fluctuation of the base electrode depending on the signal frequency of the output signal of the solid-state imaging device 1. Including the door.
[Selection] Figure 2

Description

  The present invention relates to an imaging apparatus that processes luminance signals output from a light receiving element and outputs image information, and particularly suppresses deterioration of output characteristics while suppressing adverse effects due to heat generation in a circuit at the final output stage. Regarding technology.

In recent years, imaging devices such as home video cameras and digital still cameras have become popular.
Some of these imaging devices use a solid-state imaging device that sequentially outputs output signals of a plurality of light receiving elements arranged two-dimensionally using a plurality of vertical CCDs and one or more horizontal CCDs.

The solid-state imaging device as described above is described in detail in Non-Patent Document 1.
Further, Japanese Patent Application Laid-Open No. 2004-151867 discloses a conventional technique that mentions measures for heat dissipation of a solid-state imaging device.
Patent Document 1 describes that the amount of heat generated by the solid-state imaging device can be halved by providing the final constant current source unit of the output unit including the source follower circuit outside the solid-state imaging device.

Television Society Technical Report “New Driving Method for CPD Solid-State Image Sensor” (March 16, 1982, Matsushita Electronics Industrial Co., Ltd., Semiconductor Research Institute, Kenro Sone and 6 others)

Japanese Patent No. 2982353

However, in Patent Document 1, the heat source is merely dispersed, and the constant current source unit provided outside becomes a new heat source having a heat generation amount equivalent to that of the solid-state imaging device. The amount of heat generated is the same as before, and there is no description about heat dissipation measures for a new heat source, so it is unclear whether the heat dissipation characteristics of the entire device will be improved.
On the other hand, since a light receiving element is usually arranged at the center of the solid-state image sensor, circuits that are not required for each light receiving element are arranged in the peripheral portion.

Therefore, the output part with a relatively large amount of heat generation is arranged in one place in the peripheral part. However, when the wafer thickness of the solid-state image sensor is made thinner than a certain level, the heat generated in the output part is the entire solid-state image sensor. However, the phenomenon that only the temperature of the light receiving element in the vicinity of the output portion rises occurs.
On the other hand, the dark current tends to increase in the light receiving element as the temperature rises.

Therefore, the dark current of the light receiving elements around the output section increases, the image becomes locally white, and the quality deteriorates.
This phenomenon begins to occur when the thickness of the wafer of the solid-state imaging device is reduced to about 500 μm, and becomes particularly noticeable when the thickness of the wafer is made thinner than about 400 μm.
In order to solve the above problem, when considering a configuration in which an output unit is provided outside a solid-state imaging device including a light receiving element, the constant current source circuit in the output unit is large, so instead of the constant current source circuit An effective method is to generate a necessary voltage by resistance division and apply it to the base terminal of the NPN transistor to obtain a desired coulometric value.

However, the NPN transistor in the current source provided outside the solid-state imaging device has a relatively large parasitic capacitance between the base and the collector, so that the output due to this parasitic capacitance increases as the output frequency increases with the recent increase in the number of pixels. A problem arises in that feedback is applied to the signal and the output gain is reduced.
Therefore, the present invention suppresses the deterioration of quality due to only the temperature of the light receiving element in the vicinity of the output unit when the wafer thickness is reduced, and the NPN in the current source provided outside the solid-state imaging element. An object of the present invention is to provide an imaging device capable of suppressing deterioration of output characteristics caused by parasitic capacitance between a base and a collector of a transistor.

  In order to achieve the above object, an imaging apparatus according to the present invention is an imaging apparatus that processes luminance signals output from a plurality of light receiving elements and outputs image information, and includes at least one output circuit; A buffer circuit for converting the output signal of the last stage of the output circuit to output the image information, wherein the last stage of the output circuit is a source follower circuit, and a current source of the source follower circuit is the plurality of light receiving circuits. The current source is provided outside a solid-state imaging device including an element, and the current source includes a resistance dividing circuit that resistance-divides a constant voltage and outputs a divided voltage from a resistance dividing point; the divided voltage is applied to a base electrode; A grounded-emitter transistor connected to the output line of the solid-state image sensor, and a signal frequency of the output signal of the solid-state image sensor connected between the resistance division point and GND Characterized in that it comprises a suppressing capacitor voltage fluctuations of the dependent the base electrode.

Due to the configuration described in the means for solving the problem, the current source is provided outside the solid-state imaging device including the light receiving element, so that deterioration in the quality of image information due to local rise in the temperature of the light receiving element is suppressed. Moreover, since the voltage fluctuation of the base electrode is suppressed by the capacitor, the output gain of the source follower circuit does not decrease.
In the imaging device, the capacitor may have a high frequency characteristic corresponding to the signal frequency, and a capacitor corresponding to a parasitic capacitance between a base and a collector in the grounded emitter transistor.

As a result, the signal frequency can be followed, the influence of the parasitic capacitance between the base and the collector in the grounded-emitter transistor can be mitigated, and the decrease in the output gain of the source follower circuit can be suppressed.
An imaging device according to the present invention is an imaging device that processes luminance signals output from a plurality of light receiving elements and outputs image information, and includes at least one output circuit and an output signal at the last stage of the output circuit. A first buffer circuit that converts the impedance of the output circuit and outputs the image information, the last stage of the output circuit is a source follower circuit, and the current source of the source follower circuit is external to the solid-state imaging device including the plurality of light receiving elements. The current source includes a resistance dividing circuit that divides a predetermined constant voltage by resistance and outputs a divided voltage, a second buffer circuit that lowers an output impedance of the resistance dividing circuit, and an output voltage of the second buffer circuit Is applied to the base electrode and the collector electrode is connected to the output line of the solid-state imaging device.

Accordingly, since the current source is provided outside the solid-state imaging device including the light receiving element, it is possible to suppress a decrease in the quality of the image information due to a local rise in the temperature of the light receiving element, and the second buffer circuit can provide resistance. Since the output impedance of the dividing circuit is lowered, the voltage fluctuation of the base electrode can be suppressed, and the output gain of the source follower circuit does not decrease.
In the imaging device, the grounded-emitter transistor may be an NPN transistor, and the second buffer circuit may include an NPN transistor in which the divided voltage is applied to a base electrode.

Thus, since the two transistors are the same NPN transistor, they can be generated in the same process, and the production cost can be reduced.
In the imaging device, the grounded-emitter transistor may be an NPN transistor, and the second buffer circuit may include a PNP transistor in which the divided voltage is applied to a base electrode.

As a result, the types of the two transistors are different, and changes in characteristics due to fluctuations in temperature cancel out, so that fluctuations in characteristics due to temperature can be suppressed.
In the imaging apparatus, the grounded-emitter transistor may have a rated current of 1 mA or more and 20 mA or less.
As a result, the rated current of a general transistor is 100 mA or more, while the rated current of a grounded-emitter transistor is reduced to 1 mA or more and 20 mA or less, thereby reducing the parasitic capacitance between the base and the collector. The characteristics can be improved.

  An imaging device according to the present invention is an imaging device that processes luminance signals output from a plurality of light receiving elements and outputs image information, and includes at least one output circuit and an output signal at the last stage of the output circuit. A first buffer circuit that converts the impedance of the output circuit and outputs the image information, the last stage of the output circuit is a source follower circuit, and the current source of the source follower circuit is external to the solid-state imaging device including the plurality of light receiving elements. And the current source includes a J-FET in which a gate electrode and a source electrode are grounded and a drain electrode is connected to an output line of the solid-state imaging device.

As a result, since the current source is provided outside the solid-state imaging device including the light receiving element, it is possible to suppress deterioration in the quality of image information due to local rise in the temperature of the light receiving element, and resistance division by the J-FET Since the output impedance of the circuit is lowered, the voltage fluctuation of the base electrode can be suppressed, and the output gain of the source follower circuit does not decrease.
In the imaging apparatus, the source electrode may be grounded via a source resistor.

As a result, variations in drain current, particularly due to temperature changes, can be suppressed.
In the imaging apparatus, the source resistance may be set such that the relationship between the gate-source voltage and the drain current is not affected by temperature.
Accordingly, it is possible to suppress the characteristic variation due to the temperature by appropriately setting the resistance value.

It is a figure which shows schematic structure of the imaging system in Embodiment 1 of this invention. 3 is a diagram showing a detailed circuit of an external output unit 2. FIG. 3 is a diagram illustrating a detailed circuit of an external output unit 20. FIG. 3 is a diagram illustrating a detailed circuit of an external output unit 30. FIG. 3 is a diagram showing a detailed circuit of an external output unit 40. FIG. It is a figure which shows the relationship between the drain-source voltage Vds and the drain current Id in each gate-source voltage Vgs (small signal junction FET). It is a figure which shows the relationship between the gate-source voltage Vgs and drain current Id in each temperature Ta about small signal junction FET.

(Embodiment 1)
<Overview>
In the first embodiment of the present invention, the current source of the source follower circuit at the last stage of the output unit is connected to the light receiving element in order to suppress the degradation of the quality of the image information due to only the temperature of the light receiving element in the vicinity of the output unit rising. In order to suppress the deterioration of output characteristics caused by the parasitic capacitance between the base and collector of the NPN transistor in the current source provided outside the solid-state imaging device, An imaging system that suppresses voltage fluctuations of a base electrode by including a capacitor having a high frequency characteristic corresponding to a signal frequency of an output signal of the imaging element and a capacitance corresponding to the parasitic capacitance.

<Configuration>
FIG. 1 is a diagram illustrating a schematic configuration of an imaging system according to Embodiment 1 of the present invention.
The imaging system of Embodiment 1 is built in an imaging device such as a video camera or a digital still camera, and photoelectrically converts a subject image formed by a lens and outputs image information. As shown, the solid-state imaging device 1, the external output unit 2, the signal processing unit 3, and the driving unit 4 are configured.

  The solid-state imaging device 1 is driven by a drive unit 4 and is projected onto each light receiving element in which a plurality of subject images formed by a lens (not shown) are two-dimensionally arranged. A conventional solid-state imaging device that outputs a generated luminance signal to the external output unit 2 in a predetermined order using a plurality of vertical CCDs and one horizontal CCD, and the last stage of the output unit is a source follower circuit Thus, the constant current source part of the source follower circuit is deleted.

In this specification, the description will be made using an example in which there is one horizontal CCD, but a plurality of horizontal CCDs may be provided.
The external output unit 2 is connected between the solid-state imaging device 1 and the signal processing unit 3, and performs conversion necessary for outputting the output of the solid-state imaging device 1 to the signal processing unit 3.
The signal processing unit 3 issues a driving instruction to the driving unit 4, processes the luminance signal output from the external output unit 2, and outputs image information to the outside.

The drive unit 4 drives the solid-state imaging device 1 based on a drive instruction from the signal processing unit 3.
FIG. 2 is a diagram showing a detailed circuit of the external output unit 2.
As shown in FIG. 2, the external output element 2 includes a current source unit 5 and a final stage buffer unit 6.
The current source unit 5 is an electric circuit corresponding to a constant current source unit included in the conventional solid-state imaging device, and as shown in FIG. 2, a resistor 7, a resistor 8, a grounded emitter transistor 9, a resistor 10, A source follower circuit is formed by a resistor 11 and a capacitor 12 together with the last stage circuit of the output unit in the solid-state imaging device 1.

The final stage buffer unit 6 is a buffer circuit that outputs image information by impedance conversion of output signals from the solid-state imaging device 1 and the current source unit 5, and includes a buffer transistor 13, a resistor 14, and a resistor 15.
Resistor 7 and resistor 8 form a resistance dividing circuit, and a predetermined constant voltage is divided by resistance and a divided voltage is output from the resistance dividing point. Here, the predetermined constant voltage is VDD = 12V, the resistor 7 is connected between VDD and the resistance dividing point and is 18 kΩ, and the resistor 8 is connected between the resistance dividing point and GND and is 8.2 kΩ. And

  The grounded emitter transistor 9 is an NPN transistor in which a divided voltage is applied to a base electrode, a collector electrode is connected to an output line of the solid-state imaging device 1, and an emitter electrode is grounded via a resistor 10. Here, a commercially available general NPN transistor can be used as the grounded-emitter transistor 9, but only a current of about 1 to 10 mA flows between the collector and the emitter of the grounded-emitter transistor 9. As for the rated current of the common emitter transistor 9, a maximum of about 20 mA is sufficient even when high frequency driving and a large capacity load are taken into consideration. Therefore, it is desirable to use a small transistor with excellent frequency characteristics such as a rated current of about 1 mA or more and 20 mA or less, and a small parasitic current between the base and the collector due to a small rated current. Moreover, since the rated current of a general transistor is 50 to 100 mA and is larger than necessary for this circuit, it is desirable to produce a small-scale transistor exclusively for this circuit.

The resistor 10 is 1.3 kΩ here. The resistor 11 is used for preventing oscillation, and is 100Ω here.
The grounded emitter transistor 9 has a parasitic capacitance between the base and the collector. Due to this, the output signal of the source follower wraps around the base and lowers the output gain of the source follower circuit. The capacitor 12 is connected between the resistance dividing point and GND, and suppresses voltage fluctuation of the base electrode depending on the signal frequency of the output signal of the solid-state imaging device 1.

  Since the capacitor 12 must have a high frequency characteristic corresponding to the signal frequency of the output signal of the solid-state imaging device 1, a tantalum capacitor or a multilayer ceramic capacitor having a relatively good high frequency characteristic is used. Since it is necessary to provide a sufficiently large capacitance with respect to the parasitic capacitance between the collectors, preferably 10 times or more, the capacitance is set to 0.001 μF here.

  The buffer transistor 13 is an NPN transistor in which the output signal of the solid-state imaging device 1 is applied to the base electrode via the resistor 14, the collector electrode is connected to a predetermined potential, and the emitter electrode is grounded via the resistor 15. Here, since only a current of about 1 to 10 mA flows between the collector and the emitter of the buffer transistor 13, a small transistor having a rated current of about 1 mA or more and about 20 mA or less is produced exclusively for this circuit like the grounded emitter transistor 9. It is desirable.

Although the resistor 14 is not always necessary, the resistor 14 can prevent oscillation or suppress overshoot and undershoot which are problems when the output signal of the CCD is increased in speed.
<Summary>
As described above, according to the imaging system of Embodiment 1 of the present invention, the current source of the source follower circuit at the last stage of the output unit is provided outside the solid-state imaging device including the light receiving device, so that the wafer thickness is 500 μm. It is possible to suppress degradation of the quality of the image information due to only the temperature of the light receiving element in the vicinity of the output unit, which occurs when the degree is about, and it has high frequency characteristics corresponding to the signal frequency of the output signal, By providing a capacitor with a sufficiently large capacitance to the parasitic capacitance between the base and collector of the NPN transistor in the source at the resistance division point, the voltage fluctuation of the base electrode depending on the signal frequency of the output signal is suppressed and output Gain can be improved.

When the output gain according to the configuration of the first embodiment of the present invention is compared with the case where the capacitor 12 is not provided, an improvement of about 5% in the actual measurement value is confirmed.
(Embodiment 2)
<Overview>
In the second embodiment of the present invention, the current source of the source follower circuit at the last stage of the output unit is connected to the light receiving element in order to suppress the deterioration of the quality of the image information due to only the temperature of the light receiving element in the vicinity of the output unit rising. In order to suppress the deterioration of output characteristics caused by the parasitic capacitance between the base and collector of the NPN transistor in the current source provided outside the solid-state imaging device An imaging system that suppresses voltage fluctuations of the base electrode by including a buffer circuit for lowering impedance in the current source.

<Configuration>
The imaging system according to the second embodiment is obtained by replacing the external output unit 2 of the imaging system according to the first embodiment with the external output unit 20, and the same components as those in the first embodiment are denoted by the same reference numerals. The description is omitted.
The imaging system according to the second embodiment includes a solid-state imaging device 1, an external output unit 20, a signal processing unit 3, and a driving unit 4.

The external output unit 20 is connected between the solid-state imaging device 1 and the signal processing unit 3, and performs conversion necessary for outputting the output of the solid-state imaging device 1 to the signal processing unit 3.
FIG. 3 is a diagram showing a detailed circuit of the external output unit 20.
As shown in FIG. 3, the external output unit 20 includes a current source unit 21 and a final stage buffer unit 6.

The current source unit 21 is an electric circuit corresponding to a constant current source unit included in the conventional solid-state imaging device. As shown in FIG. 3, a resistor 22, a resistor 23, a resistor 24, a buffer transistor 25, a resistor 26, a grounded emitter transistor 27, and a resistor 28. A source follower circuit is formed together with the last stage circuit of the output section in the solid-state imaging device 1.
The resistor 22, the resistor 23, and the resistor 24 form a resistance dividing circuit, and a predetermined constant voltage is divided by resistance and a divided voltage is output from the resistance dividing point. Note that the current value can be changed by grounding the current external setting terminal through grounding or an arbitrary resistor.

Here, a predetermined constant voltage is set to VDD = 12V, the resistor 22 is connected between VDD and the resistance dividing point, and is 18 kΩ, and the resistor 23 is connected between the resistance dividing point and the current external setting terminal to 4.1 kΩ. The resistor 24 is connected between the current external setting terminal and GND and is 8.2 kΩ.
In the buffer transistor 25, the divided voltage is applied to the base electrode, the collector electrode is connected to a predetermined constant voltage, the emitter electrode is connected to the base terminal of the grounded-emitter transistor 27, and is connected to GND via the resistor 26. The NPN transistor is a buffer circuit that lowers the output impedance of the resistance divider circuit in order to suppress degradation of output characteristics caused by parasitic capacitance between the base and collector of the transistor.

  The grounded emitter transistor 27 is an NPN transistor in which the emitter electrode of the buffer transistor 25 is connected to the base electrode, the collector electrode is connected to the output line of the solid-state imaging device 1, and the emitter electrode is grounded via the resistor 28. Here, it is desirable for the grounded-emitter transistor 27 to produce a small transistor with a rated current of about 1 mA or more and about 20 mA or less dedicated to this circuit, like the grounded emitter transistor 9.

Since the buffer transistor 25 has a current of only about 1 to 10 mA between the collector and the emitter, a small transistor having the same rated current as the grounded emitter transistor 27 of about 1 mA to 20 mA may be used.
Here, the resistor 26 is 4.7 kΩ and the resistor 28 is 1.3 kΩ.
<Summary>
As described above, according to the imaging system of the second embodiment of the present invention, the current source of the source follower circuit at the last stage of the output unit is provided outside the solid-state imaging device including the light receiving device, so that the wafer thickness is 500 μm. It is possible to suppress degradation of the quality of image information due to only the temperature of the light receiving element in the vicinity of the output, which occurs when the thickness is made thinner, and a buffer circuit that lowers the output impedance of the resistance divider circuit is provided as a current source. By including it, it is possible to suppress the voltage fluctuation of the base electrode depending on the signal frequency of the output signal and improve the output gain of the source follower circuit.
(Embodiment 3)
<Overview>
The third embodiment of the present invention is an imaging system in which the buffer transistor 25 included in the current source unit 21 of the second embodiment is changed from an NPN transistor to a PNP transistor in order to suppress characteristic variation due to temperature.

<Configuration>
The imaging system of the third embodiment is obtained by replacing the external output unit 20 of the imaging system of the second embodiment with an external output unit 30, and the same components as those of the second embodiment are denoted by the same numbers. The description is omitted.
The imaging system according to the third embodiment includes a solid-state imaging device 1, an external output unit 30, a signal processing unit 3, and a driving unit 4.

The external output unit 30 is connected between the solid-state imaging device 1 and the signal processing unit 3, and performs conversion necessary for outputting the output of the solid-state imaging device 1 to the signal processing unit 3.
FIG. 4 is a diagram illustrating a detailed circuit of the external output unit 30.
As shown in FIG. 4, the external output unit 30 includes a current source unit 31 and a final stage buffer unit 6.

The current source unit 31 is an electric circuit corresponding to a constant current source unit included in the conventional solid-state imaging device. As shown in FIG. 4, a resistor 34, a resistor 23, a resistor 24, a buffer transistor 32, a resistor 33, a grounded emitter transistor 27, and a resistor 28. A source follower circuit is formed together with the last stage circuit of the output section in the solid-state imaging device 1.
In the buffer transistor 32, the divided voltage is applied to the base electrode, the collector electrode is connected to GND, the emitter electrode is connected to the base terminal of the grounded-emitter transistor 27, and is connected to a predetermined constant voltage via the resistor 33. A PNP transistor is a buffer circuit that lowers the output impedance of the resistance divider circuit in order to suppress deterioration of output characteristics caused by parasitic capacitance between the base and collector of the transistor. Here, like the buffer transistor 25, the buffer transistor 32 may be a small transistor having a rated current of about 1 mA or more and 20 mA or less.

Here, the resistor 33 is 8.2 kΩ and the resistor 34 is 30 kΩ.
<Summary>
As described above, according to the imaging system of the third embodiment of the present invention, the buffer transistor included in the current source unit of the second embodiment is changed to the PNP transistor, so that all the same as in the second embodiment. Since the transistors are of the same type, it is disadvantageous in that it is easy to unify the production process and the production cost is reduced, but in other respects, there are the same effects as in the second embodiment, and further, the buffer transistor 32 and Since the change in the Vbe characteristic due to the temperature change of the grounded-emitter transistor 27 cancels out, there is an excellent effect that the characteristic change due to the temperature can be suppressed.
(Embodiment 4)
<Overview>
In the fourth embodiment of the present invention, the current source of the source follower circuit at the last stage of the output unit is connected to the light receiving element in order to suppress the deterioration of the quality of the image information due to only the temperature of the light receiving element in the vicinity of the output unit rising. In order to suppress deterioration of output characteristics caused by parasitic capacitance between the base and collector of the NPN transistor in the current source provided outside the solid-state imaging device Is an imaging system in which a current source is configured by a J-FET (junction field effect transistor) having a drain electrode connected to the output line of the solid-state imaging device, and the voltage fluctuation of the base electrode is suppressed.

<Configuration>
The imaging system according to the fourth embodiment is obtained by replacing the external output unit 2 of the imaging system according to the first embodiment with an external output unit 40. Components similar to those in the first embodiment are denoted by the same reference numerals, The description is omitted.
The imaging system according to the fourth embodiment includes a solid-state imaging device 1, an external output unit 40, a signal processing unit 3, and a driving unit 4.

The external output unit 40 is connected between the solid-state imaging device 1 and the signal processing unit 3, and performs conversion necessary for outputting the output of the solid-state imaging device 1 to the signal processing unit 3.
FIG. 5 is a diagram showing a detailed circuit of the external output unit 40.
As shown in FIG. 5, the external output unit 40 includes a current source unit 41 and a final stage buffer unit 6.

The current source unit 41 is an electric circuit corresponding to a constant current source unit included in the conventional solid-state imaging device, and includes a J-FET 42 and a source resistor 43 as shown in FIG. A source follower circuit is formed together with the last stage circuit of the output section in the element 1.
The J-FET 42 is a small signal junction FET in which a base electrode is grounded, a source electrode is grounded via a source resistor 44, and a drain electrode is connected to an output line of the solid-state imaging device 1. Here, as the J-FET 42, a commercially available general small-signal junction FET can be used. Since only a current of about 3 mA flows between the drain and source of the J-FET 42, for example, a small-signal junction FET having a drain current of about 3 mA is used.

In place of the small signal junction FET, an element and a circuit having characteristics equivalent to those of the small signal junction FET, such as a constant current diode, may be used.
Although the source resistor 43 is not necessarily required, the use of the source resistor has an advantage that a gate-source voltage is generated and variation in drain current can be suppressed. Here, it is assumed that the rated current of the J-FET 42 is set larger than the necessary current value, and a source resistance of the required current value is inserted between the gate and the source.

Here, the source resistance 43 is 160Ω.
FIG. 6 shows the drain-source voltage at each gate-source voltage Vgs (0 V, -0.1 V, -0.2 V, -0.3 V, -0.4 V) for a certain small signal junction FET (2SK1103). It is a figure which shows the relationship between Vds and the drain current Id.
As shown in FIG. 6, when the gate-source voltage Vgs is −0.4 V and the drain-source voltage Vds is 3 V or more, the drain current Id is almost constant, and the lower the potential difference between the gate and the source, the lower the potential. The drain current Id is saturated at the drain-source voltage Vds, and current variation between solids can be suppressed by the self-bias effect.

Further, by setting the source resistance 43 to an appropriate value, it is possible to suppress the characteristic variation due to temperature.
FIG. 7 is a diagram showing the relationship between the gate-source voltage Vgs and the drain current Id at each temperature Ta (−25 ° C., 25 ° C., 75 ° C.) for the small-signal junction FET (2SK1103).

As shown in FIG. 7, when the gate-source voltage Vgs = −0.45 V, the drain current is substantially constant at any temperature.
Therefore, if the source resistance 43 is set to such a value that the relationship between the gate-source voltage and the drain current is not affected by the temperature, the characteristic fluctuation due to the temperature can be suppressed.
For example, in the small-signal junction FET, the source resistance 43 is set so that the gate-source voltage Vgs = −0.45 V, and the characteristic variation due to temperature is suppressed.

<Summary>
As described above, according to the imaging system of the fourth embodiment of the present invention, the current source of the source follower circuit at the last stage of the output unit is provided outside the solid-state imaging device including the light receiving device, so that the wafer thickness is 500 μm. It is possible to suppress degradation of image quality caused by only the temperature of the light receiving element in the vicinity of the output portion that occurs when the thickness is made thinner than that, and for current setting by configuring a current source with a J-FET. Therefore, the number of parts can be reduced and the output gain of the source follower circuit can be improved.

In addition, by using a source resistance having an appropriate value, the drain current can be stabilized, variation between solids can be suppressed, and variation in characteristics due to temperature can be suppressed.
In each embodiment, an NPN transistor is used for the final stage buffer unit 6, but a PNP transistor may be used. In general, since the output response of the CCD greatly depends on the falling response characteristic, the use of a PNP transistor in the final stage buffer unit 6 increases the falling slew rate without increasing the emitter current more than necessary. Can do. Therefore, it is more advantageous in terms of response characteristics to use a PNP transistor for the final stage buffer unit 6 which is the output unit of the CCD.

  In each of the embodiments of the present invention, the application example of the output unit of the CCD has been described. However, the MOS type sensor including the CMOS sensor has the same output stage as the output unit of the CCD. If so, the same can be applied.

  The present invention can be applied to imaging devices such as home video cameras and digital still cameras. According to the present invention, when the wafer thickness of the solid-state image pickup device is reduced, the current source provided outside the solid-state image pickup device is prevented from deterioration of image quality due to only the temperature rise of the light receiving device near the output section. It is possible to provide a solid-state imaging device that suppresses the deterioration of output characteristics caused by the parasitic capacitance between the base and collector of the NPN transistor therein, and can contribute to improvement in performance such as image quality of the imaging device.

  Further, it can be applied not only to home use but also to any imaging device.

DESCRIPTION OF SYMBOLS 1 Solid-state image sensor 2 External output part 3 Signal processing part 4 Drive part 5 Current source part 6 Final stage buffer part 7 Resistor 8 Resistor 9 Common emitter transistor 10 Resistor 11 Resistor 12 Capacitor 13 Buffer transistor 14 Resistor 15 Resistor 20 External output part 21 Current source 22 Resistor 23 Resistor 24 Resistor 25 Buffer transistor 26 Resistor 27 Common emitter transistor 28 Resistor 30 External output unit 31 Current source unit 32 Buffer transistor 33 Resistor 34 Resistor 40 External output unit 41 Current source unit 42 J-FET
43 Source resistance

Claims (6)

A solid-state imaging device in which a plurality of light receiving elements are arranged;
At least one output circuit;
An image pickup apparatus comprising: a buffer circuit that outputs an image information by impedance-converting an output signal at a last stage of the output circuit, processes a luminance signal output from the plurality of light receiving elements, and outputs the image information In
The last stage of the output circuit is a source follower circuit,
A current source of the source follower circuit is provided outside the first semiconductor substrate on which the plurality of light receiving elements are formed;
The current source is
A resistance dividing circuit that divides a constant voltage by resistance and outputs a divided voltage from a resistance dividing point;
A grounded-emitter transistor in which the divided voltage is applied to a base electrode, and a collector electrode is connected to an output line of the solid-state imaging device;
A capacitor connected between the resistance dividing point and GND and suppressing voltage fluctuation of the base electrode depending on a signal frequency of an output signal of the solid-state imaging device;
The capacitor has a capacitance of 10 times or more with respect to a parasitic capacitance between a base and a collector in the grounded-emitter transistor,
The imaging device, wherein the first semiconductor substrate has a thickness of less than 500 μm. The capacitor is
The imaging device according to claim 1, wherein the imaging device is a tantalum capacitor or a multilayer ceramic capacitor. The imaging apparatus according to claim 1, wherein a resistor for preventing oscillation is connected to an input of the buffer circuit. The grounded emitter transistor is:
The rated current is 1 mA or more and 20 mA or less. The imaging apparatus according to any one of claims 1 to 3.   The imaging apparatus according to claim 1, wherein the output circuit is an output unit of a CCD.   The imaging apparatus according to claim 1, wherein the output circuit is an output unit of a MOS sensor.

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