JP2010199459A - Method of manufacturing transistor element - Google Patents

Abstract

PROBLEM TO BE SOLVED To suppress the generation of parasitic capacitance by accurately aligning a source / drain electrode with respect to a gate electrode.
SOLUTION: A gate electrode 320 made of metal is formed on a transparent glass substrate 310, a transparent gate insulating layer 330 is formed thereon, and further made of ITO which is a source of source / drain electrodes 350 and 360. A conductive layer is formed, and its upper surface is covered with a negative resist layer. A mask having a light-transmitting property in a predetermined region including the source / drain formation region is disposed on the lower surface side of the substrate. Light is irradiated from below, and back exposure is performed so that the shadow generated by the light shielding region of the mask and the shadow generated by the gate electrode 320 become a non-exposed region of the resist layer, and patterned to form the source electrode 350 and the drain electrode 360. Form. An oxide semiconductor channel layer 340 made of InGaZnO ₄ is directly formed thereon, and a good ohmic contact is obtained while omitting the high-concentration impurity diffusion layer.
[Selection] Figure 5

Description

  The present invention relates to a method for manufacturing a transistor element, and more particularly to a technique for manufacturing an “inverted staggered” type thin film transistor element.

  A thin film transistor is a kind of field effect transistor that controls a current flowing between a source and a drain through a semiconductor channel layer by a voltage applied to a gate electrode, and is widely used as a driving element of a liquid crystal display. In the future, it is expected to be used for electronic paper and RFID tags.

  Various types of thin film transistors are known. For example, in Patent Document 1 below, a so-called “staggered type” thin film transistor in which a source electrode and a drain electrode are formed on a substrate. A manufacturing method of a so-called “inverted staggered type” thin film transistor in which a gate electrode is formed on a substrate is disclosed in Patent Document 2. In addition, as a semiconductor channel layer (semiconductor active layer) constituting a thin film transistor, silicon-based semiconductors such as amorphous silicon and polysilicon have been used for a long time, but recently, organic semiconductors and oxide semiconductors have been used. An example has also been proposed. For example, Patent Document 3 below discloses a field effect transistor using an oxide semiconductor containing ZnO as a semiconductor channel layer.

Japanese Patent Laid-Open No. 10-189977 Japanese Patent Laid-Open No. 9-90426 JP 2004-103957 A

  As described above, in the thin film transistor, the current between the source and drain electrodes is controlled by the voltage applied to the gate electrode. Here, in the case of an “inverted staggered” type thin film transistor, the source electrode and the drain electrode are arranged above the gate electrode. At this time, a part of the source electrode / gate electrode or the drain electrode If a part of the gate electrode overlaps in the vertical direction, a parasitic capacitance is generated between the electrodes arranged above and below. Such parasitic capacitance is not preferable because it causes the operation of the transistor to become unstable and also causes the operation speed to be delayed.

  In order to eliminate such parasitic capacitance, it is necessary to adopt a structure that eliminates the vertical overlap between the source electrode and the gate electrode and the vertical overlap between the drain electrode and the gate electrode. However, it is difficult for the conventional general manufacturing method to accurately align the source / drain electrodes with respect to the gate electrode. In a conventional manufacturing process, a photomask for forming a gate electrode and a photomask for forming a source / drain electrode are separately prepared, and patterning is performed in separate steps. Of course, if the alignment of the photomask can be performed accurately, it is possible to ensure sufficient alignment between the formation position of the source / drain electrodes and the formation position of the gate electrode. An error is inevitable in aligning the photomask. For this reason, the conventional manufacturing method has a problem that the generation of the parasitic capacitance described above cannot be avoided.

  Accordingly, an object of the present invention is to provide a method of manufacturing a transistor element that can accurately align a source / drain electrode with respect to a gate electrode and can suppress generation of parasitic capacitance. .

(1) According to a first aspect of the present invention, a transistor element that controls a current flowing between a source and a drain through a semiconductor channel layer by a voltage applied to a gate electrode is sensitive to light in a predetermined photosensitive wavelength region. In a method of manufacturing by a process including a patterning process for forming a source / drain electrode using a resist having a property,
A first stage in which at least an upper surface has an insulating property and a substrate made of a material transparent with respect to light in the photosensitive wavelength range is prepared;
A second step of forming a gate electrode layer made of a conductive material opaque to light in the photosensitive wavelength region on the substrate;
A gate insulating layer made of an insulating material transparent to light in the photosensitive wavelength range is formed on the substrate including the gate electrode layer, and a conductive material made of a conductive material transparent to light in the photosensitive wavelength range is formed on the upper surface. A third stage of forming a layer;
A negative resist layer having photosensitivity to light in the photosensitive wavelength region is formed on the upper surface of the conductive layer, and a source / transparent region partially overlapping the gate electrode layer when observed from above A photomask for forming the drain electrode is disposed below the substrate, and the light of the above-mentioned photosensitive wavelength region is irradiated from the lower side of the substrate, and the shadow generated by the light shielding region of the photomask and the shadow generated by the gate electrode layer are negative. Back exposure is performed so as to be a non-exposed region on the resist layer, patterning is performed to remove a portion corresponding to the non-exposed region of the conductive layer, and the conductive layer is disposed between each other via a gap portion by the remaining portion. Forming a source electrode layer and a drain electrode layer,
A fifth step of forming a semiconductor channel layer made of a complex oxide of indium, gallium, and zinc and disposed in the gap so as to straddle part of the source electrode layer and part of the drain electrode layer;
Is to do.

(2) According to a second aspect of the present invention, a transistor element that controls a current flowing between a source and a drain through a semiconductor channel layer by a voltage applied to a gate electrode is sensitive to light in a predetermined photosensitive wavelength range. In a method of manufacturing by a process including a patterning process for forming a source / drain electrode using a resist having a property,
A first stage in which at least an upper surface has an insulating property and a substrate made of a material transparent with respect to light in the photosensitive wavelength range is prepared;
A second step of forming a gate electrode layer made of a conductive material opaque to light in the photosensitive wavelength region on the substrate;
A gate insulating layer made of an insulating material transparent to light in the photosensitive wavelength range is formed on the substrate including the gate electrode layer, and a conductive material made of a conductive material transparent to light in the photosensitive wavelength range is formed on the upper surface. A third stage of forming a layer;
This conductive layer is patterned using a photomask for forming source / drain electrodes, and is arranged so as to straddle the gate electrode layer when observed from above, and partially overlaps the gate electrode layer A fourth step of forming a source / drain electrode preparation layer forming a region;
A negative resist layer having photosensitivity to light in the photosensitive wavelength region is formed on the upper surface of the source / drain electrode preparation layer, and light in the photosensitive wavelength region is irradiated from the lower side of the substrate. Back exposure is performed so that the generated shadow becomes a non-exposed region on the negative resist layer, patterning is performed to remove a portion corresponding to the non-exposed region of the source / drain electrode preparation layer, and the source / drain electrode preparation layer is formed. A fifth step of forming a source electrode layer and a drain electrode layer disposed with a gap between them by the remaining portion;
A sixth step of forming a semiconductor channel layer made of a complex oxide of indium, gallium, and zinc and disposed in the gap so as to straddle part of the source electrode layer and part of the drain electrode layer;
Is to do.

(3) According to a third aspect of the present invention, a transistor element that controls a current flowing between a source and a drain through a semiconductor channel layer by a voltage applied to a gate electrode is sensitive to light in a predetermined photosensitive wavelength region. In a method of manufacturing by a process including a patterning process for forming a source / drain electrode using a resist having a property,
A first stage in which at least an upper surface has an insulating property and a substrate made of a material transparent with respect to light in the photosensitive wavelength range is prepared;
A second step of forming a gate electrode layer made of a conductive material opaque to light in the photosensitive wavelength region on the substrate;
A gate insulating layer made of an insulating material transparent to light in the photosensitive wavelength range is formed on the substrate including the gate electrode layer, and a conductive material made of a conductive material transparent to light in the photosensitive wavelength range is formed on the upper surface. A third stage of forming a layer;
On the upper surface of this conductive layer, a negative resist layer having photosensitivity to light in the photosensitive wavelength range is formed, and the shadow generated by the gate electrode layer is irradiated with light in the photosensitive wavelength range from the lower side of the substrate. Back exposure is performed to form a non-exposed region on the negative resist layer, patterning is performed to remove a portion corresponding to the non-exposed region of the conductive layer, and a source / drain electrode preparation layer is formed by the remaining portion of the conductive layer And a fourth stage
Using a photomask for forming a source / drain electrode having a pattern of a closed region that straddles the gate electrode layer when observed from above, a portion corresponding to the closed region is formed on the source / drain electrode preparation layer. A fifth step of performing patterning to be left, and forming a source electrode layer and a drain electrode layer disposed with a gap between them by a remaining portion of the source / drain electrode preparation layer;
A sixth step of forming a semiconductor channel layer made of a complex oxide of indium, gallium, and zinc and disposed in the gap so as to straddle part of the source electrode layer and part of the drain electrode layer;
Is to do.

(4) According to a fourth aspect of the present invention, in the method of manufacturing a transistor element according to the first to third aspects described above,
In the first stage, a substrate made of glass or synthetic resin is prepared,
In the second stage, a metal is used as a material for forming the gate electrode layer.

(5) According to a fifth aspect of the present invention, in the method for manufacturing a transistor element according to the first to fourth aspects described above,
In the third stage, silicon oxide or silicon nitride is used as a material for forming the gate insulating layer.

(6) According to a sixth aspect of the present invention, in the method for manufacturing a transistor element according to the first to fifth aspects described above,
In the third stage, ITO or IZO is used as a material for forming the conductive layer.

  In the method for manufacturing a transistor element according to the present invention, since the semiconductor channel layer is made of a semiconductor made of a composite oxide of indium, gallium, and zinc, high-concentration impurities are formed between the source and drain electrodes and the semiconductor channel layer. There is no need to provide a diffusion layer. In addition, an opaque conductive material is used for the gate electrode layer and a transparent material is used for each of the other layers. When performing the patterning process for forming the source electrode layer and the drain electrode layer, the gate electrode layer is a part of the photomask. Since the back exposure is performed as a part, it is possible to form a source electrode layer and a drain electrode layer having self-alignment with the gate electrode layer. As a result, the source / drain electrodes can be accurately aligned with respect to the gate electrode, and the generation of parasitic capacitance can be suppressed.

It is a sectional side view showing the basic structure of a thin film transistor element of “inverted staggered top contact type”. It is a sectional side view showing the basic structure of a thin film transistor element of “inverted staggered / bottom contact type”. FIG. 3 is a side sectional view showing a cause of parasitic capacitance in the thin film transistor element shown in FIG. 2. FIG. 4 is a top view of the thin film transistor element shown in FIG. 3. It is a sectional side view which shows the basic structure of the "inverted staggered bottom contact type" thin-film transistor element produced with the manufacturing method which concerns on this invention. FIG. 6 is a top view of the thin film transistor element shown in FIG. 5. It is a sectional side view showing the process of the 1st stage-the 3rd stage of the manufacturing method concerning the present invention. It is a top view of the 1st photomask M1 used for the manufacturing method which concerns on this invention. It is a sectional side view which shows the front | former stage process of the 4th step of the manufacturing method which concerns on this invention. It is a top view of the 2nd photomask M2 used for the manufacturing method concerning the present invention. It is a sectional side view which shows the middle stage process of the 4th step of the manufacturing method which concerns on this invention. In the manufacturing method which concerns on this invention, it is a top view of the gate electrode layer which functions as a photomask M1 ^* . FIG. 13 is a plan view of a photomask obtained by synthesizing the photomask M1 ^* shown in FIG. 12 and the photomask M2 shown in FIG. It is a sectional side view showing the latter process of the 4th step of the manufacturing method concerning the present invention. It is a sectional side view showing the process of the 5th step of the manufacturing method concerning the present invention. It is a top view of the 3rd photomask M3 used for the manufacturing method concerning the present invention. A second photomask M2 ^* plan view of a used in another embodiment of the manufacturing method according to the present invention. In another embodiment of the manufacturing method concerning this invention, it is a sectional side view which shows the 1st process which forms a source electrode layer and a drain electrode layer. In another embodiment of the manufacturing method concerning this invention, it is a sectional side view which shows the 2nd process of forming a source electrode layer and a drain electrode layer.

  Hereinafter, the present invention will be described based on the illustrated embodiments.

<<< §1. General thin film transistor structure >>
As described above, the thin film transistor is a field effect transistor that controls the current flowing between the source and the drain through the semiconductor channel layer (semiconductor active layer) by the voltage applied to the gate electrode.

  FIG. 1 is a side sectional view showing a basic structure of a thin film transistor element 100 called an “inverted staggered type”. In general, in the case of a “staggered type” thin film transistor element, a source electrode layer and a drain electrode layer are formed on a substrate, and a semiconductor channel layer, a gate insulating layer, and a gate electrode layer are sequentially stacked thereon. In the case of an “inverted staggered” type thin film transistor element, a gate electrode layer is formed on a substrate, and a gate insulating layer, a source electrode layer, a drain electrode layer, A structure in which semiconductor channel layers are sequentially stacked is adopted.

  The example shown in FIG. 1 is an example of an “inverted staggered” thin film transistor element that is most popular at present. As illustrated, a gate electrode layer 120 is formed on a substrate 110 made of an insulating material such as glass or synthetic resin, and a gate insulating layer 130 is formed thereon. A semiconductor channel layer 140 that functions as an active layer is formed on the gate insulating layer 130, and a source electrode layer 150 and a drain electrode layer 160 are further formed. Note that high-concentration impurity diffusion layers 141 and 142 are provided at the interface between the semiconductor channel layer 140, the source electrode layer 150, and the drain electrode layer 160. This is because the source / drain electrodes and the semiconductor active layer are separated from each other. This is to ensure good ohmic contact therebetween.

  In the thin film transistor element 100 having such a structure, when a voltage is applied between the source electrode layer 150 and the drain electrode layer 160, a current can flow through the semiconductor channel layer 140, and the amount of current flows to the gate electrode layer 120. It can be controlled by the applied voltage.

  On the other hand, FIG. 2 shows an example of an “inverted staggered” thin film transistor element 200 adopting another structure. In the case of this thin film transistor element 200 as well, the gate electrode layer 220 is formed on the substrate 210 made of an insulating material such as glass or synthetic resin, and the gate insulating layer 230 is formed thereon as shown in FIG. This is exactly the same as the thin film transistor element 100 shown. However, a source electrode layer 250 and a drain electrode layer 260 are first formed on the gate insulating layer 230, and a semiconductor channel layer 240 functioning as an active layer is formed thereon. Again, high-concentration impurity diffusion layers 241 and 242 are provided at the interfaces between the semiconductor channel layer 240, the source electrode layer 250, and the drain electrode layer 260, and good ohmic contact is provided between the source / drain electrodes and the semiconductor active layer. The structure to secure is adopted.

  In the thin film transistor element 100 shown in FIG. 1, ohmic contact portions (formation portions of the high concentration impurity diffusion layers 141 and 142) between the source / drain electrode layers 150 and 160 and the semiconductor channel layer 140 are formed on the upper surface of the semiconductor channel layer 140. Therefore, it is generally called “top contact type”. On the other hand, the thin film transistor element 200 shown in FIG. 2 has an ohmic contact portion (a portion where the high-concentration impurity diffusion layers 241 and 242 are formed) between the source / drain electrode layers 250 and 260 and the semiconductor channel layer 240. Since it is formed on the lower surface of 240, it is generally called “bottom contact type”.

  In the “bottom contact type” shown in FIG. 2, a step of forming the high concentration impurity diffusion layers 241 and 242 on the lower surface of the semiconductor channel layer 240 is required. For this reason, the manufacturing process must be more complicated than the “top contact type” shown in FIG. Therefore, at present, the “top contact type” shown in FIG. 1 is the mainstream as commercial mass-produced products.

  The gate electrode layers 120 and 220, the source electrode layers 150 and 250, and the drain electrode layers 160 and 260 may be made of any material as long as it is a conductive material having good conductivity. Usually, a metal such as aluminum, molybdenum, tungsten, or titanium is often used as each electrode layer, but an oxide conductive material such as ITO may be used as the electrode layer. On the other hand, the gate insulating layers 130 and 230 may be made of any material as long as it is an insulating material, but a silicon compound such as silicon oxide or silicon nitride is often used.

Further, silicon semiconductors such as amorphous silicon and polysilicon are usually used as the semiconductor channel layers 140 and 240, and the high-concentration impurity diffusion layers 141, 142, 241, and 242 are made of these silicon semiconductors. An n ⁺ diffusion layer in which an n-type impurity is implanted is used. In order to ensure good ohmic contact between the source electrode layers 150, 250 and the drain electrode layers 160, 260 made of metal, ITO, etc. and the semiconductor channel layers 140, 240 made of silicon-based semiconductor, practically n High-concentration impurity diffusion layers 141, 142, 241, and 242 made of a ⁺ diffusion layer are indispensable.

<<< §2. Cause of parasitic capacitance >>>
As described above, in the thin film transistor, when a part of the source electrode / gate electrode or a part of the drain electrode / gate electrode overlaps in the vertical direction, a parasitic capacitance is generated between the vertically arranged electrodes. Such parasitic capacitance is not preferable because it causes the operation of the transistor to become unstable and also causes the operation speed to be delayed.

  FIG. 3 is a side sectional view showing the cause of parasitic capacitance in the “reverse staggered / bottom contact type” thin film transistor element 200 shown in FIG. 2, and FIG. 4 is a top view thereof. The side sectional view of FIG. 3 shows a section obtained by cutting the thin film transistor element 200 shown in FIG. 4 at the position of the cutting line 3-3.

  As shown in FIG. 3, a gate insulating layer 230 is formed above the gate electrode layer 220, and a source electrode layer 250 and a drain electrode layer 260 are formed on the upper surface thereof. Further thereon, a silicon-based semiconductor channel layer 240 is arranged via high-concentration impurity diffusion layers 241 and 242. As described above, the high concentration impurity diffusion layers 241 and 242 serve to ensure good ohmic contact with the semiconductor channel layer 240.

  In the case of the example shown here, the gate electrode layer 220 extends to the upper and lower ends of the substrate 210 as shown in the top view of FIG. This is because the structure is continuous with the gate electrode layer (not shown). Further, the source electrode layer 250 extends to the left end of the substrate 210, and the drain electrode layer 260 extends to the right end of the substrate 210. This is because a structure connected to a wiring layer (not shown) is employed. Here, for convenience of explanation, only the structure of a single thin film transistor element is shown, but in practice, a large number of thin film transistor elements are arranged in a matrix form on a single substrate, and if necessary, Specific electrode layers of the individual transistor elements are connected to each other. Of course, actually, in addition to the components shown in the figure, wirings for individual electrode layers, protective films covering the individual electrode layers, and the like are formed, but the description thereof is omitted here.

  3 and 4, the contour reference line L1 indicates the inner contour position of the source electrode layer 250 (right end in the figure), and the contour reference line L2 indicates the inner contour position of the drain electrode layer 260 (left end in the figure). ing. On the other hand, the contour reference line L3 indicates the left contour position of the gate electrode layer 220, and the contour reference line L4 indicates the right contour position of the gate electrode layer 220. As shown in the figure, the contour reference line L1 is located on the right side of the contour reference line L3, and the contour reference line L2 is located on the left side of the contour reference line L4. Therefore, the top view of FIG. 4 is hatched. , Overlapping regions D1 and D2 where the electrodes overlap vertically are generated. In other words, the width of the gate electrode layer 220 protrudes from the contour reference lines L1 and L2 of the source / drain electrodes.

  In this way, if the design is made on the assumption that the overlapping regions D1 and D2 are generated in advance, the alignment of the photomask is incomplete, so the source electrode layer 250 and the drain electrode layer 260 with respect to the substrate 210 are not aligned. Even if the position shifts or the position of the gate electrode layer 220 with respect to the substrate 210 shifts, the gate electrode layer is sufficiently positioned to cover the region where the source-drain current is generated in the semiconductor channel layer 240. 220 can be arranged.

  However, if the design is made on the assumption that the overlapping regions D1 and D2 are generated in this way, the generation of parasitic capacitance between the two electrodes is inevitable. That is, the source electrode layer 250 and the gate electrode layer 220 are vertically overlapped in an overlapping region D1 shown by hatching in FIG. 4, and the drain electrode layer 260 and the gate electrode layer 220 are hatched in FIG. In the overlapping region D2 shown in FIG. For this reason, parasitic capacitance is generated in the overlapping regions D1 and D2, which causes the operation of the transistor to become unstable, and also causes the operation speed to be delayed.

  Therefore, if an ideal structure that does not cause parasitic capacitance is adopted, the position of the contour reference line L1 is made to coincide with the position of the contour reference line L3, and the position of the contour reference line L2 is made to coincide with the position of the contour reference line L4. It is preferable to design such that the overlapping regions D1 and D2 do not occur. However, it is very difficult to manufacture a thin film transistor device based on such a design by the conventional method. In the conventional manufacturing process, a photomask for forming the gate electrode layer 220 and a photomask for forming the source electrode layer 250 and the drain electrode layer 260 are separately prepared, and patterning is performed in separate processes. Is called. For this reason, in order to manufacture an element having the above-described ideal structure, it is necessary to accurately align the two photomasks. However, it is technically difficult to perform such accurate alignment in a mass-produced process. For this reason, in the conventional method, as illustrated in FIG. 3, it is necessary to design in consideration of the alignment error in advance, and generation of parasitic capacitance cannot be sufficiently suppressed.

<<< §3. Basic concept of manufacturing method according to the present invention >>
The first point of view of the present invention is to realize an ideal structure capable of suppressing parasitic capacitance by forming the source electrode and the drain electrode by patterning using back exposure from the lower surface side of the substrate. The second point of view of the present invention is that the semiconductor channel layer is made of a complex oxide of indium, gallium, and zinc, so that high-concentration impurity diffusion can be achieved between the source and drain electrodes and the semiconductor channel layer. It is the point which ensures a favorable ohmic contact, without providing a layer.

  FIG. 5 is a side sectional view showing a basic structure of a “reverse staggered / bottom contact type” thin film transistor element 300 produced by the manufacturing method according to the present invention, and FIG. 6 is a top view thereof. The side sectional view of FIG. 5 shows a cross section of the thin film transistor element 300 shown in FIG. 6 taken along the line 5-5.

  As shown in FIG. 5, a thin film transistor element 300 according to the present invention includes a gate electrode layer 320 formed on a substrate 310 made of an insulating material such as glass or synthetic resin, and a gate insulating layer 330 formed thereon. Yes. Further, a source electrode layer 350 and a drain electrode layer 360 are first formed on the gate insulating layer 330, and a semiconductor channel layer 340 functioning as an active layer is formed thereon. However, the semiconductor channel layer 340, the source electrode layer 350, and the drain electrode layer 360 are in direct contact with each other, and the high-concentration impurity diffusion layer provided in the conventional thin film transistor element 200 shown in FIG. Reference numerals 241 and 242 are omitted. The reason will be described later.

  Another difference from the structure of the thin film transistor element 200 shown in FIG. 3 is the positional relationship between the contour of the gate electrode layer and the contour of the source / drain electrode layer. That is, in the thin film transistor element 300 illustrated in FIG. 5, it can be seen that the contour reference lines L5 and L6 of the source electrode layer 350 and the drain electrode layer 360 coincide with the contour reference lines L5 and L6 of the gate electrode layer 320. Therefore, vertical overlap between the source electrode layer 350 and the gate electrode layer 320 and vertical overlap between the drain electrode layer 360 and the gate electrode layer 320 do not occur, and generation of parasitic capacitance can be suppressed. It becomes possible.

  Comparing the top view of FIG. 4 with the top view of FIG. 6, it can be seen that the overlapping regions D1 and D2 that occur in the conventional thin film transistor element 200 do not occur in the thin film transistor element 300 of the present invention. Thus, in order to accurately match the contour positions of the electrode layers, in the present invention, the source electrode layer 350 and the drain electrode layer 360 are formed by patterning using the gate electrode layer 320 itself as a mask.

  In FIG. 5, let us consider a case where the substrate 310, the gate insulating layer 330, the source electrode layer 350, and the drain electrode layer 360 are made of a transparent material, and the gate electrode layer 320 is made of an opaque material. In the present application, “transparent” or “opaque” means transparency or opaqueness to light in the photosensitive wavelength region of a negative resist used for forming a source electrode and a drain electrode, as will be described later. Hereinafter, it is simply referred to as “transparent” or “opaque”.

  Here, a negative resist layer is used to form the source electrode layer 350 and the drain electrode layer 360. When back exposure is performed from the lower surface side of the substrate 310, an opaque gate electrode is formed on the negative resist layer. The shadow of the layer 320 falls, and patterning using the gate electrode layer 320 itself as a light shielding region of the photomask becomes possible. Therefore, no alignment error occurs between the gate electrode layer 320 and the formed source electrode layer 350 and drain electrode layer 360, and the generation of parasitic capacitance is suppressed as in the example shown in FIG. An ideal structure can be obtained.

  Here, as the transparent substrate 310, a general substrate made of a material such as glass or synthetic resin may be used. For the transparent gate insulating layer 330, a general insulating material such as a silicon oxide film or a silicon nitride film may be used. Alternatively, aluminum oxide or the like can be used as a transparent insulating material. Furthermore, oxide conductive materials such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide) are known as transparent conductive materials for forming the source electrode layer 350 and the drain electrode layer 360. On the other hand, as a conductive material used for the opaque gate electrode layer 320, a general metal such as aluminum, molybdenum, tungsten, or titanium can be used.

  As described above, one of the important features of the present invention is the material used for the semiconductor channel layer 340. In the case of a general thin film transistor, a silicon-based semiconductor such as amorphous silicon or polysilicon is used as the semiconductor channel layer. When the semiconductor channel layer is formed using such a silicon-based semiconductor, the source is In order to ensure good ohmic contact with the drain electrode, it is essential to interpose a high concentration impurity diffusion layer.

Therefore, the inventors of the present application focused on an oxide called InGaZnO ₄ (Indium Gallium Zinc Oxide). This InGaZnO ₄ is a kind of oxide semiconductor, and its characteristics as a semiconductor are, for example, “Kenji Nomura et al. Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors. Nature 432, 488-491 ( 2004). ".

According to an experiment conducted by the present inventor, when this InGaZnO ₄ is used as a semiconductor channel layer, even when a structure in which the source electrode layer and the drain electrode layer are in direct contact with the semiconductor channel layer is adopted, there is practical use between the two. It was confirmed that sufficient ohmic contact could be secured. When a conventional general semiconductor material (mainly silicon-based semiconductor material such as amorphous silicon or polysilicon) is used as a semiconductor channel layer, in order to ensure good ohmic contact with the source / drain electrode layer, In practice, it is indispensable to interpose a high-concentration impurity diffusion layer composed of an n ⁺ diffusion layer or the like, but in the case of a thin film transistor using InGaZnO ₄ as a semiconductor channel layer, the interposition of such a high-concentration impurity diffusion layer is necessary. Even if the insertion was omitted, it was confirmed that good ohmic contact was obtained between the source / drain electrode layer and the semiconductor channel layer.

Such good ohmic contact characteristics can be seen not only in the composition “InGaZnO ₄ ” but also in the composition that is a variation thereof. In general, a composite oxide of indium, gallium, and zinc (Indium Gallium Zinc Oxide) includes an indium oxide “In ₂ O ₃ ”, a gallium oxide “Ga ₂ O ₃ ”, and a zinc oxide “ZnO”. If the ratio of the number of molecules of In, Ga, and Zn is x: y: z (x, y, z are arbitrary positive numbers), the basic composition is , “(In ₂ O ₃ ) _{x / 2} (Ga ₂ O ₃ ) _{y / 2} (ZnO) _z ”. If this is expressed by a composition formula indicating the number of each molecule, it becomes “(In) x (Ga) y (Zn) z (O) w”, and the molecular number w of oxygen is “w = (3/2). ) X + (3/2) y + z ". In addition, an oxygen deficiency is generated, that is, “(In) x (Ga) y (Zn) z (O) w” (where w = (3/2) x + (3/2) y + z−δ). Even in such a composition (δ is the number of deficient oxygen), the above ohmic characteristics are exhibited.

In the present invention, “indium / gallium / zinc composite oxide” means indium oxide “In ₂ O ₃ ”, gallium oxide “Ga ₂ O ₃ ”, zinc oxide “ It means a material including a mixture with “ZnO” and a material in which oxygen vacancies are generated, and will be abbreviated as “IGZO” hereinafter.

  The inventor of the present application conducted an experiment on a case where a metal material such as aluminum, molybdenum, tungsten, or titanium, or an oxide conductive material such as ITO or IZO was used as the source / drain electrode layer. When IGZO was used for the semiconductor channel layer, good ohmic contact was obtained. Although the theoretical consideration about the cause has not been made sufficiently at the present stage, when the IGZO is used for the semiconductor channel layer, the inventor of the present application has electrons as the carriers in the semiconductor, and the holes are not. I think that it is influenced by having little involvement as a career.

  When the semiconductor channel layer 340 made of IGZO is formed in this way, a source / drain made of a general conductive material such as a metal material such as aluminum, molybdenum, tungsten, or titanium, or an oxide conductive material such as ITO or IZO. Even if a structure in which the electrode layer is brought into direct contact is obtained, it is possible to ensure good ohmic contact.

  Therefore, if IGZO is used as a material for the semiconductor channel layer 340, a thin film transistor 300 having a simple structure as shown in FIG. 5 can be realized. In the thin film transistor 300 according to the present invention shown in FIG. 5, the formation process of the high concentration impurity diffusion layer required in the conventional thin film transistor 200 as shown in FIG. 3 can be omitted, and thus the manufacturing process is simplified. Is possible.

<<< §4. Basic Embodiment of Manufacturing Method According to the Present Invention >>
Here, a basic embodiment of a method for manufacturing a thin film transistor according to the present invention will be described. First, as shown in FIG. 7A, a substrate 310 made of a transparent material having at least an insulating surface is prepared (generally, if an insulating substrate such as glass or synthetic resin is prepared). A non-transparent first conductive layer 325 is formed thereon. The first conductive layer 325 is for forming the gate electrode layer 320, and may be made of a metal material such as aluminum, molybdenum, tungsten, or titanium.

  Subsequently, a first photomask M1 having a pattern as shown in FIG. 8 is prepared. The first photomask M1 is a mask used for forming the gate electrode layer 320, and the hatched portion serves as a light shielding region, and the illustrated light transmitting region A1 corresponds to the gate electrode layer 320. become. As will be described later, the gate electrode layer 320 itself formed by patterning using the first photomask M1 is now used as a mask for patterning the source electrode layer and the drain electrode layer. . That is, the left and right contour reference lines L5 and L6 of the translucent area A1 of the first photomask M1 shown in FIG. 8 correspond to the contour reference lines L5 and L6 shown in FIG.

  If patterning using the first photomask M1 is performed on the first conductive layer 325 shown in FIG. 7A, a gate electrode layer 320 is formed as shown in FIG. 7B. Can do. More specifically, a negative photosensitive resist layer (not shown) is formed on the upper surface of the first conductive layer 325 shown in FIG. 7A, and the first photosensitive layer shown in FIG. The photomask M1 is disposed, and light is further irradiated from a light source disposed above the photomask M1, and only the region corresponding to the translucent region A1 in the resist layer is exposed and exposed.

  Thereafter, by developing the resist layer and removing the non-photosensitive portion, the resist layer can be left only in the region corresponding to the light-transmitting region A1. Of course, it is possible to perform the same process using a positive photosensitive resist (in this case, an inversion mask reverse to the pattern of the first photomask M1 shown in FIG. 8 is used). . Next, when the remaining conductive layer is used as a protective film and the first conductive layer 325 is etched, the gate electrode layer 320 can be formed. Thereafter, if the remaining resist layer is removed and washed, the structure shown in FIG. 7B can be obtained.

  Subsequently, as shown in FIG. 7C, a gate insulating layer 330 made of a transparent insulating material is formed on the substrate 310 including the gate electrode layer 320, and a transparent conductive material is formed on the upper surface thereof. A second conductive layer 370 made of a material is formed. Specifically, as the material of the gate insulating layer 330, for example, silicon oxide or silicon nitride can be used, and as the material of the second conductive layer 370, for example, ITO or IZO can be used.

  Next, as shown in FIG. 9, a negative resist layer 380 is formed on the upper surface of the second conductive layer 370. In order to expose the negative resist layer 380, a second photomask M2 having a pattern as shown in FIG. 10 is prepared. The second photomask M2 is a physical mask in which a light-transmitting region A2 for forming a source / drain electrode is formed between shaded regions shown by hatching. The light-transmitting region A2 is a light-transmitting region that partially overlaps the gate electrode layer 320 when observed from above. As described above, the planar pattern of the gate electrode layer 320 has the same shape as the light-transmitting region A1 of the first mask M1 shown in FIG. The translucent region A2 of the second mask M2 shown in FIG. 10 has an elongated shape that crosses the planar pattern of the gate electrode layer 320 at the central portion. As will be described later, the left portion of the translucent region A2 forms a planar pattern of the source electrode layer 350, and the right portion plays a role of forming a planar pattern of the drain electrode layer 360.

Next, as shown in FIG. 11, the second photomask M2 is disposed below the substrate 310, and light in the photosensitive wavelength region of the negative resist layer 380 is irradiated from the lower side of the substrate, so that the second photomask Back exposure is performed such that the shadow generated by the light shielding region of M2 and the shadow generated by the gate electrode layer 320 become a non-exposed region on the negative resist layer 380. In such back exposure, the opaque gate electrode layer 320 functions as a photomask M1 ^* as shown in FIG. This photomask M1 ^* is obtained by inverting the photomask M1 shown in FIG. 8, and is provided with translucent areas A3 and A4 on both the left and right sides, and the central part sandwiched between them is defined as a light shielding area A1 ^*. Function. The left and right contour lines of the light shielding area A1 ^* correspond to the contour reference lines L5 and L6 shown in FIG. After all, in this back exposure, as shown in FIG. 13, the same exposure result as that obtained when the photomask “M1 ^* + M2” obtained by synthesizing the photomask M1 ^* and the photomask M2 is obtained.

  If patterning based on such back exposure is performed, portions of the negative resist layer 380 corresponding to the light-transmitting regions A5 and A6 shown in FIG. 13 become exposure regions. Therefore, the negative resist layer 380 is developed. If the non-photosensitive portion is removed, the remaining resist layer can be formed only in the regions corresponding to the light transmitting regions A5 and A6. Therefore, if the remaining resist layer is used as a protective film and the etching process is performed on the second conductive layer 370, finally, as shown in FIG. An electrode layer 350 and a drain electrode layer 360 can be formed.

  Here, since the right end of the source electrode layer 350 is formed by a mask having the left end of the gate electrode layer 320 as an edge, the right end position of the source electrode layer 350 and the left end position of the gate electrode layer 320 are both contour references. It coincides with the position of the line L5. Similarly, since the left end of the drain electrode layer 360 is formed by a mask having the right end of the gate electrode layer 320 as an edge, the left end position of the drain electrode layer 360 and the right end position of the gate electrode layer 320 are both contour references. It coincides with the position of the line L6. Therefore, the structure shown in FIG. 14 is an ideal structure in which when the source electrode layer 350, the drain electrode layer 360, and the gate electrode layer 320 are projected onto the upper surface of the substrate 310, the electrodes do not overlap on the projection plane. Thus, the generation of parasitic capacitance can be suppressed.

  Subsequently, as shown in FIG. 15, a semiconductor layer 390 is formed on the substrate 310 including the gate insulating layer 330, the source electrode layer 350, and the drain electrode layer 360, and a negative resist layer 395 is formed on the upper surface thereof. Form. Here, the semiconductor layer 390 is a layer for forming a semiconductor channel layer, and is formed of an oxide semiconductor made of IGZO (a composite oxide of indium, gallium, and zinc). As described in §3, if a semiconductor layer made of IGZO is used, good ohmic contact with the source / drain electrode layer can be ensured even if the high-concentration impurity diffusion layer is omitted. Accordingly, in FIG. 15, good ohmic contact is obtained between the source electrode layer 350 and the semiconductor layer 390 made of IGZO, or between the drain electrode layer 360 and the semiconductor layer 390 made of IGZO.

  Note that in order to form the semiconductor layer 390 made of IGZO, the structure shown in FIG. 14 is accommodated in a vacuum chamber, and a material necessary for the composition of IGZO is accommodated as a target, and film formation by general sputtering is performed. Can be done.

  Next, a third photomask M3 having a pattern as shown in FIG. 16 is prepared. The third photomask M3 is a mask used for forming the semiconductor channel layer 340, and the illustrated light transmitting region A7 is a region corresponding to the semiconductor channel layer 340. Therefore, patterning using the third photomask M3 is performed on the semiconductor layer 390 illustrated in FIG. 15, and the semiconductor layer 390 extends over a portion of the source electrode layer 350 and a portion of the drain electrode layer 360 as illustrated in FIG. A semiconductor channel layer 340 is formed.

  More specifically, the third photomask M3 shown in FIG. 16 is arranged above the structure shown in FIG. 15, and light is emitted from the light source arranged thereabove to transmit light in the resist layer. Only the area corresponding to the area A7 is exposed and exposed. Subsequently, if the resist layer is developed to remove the non-photosensitive portion, the resist layer can be left only in the region corresponding to the translucent region A7. Of course, it is possible to perform the same process using a positive photosensitive resist (in this case, an inversion mask reverse to the pattern of the third photomask M3 shown in FIG. 16 is used). .

  Next, the semiconductor channel layer 340 can be formed by etching the semiconductor layer 390 using the remaining resist layer as a protective film. Thereafter, if the remaining resist layer is removed and washed, the structure shown in FIG. 5 can be obtained.

  As mentioned above, although the example of the manufacturing method which concerns on basic embodiment of this invention was described, the formation method of each layer is not necessarily limited to the example mentioned above. For example, the gate electrode layer 320 may be formed by a printing process. Further, the planar pattern of each layer is not limited to the above example. For example, in the above example, the gate insulating layer 330 has a planar pattern extending over the entire surface of the substrate 310, but is formed in at least a region necessary for insulation between the semiconductor channel layer 340 and the gate electrode layer 320. If it is enough.

  After all, in the basic embodiment described in §4, a first step of preparing a substrate 310 made of a transparent material having at least an insulating surface, and a gate electrode made of an opaque conductive material on the substrate 310. A second step of forming the layer 320, and a gate insulating layer 330 made of a transparent insulating material is formed on the substrate 310 including the gate electrode layer 320, and a conductive layer made of a transparent conductive material is formed on the upper surface thereof. A third step of forming 370, and forming a negative resist layer 380 on the upper surface of the conductive layer 370, and having a light-transmitting region A2 partially overlapping with the gate electrode layer 320 when observed from above A photomask M2 for forming a drain electrode is arranged below the substrate 310, irradiated with light from the lower side of the substrate, and a shadow and a gate electrode layer generated by a light-shielding region of the photomask M2. The back surface exposure is performed so that the shadow caused by the light becomes a non-exposed region on the negative resist layer 380, and patterning is performed to remove a portion corresponding to the non-exposed region of the conductive layer 370, and the remaining portion of the conductive layer 370 A fourth step of forming a source electrode layer 350 and a drain electrode layer 360 disposed with a gap between each other, a composite oxide of indium, gallium, and zinc, and a portion of the source electrode layer 350 and A fifth step of forming the semiconductor channel layer 340 disposed in the gap so as to span a part of the drain electrode layer 360 may be performed.

<<< §5. Another embodiment of the production method according to the present invention >>
Here, a modification of the basic embodiment described in §4 will be described. In the case of the basic embodiment of §4, as shown in FIG. 11, it is necessary to dispose the second mask M2 on the lower surface side of the substrate 310 in the back exposure process. However, when a sufficient space cannot be secured below the substrate 310, or when the substrate 310 has light diffusibility, it is not preferable to perform exposure by arranging a mask on the lower surface side of the substrate 310. There can be cases. In such a case, another embodiment described here is effective.

In this other embodiment, a mask M2 ^* shown in FIG. 17 is prepared instead of the mask M2 shown in FIG. 10 as the second photomask for forming the source / drain electrodes. This mask M2 ^* is an inverted version of the mask M2. Then, after obtaining the structure shown in FIG. 7C by the same process as described in the basic embodiment of §4, a positive resist layer 381 is formed on the upper surface thereof, and the structure shown in FIG. Get the body. Here, as shown in FIG. 18, the prepared photomask M2 ^* is arranged on the upper side, and light is irradiated from above to perform the upper surface exposure.

When patterning based on such top exposure is performed, in the positive resist layer 381, a portion corresponding to the light shielding region A2 ^* shown in FIG. 17 is a non-exposed region, and a portion corresponding to the light transmitting regions A8 and A9 is an exposed region. Therefore, if the positive resist layer 381 is developed to remove the photosensitive portion, the resist layer can be left only in the region corresponding to the light shielding region A2 ^* . Therefore, if the remaining resist layer is used as a protective film and the second conductive layer 370 is etched, a source / drain conductive layer 375 as shown in FIG. 19 can be obtained (at this time). The resist layer 382 has not been formed yet). Since the source / drain conductive layer 375 obtained at this stage is not a final source electrode layer or drain electrode layer, it will be referred to as a source / drain electrode preparation layer 375 here.

In the sectional side view, the second conductive layer 370 shown in FIG. 18 and the source / drain electrode preparation layer 375 shown in FIG. 19 cannot be distinguished. However, when viewed as a plane pattern, the former is formed over the entire area of the substrate. The latter is a layer formed only in a region corresponding to the light shielding region A2 ^* shown in FIG. Therefore, when observed from above, the source / drain electrode preparation layer 375 is disposed so as to straddle the gate electrode layer 320 and becomes a layer that partially overlaps the gate electrode layer 320.

  Subsequently, the positive resist layer remaining on the source / drain electrode preparation layer 375 (remaining portion of the resist layer 381 in FIG. 18) is cleaned and removed, and this time, the gate insulating layer 330 and the source / drain electrodes are removed. A negative resist layer 382 is formed on the substrate 310 including the preparation layer 375. FIG. 19 shows the state at this time. Then, back exposure is performed by irradiating light in the photosensitive wavelength region from the lower side of the substrate. As shown in FIG. 19, it is not necessary to use a photomask in this back exposure. Therefore, the exposure process can be easily performed even when a sufficient space cannot be secured below the substrate 310.

  In such back exposure, since the shadow caused by the gate electrode layer 320 becomes a non-exposed region on the negative resist layer 382, a portion corresponding to the non-exposed region of the source / drain electrode preparation layer 375 (that is, the gate electrode) And a step of forming a source electrode layer 350 and a drain electrode layer 360 from the remaining portions of the source / drain electrode preparation layer 375, removing the remaining resist layer, and performing cleaning. As in the basic embodiment described in §4, the structure shown in FIG. 5 can be obtained.

In the case of the above-described embodiment, in order to obtain the source / drain electrode preparation layer 375, top exposure is performed on the positive resist layer 381 using a photomask M2 ^* as shown in FIG. The source / drain electrode preparation layer 375 can also be obtained by forming a negative resist layer instead of the type resist layer 381 and performing top surface exposure using a photomask M2 as shown in FIG.

Finally, in the basic embodiment described in §5, the first step of preparing a substrate 310 made of a transparent material having at least an insulating surface, and a gate electrode made of an opaque conductive material on the substrate 310. A second step of forming the layer 320, and a gate insulating layer 330 made of a transparent insulating material is formed on the substrate 310 including the gate electrode layer 320, and a conductive layer made of a transparent conductive material is formed on the upper surface thereof. The conductive layer 370 is patterned using a photomask M2 ^* for forming a source / drain electrode so as to straddle the gate electrode layer 320 when observed from above. A fourth step of forming a source / drain electrode preparation layer 375 that is disposed and forms a partially overlapping region with respect to the gate electrode layer 320; A negative resist layer 382 is formed on the upper surface of the pole preparation layer 375, and light is irradiated from the lower side of the substrate, so that a shadow generated by the gate electrode layer 320 becomes a non-exposed region on the negative resist layer 382. Patterning is performed to remove portions corresponding to the non-exposed regions of the source / drain electrode preparation layer 375, and the remaining portions of the source / drain electrode preparation layer 375 are arranged with a gap between them. A fifth step of forming the layer 350 and the drain electrode layer 360, and a composite oxide of indium, gallium, and zinc, and disposed in the gap so as to straddle part of the source electrode layer 350 and part of the drain electrode layer 360 And a sixth step of forming the semiconductor channel layer 340 formed.

<<< §6. Still another embodiment of the production method according to the present invention >>>
The embodiment described in §6 includes a fourth stage (patterning using a photomask M2 ^* for forming source / drain electrodes) and a fifth stage (masking the gate electrode layer 320 as a mask) of the embodiment described in §5. And the patterning of the patterning by back exposure).

That is, first, a negative resist layer 381 is formed instead of the positive resist layer 381 shown in FIG. 18, and light in the photosensitive wavelength region is irradiated from the lower side of the substrate without using a photomask. The back exposure is performed so that the generated shadow becomes a non-exposed region on the negative resist layer, and patterning for removing a portion corresponding to the non-exposed region is performed. In this case, the remaining portion of the conductive layer 370 has a planar pattern such as the translucent portion (white regions A3 and A4) of the mask M1 ^* shown in FIG. Again, the remaining portion of the conductive layer 370 is referred to as a source / drain electrode preparation layer.

Subsequently, a photomask for forming a source / drain electrode having a pattern of a closed region partially overlapping with the gate electrode layer 320 (for example, a mask M2 having a closed region A2 as shown in FIG. 10 may be used, or FIG. If the mask M2 ^* having the closed region A2 ^* as shown in FIG. 2 is prepared and the source / drain electrode preparation layer is patterned to leave a portion corresponding to the closed region, the source / drain electrode With the remaining portion of the preparation layer, a source electrode layer 350 and a drain electrode layer 360 having a planar pattern as shown in FIG. 6 are obtained.

  Finally, in the basic embodiment described in §6, a first step of preparing a substrate 310 made of a transparent material having at least an insulating surface, and a gate electrode made of an opaque conductive material on the substrate 310. A second step of forming the layer 320, and a gate insulating layer 330 made of a transparent insulating material is formed on the substrate 310 including the gate electrode layer 320, and a conductive layer made of a transparent conductive material is formed on the upper surface thereof. A third resist layer 370 is formed, and a negative resist layer is formed on the upper surface of the conductive layer 370. Light is irradiated from the lower side of the substrate, and the shadow caused by the gate electrode layer 320 is not on the negative resist layer. Back exposure is performed so as to be an exposed region, patterning is performed to remove a portion corresponding to the non-exposed region of the conductive layer 370, and the source / drain electrodes are formed by the remaining portions of the conductive layer 370. A source / drain electrode preparation layer using a photomask for forming a source / drain electrode having a pattern of a closed region that straddles the gate electrode layer 320 when observed from above; The source electrode layer 350 and the drain electrode layer 360 are formed between the remaining portions of the source / drain electrode preparation layer with a gap between them, by patterning to leave a portion corresponding to the closed region. And a semiconductor channel layer 340 made of a complex oxide of indium, gallium, and zinc and disposed in the gap so as to straddle part of the source electrode layer 350 and part of the drain electrode layer 360. The sixth stage may be performed.

3, 5: Cutting line 100: Inverted staggered top contact type thin film transistor element 110: Glass substrate 120: Gate electrode layer 130: Gate insulating layer 140: Semiconductor channel layer (silicon-based)
141, 142: High-concentration impurity diffusion layer 150: Source electrode layer 160: Drain electrode layer 200: Inverted staggered / bottom contact type thin film transistor element 210: Glass substrate 220: Gate electrode layer 230: Gate insulating layer 240: Semiconductor channel layer ( Silicon system)
241,242: High-concentration impurity diffusion layer 250: Source electrode layer 260: Drain electrode layer 300: Inverted staggered / bottom contact type thin film transistor element 310: Glass substrate 320: Gate electrode layer (metal)
325: First conductive layer (metal)
330: Gate insulating layer 340: Semiconductor channel layer (oxide semiconductor made of IGZO)
350: Source electrode layer 360: Drain electrode layer 370: Second conductive layer (ITO)
375: Source / drain electrode preparation layer 380: Negative resist layer 381: Positive resist layer 382: Negative resist layer 390: Semiconductor layer (oxide semiconductor made of IGZO)
395: Negative resist layers A1 to A9: Photomask light-transmitting regions A1 ^* , A2 ^* : Photomask light-shielding regions D1, D2: Overlapping regions L1-L6: Contour reference lines M1-M3, M1 ^* , M2 ^* : Photomask

Claims (6)

Source / drain electrode formation using a resist that has photosensitivity to light in a predetermined photosensitive wavelength range for a transistor element that controls the current flowing between the source and drain via the semiconductor channel layer by the voltage applied to the gate electrode A method including a patterning process for manufacturing,
A first step of preparing a substrate made of a material having at least an upper surface insulating property and transparent with respect to light in the photosensitive wavelength range;
Forming a gate electrode layer made of a conductive material opaque to light in the photosensitive wavelength region on the substrate;
A gate insulating layer made of an insulating material transparent to light in the photosensitive wavelength range is formed on the substrate including the gate electrode layer, and an upper surface is made of a conductive material transparent to light in the photosensitive wavelength range. A third step of forming a conductive layer;
A negative resist layer having sensitivity to light in the photosensitive wavelength region is formed on the upper surface of the conductive layer, and a source having a light-transmitting region that partially overlaps the gate electrode layer when observed from above A drain electrode forming photomask is disposed below the substrate, irradiated with light in the photosensitive wavelength region from below the substrate, and a shadow caused by the light shielding region of the photomask and a shadow caused by the gate electrode layer However, back exposure is performed so as to be a non-exposed region on the negative resist layer, patterning is performed to remove a portion corresponding to the non-exposed region of the conductive layer, and A fourth step of forming a source electrode layer and a drain electrode layer disposed in the gap through the gap,
A fifth step of forming a semiconductor channel layer made of a complex oxide of indium, gallium, and zinc and disposed in the gap so as to straddle part of the source electrode layer and part of the drain electrode layer;
A method for producing a transistor element, comprising: Source / drain electrode formation using a resist that has photosensitivity to light in a predetermined photosensitive wavelength range for a transistor element that controls the current flowing between the source and drain via the semiconductor channel layer by the voltage applied to the gate electrode A method including a patterning process for manufacturing,
A first step of preparing a substrate made of a material having at least an upper surface insulating property and transparent with respect to light in the photosensitive wavelength range;
Forming a gate electrode layer made of a conductive material opaque to light in the photosensitive wavelength region on the substrate;
A gate insulating layer made of an insulating material transparent to light in the photosensitive wavelength range is formed on the substrate including the gate electrode layer, and an upper surface is made of a conductive material transparent to light in the photosensitive wavelength range. A third step of forming a conductive layer;
The conductive layer is patterned using a photomask for forming source / drain electrodes, and is arranged so as to straddle the gate electrode layer when observed from above, and partially with respect to the gate electrode layer. A fourth step of forming a source / drain electrode preparation layer forming an overlapping region;
A negative resist layer having photosensitivity to light in the photosensitive wavelength region is formed on the upper surface of the source / drain electrode preparation layer, and the gate electrode layer is irradiated with light in the photosensitive wavelength region from below the substrate. The back surface exposure is performed so that the shadow caused by the above becomes a non-exposed region on the negative resist layer, and patterning is performed to remove a portion corresponding to the non-exposed region of the source / drain electrode preparation layer, A fifth step of forming a source electrode layer and a drain electrode layer disposed with a gap between them by the remaining portion of the drain electrode preparation layer;
A sixth step of forming a semiconductor channel layer made of a complex oxide of indium, gallium, and zinc and disposed in the gap so as to straddle part of the source electrode layer and part of the drain electrode layer;
A method for producing a transistor element, comprising: Source / drain electrode formation using a resist that has photosensitivity to light in a predetermined photosensitive wavelength range for a transistor element that controls the current flowing between the source and drain via the semiconductor channel layer by the voltage applied to the gate electrode A method including a patterning process for manufacturing,
A first step of preparing a substrate made of a material having at least an upper surface insulating property and transparent with respect to light in the photosensitive wavelength range;
Forming a gate electrode layer made of a conductive material opaque to light in the photosensitive wavelength region on the substrate;
A gate insulating layer made of an insulating material transparent to light in the photosensitive wavelength range is formed on the substrate including the gate electrode layer, and an upper surface is made of a conductive material transparent to light in the photosensitive wavelength range. A third step of forming a conductive layer;
A negative resist layer having photosensitivity to the light in the photosensitive wavelength region is formed on the upper surface of the conductive layer, and the shadow generated by the gate electrode layer is irradiated with the light in the photosensitive wavelength region from the lower side of the substrate. The back exposure is performed so as to be a non-exposed region on the negative resist layer, the patterning is performed to remove the portion corresponding to the non-exposed region of the conductive layer, and the source / drain is formed by the remaining portions of the conductive layer. A fourth step of forming an electrode preparation layer;
Using a photomask for forming source / drain electrodes having a pattern of a closed region that straddles the gate electrode layer when observed from above, the source / drain electrode preparation layer corresponds to the closed region. Patterning leaving a portion, and forming a source electrode layer and a drain electrode layer disposed with a gap between them by a remaining portion of the source / drain electrode preparation layer;
A sixth step of forming a semiconductor channel layer made of a complex oxide of indium, gallium, and zinc and disposed in the gap so as to straddle part of the source electrode layer and part of the drain electrode layer;
A method for producing a transistor element, comprising: In the manufacturing method of the transistor element in any one of Claims 1-3,
In the first stage, a substrate made of glass or synthetic resin is prepared,
In the second stage, a metal element is used as a material for forming the gate electrode layer. In the manufacturing method of the transistor element in any one of Claims 1-4,
In the third step, a method for manufacturing a transistor element, wherein silicon oxide or silicon nitride is used as a material for forming a gate insulating layer. In the manufacturing method of the transistor element in any one of Claims 1-5,
In the third step, ITO or IZO is used as a material for forming the conductive layer.

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