JP2010193564A - Semiconductor switch circuit - Google Patents

Abstract

Even if a collector voltage difference occurs at the time of turn-off due to variations in characteristics of voltage-driven semiconductor elements, the voltage sharing is made substantially uniform.
A connection line between a collector and a gate driving circuit of three or more voltage-driven semiconductor elements connected in series is magnetically coupled to each other by a common mode reactor, and a capacitor and a resistor are connected in series to the magnetic coupling winding of the reactor. Then, a voltage equalizing circuit 22 is provided in which one is connected to the collector of each voltage-driven semiconductor element and the other is connected to each gate resistance, and the reactor of at least one of the voltage equalizing circuits 22 When magnetically coupled to the reactor 16 of two or more other voltage equalizing circuits 22, the own voltage equalizing circuit 22 connects the capacitors 17 in series to the magnetic coupling windings of the respective magnetically coupled reactors 16. Then, the resistors 18 are connected in series to the parallel-connected magnetic coupling windings.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor switch circuit that equalizes voltage sharing during turn-off of a plurality of voltage-driven semiconductor elements connected in series.

  For example, an insulated gate bipolar transistor (IGBT), which is a voltage-driven semiconductor element, can be easily switched by applying a voltage to the gate, and is therefore widely used in power converters. In particular, in industrial applications, the interconnection voltage is low, and thus there are many cases where the converter capacity can be secured in one series of IGBTs.

  On the other hand, since a power converter for power has a high interconnection voltage, there are many cases where IGBTs must be connected in series. In the case of series connection, unlike one series, a part of the IGBTs connected in series may be damaged due to the influence of variations in IGBT characteristics. This is because when the IGBTs are connected in series, there is a difference in the voltage sharing of the IGBTs due to voltage changes (dv / dt) that occur at turn-off and variations in switching time.

  For example, when a voltage of 400 V is applied to two series IGBTs, it is ideal that each IGBT shares a voltage of 200 V, but one of them is transiently caused by the influence of variations in IGBT characteristics. When turned off, a voltage of 400 V at the maximum may be applied to the IGBT.

  FIG. 11 is a circuit diagram of a conventional semiconductor switch circuit including two series IGBTs 11a and 11b. The IGBTs 11a and 11b connected in series are supplied with gate signals Iga and Igb from the gate drive circuits 12a and 12b through the gate resistors 13a and 13b, respectively. The power supplied from the DC power supply 14 to the load 15 is controlled by turning on and off the IGBTs 11a and 11b.

  12 is a waveform diagram showing an example of the gate voltage and the collector voltage at the time of turn-off of the conventional semiconductor switch circuit shown in FIG. 11, and FIG. 13 is an enlarged view in which the time span of the period T1 portion of FIG. 12 is enlarged. . 12 and 13 show a case where the IGBT 11a is turned off before the IGBT 11b due to variations in characteristics of the IGBTs 11a and 11b.

  If there is a turn-off command at time t1, the gate voltage Vg becomes negative, and the IGBTs 11a and 11b start to turn off. Because the IGBT 11a is turned off before the IGBT 11b due to variations in the characteristics of the IGBTs 11a and 11b, the IGBT 11a bears the voltage of the DC power supply 14 (for example, 400V) at the time t2, and the IGBT 11b maintains the conductive state and bears the voltage. Is 0V. That is, the collector voltage of the IGBT 11a is biased toward the high side, and the collector voltage of the IGBT 11b is biased toward the low side.

  Therefore, the collector voltage Va of the IGBT 11a that has been turned off becomes the voltage of the DC power supply 14 (for example, 400V), and the collector voltage Vb of the IGBT 11b that has not been turned off remains at approximately 0V. At time t3 when the period T1 has elapsed, the IGBT 11b also starts to turn off. After the time t3, the collector voltage Va of the IGBT 11a gradually decreases, the collector voltage Vb of the IGBT 11b gradually increases, and finally the IGBT 11a, The collector voltages Va and Vb of 11b become equal, and the voltage of the DC power supply 14 is equally borne by 200V, which is 1/2. Thus, although the collector voltages Va and Vb of the two series IGBTs 11a and 11b are finally equal, in the process of turning off, the burden on the IGBT 11a that turns off first increases.

  As a countermeasure, it is conceivable to make the IGBT, which is a device, redundantly designed, but there is a drawback that the apparatus becomes large. In addition, there is a circuit in which a balance circuit in which a capacitor and a common mode reactor are connected in series is connected between a collector and a gate to suppress variations in collector voltage due to variations in IGBT characteristics during turn-off (for example, patents). Reference 1).

JP 2006-42512 A

  However, in the thing of patent document 1, if the voltage difference between series of IGBT becomes a certain level or more, a short circuit current may flow into a balance circuit and may destroy IGBT.

  FIG. 14 is a circuit diagram of the one of Patent Document 1, in which an current It flowing in a balance circuit formed by a voltage difference between IGBTs in series is indicated by an arrow. The balance circuit is formed by connecting a capacitor Ca and a common mode reactor Tr in series between the collector and gate of the IGBT 11a, and connecting a capacitor Cb and a common mode reactor Tr in series between the collector and gate of the IGBT 11b. The The current It flowing in the balance circuit is expressed by the equation (1), where Rline is the resistance of the balance circuit line.

It = (Va−Vb) / Rline (1)
That is, if the differential voltage between the collector voltages Va and Vb of the IGBTs 11a and 11b is large, the current resistance becomes excessive because the line resistance Rline of the balance circuit is very small.

  FIG. 15 is a waveform diagram showing an example of the gate voltage, the gate current, and the collector voltage at turn-off when the differential voltage between the collector voltages Va and Vb of the IGBTs 11a and 11b in the circuit shown in FIG. 14 is large. If there is a turn-off command at time t1, the gate voltage Vg becomes negative, and the IGBTs 11a and 11b start to turn off. Even if a differential voltage occurs in the collector voltages Va and Vb of the IGBTs 11a and 11b, a current It flows so that the differential voltage is eliminated by the balance circuit. At the time t2 when the differential voltage between the collector voltages Va and Vb of the IGBTs 11a and 11b becomes large, the line resistance Rline of the balance circuit is very small, so that the current It becomes excessive and a large gate current Ig flows.

  In other words, it is effective after the voltage sharing becomes uniform to some extent or when the characteristics of the IGBTs 11a and 11b are quite similar, but there is a large variation in switching dv / dt in the transient response at turn-off. In the transient state, a large difference occurs in the voltage sharing, and a very large short-circuit current It flows during the transient response at the turn-off time. If a large short circuit current It flows, the gate may be adversely affected.

  An object of the present invention is to provide a semiconductor switch circuit capable of making the voltage sharing of voltage-driven semiconductor elements connected in series substantially uniform even when a collector voltage difference occurs during turn-off due to variations in characteristics of the voltage-driven semiconductor elements. Is to provide.

  According to a first aspect of the present invention, there is provided a semiconductor switch circuit including three or more voltage-driven semiconductor elements connected in series and a gate drive for supplying a gate signal to a gate of each of the voltage-driven semiconductor elements via a gate resistor. A circuit, a common mode reactor that magnetically couples a connection line between the collector of each voltage-driven semiconductor element and the gate drive circuit, and a capacitor and a resistor connected in series to the magnetic coupling winding of the reactor. A voltage equalizing circuit connected to the collector of each of the voltage-driven semiconductor elements and the other connected to each of the gate resistors, and two or more reactors other than the voltage equalizing circuit are provided. When it is magnetically coupled to the reactors of other voltage equalization circuits, its own voltage equalization circuit Capacitor windings are connected in series with capacitors connected in series, and the resistances combined into one are connected in series to the magnetically connected windings connected in parallel, and one of the voltage-driven semiconductor elements is connected to each other. A collector is connected and the other is connected to each of the gate resistors.

  A semiconductor switch circuit according to a second aspect of the present invention is the semiconductor switch circuit according to the first aspect of the present invention, wherein the turn ratio of the reactor, the capacitance of the capacitor, or the resistance value of the resistor is set so that each of the voltage equalizing circuits is the same equivalent circuit. It is characterized by selecting.

  A semiconductor switch circuit according to a third aspect of the present invention is the semiconductor switch circuit according to the first or second aspect, wherein there are n (n is 3 or more) of the plurality of voltage-driven semiconductor elements connected in series. The equalizing circuit has n-1 reactors that are magnetically coupled to other n-1 voltage equalizing circuits other than itself.

  According to a fourth aspect of the present invention, there is provided a semiconductor switch circuit according to the first aspect of the present invention, wherein the number of the plurality of voltage-driven semiconductor elements connected in series is n (n is 3 or more), and the first stage voltage is equalized. The circuit is formed by connecting a capacitor and a resistor in series with a magnetic coupling winding of a reactor that is magnetically coupled to the second stage voltage equalization circuit at a one-to-one turn ratio, and the nth stage voltage equalization circuit is A magnetic coupling winding of a reactor magnetically coupled to the (n-1) th stage voltage equalizing circuit and a one-to-one winding ratio is connected to a capacitor having the same capacitance as that of the first stage voltage equalizing circuit. Are connected in series, and the voltage equalizing circuit of the i-th stage (i = 2 to n-1) is a reactor that is magnetically coupled to the voltage equalizing circuit of the i-1 stage in a one-to-one turn ratio. Magnetically coupled winding, i + 1 stage voltage equalization circuit, and one-to-one winding Reactor magnetic coupling windings that are magnetically coupled to each other in parallel are connected in parallel, and each of the magnetic coupling windings connected in parallel is connected in series with a capacitor of 1/2 capacity of the capacitor of the first stage voltage equalization circuit. In addition, a resistor having the same resistance value as that of the first stage voltage equalizing circuit is connected in series to the magnetically coupled windings connected in parallel.

  According to the present invention, when the reactor of the voltage equalizing circuit is magnetically coupled to the reactors of two or more other voltage equalizing circuits other than itself, a capacitor is connected to the magnetically coupled winding of each of the magnetically coupled reactors. Since the series-connected resistors are connected in parallel to each other and the combined resistors are connected in series to the parallel-connected magnetic coupling windings, the voltages of the magnetic coupling windings of the respective reactors connected in parallel are equalized. The Therefore, even when there is a variation in the characteristics of the voltage-driven semiconductor element when the voltage-driven semiconductor element is turned off, the voltage sharing can be made substantially uniform even in a transient manner, and a plurality of voltage-driven semiconductors connected in series Operational responsibilities between type semiconductor elements are equalized, leading to longer life.

FIG. 1 is a circuit diagram showing an example of a basic configuration of a semiconductor switch circuit of the present invention. FIG. 2 is a waveform diagram showing an example of a gate voltage, a collector voltage, and a reactor voltage when the semiconductor switch circuit of the basic configuration of the present invention shown in FIG. 1 is turned off. The wave form diagram which shows another example of the gate voltage at the time of turn-off of the semiconductor switch circuit of the basic composition of this invention shown in FIG. 1, a collector voltage, and the voltage of a reactor. The circuit diagram which shows the state of the voltage equalization circuit just before the turn-off of IGBT11a-11c of the semiconductor switch circuit of the basic composition of this invention shown in FIG. The circuit diagram which shows the state of the voltage equalization circuit immediately after turn-off of IGBT11a-11c of the semiconductor switch circuit of the basic composition of this invention shown in FIG. 1 is a circuit diagram showing an example of a semiconductor switch circuit according to an embodiment of the present invention. The circuit diagram which shows the state of the voltage equalization circuit immediately after turn-off of IGBT11a-11c of the semiconductor switch circuit concerning embodiment of this invention shown in FIG. FIG. 7 is a waveform diagram showing an example of a gate voltage, a collector voltage, and a reactor voltage when the semiconductor switch circuit according to the embodiment of the present invention shown in FIG. 6 is turned off. The circuit diagram which shows another example of the semiconductor switch circuit concerning embodiment of this invention. The circuit diagram of another example of the semiconductor switch circuit concerning embodiment of this invention. The circuit diagram of the conventional semiconductor switch circuit provided with 2 series IGBT11a, 11b. The wave form diagram which shows an example of the gate voltage at the time of turn-off of the conventional semiconductor switch circuit shown in FIG. The enlarged view which expanded the time span of the period T1 part of FIG. The circuit diagram of the thing of patent document 1. FIG. 15 is a waveform diagram showing an example of a gate voltage, a gate current, and a collector voltage at turn-off when the differential voltage between the collector voltages Va and Vb of the IGBTs 11a and 11b in the circuit shown in FIG. 14 is large.

  Embodiments of the present invention will be described below. First, the basic configuration of the semiconductor switch circuit of the present invention will be described. FIG. 1 is a circuit diagram showing an example of a basic configuration of a semiconductor switch circuit of the present invention.

  As shown in FIG. 1, the present invention is a common mode reactor (hereinafter simply referred to as a “common mode reactor”) that magnetically couples the connection lines of the collectors of the voltage-driven semiconductor elements 11 a to 11 c and the gate drive circuits 12 a to 12 c connected in series. (Reactors) 20a and 20b are provided, and the voltage equalization circuits 22a to 22c are provided in the magnetic coupling windings of the reactors 16ab and 16bc. The IGBTs 11a to 11c connected in series are supplied with gate signals Iga to Igc from the gate drive circuits 12a to 12c through the gate resistors 13a to 13c, respectively, and are supplied from the DC power source 14 to the load 15 by turning on and off the IGBTs 11a to 11c. Power is controlled.

  In the voltage equalization circuits 22a to 22c, capacitors 17a to 17c and resistors 18a to 18c are connected in series, one is connected to the collector of each voltage driven semiconductor element 11a to 11c, and the other is each gate resistor 13a to 13c. 13c is formed. Reactor 16ab has a magnetic coupling winding composed of primary winding 20a and secondary winding 21b, and reactor 16bc has a magnetic coupling winding composed of primary winding 20b and secondary winding 21c. is doing.

  The first-stage voltage equalization circuit 22a is formed by connecting a capacitor 17a and a resistor 18a in series to the primary winding 20a of the first reactor 16ab. The capacitance of the capacitor 17a is 2C and the value of the resistor 18a is R. It shows a case. Similarly, the third-stage voltage equalizing circuit 22c is formed by connecting a capacitor 17c and a resistor 18c in series to the secondary winding 21c of the second reactor 16bc. The capacitance of the capacitor 17c is 2C, and the value of the resistor 18a. Shows a case where R is R.

  On the other hand, in the second-stage voltage equalizing circuit 22b in the middle, a capacitor 17b1 and a resistor 18b1 are connected in series to the secondary winding 21b of the first reactor 16ab to form a first voltage equalizing series circuit 23b1. A capacitor 17b2 and a resistor 18b2 are connected in series to the primary winding 20b of the second reactor 16bc to form a second voltage equalizing series circuit 23b2, and these are connected in parallel to form the voltage equalizing circuit 22b. is doing.

  The capacitors 17b1 and 17b2 of the first and second voltage equalizing series circuits 23b1 and 23b2 connected in parallel have the capacitance 2C of the capacitors 17a and 17c of the first and third voltage equalizing circuits 22a and 22c. The value of the resistors 18b1 and 18b2 is 2R, which is twice the value R of the resistors 18a and 18c of the first and third stage voltage equalization circuits 22a and 22c. This is to make the inductances, the capacitances, and the resistance values of the reactors 16ab and 16bc of the voltage equalization circuits 22a to 22c at the respective stages equal in the equivalent circuit.

The capacitances of the capacitors 17b1 and 17b2 of the first and second voltage equalization series circuits 23b1 and 23b2 of the second stage voltage equalization circuit 22b and the resistance values of the resistors 18b1 and 18b2 are set to the first and third stages. When the capacitances of the capacitors 17a and 17c of the voltage equalization circuits 22a and 22c and the resistance values of the resistors 18a and 18c are the same, the turns ratio of the magnetic coupling windings of the reactor 16ab is 2: 1 and the magnetism of the reactor 16bc is The turn ratio of the combined winding is set to 1: 2. In this way, the turn ratio of the reactor 16ab, the capacitance of the capacitor 17 or the resistance value of the resistor 18 is selected so that the voltage equalizing circuits 22a to 22c become the same equivalent circuit. Here, the voltage equalizing circuit 22 The resistor 18 is provided to the resistor 18 because the differential voltage between the collector voltages Va to Vc of the IGBTs 11a to 11c is applied to the resistor 18, so that the short-circuit current It is suppressed even if the differential voltage between the collector voltages Va to Vc increases. Because it can. Further, the other of the voltage equalizing circuit 22 is connected to the gate resistor 13 and connected to the gate through the gate resistor 13. If the gate is directly connected to the gate without passing through the gate resistor 13, an excessive gate current is temporarily generated. This is to prevent it from flowing.

  As described above, the voltage equalization circuit of the basic configuration of the present invention has the capacitor 17 and the resistor 18 connected in series to the magnetic coupling windings (the primary winding 20 and the secondary winding 21) of the reactor 16, and the voltage uniformity. One of the circuit 22 is connected to the collector of the IGBT 11, and the other of the voltage equalizing circuit 22 is connected to the gate resistor 13.

  FIG. 2 is a waveform diagram showing an example of the gate voltage, collector voltage, and reactor voltage at turn-off of the semiconductor switch circuit of the basic configuration of the present invention shown in FIG. The waveform is shown when the characteristics of the IGBT 11c are substantially equal.

  In FIG. 2, if there is a turn-off command at time t1, the gate voltage Vg becomes negative, the IGBTs 11a to 11c begin to turn off, and the collector voltages Va to Vc of the IGBTs 11a to 11c begin to rise. The voltage equalizing circuit 22a and the first voltage equalizing series circuit 23b1 of the voltage equalizing circuit 22b are configured such that the primary winding of the reactor 16ab is eliminated so as to eliminate the difference voltage between the collector voltage Va of the IGBT 11a and the collector voltage Vb of the IGBT 11b. 20a and the secondary winding 21b generate a winding voltage VL1. Similarly, the voltage equalizing circuit 22c and the second voltage equalizing series circuit 23b2 of the voltage equalizing circuit 22b are connected to the collector voltage Vb of the IGBT 11b and the IGBT 11c. The winding voltage VL2 is generated in the primary winding 20b and the secondary winding 21c of the reactor 16bc so as to eliminate the difference voltage from the collector voltage Vc.

  At time t2, when the differential voltage between the collector voltage Va of the IGBT 11a and the collector voltage Vb of the IGBT 11b and the differential voltage between the collector voltage Vb of the IGBT 11b and the collector voltage Vc of the IGBT 11c become substantially zero, the winding voltage VL1 of the reactor 16ab and Winding voltage VL2 of reactor 16bc is zero.

  Since the characteristics of the first stage IGBT 11a and the third stage IGBT 11c are substantially equal, the winding voltage VL1 of the reactor 16ab and the winding voltage VL2 of the reactor 16bc have substantially the same characteristics, and the winding voltage VL1 and the winding voltage VL2 The voltage difference between (VL1 and VL2) is substantially zero.

  As described above, when the voltage equalizing circuit 22b is constituted by the parallel connection of the first voltage equalizing series circuit 23b1 and the second voltage equalizing series circuit 23b2, the first voltage equalizing series circuit 23b1 is A first stage IGBT 11a of another voltage equalization circuit 22a that is magnetically coupled, and a third stage IGBT 11c of another voltage equalization circuit 22c that is magnetically coupled to the second voltage equalization series circuit 23b2. When the characteristics are almost equal, the collector voltages Va to Vc of the IGBTs 11a to 11c are almost equalized and have the same potential even during the transition by the operation of the voltage equalization circuits 22a to 22c.

  FIG. 3 is a waveform diagram showing another example of the gate voltage, collector voltage, and reactor voltage at turn-off of the semiconductor switch circuit of the basic configuration of the present invention shown in FIG. The waveform in the case where there is a variation in characteristics with the IGBT 11c of the stage is shown.

  In FIG. 3, if there is a turn-off command at time t1, the gate voltage Vg becomes negative, the IGBTs 11a to 11c begin to turn off, and the collector voltages Va to Vc of the IGBTs 11a to 11c begin to rise. The voltage equalizing circuit 22a and the first voltage equalizing series circuit 23b1 of the voltage equalizing circuit 22b are configured such that the primary winding of the reactor 16ab is eliminated so as to eliminate the difference voltage between the collector voltage Va of the IGBT 11a and the collector voltage Vb of the IGBT 11b. 20a and the secondary winding 21b generate a winding voltage VL1. Similarly, the voltage equalizing circuit 22c and the second voltage equalizing series circuit 23b2 of the voltage equalizing circuit 22b are connected to the collector voltage Vb of the IGBT 11b and the IGBT 11c. The winding voltage VL2 is generated in the primary winding 20b and the secondary winding 21c of the reactor 16bc so as to eliminate the difference voltage from the collector voltage Vc.

  Since the characteristics of the first-stage IGBT 11a and the third-stage IGBT 11c vary, the winding voltage VL1 of the reactor 16ab and the winding voltage VL2 of the reactor 16bc have different voltage waveforms, and the winding voltage VL1 and the winding voltage are different. The difference voltage (VL1−VL2) from the voltage VL2 is not substantially zero, but varies between time points t1 and t2. The fluctuation of the difference voltage (VL1-VL2) affects the collector voltage Va of the IGBT 11a and the collector voltage Vc of the IGBT 11c, and the collector voltage Va and the collector voltage Vc have different waveforms between the time points t1 and t3, and after the time point t3. At about the same potential.

  As described above, when the voltage equalizing circuit 22b is constituted by the parallel connection of the first voltage equalizing series circuit 23b1 and the second voltage equalizing series circuit 23b2, the first voltage equalizing series circuit 23b1 is A first stage IGBT 11a of another voltage equalization circuit 22a that is magnetically coupled, and a third stage IGBT 11c of another voltage equalization circuit 22c that is magnetically coupled to the second voltage equalization series circuit 23b2. If there is a variation in characteristics, the collector voltage Va of the IGBT 11a and the collector voltage Vc of the IGBT 11c have different voltage waveforms at the time of transition, and there is a difference in voltage sharing to the IGBTs 11a and 11c in a transient state when the semiconductor switch circuit is turned off.

  FIG. 4 is a circuit diagram showing the state of the voltage equalization circuit immediately before the IGBTs 11a to 11c are turned off in the semiconductor switch circuit of the basic configuration of the present invention shown in FIG. Since the IGBTs 11a to 11c are in a conducting state while the IGBTs 11a to 11c are turned on (immediately before the turn-off), the collector voltage Va of the IGBT 11a, the collector voltage Vb of the IGBT 11b, and the collector voltage Vc of the IGBT 11c are zero. Further, since the difference voltage is 0, the current It flowing through the voltage equalization circuits 22a to 22c is 0.

  That is, in the first-stage voltage equalization circuit 22a, the voltage VL1 of the primary winding 20a of the reactor 16ab and the voltage VRH1 of the resistor 18a are 0, and the gate voltage Vga (for example, 15V) and the capacitor voltage CVa (for example, 15V). Are equally balanced. In the first voltage equalizing series circuit 23b1 of the second-stage voltage equalizing circuit 22b, the voltage VL1 of the secondary winding 21b of the reactor 16ab and the voltage VRH2 of the resistor 18b1 are 0, and the gate voltage Vgb ( For example, 15V) and the capacitor voltage CVb1 (for example, 15V) are equally balanced. Similarly, in the second voltage equalizing series circuit 23b2 of the second-stage voltage equalizing circuit 22b, the voltage VL2 of the primary winding 20b of the reactor 16bc and the voltage VRL2 of the resistor 18b2 are 0, and the gate voltage Vgb (For example, 15V) and capacitor voltage CVb2 (for example, 15V) are equally balanced. Further, in the third stage voltage equalization circuit 22c, the voltage VL2 of the secondary winding 21c of the reactor 16bc and the voltage VRL1 of the resistor 18c are 0, and the gate voltage Vgc (for example, 15V) and the capacitor voltage CVc (for example, 15V). Are equally balanced.

  Next, FIG. 5 is a circuit diagram showing a state of the voltage equalization circuit immediately after the IGBTs 11a to 11c are turned off in the semiconductor switch circuit having the basic configuration of the present invention shown in FIG. Since the IGBTs 11a to 11c are turned off, the polarities of the gate voltages Vga to Vgc are reversed. If the characteristics of the first-stage IGBT 11a and the second-stage IGBT 11b vary, the voltage equalization circuit 22a and the first voltage equalization series circuit 23b1 of the voltage equalization circuit 22b cause the collector voltage of the IGBT 11a. The current It is passed so as to eliminate the voltage difference between Va and the collector voltage Vb of the IGBT 11b, and the winding voltage VL1 is generated in the primary winding 20a and the secondary winding 21b of the reactor 16ab. Similarly, if the characteristics of the second stage IGBT 11b and the third stage IGBT 11c vary, the voltage equalizing circuit 22c and the second voltage equalizing series circuit 23b2 of the voltage equalizing circuit 22b are connected to the collector of the IGBT 11b. The current It is passed so as to eliminate the difference voltage between the voltage Vb and the collector voltage Vc of the IGBT 11c, and the winding voltage VL2 is generated in the primary winding 20b and the secondary winding 21c of the reactor 16bc.

  At this time, the voltage equation of the voltage equalizing circuit 22a is expressed by equation (1), the voltage equation of the first voltage equalizing series circuit 23b1 of the voltage equalizing circuit 22b is expressed by equation (2), and the voltage The equation for the voltage of the second voltage equalization series circuit 23b2 of the equalization circuit 22b is expressed by equation (3), and the voltage equation for the voltage equalization circuit 22c is expressed by equation (4).

Va + Vga = VL1-CVa + VRH1 (1)
Vb + Vgb = VL1-CVb1 + VRH2 (2)
Vb + Vgb = VL2-CVb2 + VRL2 (3)
Vc + Vgc = VL2-CVc + VRL1 (4)
Since the gate voltages Vga to Vgc are -15V, and the capacitor voltages CVa, CVb1, CVb2, and CVc are 15V immediately after the turn-off, the equations (1) to (4) to (5) to (8) are obtained. It is done.

VRH1 = Va−VL1 + 30 (5)
VRH2 = Vb−VL1 + 30 (6)
VRL2 = Vb−VL2 + 30 (7)
VRL1 = Vc−VL2 + 30 (8)
The relationship between the collector voltage Va of the first-stage IGBT 11a and the collector voltage Vb of the second-stage IGBT 11b is expressed by the expression (9) from the expressions (5) and (6), and the collector voltage Vb of the second-stage IGBT 11b. And the collector voltage Vc of the third stage IGBT 11c is shown by the expression (10) from the expressions (6) and (7). The collector voltage Vc of the third stage IGBT 11c and the collector voltage of the first stage IGBT 11a The relationship with Va is expressed by equation (11) from equations (8) and (5).

Va−Vb = VRH1−VRH2 (9)
Vb-Vc = VRL2-VRL1 (10)
Vc−Va = (VL2−VL1) + (VRL1−VRH1) (11)
As can be seen from the equation (11), the difference (Vc−Va) between the collector voltage Vc of the third-stage IGBT 11c and the collector voltage Va of the first-stage IGBT 11a is the winding voltage VL2 of the reactor 16bc and the reactor 16ab. Since the difference (VL2−VL1) from the winding voltage VL1 is included, if the characteristics of the first stage IGBT 11a and the third stage IGBT 11c vary, the collectors of the IGBTs 11a to 11c are turned off after the semiconductor switch circuit is turned off. In a transient state until the voltages Va to Vc become the same potential, the fluctuation of the difference voltage (VL1-VL2) affects the collector voltage Va of the IGBT 11a and the collector voltage Vc of the IGBT 11c. Therefore, there is a difference in voltage sharing to the IGBTs 11a and 11c in a transient state when the semiconductor switch circuit is turned off.

  Therefore, in the embodiment of the present invention, a difference is not caused in the voltage sharing to the IGBTs 11a and 11c in a transient state when the semiconductor switch circuit is turned off. That is, when the reactor is magnetically coupled to the reactor of two or more other voltage equalizing circuits other than itself in the voltage equalizing circuit 22b, and the magnetic coupling windings of the reactor are connected in parallel in the voltage equalizing circuit, The voltage of the voltage-driven semiconductor element connected in series in both the transient state and the steady state at the time of turn-off even if there are variations in the characteristics of the voltage-driven semiconductor element of two or more other voltage equalizing circuits Make the sharing almost uniform.

  FIG. 6 is a circuit diagram showing an example of a semiconductor switch circuit according to the embodiment of the present invention. In this embodiment of the present invention, the resistors 18b1 and 18b2 of the second-stage voltage equalizing circuit 22b in the middle are combined into a resistor 18b with respect to the semiconductor switch circuit having the basic configuration of the present invention shown in FIG. This is connected to the collector of the IGBT 11b. The same elements as those in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

  In FIG. 6, a capacitor 17b1 is connected to the secondary winding 21b of the first reactor 16ab, and the primary winding 20b of the second reactor 16bc is connected to the second-stage voltage equalizing circuit 22b in the middle. The capacitor 17b2 is connected in parallel. The capacitors 17b1 and 17b2 are connected to the collector of the IGBT 11b through the resistor 18b. The resistor 18b has the same value as the value R of the resistors 18a and 18c of the other voltage equalizing circuits 22a and 22c. Thereby, the first voltage equalizing series circuit 23b1 becomes a series circuit of the secondary winding 21b of the reactor 16ab and the capacitor 17b1, and the second voltage equalizing series circuit 23b2 is a primary winding 20b of the reactor 16ac. And a capacitor 17b2. The resistor 18b is shared by the first and second voltage equalizing series circuits 23b1 and 23b2.

  FIG. 7 is a circuit diagram showing a state of the voltage equalization circuit immediately after the IGBTs 11a to 11c of the semiconductor switch circuit according to the embodiment of the present invention shown in FIG. 6 are turned off.

  In FIG. 7, if the characteristics of the first-stage IGBT 11a and the second-stage IGBT 11b vary, as in the case shown in FIG. 5, the first voltage of the voltage equalization circuit 22a and the voltage equalization circuit 22b. The equalizing series circuit 23b1 causes the current It to flow so as to eliminate the differential voltage between the collector voltage Va of the IGBT 11a and the collector voltage Vb of the IGBT 11b, and the winding voltage VL1 is applied to the primary winding 20a and the secondary winding 21b of the reactor 16ab. Is generated. Similarly, if the characteristics of the second stage IGBT 11b and the third stage IGBT 11c vary, the voltage equalizing circuit 22c and the second voltage equalizing series circuit 23b2 of the voltage equalizing circuit 22b are connected to the collector of the IGBT 11b. The current It is passed so as to eliminate the difference voltage between the voltage Vb and the collector voltage Vc of the IGBT 11c, and the winding voltage VL2 is generated in the primary winding 20b and the secondary winding 21c of the reactor 16bc.

  At this time, the voltage equation of the voltage equalizing circuit 22a is expressed by equation (12), the voltage equation of the first voltage equalizing series circuit 23b1 of the voltage equalizing circuit 22b is expressed by equation (13), and the voltage The equation of voltage of the second voltage equalizing series circuit 23b2 of the equalizing circuit 22b is expressed by the equation (14), and the voltage equation of the voltage equalizing circuit 22c is expressed by the equation (15).

Va + Vga = VL1-CVa + VRH (12)
Vb + Vgb = VL1-CVb1 + VR (13)
Vb + Vgb = VL2-CVb2 + VR (14)
Vc + Vgc = VL2-CVc + VRL (15)
Here, VL1-CVb1 = VL2-CVb2, and the capacitor voltages CVa, CVb1, CVb2, and CVc are 15V immediately after the turn-off, and therefore CVb1 = CVb2. Therefore, VL1 = VL2, and when VL1 = VL, VL2 is also VL. On the other hand, since the gate voltages Vga to Vgc are −15 V, the expressions (16) to (18) are obtained from the expressions (12) to (15).

VRH = −Va + VL−30 (16)
VR = −Vb + VL−30 (17)
VRL = −Vc + VL−30 (18)
The relationship between the collector voltage Va of the first-stage IGBT 11a and the collector voltage Vb of the second-stage IGBT 11b is expressed by equation (19) from equations (16) and (17).
The relationship between the collector voltage Vb of the second-stage IGBT 11b and the collector voltage Vc of the third-stage IGBT 11c is expressed by the equation (20) from the equations (17) and (18), and the collector voltage Vc of the third-stage IGBT 11c. And the collector voltage Va of the first-stage IGBT 11a is expressed by equation (21) from equations (17) and (18).

Va−Vb = VR−VRH (19)
Vb−Vc = VRL−VR (20)
Vc−Va = VRH−VRL (21)
As can be seen from the equation (21), the difference (Vc−Va) between the collector voltage Vc of the third-stage IGBT 11c and the collector voltage Va of the first-stage IGBT 11a includes the winding voltage VL2 of the reactor 16bc and the reactor 16ab. Since the difference (VL2−VL1) from the winding voltage VL1 is not included, even if the characteristics of the first stage IGBT 11a and the third stage IGBT 11c vary, the IGBT 11a˜ In a transient state until the collector voltages Va to Vc of 11c become the same potential, the fluctuation of the differential voltage (VL1-VL2) does not affect the collector voltage Va of the IGBT 11a or the collector voltage Vc of the IGBT 11c. Therefore, it is possible to prevent a difference in voltage sharing between the IGBTs 11a and 11c in a transient state when the semiconductor switch circuit is turned off.

  FIG. 8 is a waveform diagram showing an example of a gate voltage, a collector voltage, and a reactor voltage when the semiconductor switch circuit according to the embodiment of the present invention shown in FIG. 6 is turned off.

  In FIG. 8, if there is a turn-off command at time t1, the gate voltage Vg becomes negative, the IGBTs 11a to 11c begin to turn off, and the collector voltages Va to Vc of the IGBTs 11a to 11c begin to rise. The voltage equalizing circuit 22a and the first voltage equalizing series circuit 23b1 of the voltage equalizing circuit 22b are configured such that the primary winding of the reactor 16ab is eliminated so as to eliminate the difference voltage between the collector voltage Va of the IGBT 11a and the collector voltage Vb of the IGBT 11b. 20a and the secondary winding 21b generate a winding voltage VL1. Similarly, the voltage equalizing circuit 22c and the second voltage equalizing series circuit 23b2 of the voltage equalizing circuit 22b are connected to the collector voltage Vb of the IGBT 11b and the IGBT 11c. The winding voltage VL2 is generated in the primary winding 20b and the secondary winding 21c of the reactor 16bc so as to eliminate the difference voltage from the collector voltage Vc.

  Even if the characteristics of the first-stage IGBT 11a and the third-stage IGBT 11c vary, the winding voltage VL1 of the reactor 16ab and the winding voltage VL2 of the reactor 16bc are equal to the first voltage of the voltage equalization circuit 22b. Since the common series circuit 23b1, the second voltage equalization series circuit 23b2, and the resistor 18b are common, the winding voltage VL1 and the winding voltage VL2 are equal. Therefore, the differential voltage (VL1-VL2) between the winding voltage VL1 and the winding voltage VL2 does not affect the collector voltage Va of the IGBT 11a or the collector voltage Vc of the IGBT 11c. The reason why the collector voltage Va of the IGBT 11a and the collector voltage Vc of the IGBT 11c have different characteristics from the time point t1 to t2 is due to variation in characteristics between the first-stage IGBT 11a and the third-stage IGBT 11c.

  As described above, when the voltage equalizing circuit 22b is constituted by the parallel connection of the first voltage equalizing series circuit 23b1 and the second voltage equalizing series circuit 23b2, the first voltage equalizing series circuit 23b1 is A first stage IGBT 11a of another voltage equalization circuit 22a that is magnetically coupled, and a third stage IGBT 11c of another voltage equalization circuit 22c that is magnetically coupled to the second voltage equalization series circuit 23b2. Even if there is a variation in characteristics, the collector voltage Va of the IGBT 11a and the collector voltage Vc of the IGBT 11c are not affected by the difference voltage (VL1-VL2) between the winding voltage VL1 and the winding voltage VL2 during the transition. Even in a transient state when the semiconductor switch circuit is turned off, the voltage sharing to the IGBTs 11a and 11c can be made substantially equal.

  FIG. 9 is a circuit diagram showing another example of the semiconductor switch circuit according to the embodiment of the present invention. In this example, in contrast to the example shown in FIG. 6, the number of voltage-driven semiconductor elements connected in series is n.

  As shown in FIG. 9, the first-stage voltage equalizing circuit 22a includes a capacitor 17a and a primary winding 20a of a reactor 16ab that are magnetically coupled to the second-stage voltage equalizing circuit 22b at a turns ratio of 1: 1. Resistor 18b is connected in series, and nth stage voltage equalization circuit 22n is magnetically coupled to n-1th stage voltage equalization circuit 22n-1 in a one-to-one turns ratio. -1) A capacitor 17n having the same capacity as that of the first-stage voltage equalizing circuit 22a and a resistor 18n having the same resistance value are connected in series to the n secondary winding 21n.

  On the other hand, the second-stage voltage equalization circuit 22b to the (n-1) th stage voltage equalization circuit 22n-1 have voltage equalization circuits 22a to 22n one stage higher than their own voltage equalization circuits 22b to 22n-1. -2 and reactors 16ab to 16 (n-2) (n-1) are magnetically coupled to each other at a one-to-one winding ratio, and voltage equalization is one stage lower than their own voltage equalization circuits 22b to 22n-1. The circuits 22c to 22n and the reactors 16bc to 16 (n-1) n are magnetically coupled to each other at a turns ratio of 1: 1.

  And the 1st voltage equalization series by which the secondary windings 21b-21n-1 of the reactors 16ab-16 (n-2) (n-1) and the capacitor | condenser 17b1-17 (n-1) 1 were connected in series. Circuits 23b1 to 23 (n-1) 1, first windings 20b to 20n-1 of reactors 16bc to 16 (n-1) n, and capacitors 17b2 to 17 (n-1) 2 are connected in series. 2 voltage equalizing series circuits 23b2 to 23 (n-1) 2, and the first voltage equalizing series circuits 23b1 to 23 (n-1) 1 and the second voltage equalizing series circuits 23b2 to 23b2. 23 (n-1) 2 are connected in parallel.

  Also in this example, since the parallel circuit of the reactor and the capacitor connected in parallel in the intermediate stage is combined into a common resistor and connected to the collector of the IGBT, the same effect as in the example shown in FIG. 6 can be obtained. .

  FIG. 10 is a circuit diagram of another example of the semiconductor switch circuit according to the embodiment of the present invention. This example shows a case where the voltage equalizing circuit 22 has three voltage equalizing series circuits 23. That is, in the semiconductor switch circuit, four IGBTs 11a to 11d are connected in series, and each of the voltage equalization circuits 22a to 22d is magnetically coupled to the other three voltage equalization circuits 22 other than itself. Has a reactor.

  Each of the voltage equalizing circuits 22a to 22d includes three voltage equalizing series circuits 23a1 to 23a3, 23b1 to 23b3, 23c1 to 23c3, and 23d1 to 23d3, and these three voltage equalizing series circuits. The resistors 23a1 to 23a3, 23b1 to 23b3, 23c1 to 23c3, and 23d1 to 23d3 share the resistors 18a to 18d, respectively.

  Although FIG. 10 shows a case where four IGBTs 11a to 11d are connected in series, the present invention can be similarly applied to a case where n IGBTs 11a to 11n are connected in series. In this case, each of the voltage equalization circuits 22 a to 22 d has n−1 voltage equalization series circuits 23. In this case as well, the same effect as in the example shown in FIG. 6 can be obtained.

DESCRIPTION OF SYMBOLS 11 ... IGBT, 12 ... Gate drive circuit, 13 ... Gate resistance, 14 ... DC power supply, 15 ... Load, 16 ... Reactor, 17 ... Capacitor, 18 ... Resistance, 19 ... Voltage divider circuit, 20 ... Primary winding, 21 ... Secondary winding, 22 ... Voltage equalization circuit, 23 ... Voltage equalization series circuit

Claims (4)

Three or more voltage-driven semiconductor elements connected in series, a gate driving circuit that supplies a gate signal to the gate of each of the voltage-driven semiconductor elements via a gate resistor, and each of the voltage-driven semiconductor elements A common mode reactor that magnetically couples a connection line between the collector and the gate drive circuit, and a capacitor and a resistor connected in series to the magnetic coupling winding of the reactor, one of which is connected to the collector of each of the voltage-driven semiconductor elements A voltage equalizing circuit connected to each of the gate resistors, and a magnetic coupling between a reactor of at least one voltage equalizing circuit and a reactor of two or more other voltage equalizing circuits other than itself When this is done, the self-voltage equalization circuit will connect capacitors in series to the magnetically coupled windings of each magnetically coupled reactor. Are connected in parallel, and are connected in series to the magnetically coupled windings connected in parallel, one connected to the collector of each of the voltage-driven semiconductor elements and the other connected to each of the gate resistors A semiconductor switch circuit connected to the circuit. 2. The semiconductor switch circuit according to claim 1, wherein a turn ratio of the reactor, a capacitance of a capacitor, or a resistance value of a resistor is selected so that each of the voltage equalizing circuits has the same equivalent circuit. The number of the voltage-driven semiconductor elements connected in series is n (n is 3 or more), and each of the voltage equalization circuits is magnetically coupled with other n-1 voltage equalization circuits other than itself. 3. The semiconductor switch circuit according to claim 1, further comprising n-1 reactors to be coupled. The number of voltage-driven semiconductor elements connected in series is n (n is 3 or more), and the first-stage voltage equalizing circuit is mutually connected to the second-stage voltage equalizing circuit at a one-to-one turn ratio. A capacitor and a resistor are connected in series to a magnetic coupling winding of a magnetically coupled reactor, and an nth stage voltage equalizing circuit is mutually connected with an n−1th stage voltage equalizing circuit at a one-to-one turn ratio. A magnetic coupling winding of a reactor to be magnetically coupled is formed by connecting a capacitor having the same capacitance and a resistor having the same resistance value as the first-stage voltage equalizing circuit in series, and the i-th stage (i = 2 to n−1). The voltage equalization circuit of FIG. 1 is a one-to-one correspondence between the reactor magnetic coupling winding and the (i + 1) th stage voltage equalization circuit, which are magnetically coupled to each other at the 1: 1 turn ratio. Reactor magnetically coupled windings that are magnetically coupled with each other in turn ratio are connected in parallel. A ½ capacitor of the capacitor of the first stage voltage equalization circuit is connected in series to each connected magnetic coupling winding, and the first stage voltage equalization is connected in parallel to the magnetic coupling winding. The semiconductor switch circuit according to claim 1, wherein resistors having the same resistance value as the resistors of the circuit are connected in series.

Images