JP2010192758A - Method of manufacturing semiconductor device - Google Patents

Abstract

A semiconductor device manufacturing method for uniformly annealing a surface of a semiconductor substrate is provided.
A step of implanting a first impurity element into a semiconductor substrate, a film formation step of forming an oxide film or a nitride film to be an insulating film over the semiconductor substrate, and a silicon film over the insulating film are formed. A silicon film forming step, an implantation step of implanting a second impurity element into the silicon film, and irradiating the silicon film into which the second impurity element has been implanted with light having a wavelength shorter than the wavelength of the absorption edge of silicon. By a method of manufacturing a semiconductor device, comprising: a short wavelength light annealing step; and a long wavelength light annealing step of irradiating the silicon film with light having a wavelength longer than the wavelength of the absorption edge of silicon after the short wavelength light annealing step. Solve the above problems.
[Selection] Figure 3

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In order to obtain a fine and high-performance transistor, it is necessary to reduce the parasitic resistance of the source / drain extension. For this purpose, a shallow, low-resistance source / drain extension with a sharp dopant profile is formed. It is necessary to do. However, in RTA (Rapid Thermal Annealing) with an annealing time of about 10 seconds and sRTA (spikeRTA) with an annealing time of about 1 second, the activation rate of the dopant decreases when the annealing temperature is lowered to form a shallow junction. Sheet resistance will increase. Further, when the annealing temperature is raised to lower the sheet resistance, the dopant diffusion increases and the junction becomes deep. For this reason, in recent years, a millisecond annealing technique capable of heating to a temperature exceeding 1200 ° C. in an extremely short time of about 1 msec, such as flash lamp annealing and laser annealing, has been studied (for example, non-patent literature). 1).

  By the way, when heating is performed by irradiating light on a semiconductor substrate on which a pattern such as an electrode is formed, due to a difference in light absorption rate between a region where a pattern such as an electrode is formed and a region where the pattern is not formed, the pattern is changed. Uneven temperature distribution depending on the temperature will occur. For this reason, a semiconductor substrate on which a pattern such as an electrode is formed has a problem that the entire semiconductor substrate cannot be uniformly heated by direct light irradiation. Further, in the annealing by the millisecond annealing technique, since the annealing time is extremely short, the heat diffusion length in the semiconductor substrate being annealed is shorter than the annealing such as RAT. Therefore, annealing by the millisecond annealing technique is more likely to cause unevenness in temperature distribution depending on the pattern than annealing such as RAT.

  As a method for suppressing such uneven temperature distribution in the semiconductor substrate, an absorber film is formed on the surface of the semiconductor substrate and heated, a method of optimizing the pattern arrangement, and p-polarized light is incident at a Brewster angle. There are methods. Among them, the method for optimizing the pattern arrangement is not practical because the shape and arrangement of the pattern are limited, and the method depending on the pattern is not suitable for the method in which p-polarized light is incident at the Brewster angle. The uneven distribution cannot be completely eliminated. Therefore, the most promising method is to form and heat the absorber film. In this method, an absorber film that absorbs light is formed on the surface of a semiconductor substrate on which a pattern has been formed, and this absorber film is irradiated with light for heating. As a result, light can be absorbed uniformly in the absorber film, and the surface of the semiconductor substrate can be heated uniformly without depending on the pattern formed through the absorber film.

  Examples of the material used for such an absorber film include Si, Ti, TiN, Ta, W, Pt, and the like (for example, Patent Documents 1 and 2).

When a CO ₂ laser capable of high-temperature annealing in a short time is used for a semiconductor substrate on which an absorber film is formed, a metal film such as Ti emits light with a wavelength of 10.6 μm of CO ₂ laser light. It will be reflected. In addition, when Si is used as the absorber film, the light having a wavelength of 10.6 μm of the CO ₂ laser beam is light having a wavelength longer than the wavelength at the absorption edge of Si, and thus transmits through the silicon serving as the absorber film. End up.

Special table 2007-525844 US Pat. No. 6,300,208

Akio Shima, Yun Wang, Somit Talwar and Atsushi Hiraiwa, “Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS”, 2004 Symposium on VLSI Technology Digest of Technical Papers.

  In the process of activating the impurities in the silicon substrate using laser annealing, it is necessary to develop an absorber technique for suppressing the diffusion of impurities in the silicon substrate and improving the temperature uniformity of the silicon substrate. .

  According to one aspect of the present embodiment, a step of implanting a first impurity element into a semiconductor substrate, a film formation step of forming an oxide film or a nitride film serving as an insulating film on the semiconductor substrate, and the insulating film A silicon film forming step of forming a silicon film thereon, an injection step of injecting a second impurity element into the silicon film, and a wavelength of an absorption edge of silicon in the silicon film into which the second impurity element has been injected A short-wavelength light annealing step of irradiating light of a short wavelength; and a long-wavelength light annealing step of irradiating the silicon film with light having a wavelength longer than the wavelength of the absorption edge of silicon after the short-wavelength light annealing step. Have.

  According to another aspect of the present embodiment, a step of implanting a first impurity element into a semiconductor substrate, a step of forming an insulating film on the semiconductor substrate, and a thermal CVD method on the insulating film are performed by a thermal CVD method. A step of forming a silicon film containing two impurity elements, and a long-wavelength light annealing step of irradiating the silicon film with light having a wavelength longer than the wavelength of the absorption edge of silicon.

  According to another aspect of the present embodiment, a step of forming a gate electrode on a semiconductor substrate, a step of implanting a first impurity element into the semiconductor substrate using the gate electrode as a mask, and a first impurity A step of forming an insulating film on the semiconductor substrate into which the element is implanted; a step of forming a silicon film containing a second impurity on the insulating film; and a wavelength longer than the absorption edge of silicon in the silicon film A step of irradiating light of a wavelength, and a step of removing the silicon film.

  According to the disclosed method for manufacturing a semiconductor device, the impurity element doped in the semiconductor substrate can be uniformly activated by annealing using light having a wavelength longer than the wavelength at the absorption edge of silicon.

Process drawing (1) of the manufacturing method of the semiconductor device in 1st Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (3) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (4) of the manufacturing method of the semiconductor device in the first embodiment Relationship between the thickness of the silicon film 22 containing the dopant, the transmittance and the absorptance Relationship diagram between etching time by TMAH and film thickness of etched silicon film

  The form for implementing is demonstrated below.

[First Embodiment]
A method for manufacturing the semiconductor device according to the first embodiment will be described. 1 to 4 show steps of a method for manufacturing a CMOS transistor according to the present embodiment. 1A to 4O, the left diagram shows a region where a semiconductor element (transistor) is formed on the semiconductor substrate, and the right diagram shows a resistor element formed on the semiconductor substrate. It shows the area to be.

  First, as shown in FIG. 1A, an element isolation region 2 that defines an n-channel active region 3 and a p-channel active region 4 is formed in a silicon substrate 1 that is a semiconductor substrate. For example, an oxide film and a nitride film are stacked on the silicon substrate 1 and patterned using a resist pattern to form a nitride film pattern. Next, using this nitride film pattern as a mask, the silicon substrate is etched to form shallow trenches (grooves) for element isolation. After that, if necessary, an oxide film and a nitride film liner are formed on the trench surface, and the formed trench is filled with an oxide film formed by a high-density plasma (HDP) chemical vapor deposition method (CVD method). The oxide film to be formed is removed by chemical mechanical polishing (CMP). In this way, the element isolation region 2 is formed by shallow trench isolation (STI). Next, a p-type impurity is implanted into the n-channel active region 3 to form a p-well (n-channel region) 3a, and an n-type impurity is implanted into the p-channel active region 4 to form an n-well (p-channel region). 4a is formed. Next, the surfaces of the n-channel active region 3 and the p-channel active region 4 are thermally oxidized, and nitrogen is introduced as necessary to form the gate insulating film 5. Thereafter, a polycrystalline silicon film is deposited on the gate insulating film 5 by a CVD method, a resist mask is formed, and then etching is performed to form gate electrodes 6a and 6b. The element isolation region 2 is formed in the same manner also in the region where the resistance element is formed.

Next, as shown in FIG. 1B, a resist mask 7 covering the p-channel active region 4 is formed. Thereafter, in the n-channel active region 3 exposed from the resist mask 7, the gate electrode 6a is used as a mask and boron (B), which is a p-type impurity, is contrasted at a tilt angle of 0 ° to 45 ° on both sides of the gate electrode 6a. Inject from 4 directions. The acceleration energy at this time is 3 keV to 10 keV, and the dose amount is 5 × 10 ¹² cm ⁻² to 2 × 10 ¹³ cm ⁻² , thereby forming the p-type pocket region 11. Note that the tilt angle indicates the angle in the case of ion implantation from four contrasting directions. The dose amount indicates a dose amount from one direction, and the total dose amount when ions are implanted from four directions is four times the dose amount. Indium (In) may be used as the p-type impurity. When indium is used, ions are implanted from four contrasting directions with a tilt angle of 0 ° to 45 ° with an acceleration energy of 30 keV to 100 keV and a dose of 5 × 10 ¹² cm ⁻² to 2 × 10 ¹³ cm ⁻² . The resist mask 7 is similarly formed in the region where the resistance element is formed.

Next, as shown in FIG. 1C, ion implantation for forming an n-type extension region is performed. Specifically, n-type impurities, here arsenic (As), are ion-implanted into the n-channel active region 3 exposed from the resist mask 7 using the gate electrode 6a as a mask on both sides of the gate electrode 6a. Region 13 is formed. The conditions for ion implantation of arsenic are as follows: acceleration energy 1 keV to 5 keV (may be 0.5 keV to 10 keV), dose 5 × 10 ¹⁴ cm ⁻² to 2 × 10 ¹⁵ cm ⁻² , tilt angle 0 ° to 10 ° (0 It may be from 30 ° to 30 °. As the n-type impurity, phosphorus (P) may be used. The conditions for phosphorus ion implantation are acceleration energy of 0.5 keV to 3 keV (may be 0.3 keV to 5 keV), a dose of 5 × 10 ¹⁴ cm ⁻² to 2 × 10 ¹⁵ cm ⁻² , and a tilt angle of 0 ° to It is 10 ° (may be 0 ° to 30 °). Thereafter, the resist mask 7 is removed.

Next, as shown in FIG. 1D, a resist mask 8 covering the n-channel activation region 3 is formed. After that, in the p-channel active region 4 exposed from the resist mask 8, the gate electrode 6b is used as a mask and antimony (Sb), which is an n-type impurity, is contrasted with a tilt angle of 0 ° to 45 ° on both sides of the gate electrode 6b. Inject from 4 directions. The acceleration energy at this time is 30 keV to 100 keV, and the dose is 5 × 10 ¹² cm ⁻² to 2 × 10 ¹³ cm ⁻² , thereby forming the n-type pocket region 14. As the n-type impurity, arsenic or phosphorus may be used instead of antimony. The resist mask 8 is formed in the same manner in the region where the resistance element is formed.

Next, as shown in FIG. 2E, ion implantation for forming a p-type extension region is performed. Specifically, boron (B), which is a p-type impurity, is ion-implanted into both sides of the gate electrode 6b into the p-channel active region 4 exposed from the resist mask 8 using the gate electrode 6b as a mask. 16 is formed. The boron ion implantation conditions were acceleration energy of 0.5 keV or less (or 1 keV or less), a dose of 1 × 10 ¹⁴ cm ⁻² to 2 × 10 ¹⁵ cm ⁻² , and a tilt angle of 0 ° to 10 ° (0 It may be from 30 ° to 30 °. Thereafter, the resist mask 8 is removed.

  Next, as shown in FIG. 2F, a silicon oxide film is deposited on the entire surface by a CVD method or the like, and this silicon oxide film is anisotropically etched (etched back), so that the silicon oxide film is removed from each gate electrode. Sidewalls 9 are formed so as to remain only on the side surfaces of 6a and 6b.

Next, as shown in FIG. 2G, deep source / drain regions (deep SD regions) are respectively formed in the n-channel active region 3 and the p-channel active region 4 using a resist mask. Specifically, a resist mask that opens only in the n-channel active region 3 is formed, the gate electrode 6a and the sidewall 9 are used as a mask in the n-channel active region 3, and phosphorous that is an n-type impurity is formed on both sides of the gate electrode 6a. (P) is ion-implanted to form a deep SD region 17. The conditions for the ion implantation of phosphorus are acceleration energy of 5 keV to 20 keV (may be 1 keV to 20 keV), dose amount 2 × 10 ¹⁵ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² (2 × 10 ¹⁵ cm ⁻² to 2 × 10 ¹⁶ cm ⁻² ), and a tilt angle of 0 ° to 10 ° (may be 0 ° to 30 °). Thereafter, the formed resist mask is removed. Arsenic may be used as the n-type impurity. Next, a resist mask in which only the p-type channel active region 4 is opened is formed. Thereafter, boron (B), which is a p-type impurity, is ion-implanted into both sides of the gate electrode 6b into the p-channel active region 4 exposed from the resist mask, using the gate electrode 6b and the sidewall 9 as a mask. 18 is formed. The boron ion implantation conditions are acceleration energy of 2 keV to 5 keV, a dose of 2 × 10 ¹⁵ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² , and a tilt angle of 0 ° to 10 °. Thereafter, the formed resist mask is removed. BF ₂ ⁺ may be used as the p-type impurity ions. Similarly, in the region where the resistance element is formed, the deep region 27 is formed by performing the ion implantation of phosphorus, which is an n-type impurity, or the ion implantation of boron, which is a p-type impurity, in the above process.

Next, as shown in FIG. 3H, an insulating film 21 as an etch stop film is formed to a thickness of about 1 to 20 nm, here 10 nm. The insulating film 21 is a film made of a material having high selectivity for etching with Si, and is, for example, an oxide film or a nitride film. The insulating film 21 is formed at a low temperature such that the implanted impurity does not diffuse in the n-type extension region 13, the p-type extension region 14, and the deep SD regions 17 and 18, for example, a temperature of 500 ° C. or less. . When disilane (Si ₂ H ₆ ) and N ₂ O are used, a film can be formed at a rate of about 5 nm / min at 500 ° C.

Next, as shown in FIG. 3I, after a silicon film 22 of about 100 nm is formed on the insulating film 21, phosphorus ions are implanted. The silicon film 22 is formed at a low temperature such that the implanted impurity does not diffuse in the n-type extension region 13, the p-type extension region 14, and the deep SD regions 17 and 18, for example, a temperature of 500 ° C. or less. . Specific examples of the film forming method include a sputtering method using a silicon target, a thermal CVD method using a silane (SiH ₄ ) gas or a disilane (Si ₂ H ₆ ) gas, and a plasma CVD method. When disilane (Si ₂ H ₆ ) is used, the film can be formed at a rate of about 12 nm / min at 480 ° C. Further, after the silicon film 22 is formed, if unevenness is formed on the surface, a planarization process is performed by CMP or the like. Thereafter, an impurity element is added as a dopant into the silicon film 22 by ion implantation. However, the ion implantation is performed under such a condition that the impurity element does not reach the gate electrodes 6 a and 6 b and the silicon substrate 1. At this time, phosphorus, arsenic, boron, or the like is suitable as an impurity element used for ion implantation. These impurity elements are most suitable because they have a high activation rate in silicon, and in particular, phosphorus has a high solid solubility limit in silicon. Further, the impurity concentration of the silicon film 22 in the ion implantation is preferably 1 × 10 ²⁰ cm ⁻³ or more.

Next, as shown in FIG. 3J, heat treatment is performed for about 0.1 to 100 seconds. This heat treatment is performed by optimizing the formed CMOS transistor, and the silicon substrate 1 and the silicon film 22 are heated at 800 to 1000 ° C. for about 1 second in order not to diffuse impurities in the semiconductor substrate 1 more than necessary. Is done. Under such annealing conditions, the activation rate of impurities in the semiconductor substrate 1, particularly boron and arsenic, is low, and it is difficult to lower the resistance value to a desired value, but the impurities implanted into the silicon film 22, For example, phosphorus can generate carriers with a concentration exceeding 5 × 10 ²⁰ cm ⁻³ . A light source in the case of spike annealing using lamp annealing for this heat treatment is, for example, a tungsten halogen lamp, and contains a lot of light components having a wavelength shorter than the wavelength 1117 nm at the absorption edge of silicon. Since light having a wavelength shorter than the wavelength at the absorption edge of silicon is directly absorbed by the silicon film 22, the silicon film 22 functions as an absorber. Therefore, the surface of the semiconductor substrate can be heated uniformly without depending on the pattern formed in this heat treatment. Impurities implanted into the silicon film 22 by this spike annealing are diffused and activated in the silicon film 22. As the light source used in this step, a light source other than a tungsten halogen lamp can be used as long as it emits light shorter than the wavelength of the absorption edge of silicon. Further, when the ion-implanted impurity element is phosphorus or arsenic, it is easily diffused outward by spike annealing. Therefore, by performing spike annealing in a nitrogen atmosphere containing oxygen, or by performing spike annealing after forming an oxide film on the surface of the silicon film 22, the outward diffusion of impurity elements is suppressed, A decrease in impurity concentration can be prevented.

Next, as shown in FIG. 3 (k), millisecond annealing is performed by irradiating CO ₂ laser light of about 1 msec. The wavelength of the CO ₂ laser light is 10.6 μm, which is light having a wavelength longer than the wavelength 1117 nm of the absorption edge of silicon. Thus, although light is transmitted in the case of silicon alone, CO ₂ laser light is absorbed by free carriers because a high concentration impurity element is diffused and activated by the spike annealing described above. Therefore, even light having a wavelength longer than the wavelength at the absorption edge of silicon is absorbed and functions as an absorber film. The irradiated CO ₂ laser light is absorbed by the silicon film 22 in which the impurities are activated and converted into heat, and the heat is transmitted to the silicon substrate 1 through the insulating film 21 and passes through the surface of the silicon substrate 1. Heat evenly. By this millisecond annealing with CO ₂ laser light, the silicon substrate 1 is heated to 1200 to 1300 ° C., which is higher than the heat treatment performed in FIG. Therefore, the impurities implanted in the n-type extension region 13 and the p-type extension region 14 and the deep SD regions 17 and 18 on the surface of the silicon substrate 1 can be activated to a high concentration. The millisecond annealing time is performed by optimizing the time depending on the formed CMOS transistor, and is performed, for example, in the range of 0.1 msec to 100 msec. The spike annealing is for the purpose of diffusion and activation of impurities in the silicon film 22, and the millisecond annealing is for the purpose of activation of impurities in the silicon substrate 1. Therefore, the temperature in the silicon substrate 1 is higher in the millisecond annealing than in the spike annealing. In this way, by activating the impurities in the semiconductor substrate 1 by combining two annealings, it becomes possible to reduce the resistance of the source / drain extension part while keeping the junction depth of the source / drain extension part shallow. A fine and high-performance transistor can be obtained. In addition, crystal defects (damage) of the semiconductor substrate 1 generated when various impurities are ion-implanted into the semiconductor substrate 1 in spike annealing can be recovered. Further, the impurities implanted into the semiconductor substrate 1 can be appropriately diffused.

  Next, as shown in FIG. 4L, the silicon film 22 is peeled off. Specifically, by using organic alkali or strong alkali, the silicon film 22 can be etched without etching the oxide film or the nitride film. As will be described later, when TMAH is used as the organic alkali, the impurity element serving as a dopant in the silicon film 22 is preferably phosphorus or arsenic. In addition to the wet etching described above, the silicon film 22 can also be removed by dry etching.

  Next, as shown in FIG. 4M, the insulating film 21 is removed. At this time, the silicide block film 21a can be formed using the insulating film 21 in the region where the resistance element is formed. Specifically, a resist mask is formed on the insulating film 21, leaving the insulating film 21 in a desired shape, and the remaining insulating film 21 can be used as the silicide block film 21a.

  Next, as shown in FIG. 4N, a silicide metal, for example, nickel (Ni) is formed by sputtering to form a silicide metal film 23.

  Next, as shown in FIG. 4 (o), by performing heat treatment at a temperature of 200 ° C. to 250 ° C. for about 1 to 3 minutes, silicon and deep SD regions 17 and 18 on the surfaces of the gate electrodes 6a and 6b and The silicide layer 24 is formed by reacting silicon and nickel on the surface of the deep region 27. Thereafter, unreacted nickel may be removed by wet etching, and annealing may be performed at 350 ° C. to 450 ° C. for 1 to 3 minutes in order to reduce the resistance of the silicide layer. As a result, in the region where the resistance element is to be formed, the resistance element having the deep region 27 under the silicide block film 21a as the resistance portion is formed.

  Thereafter, a CMOS transistor is manufactured through processes such as formation of a contact etch stopper film, formation of an interlayer insulating film covering the entire surface, formation of contact holes and a wiring layer for embedding the contact holes. In addition to the step shown in FIG. 2G, the ion implantation in the region where the resistance element is formed may be the step shown in FIGS. 1B and 1C, or FIG. Further, the diffusion layer region 27 can be formed in the same manner by performing the steps shown in FIG.

In general, the oxide film and the nitride film used as the insulating film 21 used in the method for manufacturing a semiconductor device in the present embodiment have a thermal conductivity lower than that of silicon. For this reason, in order to transmit heat uniformly and efficiently to the surface of the silicon substrate 1 by heat treatment by irradiation with CO ₂ laser light shown in FIG. On the other hand, when removing the silicon film 22 shown in FIG. 4L, it is necessary to protect the surface of the silicon substrate 1, and impurities in the silicon film 22 are caused by spike annealing or millisecond annealing. It is necessary to prevent it from spreading. Therefore, the insulating film 21 needs to have a sufficient thickness.

Also, the injection amount of an impurity element into the silicon film 22 shown in FIG. 3 (i), increasing the amount of injected impurity element, by the carrier concentration after activation annealing is increased, the wavelength of CO ₂ laser light It is known that the absorption coefficient of the silicon film 22 at a certain 10.6 μm increases.

The absorption coefficient here is a constant indicating how much light the medium absorbs when it enters a certain medium, and the intensity I of light when traveling through a medium with an absorption coefficient α by a distance d is When the intensity of light before entering the medium is I ₀ , the following equation (1) is obtained.
I = I ₀ e ^-αd (1)

Specifically, the absorption coefficient when the carrier concentration in silicon is 1 × 10 ²⁰ cm ⁻³ is 4 × 10 ⁴ cm ⁻¹ , and the absorption coefficient when the carrier concentration is 5 × 10 ²⁰ cm ⁻³ is 4 × 10 ⁵ cm ⁻¹ units. If the carrier concentration is 4 × 10 ⁵ cm ⁻¹ , 90% or more of light can be absorbed with a film thickness of about 100 nm. Therefore, it is preferable that the carrier concentration in the silicon film 22 is 5 × 10 ²⁰ cm ⁻³ or more at which the absorption coefficient is 4 × 10 ⁵ cm ⁻¹ or more. Since the carrier concentration in the silicon film does not become higher than the impurity concentration, it is necessary to increase the amount of impurity implantation to a required carrier concentration. When the silicon film thickness is 100 nm, if an impurity of 1 × 10 ¹⁶ cm ⁻³ is implanted to prevent the loss of impurities due to outward diffusion in the RTA, the average concentration in the silicon film is 1 × 10 ²¹ cm ^−3. Can be filled with impurities.

FIG. 5 shows the relationship between the thickness of the silicon film 22 to be formed and the absorption rate in the silicon film 22 when irradiated with CO ₂ laser light. As shown in this figure, when the carrier concentration in the silicon film 22 is 5 × 10 ²⁰ cm ⁻³ , the formed silicon film 22 has a film thickness of 100 nm and an absorptance of 90% or more, which is efficient. Uniform heating can be performed. Further, since the thickness of the silicon film 22 can be increased to absorb more light, the thickness of the formed silicon film 22 is preferably 100 nm or more.

  However, the heat diffusion length of Si during annealing on the order of milliseconds is about 100 μm, and if the film thickness is sufficiently smaller than the diffusion length, the temperature in the absorber can be regarded as almost constant, If the diffusion length is equal to or thicker than the diffusion length, a temperature gradient (temperature decrease) occurs in the absorber, and even if the absorber surface is heated to 1300 ° C or higher, the temperature of the semiconductor element formed on the semiconductor substrate surface is sufficiently high. Therefore, it is desirable that the film thickness be sufficiently thinner than the heat diffusion length, for example, within 1 μm.

  FIG. 6 shows the relationship between the etching time and the etching amount of TMAH (tetramethylmethylammonium hydroxide) in polysilicon. As shown in this figure, compared with non-doped silicon, silicon doped with arsenic and phosphorus is easily etched by TMAH, and silicon doped with boron is hardly etched by TMAH. For this reason, when etching the silicon film 22 by TMAH, it is preferable to dope arsenic or phosphorus.

[Second Embodiment]
Next, a second embodiment will be described. In the second embodiment, in place of the formation of the silicon film 22 and the ion implantation and spike annealing in the first embodiment, a semiconductor device in which the silicon film 22 mixed with impurities is formed by a thermal CVD method is manufactured. Is the method.

Specifically, a silicon film 22 containing an impurity is formed by thermal CVD for those formed up to FIG. 3H in the first embodiment. As a method for forming the silicon film 22 containing impurities by a thermal CVD method, there is a method of forming a film at a substrate temperature of 500 to 550 ° C. using monosilane (SiH ₄ ) and phosphine (PH ₃ ) as raw materials. As another method, there is a method of forming a film at a substrate temperature of 400 to 550 ° C. using disilane (Si ₂ H ₆ ) and phosphine (PH ₃ ) as raw materials. If the substrate temperature of the silicon substrate 1 is 600 ° C. or less, the diffusion of the implanted impurities in the silicon substrate 1 is hardly affected. In addition to the above monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ), dichlorosilane (SiH ₂ Cl ₂ ), tetrachlorosilane (SiCl ₄ ), and hexachlorodisilane (Si ₂ Cl ₆ ) can also be used. It is.

Thereafter, the first embodiment is performed by performing the steps after the step of performing the millisecond annealing by irradiating the CO ₂ laser light of about 1 msec shown in FIG. 3 (k) in the first embodiment. A semiconductor device can be manufactured in the same manner as described above. In this embodiment mode, a silicon film containing impurities formed by a thermal CVD method is normally activated immediately after film formation, and therefore absorbs light having a wavelength longer than that of the absorption edge of silicon. Therefore, it is possible to perform millisecond annealing for irradiating light having a long wavelength without performing spike annealing for irradiating light having a shorter wavelength than the absorption edge of silicon.

  Although the embodiment has been described in detail above, it is not limited to the specific embodiment, and various modifications and changes can be made within the scope described in the claims.

Regarding the above description, the following additional notes are disclosed.
(Appendix 1)
Injecting a first impurity element into the semiconductor substrate;
A film forming step of forming an oxide film or a nitride film serving as an insulating film on the semiconductor substrate;
A silicon film forming step of forming a silicon film on the insulating film;
An implantation step of implanting a second impurity element into the silicon film;
A short wavelength light annealing step of irradiating the silicon film into which the second impurity element is implanted with light having a wavelength shorter than the wavelength of the absorption edge of silicon;
After the short wavelength light annealing step, a long wavelength light annealing step of irradiating the silicon film with light having a wavelength longer than the wavelength of the absorption edge of silicon,
A method for manufacturing a semiconductor device, comprising:
(Appendix 2)
2. The method of manufacturing a semiconductor device according to appendix 1, wherein the concentration of the second impurity element implanted into the silicon film in the implantation step is 1 × 10 ²⁰ cm ⁻³ or more.
(Appendix 3)
3. The method of manufacturing a semiconductor device according to appendix 1 or 2, wherein a light source used in the short wavelength light annealing step is a tungsten halogen lamp.
(Appendix 4)
4. The method for manufacturing a semiconductor device according to any one of appendices 1 to 3, wherein the light irradiation time in the long wavelength light annealing step is shorter than the light irradiation time in the short wavelength light annealing step.
(Appendix 5)
The short wavelength light annealing step is performed at a first temperature, the long wavelength light annealing step is performed at a second temperature, and the second temperature is higher than the first temperature. 5. A method for manufacturing a semiconductor device according to any one of 1 to 4.
(Appendix 6)
Injecting a first impurity element into the semiconductor substrate;
Forming an insulating film on the semiconductor substrate;
Forming a silicon film containing a second impurity element on the insulating film by a thermal CVD method;
A long wavelength light annealing step of irradiating the silicon film with light having a wavelength longer than the wavelength of the absorption edge of silicon;
A method for manufacturing a semiconductor device, comprising:
(Appendix 7)
7. The method of manufacturing a semiconductor device according to any one of appendices 1 to 6, further comprising a silicon film removing step of removing the silicon film after the long wavelength light annealing step.
(Appendix 8)
The method of manufacturing a semiconductor device according to appendix 7, wherein the silicon film removing step is etching using TMAH.
(Appendix 9)
9. The method of manufacturing a semiconductor device according to any one of appendices 1 to 8, wherein an element isolation region and an electrode are formed on a surface of the semiconductor substrate.
(Appendix 10)
10. The method for manufacturing a semiconductor device according to any one of appendices 1 to 9, wherein the second impurity element is any one of boron, phosphorus, and arsenic.
(Appendix 11)
11. The method of manufacturing a semiconductor device according to any one of appendices 1 to 10, wherein the thickness of the silicon film is 100 nm or more.
(Appendix 12)
12. The method of manufacturing a semiconductor device according to any one of appendices 1 to 11, wherein a light source used in the long wavelength light annealing step is a CO ₂ laser.
(Appendix 13)
The semiconductor substrate is a silicon substrate;
After the silicon film removing step, an insulating film removing step for removing a part of the insulating film on the silicon substrate.
A silicide metal film forming step of forming a silicide metal film on the surface of the remaining insulating film and the silicon substrate;
A silicidation step of forming a silicide layer by reacting silicon on the surface of the silicon substrate with the silicide metal by heat treatment;
A silicide metal removal step of removing the silicide metal that was not silicided in the silicidation step;
The method for manufacturing a semiconductor device according to any one of appendices 7 to 12, characterized in that:
(Appendix 14)
Forming a gate electrode on the semiconductor substrate;
Implanting a first impurity element into the semiconductor substrate using the gate electrode as a mask;
Forming an insulating film on the semiconductor substrate implanted with the first impurity element;
Forming a silicon film containing a second impurity on the insulating film;
Irradiating the silicon film with light having a wavelength longer than the wavelength of the absorption edge of silicon;
Removing the silicon film;
A method for manufacturing a semiconductor device, comprising:

1 Silicon substrate 2 STI
3 n channel active region 3a p well (n channel region)
4 p channel active region 4a n well (p channel region)
5 Gate insulating films 6a and 6b Gate electrodes 7 and 8 Resist mask 9 Side wall 11 p-type pocket region 13 n-type extension region 14 n-type pocket region 16 p-type extension regions 17 and 18 Deep SD region 21 Insulating film 22 Silicon film 23 Silicide metal film 24 Silicide layer 27 Deep region

Claims (7)

Injecting a first impurity element into the semiconductor substrate;
A film forming step of forming an oxide film or a nitride film serving as an insulating film on the semiconductor substrate;
A silicon film forming step of forming a silicon film on the insulating film;
An implantation step of implanting a second impurity element into the silicon film;
A short wavelength light annealing step of irradiating the silicon film into which the second impurity element is implanted with light having a wavelength shorter than the wavelength of the absorption edge of silicon;
After the short wavelength light annealing step, a long wavelength light annealing step of irradiating the silicon film with light having a wavelength longer than the wavelength of the absorption edge of silicon,
A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the implantation step, a concentration of the second impurity element implanted into the silicon film is 1 × 10 ²⁰ cm ⁻³ or more.   The short wavelength light annealing step is performed at a first temperature, the long wavelength light annealing step is performed at a second temperature, and the second temperature is higher than the first temperature. Item 3. A method for manufacturing a semiconductor device according to Item 1 or 2. Injecting a first impurity element into the semiconductor substrate;
Forming an insulating film on the semiconductor substrate;
Forming a silicon film containing a second impurity element on the insulating film by a thermal CVD method;
A long wavelength light annealing step of irradiating the silicon film with light having a wavelength longer than the wavelength of the absorption edge of silicon;
A method for manufacturing a semiconductor device, comprising:   5. The method of manufacturing a semiconductor device according to claim 1, further comprising a silicon film removing step of removing the silicon film after the long-wavelength light annealing step. 6.   6. The method of manufacturing a semiconductor device according to claim 1, wherein the second impurity element is any one of boron, phosphorus, and arsenic. Forming a gate electrode on the semiconductor substrate;
Implanting a first impurity element into the semiconductor substrate using the gate electrode as a mask;
Forming an insulating film on the semiconductor substrate implanted with the first impurity element;
Forming a silicon film containing a second impurity on the insulating film;
Irradiating the silicon film with light having a wavelength longer than the wavelength of the absorption edge of silicon;
Removing the silicon film;
A method for manufacturing a semiconductor device, comprising:

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