JP2010192610A - Method of manufacturing and method of inspecting base material for printed wiring board having multiple development patterns formed, method of manufacturing and method of inspecting multiple-patterned printed wiring board, method of manufacturing semiconductor device, and exposure mask - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily decide that the amount of a relative position shift between wiring patterns as adjacent units formed on a multiple-patterned printed wiring board is to exceed or has exceeded a prescribed value without using a measuring machine etc., increasing the number of processes, nor increasing the cost. <P>SOLUTION: A photosensitive resin film 5 on a base material 3 for a printed wiring board is exposed through an exposure mask 6 to form an exposed pattern part 22a and an unexposed pattern part 21a for position precision decision making, and the base material 3 is fed in steps to form an unexposed pattern part 21a having smaller area than the exposed pattern part 22a at a position corresponding to the exposed pattern part 22a and an exposed pattern part 22a having larger area than the unexposed pattern part 21a at a position corresponding to the unexposed pattern part 21a. When the amount of the relative position shift between adjacent units exceeds the prescribed value K, part of the unexposed pattern part is left as an unexposed pattern 23 for position shift decision making and developed to form a developed pattern 23a for position shift decision making. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for producing a multi-sided printed wiring board in which a large number of wiring patterns per unit are formed, such as a rigid wiring board, a flexible printed wiring board, a TAB (Tape Automated Bonding) tape, and a COF (Chip On Film) tape, The present invention also relates to an inspection method for a multi-sided printed wiring board that inspects whether or not the relative positional deviation between adjacent unit patterns exceeds a specified value. In addition, the present invention relates to a manufacturing method and an inspection method for a substrate for a printed wiring board on which a multi-sided development pattern is formed in the manufacturing process of such a multi-sided printed wiring board. In addition, the present invention relates to an exposure mask used in a method for producing a substrate for printed wiring boards on which a multi-sided development pattern is formed. The present invention also relates to a method for manufacturing a semiconductor device in which mounting of a semiconductor element is determined using an inspection method for a multi-sided printed wiring board.

  In recent years, printed wiring boards have tended to be miniaturized and miniaturized, and the area has been increased by widening or lengthening the base material in order to improve productivity and reduce the cost of the base material. A multi-sided printed wiring board is manufactured in which the number of impositions of the wiring pattern is increased, and an electrical continuity test is performed on the formed multi-sided printed wiring board.

  Conventionally, a multi-sided COF tape, which is a multi-sided printed wiring board, has been manufactured, for example, as shown in FIGS. First, as shown in FIG. 11 (A), a printed wiring board base material 103 is prepared in which a conductor 102 for forming a wiring pattern is provided in a solid shape on the surface of an insulating base material 101, as shown in FIG. Then, a sprocket hole 104 is punched out along both edges using a mold or the like, and then a photosensitive resin is applied to the surface of the conductor 102 and dried as shown in FIG. 11C. A film 105 is formed.

  Then, using the exposure mask 106 shown in FIG. 12, the sprocket hole mask pattern 114 formed on the exposure mask 106 and the above-described sprocket hole 104 are recognized by an optical recognition device so that their positions overlap each other. After positioning by performing position control, exposure is performed by irradiating exposure light beam 107 through exposure mask frame 130 as shown in FIG. In the exposure mask 106 shown in FIG. 12, the portion without hatching is the translucent portion 106A, and the portion with hatching is the light shielding portion 106B. When exposure is performed in this way, the exposure resin 106 is exposed to the photosensitive resin film 105. Since no light is applied to the projected portion 106 of the wiring pattern mask pattern 108A, an unexposed wiring pattern portion 108a that is not exposed is generated as shown in FIG. 11D.

  Thereafter, the printed wiring board substrate 103 having the exposed photosensitive resin film 105 is stepped and conveyed by an amount corresponding to the unit pattern region A dimension of the exposure mask 106 shown in FIG. Then, the sprocket hole mask pattern 114 and the sprocket hole 104 provided on the exposure mask 106 are recognized by the optical recognition device, and the position is controlled so that the sprocket hole mask pattern 114 and the sprocket hole 104 overlap each other. Thereafter, exposure is performed by irradiating the exposure light beam 107 again.

  By repeating these steps, a large number of unexposed wiring pattern portions 108a are generated for each unit, and then development is performed to form a wiring development pattern 108c as shown in FIG. 11E. The unexposed photosensitive resin film 105 is also left as the reinforcing pattern development pattern 108f, and the substrate 109 for the printed wiring board on which the multi-sided development pattern is formed is formed.

  In general, a positive type in which a portion of the photosensitive resin film exposed by exposure to light is exposed by the development process and a photosensitive resin film in an unexposed state in a portion not exposed to the exposure light are developed. Although there is a negative type that is removed by processing, the above description is a positive type in which the photosensitive resin film 105 is removed by development processing.

  Next, the wiring development pattern 108c and the reinforcing pattern development pattern 108f are used as an etching resist, and the conductor 102 is etched. Then, the etching resist is removed with an alkaline solution. As a result, as shown in FIG. 11 (F), a plurality of wiring patterns 108d for each unit and a test pad portion 108e as a part thereof are arranged in the length direction of the insulating base material 101 on the surface of the insulating base material 101. At the same time, the reinforcing pattern 108g is formed, and the multi-sided COF tape 110, on which, for example, tin plating 126 necessary for rust prevention and connection of semiconductor elements is applied, is completed. FIG. 13 shows the plane of the multi-sided COF tape 110. FIG. 11F is an arrow direction cross section along the line D4-D4.

  However, the sprocket holes 104 are generally formed by punching near the both ends of the printed wiring board substrate 103 using a die. The insulating base material 101 constituting the punched printed wiring board base material 103 uses polyimide or the like, so that it expands and contracts under the influence of humidity. Therefore, the dimension between the sprocket holes 104 formed on the printed wiring board base material 103 may differ from the design value during exposure.

  Further, the sprocket hole 104 may generate burrs, whiskers, debris, etc. by punching with a mold, and the sprocket hole 104 may be deformed through a processing step before the exposure step. Therefore, even if it is recognized by the optical recognition device and the position is controlled so that the sprocket hole mask pattern 114 and the sprocket hole 104 overlap, the relative position between the printed wiring board base material 103 and the exposure mask 106 is increased. Misalignment may occur.

  When a relative deviation occurs in the positional relationship between the printed wiring board substrate 103 and the exposure mask 106, a positional deviation also occurs in the positional relationship between the adjacent wiring patterns 108d. In FIG. 13, when exposure is performed in the order of the unit pattern areas A1 to A2 using the conventional exposure mask 106, a relative positional deviation also occurs in the positional relationship between the wiring pattern 108d groups formed for each unit. , A state deviated by + α from the specified value K of the relative positional deviation amount, that is, a state deviated by K + α. Here, the specified value K of the relative positional deviation amount is a value determined in order to prevent the probe pin from being detached from the test pad portion 108e during the subsequent continuity test.

  By the way, the multi-sided COF tape 110 shown in FIG. 13 formed in this way is generally inspected by using an appearance inspection device using an optical recognition device. However, if a short 108h due to a fine wire that exceeds the resolution limit of the optical recognition device has occurred, there is a possibility that the short 108h is not detected and an erroneous determination is made. Therefore, after the inspection by the appearance inspection apparatus, the continuity inspection is performed by bringing the probe pin into contact with the test pad portion 108e which is a part of the wiring pattern 108d.

  In this continuity test, in order to increase the efficiency of the test, for example, a contact position 120 of the probe pin shown in FIG. 13, for example, two unit wiring patterns 108d formed in the unit pattern areas A2 and A3. Simultaneously, the probe pins are simultaneously brought into contact with the test pad portion 108e. In order to further increase the efficiency, this continuity test may be performed simultaneously on a group of wiring patterns 108d of three or more units.

  However, in the illustrated example, the relative positional deviation amount between the wiring pattern 8d groups for each unit formed in the unit pattern areas A2 and A3 is a predetermined value determined to prevent the probe pin from being detached from the test pad portion 108e. It is larger than K by + α, and shows a state in which the probe pin is detached from the test pad portion 108e. Therefore, in the case of the illustrated example, there is a problem that the continuity test cannot be accurately performed. Even if a short 108h is generated between the wiring patterns 108d and an electrical short circuit occurs, there is a problem in that the short circuit is not judged as a defective product and is erroneously judged as a good product. In this example, the continuity test is only a short test, and an open test is not performed.

  The probe pin contact position 120 shown in FIG. 13 shows a state when the probe pin is positioned by recognizing the test pad portion 108e of the wiring pattern 108d for each unit formed in the unit pattern region A2. It is. Although not shown, when the test pad portion 108e of the wiring pattern 108d for each unit formed in the unit pattern region A3 is recognized and the probe pin is positioned, the test pad formed in the unit pattern region A2 is used. There arises a problem that the probe pin is detached from the portion 8e.

  Now, in the multi-sided COF tape 110 manufactured as shown in FIG. 11 (F) or FIG. 13, a semiconductor element 111 is mounted for each unit pattern region A as shown in FIG. The semiconductor device 127A for each unit is formed by being connected to the wiring pattern 108d through the gold bump 112 and sealed with the sealing resin 113, and the multi-faced semiconductor device 127 is manufactured. FIG. 14 shows a plane of the multifaceted semiconductor device 127. FIG. 11G is an arrow direction cross section along the D5-D5 line.

  Therefore, as shown in FIG. 14, for example, the wiring pattern 108d for each unit formed in the unit pattern area A3 is correctly defective because the short 108h has occurred, but is erroneously determined to be a good product by the continuity test. Therefore, there is a problem that the semiconductor element 111 is mounted and is wasted.

  By the way, after mounting a large number of semiconductor elements 111 and forming the multi-faced semiconductor device 127, the probe pin is brought into contact with the test pad portion 108e to perform an electrical inspection. In order to increase the efficiency of the inspection, For example, as in the probe pin contact position 120 shown in FIG. 14, the probe pin may be simultaneously contacted with the test pad portion 108e formed in the unit pattern areas A2 and A3, and an electrical inspection may be performed simultaneously. . In order to further increase the efficiency, an electrical inspection may be simultaneously performed on the semiconductor device 127A of every three or more units.

  In such a case, the wiring pattern 108d for each unit formed in the unit pattern area A3 is relatively shifted from the wiring pattern 108d for each unit formed in the unit pattern area A2 by S1. When the A2 test pad portion 108e is recognized and positioned and the probe pin is brought into contact, the probe pin is removed from the test pad portion 108e formed in the unit pattern region A3, and electrical inspection cannot be performed. Therefore, it is determined to be defective. Since the semiconductor device 127A for each unit has a short 108h and is defective, there is no problem with the defect determination, but there is a problem that the semiconductor element 111 that has already been mounted is wasted.

  Conversely, when the test pad portion 108e formed in the unit pattern region A3 is recognized and the probe pin is brought into contact with the reference portion 108e as a reference, the probe pin is detached from the test pad portion 108e formed in the unit pattern region A2. It will be. For this reason, even if the semiconductor device 127A for each unit formed in the pattern region A2 is a non-defective product, there is a problem that electrical inspection cannot be performed and a failure is determined.

  As described above, according to the conventional technique, even if the relative positional deviation amount between the adjacent wiring pattern 108d groups for each unit exceeds the specified value, it cannot be determined as defective, and as a result, the wiring pattern 108d group for each unit. There is a problem that the semiconductor element 111 is wasted and the semiconductor element 111 is wasted.

  Incidentally, an exposure method using an exposure original drawing substrate (exposure mask) as described in Patent Document 1 has been proposed in the prior art. Specifically, for example, as shown in FIGS. 15 to 17, the substrate to be exposed is exposed using an exposure original drawing substrate provided with marks for overlay accuracy evaluation. In the figure, hatched portions indicated by diagonal lines are pattern portions corresponding to light shielding portions, and pattern portions indicated by dotted lines indicate pattern portions formed in advance on the substrate to be exposed by previous exposure. In this way, the pattern already formed on the substrate to be exposed is combined with the pattern formed later, and the relative position shift of these patterns is obtained with a length measuring machine, and the exposure patterns are superimposed. It is for evaluating accuracy.

Japanese Patent Laid-Open No. 06-337515

  However, in such a conventional technique, it is determined whether or not the relative positional deviation amount between the pattern already formed on the substrate to be exposed and the pattern formed later is outside the specified value by measuring with a measuring machine. Since a measuring machine is required and a process for measuring the relative positional deviation amount is required, it is complicated to determine whether the relative positional deviation amount is outside the specified value. It was. Further, if the determination is performed automatically, there is a problem that the measuring device and the inspection device become very complicated and large, and the cost is increased.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a relative positional deviation between adjacent wiring patterns formed on a multi-sided printed wiring board without requiring a measuring instrument or the like and increasing the number of processes, thereby causing an increase in cost. A method for manufacturing a substrate for a multi-sided development pattern formed printed wiring board and an inspection method, a method for manufacturing a multi-sided printed wiring board, and an amount that exceeds a specified value or can easily be determined An object is to provide an inspection method, a semiconductor device manufacturing method, and an exposure mask.

In order to achieve this object, the first means of the present invention is a method for producing a substrate for a printed wiring board on which a multi-sided development pattern is formed,
The printed wiring board substrate is stepped for each unit pattern area,
The photosensitive resin film covering the conductor of the printed wiring board base material is exposed through the electro-optic mask in the previous and subsequent steps, and the unexposed wiring pattern portion is positioned at the corresponding position before and after the step feed. An unexposed pattern portion for accuracy determination and an exposed pattern portion for position accuracy determination of a larger area are generated,
When the unexposed pattern portion for position accuracy determination is generated in the previous step, it is changed to the state exposed in the exposed pattern portion for position accuracy determination in the next step, while in the previous step When the exposed pattern portion for position accuracy determination has been generated, since it has already been exposed in the next step, the exposed pattern portion for position accuracy determination is made not to appear,
When the relative positional deviation amount between the unexposed wiring pattern portions for each adjacent unit exceeds a specified value, the position of the corresponding unexposed pattern portion for position accuracy determination and the exposed pattern portion for position accuracy determination is A part of the unexposed pattern portion for position accuracy determination is left as an unexposed pattern for position shift determination,
Thereafter, the unexposed wiring pattern portion is developed to form a wiring development pattern, and the positional deviation determination unexposed pattern is developed to form a positional deviation determination development pattern.
It is characterized by that.

The second means of the present invention is a method for inspecting a substrate for a printed wiring board with a multi-sided development pattern formed by the manufacturing method according to claim 1,
By detecting the development pattern for determining misregistration, it is determined that the relative misregistration amount between the development patterns for wiring for each adjacent unit exceeds a specified value.

The third means of the present invention is a method for manufacturing a multi-sided printed wiring board,
The printed wiring board substrate is stepped for each unit pattern area,
The photosensitive resin film covering the conductor of the printed wiring board base material is exposed through the electro-optic mask in the previous and subsequent steps, and the unexposed wiring pattern portion is positioned at the corresponding position before and after the step feed. An unexposed pattern portion for accuracy determination and an exposed pattern portion for position accuracy determination of a larger area are generated,
When the unexposed pattern portion for position accuracy determination is generated in the previous step, it is changed to the state exposed in the exposed pattern portion for position accuracy determination in the next step, while in the previous step When the exposed pattern portion for position accuracy determination has been generated, since it has already been exposed in the next step, the exposed pattern portion for position accuracy determination is made not to appear,
When the relative positional deviation amount between the unexposed wiring pattern portions for each adjacent unit exceeds a specified value, the position of the corresponding unexposed pattern portion for position accuracy determination and the exposed pattern portion for position accuracy determination is A part of the unexposed pattern portion for position accuracy determination is left as an unexposed pattern for position shift determination,
Thereafter, the unexposed wiring pattern portion is developed to form a wiring development pattern, and the positional deviation determination unexposed pattern is developed to form a positional deviation determination development pattern.
After the conductor is etched using the development pattern for wiring and the development pattern for determining misalignment, the developed pattern is peeled off, and the misalignment determination is performed together with the wiring pattern on the printed wiring board substrate. An etching pattern is formed,
It is characterized by that.

A fourth means of the present invention is an inspection method for a multi-sided printed wiring board formed by the manufacturing method according to claim 4,
By detecting the etching pattern for determining the positional deviation, it is determined that the relative positional deviation amount between the wiring patterns for each adjacent unit exceeds a specified value.

A fifth means of the present invention is a method for manufacturing a semiconductor device,
The semiconductor device is not mounted on the determined wiring pattern when it is determined by the inspection method according to claim 4 that the relative positional deviation amount between the wiring patterns for each adjacent unit exceeds a specified value. It is characterized by that.

6th means of this invention is an exposure mask used with the manufacturing method of Claim 1 or 3, Comprising:
It consists of a light transmitting part and a light shielding part,
The translucent portion is provided with a wiring pattern mask pattern for forming the unexposed wiring pattern portion and a first position accuracy determining mask pattern for forming the position accuracy determining unexposed pattern portion. on the other hand,
The light shielding portion is provided with a second position accuracy determination mask pattern that forms the exposed pattern portion for position accuracy determination.
It is characterized by that.

According to a seventh means of the present invention, in the exposure mask according to claim 6,
A plurality of sets of the first position accuracy determination mask pattern and the second position accuracy determination mask pattern are provided.

  According to the method for manufacturing a printed wiring board substrate with a multi-sided development pattern formed thereon according to the first means of the present invention, when the relative positional deviation amount between the unexposed wiring pattern portions for each adjacent unit exceeds a specified value. The positions of the unexposed pattern portion for position accuracy determination and the exposed pattern portion for position accuracy determination are misaligned, and a part of the unexposed pattern portion for position accuracy determination is left as an unexposed pattern for position misalignment determination, Thereafter, the undeveloped pattern for position deviation determination is developed to form a development pattern for position deviation determination. Therefore, the development pattern for position deviation determination is detected by visual observation with a magnifying glass or by an optical recognition device. The wiring pattern for each adjacent unit formed on the multi-sided printed wiring board without using a measuring instrument or increasing the number of processes and causing an increase in cost. Can be relative positional deviation amount of each other and can be recognized readily detected that exceeds a specified value.

  According to the method for inspecting a printed wiring board substrate with a multi-sided development pattern formed thereon according to the second means of the present invention, the development pattern for position deviation determination formed by developing the unexposed pattern for position deviation determination is detected. In this case, it is determined that the relative positional deviation between the wiring development patterns for each adjacent unit exceeds the specified value, so that the wiring patterns for each adjacent unit formed on the multi-sided printed wiring board are relative to each other. It can be easily detected and recognized that the amount of positional deviation exceeds a specified value.

  According to the method of manufacturing the multi-sided printed wiring board according to the third means of the present invention, when the relative positional deviation amount between the unexposed wiring pattern portions for each adjacent unit exceeds a specified value, the corresponding position accuracy determination The position of the unexposed pattern part for position detection and the exposed pattern part for position accuracy determination are misaligned, and a part of the unexposed pattern part for position accuracy determination is left as an unexposed pattern for position misalignment determination. The unexposed pattern is developed to form a development pattern for determining misalignment. After the conductor is etched using the development pattern for misalignment determination, the developed pattern is peeled off and printed on the printed wiring board substrate. Since the etching pattern for misregistration determination is formed together with the wiring pattern, the etching pattern for misregistration determination is visually checked with a magnifying glass. By detecting with a scientific recognition device, without using a measuring machine or increasing the number of processes and incurring costs, the wiring patterns of adjacent units formed on the multi-sided printed wiring board It is possible to easily detect and recognize that the relative positional deviation amount exceeds the specified value.

  According to the method for inspecting a multi-sided printed wiring board according to the fourth means of the present invention, after the conductor is etched, the development pattern for determining misalignment used for the etching is peeled off and the printed wiring board substrate When the positional deviation determination etching pattern is detected, the relative positional deviation amount between the adjacent wiring patterns for each unit is determined to exceed the specified value. Therefore, it is possible to easily detect and recognize that the relative positional deviation amount exceeds the specified value.

  According to the semiconductor device manufacturing method of the fifth means of the present invention, when it is determined that the relative positional deviation amount between the wiring patterns of adjacent units exceeds the specified value, the determined wiring pattern includes Since no semiconductor element is mounted, useless consumption of the semiconductor element can be eliminated.

  According to the exposure mask of the sixth means of the present invention, when a multi-sided printed wiring board is manufactured using the exposure mask, the amount of relative positional deviation between unexposed wiring pattern portions for each adjacent unit exceeds a specified value. When the position of the corresponding unexposed pattern portion and the exposed pattern portion is shifted, a part of the unexposed pattern portion is left as an unexposed pattern for misalignment determination on the printed wiring board substrate, and then Since the undeveloped pattern for position deviation determination is developed to form a development pattern for position deviation determination, or the etching pattern for position deviation determination is formed using the development pattern for position deviation determination. Wiring for each unit by detecting the development pattern for misregistration and the etching pattern for misregistration by visual observation with a magnifier or an optical recognition device It can be relative positional deviation amount between the developed pattern that exceeds a specified value, or a recognizable easily detect that exceeded.

  According to the exposure mask of the seventh means of the present invention, since a plurality of sets of the first position accuracy determination mask pattern and the second position accuracy determination mask pattern are provided, wiring for each adjacent unit is provided. Therefore, it is possible to improve the accuracy of detecting and recognizing that the relative positional deviation amount between the development patterns for use exceeds the specified value.

(A) thru | or (H) is sectional drawing which shows the manufacturing process of the semiconductor device which mounted the semiconductor element on the COF tape. It is a top view of the exposure mask used in the manufacturing process shown in FIG. The top view which shows the state which the base material for printed wiring boards was stepped in the manufacturing process, the 1st position accuracy determination unexposed pattern part overlapped with the 2nd position accuracy determination mask pattern, and was exposed and changed. It is. (A) is a first position accuracy determination mask pattern formed on the exposure mask shown in FIG. 2, and (B) is a plan view showing dimensions of a second position accuracy determination mask pattern. (A) thru | or (C) is a plane which shows the positional relationship of the unexposed pattern part for 1st positional accuracy determination, and the exposed pattern part for 2nd positional accuracy determination at the time of manufacturing by the manufacturing process shown in FIG. 1, respectively. It is a schematic diagram. It is a top view of the base material for printed wiring boards in which the multi-surface development pattern formation manufactured by the manufacturing process shown in FIG. It is a top view of the multi-faced COF tape manufactured by the manufacturing process shown in FIG. (A) And (B) is a schematic cross section which shows the relationship between the development pattern for position shift determination manufactured at the manufacturing process shown in FIG. 1, and the etching pattern for position shift determination. It is a top view of the multi-faced semiconductor device manufactured by the manufacturing process shown in FIG. It is a top view of the base material for printed wiring boards in which the multi-row multi-sided development pattern formation which is another example manufactured based on the manufacturing process by this invention is carried out. (A) thru | or (G) are sectional drawings which show the conventional manufacturing process of the semiconductor device which mounted the semiconductor element on the COF tape. It is a top view of the exposure mask used in the manufacturing process shown in FIG. It is a top view of the multi-faced COF tape manufactured based on the manufacturing process shown in FIG. It is a top view of the semiconductor device which mounted the semiconductor element on the COF tape shown in FIG. (A) And (B) is a top view which shows the example of the mark for each conventional overlay accuracy evaluation. (A) And (B) is a top view which shows the example of the mark for a different conventional overlay accuracy evaluation. (A) thru | or (C) is a top view which shows the example of the mark for another conventional overlay accuracy evaluation, respectively.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1A to 1H show a manufacturing process of a semiconductor device in which a semiconductor element is mounted on a COF tape.

  In the illustrated manufacturing process, a printed wiring board substrate 3 is prepared in which a conductor 2 for forming a wiring pattern is provided in a solid shape on the surface of an insulating substrate 1 as shown in FIG. As the insulating substrate 1, generally, polyimide having a thickness of 12.5 to 50 μm is used. For example, the product name “UPILEX” manufactured by Ube Industries, Ltd., the product name “Kapton” manufactured by Toray DuPont Co., Ltd., and the like are used. And the conductor 2 formed with the metal using the sputtering method or the electroplating method is formed on one side of such an insulating base material 1. In this example, a product name “Esperflex” manufactured by Sumitomo Metal Mining Co., Ltd., in which a conductor 2 is formed by copper plating after sputtering a nickel alloy, is used.

  As shown in FIG. 1 (B), sprocket holes 4 are provided on the printed wiring board base material 3 in a longitudinal direction along both edges at regular intervals.

  Thereafter, as shown in FIG. 1C, the printed wiring board substrate 3 is conveyed using the sprocket holes 4, and the photosensitive resin is uniformly applied to the surface of the conductor 2 using a roll coater or the like. The photosensitive resin film 5 covering the conductor 2 is formed by applying and drying and curing. In general, a positive type in which a portion of the photosensitive resin film 5 irradiated with exposure light by exposure is removed by a development process and a photosensitive resin film 5 in a portion not irradiated with the exposure light beam are removed by development processing. There is a negative type, and in this example, a case where a positive type photosensitive resin film 5 is used will be described.

  Next, the exposure is performed as shown in FIG. 1D using the exposure mask 6 shown in FIG. In FIG. 2, 6A without hatching is a translucent part, and 6B with hatching is a light-shielding part. In the translucent portion 6A, the first positional accuracy for generating the wiring pattern mask pattern 8A for generating an unexposed wiring pattern portion 8a described later on the conductor 2 and the unexposed pattern portions 21a and 21b for determining the positional accuracy. Determination mask patterns 21A and 21B are provided. On the other hand, the light shielding portion 6B includes second position accuracy determination mask patterns 22A and 22B for generating exposed position portions 22a and 22b for position accuracy determination, which will be described later, on the conductor 2, and a sprocket hole mask pattern 14. Is provided.

  Here, the second positional accuracy determination mask pattern 22A is formed to have a larger area than the first positional accuracy determination mask pattern 21A, and the second positional accuracy determination mask pattern 22B is the same as the first positional accuracy determination mask pattern 22B. The area is larger than the position accuracy determination mask pattern 21B. The dimensions of the first position accuracy determination mask pattern 21A (21B) and the second position accuracy determination mask pattern 22A (22B) provided on the exposure mask 6 will be described later with reference to FIG.

  Then, the sprocket hole mask pattern 14 of the exposure mask 6 shown in FIG. 2 and the sprocket holes 4 formed on the printed wiring board base 3 are recognized by an optical recognition device, and the position is controlled so that the respective positions coincide. After positioning, the exposure light beam 7 is irradiated as shown in FIG. 1D, the exposure range is defined by the exposure mask frame 30, and the entire mask surface is exposed (previous exposure). At this time, the photosensitive resin film 5 on the printed wiring board substrate 3 is changed to a state in which only the portion that is exposed to the exposure light beam 7 through the exposure mask 6 is exposed and is shielded by the exposure mask 6. The part remains unexposed.

  As a result, the first position accuracy judgment mask pattern 21A, 21B and the wiring pattern mask pattern 8A are shielded from light, so that the first position accuracy judgment unexposed that is projected by exposure and remains unexposed. Pattern portions 21a and 21b and unexposed wiring pattern portion 8a are generated. Further, since the periphery of the sprocket hole mask pattern 14 is also shielded, the unexposed reinforcement pattern 8i is also generated at the same time. On the other hand, during the previous exposure, the exposure pattern 7 is irradiated with the exposure light beam 7 through the second position accuracy determination mask patterns 22A and 22B, and the exposed pattern portions 22a and 22b for the second position accuracy determination are exposed. Generated. Note that the exposure mask 6 in FIG. 1D is a cross-section in the direction of the arrows along the line M1-M1 in FIG.

  Then, after the printed wiring board substrate 3 is stepped in the −Y direction of the exposure mask 6 shown in FIG. 2 by a dimension corresponding to the unit pattern area A, the sprocket hole mask pattern 14 and After performing positioning so that the positions of the sprocket holes 4 coincide with each other, the exposure light beam 7 is irradiated in the same manner, the exposure range is defined by the exposure mask frame 30, and the next exposure (substantially on the entire mask surface) (After exposure). Then, by the subsequent exposure, the first unexposed pattern portions 21a and 21b for position accuracy determination, the unexposed wiring pattern portion 8a, and the unexposed reinforcement pattern 8i that are not exposed in the same manner are simultaneously generated. On the other hand, during the subsequent exposure, the exposure pattern 7 is irradiated with the exposure light beam 7 via the second position accuracy determination mask patterns 22A and 22B, and the exposed pattern portions 22a and 22b for position accuracy determination are exposed. Generated.

  In addition, when the positioning is correctly performed at this time, and the positional deviation amount between the unexposed wiring pattern portions 8a for each adjacent unit is within a specified value, as shown in FIG. The first position accuracy determination unexposed pattern portion 21a is located at a position corresponding to 22A, and the second position accuracy determination unexposed pattern portion 22b is located at a position corresponding to the first position accuracy determination mask pattern 21B. come. Then, the second position accuracy determination exposed pattern portion 22a is generated by the second position accuracy determination mask pattern 22A, and the first position accuracy determination unexposed pattern portion 21a having a smaller area than the first pattern accuracy determination unexposed pattern portion 21a. 2 enters the exposed pattern portion 22a for determining position accuracy and changes to an exposed state. Even if the first position accuracy determination mask pattern 21B is shielded from light, the second position accuracy determination exposed pattern portion 22b having a larger area has already been generated and is in an exposed state. Therefore, the first exposed pattern portion 21b for determining position accuracy does not appear.

  In this way, unexposed pattern portions 21a and 21b for position accuracy determination and exposed pattern portions 22a and 22b having a larger area are generated at corresponding positions before and after step feed. When the determination unexposed pattern portion 21a is generated, it is changed to the state exposed by the position accuracy determination exposed pattern portion 22a in the next step, while the position accuracy determination exposed in the previous step. When the pattern portion 22b is generated, it is already exposed in the next step, so that the generated position accuracy determining exposed pattern portion 21b does not appear.

  Corresponding to the positioning of the substrate 3 for printed wiring board 3, exposure of the photosensitive resin film 5 covering the conductor 2 on the substrate 3 for printed wiring board 3 through the lightning mask 6, and unit pattern area A Step feed for each dimension to be performed is repeated. The step feed is not limited to the −Y direction, and may be performed in the + Y direction.

  By the way, as described above, the sprocket hole 4 is generally formed by punching near both ends of the printed wiring board substrate 3 using a mold, and the insulating substrate constituting the punched printed wiring board substrate 3 is formed. Since the material 1 uses polyimide or the like, it expands and contracts under the influence of humidity. For this reason, the sprocket hole 4 formed near both ends of the printed wiring board substrate 3 may be different in design from the design value when exposed to the other sprocket hole 4.

  On the other hand, burrs, whiskers, debris, and the like are generated in the sprocket hole 4 punched and formed by the mold, and the sprocket hole 4 may be deformed through the processing steps before the exposure step. For this reason, even if the sprocket hole mask pattern 14 and the sprocket hole 4 are recognized by the optical recognition device and the position control is performed so that the respective positions overlap and coincide with each other, a relative displacement may occur. . And since the limit value of the accuracy of the optical recognition device and the position control is added, there is a problem that the amount of relative positional deviation is further increased.

  For this reason, when a relative positional deviation between the sprocket hole mask pattern 14 and the sprocket hole 4 occurs, the first unexposed pattern portion 21a (21b for position accuracy determination) generated by the previous exposure and the subsequent exposure. ) And the second positional accuracy determination exposed pattern portion 22a (22b), the relative positional deviation also occurs. At the same time, the same amount of relative positional deviation also occurs in the relative positions of the adjacent unexposed wiring pattern portion 8a groups generated by the previous exposure and the subsequent exposure.

  By the way, in order to prevent the probe pin from being detached from the test pad portion at the time of subsequent continuity inspection as in the conventional case, a specified value K is set as the relative positional deviation amount.

  The relative positional deviation amount between the first position accuracy determining unexposed pattern portion 21a (21b) and the second positional accuracy determining exposed pattern portion 22a (22b) exceeds the specified value K of the relative positional deviation amount. In this case, during the subsequent exposure, the first position accuracy determination unexposed pattern portion 21a (21b) is partially exposed by the light shielding portion around the second position accuracy determination exposed pattern portion 22a (22b). As shown in FIG. 1E, the unexposed pattern 23 for determining the relative position deviation is formed so that the light beam 7 does not strike and remains unexposed. In addition, the exposure mask 6 shown to FIG. 1 (E) is an arrow direction cross section along the M2-M2 line of the exposure mask 6 shown in FIG.

  Next, the dimensions of the first position accuracy determination mask pattern 21A (21B) and the second position accuracy determination mask pattern 22A (22B) provided on the exposure mask 6 will be described. Now, as shown in FIGS. 4A and 4B, the dimensions of the first position accuracy determination mask pattern 21A (21B) provided on the exposure mask 6 are W1 and H1, respectively, and the second position accuracy determination is performed. The dimensions of the mask pattern 22A (22B) are W2 and H2.

  Here, first, the dimensions of the first positional accuracy determination mask pattern 21A (21B) and the second positional accuracy determination mask pattern 22A (22B) provided on the exposure mask 6 are the specified values of the relative positional deviation amount. When K is set, the values of W2, H2, W1, and H1 are set so that the relationship of K = (W2−W1) / 2 and K = (H2−H1) / 2 is established. When the specified value K of the relative positional deviation amount is set to 30 μm (below), for example, if W2 = H2 = 100 μm, W1 = H1 = 40 μm is obtained from the relational expression.

  Next, in the case of this set value, the relative positional deviation amount between the first position accuracy determination unexposed pattern portion 21a (21b) and the second position accuracy determination exposed pattern portion 22a (22b) is S. If S = 31 μm occurs, a value further exceeding the specified value K of the relative positional deviation amount is SK = 1 μm. Then, as shown in the schematic diagram of FIG. 5A, a part of the first position accuracy determining unexposed pattern portion 21a (21b) is not exposed by the subsequent exposure, and therefore remains unexposed. Thus, an unexposed pattern 23 for misregistration determination is generated with a width Z = 1 μm.

  Thus, when the unexposed pattern 23 for misregistration determination is generated with a width Z = 1 μm, it remains without being removed even after development performed later, and the misregistration determination development pattern 23a having the same width has a width of 1 μm. It is formed. However, when the width of the development pattern 23a for determining the positional deviation formed in this way is 1 μm, it is difficult to detect it visually by a magnifying glass or by an optical recognition device.

  Therefore, in order to enable detection with a magnifying glass or an optical recognition device, a constant β is set, and K−β = (W2−W1) / 2 and K−β = (H2−H1) / 2. The values of W2, H2, W1, and H1 are set so that the equation holds. From this relationship, for example, when β = 5 μm and W2 = H2 = 100 μm, W1 = H1 = 50 μm is obtained. Here, when the relative positional deviation amount S = 31 μm is generated in the same manner as described above, the state as shown in FIG. 5B is obtained, and the unexposed pattern 23 for positional deviation determination is generated with the width Z = 6 μm. From these relationships, Z = S− (K−β) is established, and the relative positional deviation amount S = 31 μm and K−β = 25 μm. Therefore, the unexposed pattern 23 for positional deviation determination is generated with the width Z = 6 μm. The Further development is performed to form a development pattern 23a for determining relative positional deviation with a width of 6 μm.

  In this way, by setting the constant β, the width of the unaligned pattern 23 for position shift determination can be increased even when the relative position shift amount S slightly exceeds the relative position shift amount specified value K = 30 μm. Since the constant β is formed more widely, setting the constant β also secures the safety factor. Note that the value of the constant β is preferably set to about β = 5 μm in view of the visual observation by the magnifying glass or the detection capability of the optical recognition device.

  By the way, as described above, the first position accuracy determination unexposed pattern portion 21a that has not been exposed in the previous exposure has passed through the second position accuracy determination mask pattern 22A in the subsequent exposure. The exposure light 7 is overlapped and changed to the exposed state. Next, β = 5 μm, W2 = H2 = 100 μm, W1 = H1 = 50 μm are set, and a relative positional deviation amount S is generated S = 35 μm. The case will be described. As shown in the schematic diagram of FIG. 5C, a portion of the first position accuracy determination unexposed pattern portion 21a is not irradiated with the exposure light beam 7, and thus is maintained in an unexposed state, and is used for position shift determination. The unexposed pattern 23 is generated with a width Z = 10 μm from the relationship Z = S− (K−β). Further, by performing further development, a development pattern 23a for determining misalignment is formed with a width of 10 μm.

  Now, when the undeveloped pattern 23 for position misalignment determination is generated with a width Z = 10 μm, when development is performed, as shown in FIG. 1F, a portion of the unexposed pattern 23 for first position accuracy determination Is left without being removed, and a misalignment determining development pattern 23a is formed with a width of 10 μm. At the same time, the unexposed wiring pattern portion 8a and the unexposed reinforcement pattern portion 8i remain without being removed, so that the wiring development pattern 8c and the reinforcement pattern development pattern 8f are formed. In this way, the multi-sided development pattern-formed printed wiring board substrate 9 in which a plurality of wiring development patterns 8c for each unit are formed is formed. FIG. 6 shows the plane. FIG. 1 (F) is a cross-section in the direction of the arrows along the line D1-D1 in FIG.

  FIG. 6 is a plan view showing a state in which development is performed after repeated positioning, exposure, and step feed in the order of unit pattern areas A1 to A2, and the exposure position of unit pattern area A2 and the exposure position of unit pattern area A3. However, this shows a state after development when the relative deviation of 35 μm and the exposure position of the unit pattern area A3 and the exposure position of the unit pattern area A4 are relatively shifted by 35 μm. That is, it shows a state in which the relative positional deviation amount between adjacent groups of wiring development patterns 8c is generated by 35 μm. As described above, since the relative positional deviation amount between the adjacent groups of wiring development patterns 8c for each unit is 35 μm, the relative positional deviation determination development pattern 23a is formed in the unit pattern areas A2, A3, and A4. It is formed with a width of 10 μm.

  Next, when the development pattern 23a for position deviation determination is detected visually or with an optical recognition device using a magnifying glass, the unit pattern area formed in the same unit pattern region as the detected development pattern 23a for position deviation determination is used. The wiring development pattern 8c group is determined to be defective. Here, in the same unit pattern area as the development pattern for wiring 8c for each unit that has been determined to be defective, using an ink or the like that acts as an etching resist so that the defect can be easily detected in the subsequent visual inspection, It is preferable that the post-development defect determination mark 24 be formed in such a size that it can be easily detected by visual inspection.

  Then, as shown in FIG. 1G, etching and peeling are performed to form a misregistration determination etching pattern 23b together with the wiring pattern 8d and the reinforcing pattern 8g. Although not shown in FIG. 1 (G), if a defect determination mark 24 after development is formed at this time, it is used as an etching resist, and the defect determination mark 25 after etching (see FIG. 7) is used. Form. Then, for example, tin plating 26 is applied to those surfaces as rust prevention or plating suitable for connecting and mounting a semiconductor element later to form the COF tape 10 which is a multi-sided printed wiring board. FIG. 7 shows the plane. FIG. 1G is a cross-section in the direction of the arrows along the line D2-D2 in FIG.

  In addition, when the defect determination mark 24 after development is provided and the defect determination mark 24 after development is used as an etching resist to form the defect determination mark 25, the size of the defect determination mark 25 is visually checked without using a magnifying glass. It is preferable that the size of the inspection is such that it can be easily recognized so that a defect can be easily determined.

  However, if the post-development defect determination mark 24 is not provided, the post-etching defect determination mark 25 is not formed, and therefore, the positional deviation determination etching pattern 23b is detected visually by a magnifying glass or by an optical recognition device. Become. If it is detected, the wiring pattern 8d for each unit, which is formed by being simultaneously exposed to the same unit pattern region, is determined as defective.

  The misregistration determination etching pattern 23b is formed by etching using the misregistration determination development pattern 23a as an etching resist. As shown in the schematic diagram of FIG. Depending on the relationship between the PH value and the width of the positional deviation determining development pattern 23a, the top width PT1 of the positional deviation determining etching pattern 23b may be 0 μm, and the positional deviation determining development pattern 23a may be removed. As described above, when the development pattern 23a for misregistration determination is removed, the etching pattern 23b for misregistration determination disappears due to rapid etching.

  Therefore, as shown in FIG. 8B, the top width necessary to maintain the state in which the development pattern 23a for position deviation determination cannot be removed even after etching is set to PT2, and the development pattern for position deviation judgment at that time is used. When the width 23a is RW2, the top width ≧ PT2, and the misalignment determining development pattern 23a width ≧ RW2 is set. Since these values differ depending on the value of the thickness PH of the conductor 2 and the etching amount, it is preferable to obtain and set by experiments. From these experimental results, it is preferable that the constant β is set by back calculation so that the positional deviation determining development pattern 23a satisfies the width ≧ RW2. By the way, if it is the method of providing the defect determination mark 25 after an etching, it is easy to provide in the magnitude | size which does not lose | disappear even if it etches, and it is more preferable.

  The COF tape thus formed is generally inspected by an appearance inspection apparatus using an optical recognition apparatus. However, as shown in FIG. 7, there is a problem that a defect is not judged when a short 28 caused by an extra fine wire that exceeds the resolution limit of the optical recognition device occurs. A continuity test is performed by bringing a probe pin into contact with the pad portion 8e. This continuity test is a part of the wiring pattern 8d for each of the two units formed in the unit pattern areas A2 and A3, for example, a probe pin contact position 20 shown in FIG. The probe pins are simultaneously brought into contact with the test pad portion 8e group, and the continuity test is simultaneously performed. In order to further increase the efficiency, the continuity test is not limited to two, but may be performed simultaneously on a group of test pads 8e of the wiring pattern 8d for every three or more units.

  By the way, the specified value of the relative positional deviation amount regarding the wiring pattern 8d group for each adjacent unit is determined by calculating from the size of the test pad portion 8e or the like so that the probe pin does not come off from the test pad portion 8e. Is done.

  FIG. 7 shows the probe pin contact position 20 when the probe pin positioning is performed by recognizing the group of test pads 8e of the wiring pattern 8d for each unit formed in the unit pattern area A2. ing. In addition, at this time, the relative positional deviation amount between the test pad portion 8e group and the wiring pattern 8d group for each unit formed in the unit pattern areas A2 and A3 is 35 μm. This value is larger than the specified value of the relative positional deviation amount of 30 μm (below). Therefore, the probe pin is removed from the test pad portion 8e formed in the unit pattern region A3, and the continuity test cannot be performed accurately.

  Although not shown, when the test pad portion 8e, which is a part of the wiring pattern 8d for each unit formed in the unit pattern area A3, is recognized and the probe pin is positioned, it is formed in the unit pattern area A2. The probe pin will come off from the test pad portion 8e.

  Also, as shown in FIG. 7, when the short 28 has occurred, the probe pin due to the continuity test is disconnected from the test pad portion 8e, so the short cannot be detected, and the result of the continuity test is a non-defective product determination. Therefore, there is a problem that a false determination is made.

  Therefore, in the present invention, when the relative positional deviation amount between the wiring patterns 8d for each unit is larger than the predetermined value of 30 μm (below), the relative positional deviation determining development pattern 23a, the developed defect determining mark 24, the positional deviation is provided. Since any of the determination etching patterns 23b is detected by visual observation using a magnifying glass or by using an optical recognition device, and if detected, a failure determination can be made before conducting the continuity test. The problem of misjudgment can be eliminated.

  As shown in FIG. 1 (H), the COF tape 10 which is a multi-sided printed wiring board formed in the manufacturing process shown in FIG. 1 (G) has a wiring pattern 8d for each unit with gold bumps 12 interposed therebetween. Then, the semiconductor element 11 is connected, sealed with the sealing resin 13, and the semiconductor element 11 is mounted to form a multi-faced semiconductor device 27 in which a large number of semiconductor devices 27A are formed as shown in FIG. At this time, one of the defect determination mark 25 after etching and the etching pattern 23b for positional deviation determination is detected. If detected, the wiring pattern 8d for each unit formed in the same unit pattern region includes a semiconductor element. 11 is not installed. FIG. 1H shows a cross section in the direction of the arrow along the line D3-D3 in the plan view of FIG.

  In this way, the multi-faced semiconductor device 27 is formed, and as shown in FIG. 9, electrical inspection is performed by bringing the probe pins into contact with the test pad portion 8e. However, the adjacent test pad portions 8e formed in the unit pattern regions A2, A3, and A4 have a relative positional deviation of 35 μm, so that the probe pin is detached from the test pad portion 8e. Since the semiconductor element 11 is not already mounted by the defect determination, there is no problem in the erroneous determination by the continuity test. Moreover, since the semiconductor element 11 is not already mounted, the semiconductor element 11 is not wasted.

  By the way, the description so far has described the case where the printed wiring board substrate 3 is displaced in the -X direction of the exposure mask 6 shown in FIG. 2, that is, the printed wiring board substrate 3 is displaced in the width direction. It is not limited to the direction, and it may be a relative position shift due to a shift in the length direction (Y direction) or a shift in the rotation direction (θ direction), or a combination of these shifts. Good.

  Moreover, although the description so far has been described with respect to an example of a single strip COF tape, in order to improve productivity, for example, the COF tape may be formed in three strips. In this case, for example, as the exposure region to be performed at one time, three lines in the width direction and three wiring pattern groups per unit in the length direction, that is, nine wiring pattern groups per unit may be exposed simultaneously. Thereafter, development is performed to form a multi-strip multi-face development pattern group. FIG. 10 shows a plan view of the substrate 29 for printed wiring board on which the multi-strip multi-face development pattern has been formed.

  In FIG. 10, exposure is performed in order from the unit pattern area A1, and the unit pattern area A2 is exposed by being shifted by θ in the rotation direction during exposure. Due to this shift, the relative positional shift amount between adjacent wiring pattern groups for each unit is increased. Since the specified value is exceeded, a state in which a development pattern 23a for determining misalignment is formed after development is shown. Further, in order to detect the formed misalignment-determining development pattern 23a and make it easier to determine a defect in a later inspection, the size of the development can be facilitated by using an ink or the like that acts as an etching resist. A state in which the subsequent defect determination mark 24 is formed is shown. The development pattern 23a for misregistration determination is not formed in the wiring pattern group for each of the three units in the central portion of the unit pattern area A2. However, since it is exposed at the same time and misalignment occurs, it is determined as defective. Therefore, a defect determination mark 24 after development is formed.

  By the way, as shown in FIG. 10, when the deviation θ in the rotation direction is caused by the exposure, the position deviation amount increases as the distance from the center of the deviation in the rotation direction increases. The larger the position is, the larger the position shift amount is. Therefore, the number of lines when forming the COF tape increases, and the larger the width and length of the exposure area to be performed at one time, the larger the positional deviation amount, and the relative positional deviation amount between the wiring patterns of adjacent units. As a result, the effect of the present invention increases. The multi-strip multi-face development pattern group is then etched and tin-plated and then slit in a suitable process to form a single multi-position COF tape.

DESCRIPTION OF SYMBOLS 1 Insulation base material 2 Electric conductor 3 Base material for printed wiring boards 4 Sprocket hole 5 Photosensitive resin film 6 Exposure mask 7 Exposure light 8A Mask pattern for wiring patterns 8a Unexposed wiring pattern part 8c Development pattern for wiring 8d Wiring pattern 8e Test Pad part 8f Reinforcement pattern development pattern 8g Reinforcement pattern 8h Short 8i Unexposed reinforcement pattern part 9 Multi-sided development pattern-formed printed wiring board substrate 10 Multi-sided COF tape 11 Semiconductor element 12 Gold bump 13 Sealing resin 14 Sprocket hole Mask pattern 20 Probe pin contact position 21A First position accuracy determination mask pattern 21a First position accuracy determination unexposed pattern portion 21B First position accuracy determination mask pattern 21b First position accuracy determination unexposed Exposure pattern part 22 Second position accuracy determination mask pattern 22a Second position accuracy determination exposed pattern portion 22B Second position accuracy determination mask pattern 22b Second position accuracy determination exposed pattern portion 23 Unexposed for position deviation determination Pattern 23a Development pattern for misregistration judgment 23b Etching pattern for misregistration judgment 24 Defect judgment mark after development 25 Defect judgment mark after etching 26 Tin plating 27 Multi-sided semiconductor device 27A Semiconductor device 28 Short 29 Multi-strip multi-sided development pattern Formed substrate for printed wiring board 30 Frame for exposure mask A Unit pattern area K Specified value of relative positional deviation S S Relative positional deviation

Claims (7)

The printed wiring board substrate is stepped for each unit pattern area,
The photosensitive resin film covering the conductor of the printed wiring board base material is exposed through the electro-optic mask in the previous and subsequent steps, and the unexposed wiring pattern portion is positioned at the corresponding position before and after the step feed. An unexposed pattern portion for accuracy determination and an exposed pattern portion for position accuracy determination of a larger area are generated,
When the unexposed pattern portion for position accuracy determination is generated in the previous step, it is changed to the state exposed in the exposed pattern portion for position accuracy determination in the next step, while in the previous step When the exposed pattern portion for position accuracy determination has been generated, since it has already been exposed in the next step, the exposed pattern portion for position accuracy determination is made not to appear,
When the relative positional deviation amount between the unexposed wiring pattern portions for each adjacent unit exceeds a specified value, the position of the corresponding unexposed pattern portion for position accuracy determination and the exposed pattern portion for position accuracy determination is A part of the unexposed pattern portion for position accuracy determination is left as an unexposed pattern for position shift determination,
Thereafter, the unexposed wiring pattern portion is developed to form a wiring development pattern, and the positional deviation determination unexposed pattern is developed to form a positional deviation determination development pattern.
The manufacturing method of the base material for printed wiring boards in which the multi-surface development pattern formation was characterized. A method for inspecting a substrate for a printed wiring board with a multi-sided development pattern formed by the manufacturing method according to claim 1,
A multi-sided development pattern characterized in that, by detecting the development pattern for misalignment determination, it is determined that the relative misalignment amount between the development patterns for wiring for each adjacent unit exceeds a specified value. Inspection method for formed printed wiring board substrate. The printed wiring board substrate is stepped for each unit pattern area,
The photosensitive resin film covering the conductor of the printed wiring board base material is exposed through the electro-optic mask in the previous and subsequent steps, and the unexposed wiring pattern portion is positioned at the corresponding position before and after the step feed. An unexposed pattern portion for accuracy determination and an exposed pattern portion for position accuracy determination of a larger area are generated,
When the unexposed pattern portion for position accuracy determination is generated in the previous step, it is changed to the state exposed in the exposed pattern portion for position accuracy determination in the next step, while in the previous step When the exposed pattern portion for position accuracy determination has been generated, since it has already been exposed in the next step, the exposed pattern portion for position accuracy determination is made not to appear,
When the relative positional deviation amount between the unexposed wiring pattern portions for each adjacent unit exceeds a specified value, the position of the corresponding unexposed pattern portion for position accuracy determination and the exposed pattern portion for position accuracy determination is A part of the unexposed pattern portion for position accuracy determination is left as an unexposed pattern for position shift determination,
Thereafter, the unexposed wiring pattern portion is developed to form a wiring development pattern, and the positional deviation determination unexposed pattern is developed to form a positional deviation determination development pattern.
After the conductor is etched using the development pattern for wiring and the development pattern for determining misalignment, the developed pattern is peeled off, and the misalignment determination is performed together with the wiring pattern on the printed wiring board substrate. An etching pattern is formed,
A method for producing a multi-sided printed wiring board, wherein: A method for inspecting a multi-sided printed wiring board formed by the manufacturing method according to claim 4,
By detecting the positional deviation determination etching pattern, it is determined that the relative positional deviation amount between the wiring patterns for each adjacent unit exceeds a specified value. Inspection method.   The semiconductor device is not mounted on the determined wiring pattern when it is determined by the inspection method according to claim 4 that the relative positional deviation amount between the wiring patterns for each adjacent unit exceeds a specified value. A method for manufacturing a semiconductor device. An exposure mask used in the manufacturing method according to claim 1 or 3,
It consists of a light transmitting part and a light shielding part,
The translucent portion is provided with a wiring pattern mask pattern for forming the unexposed wiring pattern portion and a first position accuracy determining mask pattern for forming the position accuracy determining unexposed pattern portion. on the other hand,
The light shielding portion is provided with a second position accuracy determination mask pattern that forms the exposed pattern portion for position accuracy determination.
An exposure mask characterized by that. The exposure mask according to claim 6.
An exposure mask comprising a plurality of sets of the first positional accuracy determination mask pattern and the second positional accuracy determination mask pattern.

Images