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JP2010182958A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Semiconductor device and method of manufacturing semiconductor device Download PDF

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JP2010182958A
JP2010182958A JP2009026509A JP2009026509A JP2010182958A JP 2010182958 A JP2010182958 A JP 2010182958A JP 2009026509 A JP2009026509 A JP 2009026509A JP 2009026509 A JP2009026509 A JP 2009026509A JP 2010182958 A JP2010182958 A JP 2010182958A
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semiconductor device
semiconductor chip
convex portion
concavo
semiconductor
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JP2010182958A5 (en
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Hiroshi Ota
弘 太田
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Seiko Instruments Inc
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    • H10W72/5363
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Abstract

【課題】放熱性の良好な半導体装置および半導体装置の製造方法を提供する。
【解決手段】裏面に凹凸部を有し、凹凸部の凹部底側面および凸部端部に傾斜形状が形成されている半導体チップ1が樹脂封止された半導体装置であって、その製造方法は、半導体チップ1の裏面に凹凸部を形成する工程と、半導体チップ1をリードフレームのタブ5上に接着剤を介して固着する工程と、半導体チップ1とインナーリードとをワイヤボンドする工程と、半導体チップ1と前記インナーリードと前記ワイヤボンド用のワイヤ7とを覆うように樹脂封止する工程とからなり、半導体チップ1とタブ5とを固着する工程は減圧雰囲気で行うものである。
【選択図】図4
A semiconductor device with good heat dissipation and a method for manufacturing the semiconductor device are provided.
A semiconductor device in which a semiconductor chip 1 having a concavo-convex portion on the back surface, and an inclined shape is formed on a concave bottom surface and a convex end portion of the concavo-convex portion is resin-sealed, and a manufacturing method thereof A step of forming an uneven portion on the back surface of the semiconductor chip 1, a step of fixing the semiconductor chip 1 on the tab 5 of the lead frame via an adhesive, a step of wire bonding the semiconductor chip 1 and the inner lead, The process includes a step of resin-sealing so as to cover the semiconductor chip 1, the inner lead, and the wire bonding wire 7, and the step of fixing the semiconductor chip 1 and the tab 5 is performed in a reduced pressure atmosphere.
[Selection] Figure 4

Description

本発明は、熱放散性を高めた半導体装置および半導体装置の製造方法に関する。   The present invention relates to a semiconductor device with improved heat dissipation and a method for manufacturing the semiconductor device.

従来の半導体チップは裏面をバックグラインドした状態でリードフレームに搭載され樹脂封止された半導体装置(図6)や金属性の突起電極を設けた半導体装置(図7)となり、さらに、通常はガラスエポキシ或いはセラミック等の回路基板に実装されて使用される。その場合、半導体装置の発熱により起こる誤動作を防止するために、回路基板内に伝熱用のパターンを設けたり、熱放散用シリコンチップと半導体チップを積層させたりして構成された半導体装置が使用され、誤動作の防止が図られてきた(例えば、特許文献1参照)。   A conventional semiconductor chip is a semiconductor device (FIG. 6) mounted on a lead frame with a back-grinded back surface and resin-sealed (FIG. 6) or a semiconductor device (FIG. 7) provided with a metal protruding electrode, and is usually made of glass. It is used by being mounted on a circuit board such as epoxy or ceramic. In that case, in order to prevent malfunction caused by heat generation of the semiconductor device, a semiconductor device configured by providing a heat transfer pattern in the circuit board or stacking a heat dissipation silicon chip and a semiconductor chip is used. Therefore, prevention of malfunction has been attempted (see, for example, Patent Document 1).

特開平4−230057号公報JP-A-4-230057

しかしながら、従来の半導体装置において、半導体装置に半導体装置より大きい熱放散用シリコンチップを積層させる構造では、高密度実装や狭スペースへの実装に不向きである。   However, in a conventional semiconductor device, a structure in which a silicon chip for heat dissipation larger than that of the semiconductor device is stacked on the semiconductor device is not suitable for high-density mounting or mounting in a narrow space.

また、伝熱用パターンを充分に設けていない回路基板に従来の半導体装置(図6)を実装した場合、半導体チップから発せられた熱は半導体チップ内に蓄積され、効率良く外部に放熱出来ない為、熱による誤動作が懸念される。   When a conventional semiconductor device (FIG. 6) is mounted on a circuit board that does not have sufficient heat transfer patterns, heat generated from the semiconductor chip is accumulated in the semiconductor chip and cannot be efficiently radiated to the outside. Therefore, there is a concern about malfunction due to heat.

本発明は上記課題に鑑みなされたもので、その目的は放熱性の良好な半導体装置およびその製造方法を提供するものである。   The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device with good heat dissipation and a method for manufacturing the same.

上記課題を解決するために、本発明の半導体装置は以下のような構造とした。   In order to solve the above problems, the semiconductor device of the present invention has the following structure.

樹脂モールドで覆われた半導体チップを有する半導体装置であって、半導体チップの裏面に凹凸部を有し、凹凸部の凹部底側面および凸部端部に傾斜形状が形成されていることを特徴とする半導体装置とする。   A semiconductor device having a semiconductor chip covered with a resin mold, wherein the semiconductor chip has a concavo-convex portion on the back surface, and an inclined shape is formed on the concave bottom surface and the convex end portion of the concavo-convex portion. Semiconductor device to be used.

また、表面に突起電極を形成した半導体チップを有する半導体装置であって、半導体チップの裏面に凹凸部を有し、凹凸部の凹部底側面および凸部端部に傾斜形状が形成されていることを特徴とする半導体装置とする。   Also, a semiconductor device having a semiconductor chip with a protruding electrode formed on the surface, having a concavo-convex portion on the back surface of the semiconductor chip, and inclined shapes are formed on the concave bottom surface and the convex end portion of the concavo-convex portion. A semiconductor device characterized by the above.

さらに、上記半導体装置を製造するために以下のような方法を用いた。   Further, the following method was used to manufacture the semiconductor device.

樹脂モールドで覆われた半導体チップを有する半導体装置の製造方法であって、半導体チップの裏面に凹凸部を形成する工程と、半導体チップをリードフレームのタブ上に接着剤を介して固着する工程と、半導体チップとインナーリードとをワイヤボンドする工程と、半導体チップと前記インナーリードと前記ワイヤボンド用のワイヤとを覆うように樹脂封止する工程であって、前記固着する工程は減圧雰囲気で行うことを特徴とする半導体装置の製造方法とする。   A method of manufacturing a semiconductor device having a semiconductor chip covered with a resin mold, the step of forming an uneven portion on the back surface of the semiconductor chip, and the step of fixing the semiconductor chip on a tab of a lead frame with an adhesive A step of wire bonding the semiconductor chip and the inner lead, and a step of resin sealing so as to cover the semiconductor chip, the inner lead and the wire for wire bonding, and the fixing step is performed in a reduced pressure atmosphere. A method for manufacturing a semiconductor device is provided.

さらには、凹凸部に丸みのある傾斜形状を与えることを特徴とする半導体装置の製造方法とする。   Further, the semiconductor device manufacturing method is characterized in that a rounded and inclined shape is given to the uneven portion.

以上説明した半導体装置および半導体装置の製造方法とすることにより、放熱性の良好な半導体装置とすることができる。   With the semiconductor device and the method for manufacturing the semiconductor device described above, a semiconductor device with good heat dissipation can be obtained.

本発明による半導体チップの実施例を示す断面図および裏面図である。It is sectional drawing and the back view which show the Example of the semiconductor chip by this invention. 本発明による半導体チップの凹凸部拡大断面図Enlarged sectional view of an uneven portion of a semiconductor chip according to the present invention 本発明による半導体チップの実施例を示す断面図である。It is sectional drawing which shows the Example of the semiconductor chip by this invention. 本発明による半導体装置の実施例を示す断面図である。It is sectional drawing which shows the Example of the semiconductor device by this invention. 本発明による半導体装置の実施例を示す断面図である。It is sectional drawing which shows the Example of the semiconductor device by this invention. 従来の半導体装置を示す断面図である。It is sectional drawing which shows the conventional semiconductor device. 従来の半導体装置を示す断面図である。It is sectional drawing which shows the conventional semiconductor device.

以下に本発明の実施例を図面に基づいて説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図1(a)は本発明の第1の実施例である半導体チップの構造を示す断面図である。その半導体チップの裏面図は図1(b)〜(d)である。   FIG. 1A is a sectional view showing the structure of a semiconductor chip according to the first embodiment of the present invention. The back view of the semiconductor chip is shown in FIGS.

図1(a)に断面図示す半導体チップ1は、半導体基板よりなり、半導体基板の表面に半導体素子を有し、裏面に凹凸形状12を有する構造であり、図2の凹凸部拡大断面図に示すように凹部の底側面および凸部の端部は傾斜形状13を有している。図(b)にはストライプ状の溝2、図1(c)には格子状の溝2、図1(d)には複数の穴3を有する半導体チップの裏面が図示されている。   The semiconductor chip 1 shown in a sectional view in FIG. 1A is made of a semiconductor substrate, has a semiconductor element on the surface of the semiconductor substrate, and has a concavo-convex shape 12 on the back surface. As shown, the bottom surface of the recess and the end of the protrusion have an inclined shape 13. FIG. 1B shows a stripe-shaped groove 2, FIG. 1C shows a lattice-shaped groove 2, and FIG. 1D shows the back surface of a semiconductor chip having a plurality of holes 3.

半導体チップ1はウェハの裏面研削(バックグラインド)後に、ダイシングブレードを用いてストライプ状の溝2や格子状の溝3を形成し、次いで、シリコンエッチング装置にて等方性シリコンエッチングを行って、ブレード加工によって半導体チップの凹凸部に形成されたダメージ層を除去する。この等方性エッチングを行うことで凹凸部の急峻な部分に丸みを与え、図2に示すように凹部の底側面や凸部の端部に丸みのある傾斜形状が形成される。このようにすることで、半導体チップ1をタブ5に固着する際の接着剤4が凹凸部12に入り込み易くなり放熱性を高めるだけでなく、半導体チップにかかる応力による半導体チップの破損を防止することができる。なお、このときの溝深さは半導体チップの厚みおよび半導体素子の厚みに応じて決定する。   The semiconductor chip 1 is formed by forming a stripe-like groove 2 and a lattice-like groove 3 by using a dicing blade after backside grinding (back grinding) of the wafer, and then performing isotropic silicon etching with a silicon etching apparatus. The damage layer formed on the uneven portion of the semiconductor chip is removed by blade processing. By performing this isotropic etching, the steep portions of the concavo-convex portions are rounded, and as shown in FIG. 2, a rounded inclined shape is formed on the bottom side surface of the concave portions and the end portions of the convex portions. By doing so, the adhesive 4 when the semiconductor chip 1 is fixed to the tab 5 can easily enter the concavo-convex portion 12 and not only enhance heat dissipation but also prevent damage to the semiconductor chip due to stress applied to the semiconductor chip. be able to. The groove depth at this time is determined according to the thickness of the semiconductor chip and the thickness of the semiconductor element.

図1(d)のように穴3を有する形状は、異方性シリコンエッチング加工を行うことで形成できる。異方性シリコンエッチング加工の後に、等方性シリコンエッチング加工を施すことで凹部の底側面および凸部の端部に丸みのある傾斜形状13を形成することができる。   The shape having the hole 3 as shown in FIG. 1D can be formed by performing anisotropic silicon etching. By performing isotropic silicon etching after the anisotropic silicon etching process, it is possible to form a sloped shape 13 having rounded bottom side surfaces of the recesses and ends of the protrusions.

図1(b)〜(d)に示した溝2や穴3の形状はレーザー加工によっても得られる。レーザー加工の場合にはシリコンを溶融して溝2や穴3を形成するため、凹凸部に急峻な部分を持たないが、溶融したシリコンがウェハ裏面に飛び散り不具合となる場合がある。このような場合にはレーザー加工後にウェハ洗浄するかウェハ裏面のわずかな(1〜5μm)研削を行うことで溶融シリコンの突起を除去することができる。   The shapes of the groove 2 and the hole 3 shown in FIGS. 1B to 1D can also be obtained by laser processing. In the case of laser processing, since the groove 2 and the hole 3 are formed by melting silicon, the uneven portion does not have a steep portion, but the melted silicon may be scattered on the back surface of the wafer and cause a problem. In such a case, the projection of the molten silicon can be removed by cleaning the wafer after laser processing or grinding the back surface of the wafer slightly (1 to 5 μm).

図3はSOI構造の半導体基板に凹凸形状を形成した半導体チップを示す断面図である。半導体チップ1には埋め込み絶縁膜14が形成され、埋め込み絶縁膜14の下面近傍から半導体チップ裏面にかけて凹凸形状12が設けられている。このようにすることで、蓄熱しやすいSOI構造の半導体基板でも良好な放熱性を有する半導体チップとすることができる。   FIG. 3 is a cross-sectional view showing a semiconductor chip in which an uneven shape is formed on a SOI structure semiconductor substrate. A buried insulating film 14 is formed on the semiconductor chip 1, and an uneven shape 12 is provided from the vicinity of the lower surface of the buried insulating film 14 to the back surface of the semiconductor chip. By doing in this way, it can be set as the semiconductor chip which has favorable heat dissipation also with the semiconductor substrate of SOI structure which is easy to store heat.

図4は、図1や図3で説明した半導体チップを樹脂封止した半導体装置の断面図である。リードフレームのタブ5上に金属ペーストからなる接着剤4で半導体チップ1の裏面を固着し、半導体チップの表面とリード端子とを金線7等のワイヤにてワイヤボンドする。タブ上の半導体チップとリード端子の一部(インナーリード部)は樹脂8にて封止され、アウターリードだけが樹脂から露出する半導体装置となる。なお、接着剤4が半導体チップ1の凹凸部12に充分入り込む必要があるため、接着剤4と半導体チップ1との固着は大気圧より低圧である減圧雰囲気で行うのが望ましい。減圧雰囲気とすることで接着剤4に含有される気体が脱気され、接着剤4と凹凸部12間の脱気も促進され、凹凸部12に接着剤4が十分に入り込むことになる。これにより互いの接着面積が増加して半導体チップが発する熱を効率良くタブ5に伝熱することになる。   FIG. 4 is a cross-sectional view of a semiconductor device in which the semiconductor chip described in FIGS. 1 and 3 is sealed with resin. The back surface of the semiconductor chip 1 is fixed to the tab 5 of the lead frame with an adhesive 4 made of a metal paste, and the surface of the semiconductor chip and the lead terminal are wire-bonded with a wire such as a gold wire 7. The semiconductor chip on the tab and a part of the lead terminal (inner lead portion) are sealed with the resin 8, so that only the outer lead is exposed from the resin. In addition, since it is necessary for the adhesive 4 to sufficiently enter the concavo-convex portion 12 of the semiconductor chip 1, it is desirable that the adhesive 4 and the semiconductor chip 1 be fixed in a reduced pressure atmosphere at a pressure lower than atmospheric pressure. By setting it as a pressure-reduced atmosphere, the gas contained in the adhesive agent 4 is deaerated, the deaeration between the adhesive agent 4 and the uneven | corrugated | grooved part 12 is accelerated | stimulated, and the adhesive agent 4 penetrates into the uneven | corrugated | grooved part 12 fully. As a result, the mutual bonding area increases and the heat generated by the semiconductor chip is efficiently transferred to the tab 5.

図5は、ガラスエポキシあるいはセラミック等の基板9上に実装した半導体装置の断面図である。図1および図3に示した半導体チップ1表面上に突起電極11を設け、基板9上に配線された電極パターン10にリフロー等により接合させる。このとき半導体チップ1の裏面の凹凸は表面積が大きく、ヒートシンクの放熱用フィンと同様の役目を果たす。   FIG. 5 is a cross-sectional view of a semiconductor device mounted on a substrate 9 such as glass epoxy or ceramic. Projecting electrodes 11 are provided on the surface of the semiconductor chip 1 shown in FIGS. 1 and 3 and bonded to the electrode pattern 10 wired on the substrate 9 by reflow or the like. At this time, the unevenness on the back surface of the semiconductor chip 1 has a large surface area and plays the same role as the heat dissipation fin of the heat sink.

以上、説明したように、半導体チップの裏面にダメージフリーの凹凸形状を設けることで放熱性の良好な半導体装置とすることができる。   As described above, by providing a damage-free uneven shape on the back surface of the semiconductor chip, a semiconductor device with good heat dissipation can be obtained.

1 半導体チップ
2 半導体チップ裏面の溝
3 半導体チップ裏面の穴
4 接着剤(Agペースト)
5 タブ
6 リード端子
7 金線
8 樹脂
9 基板(ガラスエポキシ又はセラミック等)
10 電極パターン
11 突起電極(半田バンプ等)
12 凹凸形状(凹凸部)
13 傾斜形状(傾斜部)
14 埋め込み絶縁膜
DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Groove | channel on the semiconductor chip back surface 3 Hole 4 on the semiconductor chip back surface Adhesive (Ag paste)
5 Tab 6 Lead terminal 7 Gold wire 8 Resin 9 Substrate (glass epoxy or ceramic)
10 Electrode pattern 11 Projection electrode (solder bump, etc.)
12 Uneven shape (uneven portion)
13 Inclined shape (inclined part)
14 buried insulating film

Claims (10)

樹脂モールドで覆われた半導体チップを有する半導体装置であって、前記半導体チップの裏面に凹凸部を有し、前記凹凸部の凹部底側面および凸部端部に傾斜形状が形成されていることを特徴とする半導体装置。   A semiconductor device having a semiconductor chip covered with a resin mold, having a concavo-convex portion on a back surface of the semiconductor chip, and having an inclined shape formed on a concave bottom side surface and a convex end portion of the concavo-convex portion. A featured semiconductor device. 表面に突起電極を形成した半導体チップを有する半導体装置であって、前記半導体チップの裏面に凹凸部を有し、前記凹凸部の凹部底側面および凸部端部に傾斜形状が形成されていることを特徴とする半導体装置。   A semiconductor device having a semiconductor chip having a protruding electrode formed on the surface, wherein the semiconductor chip has a concavo-convex portion on the back surface, and an inclined shape is formed on the concave bottom surface and the convex end of the concavo-convex portion. A semiconductor device characterized by the above. 前記半導体チップは、埋め込み絶縁膜を有するSOI構造の半導体基板からなり、前記凹凸部は前記半導体チップ裏面から前記埋め込み絶縁膜の下面近傍まで達することを特徴とする請求項1または請求項2記載の半導体装置   3. The semiconductor chip according to claim 1, wherein the semiconductor chip is formed of an SOI structure semiconductor substrate having a buried insulating film, and the concavo-convex portion reaches from the back surface of the semiconductor chip to the vicinity of the lower surface of the buried insulating film. Semiconductor device 前記凹凸部の凹部は、平面視にてストライプ状の溝であることを特徴とする請求項1乃至請求項3のいずれか1項記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the concave portion of the concave-convex portion is a stripe-shaped groove in a plan view. 前記凹凸部の凹部は、平面視にて格子状の溝であることを特徴とする請求項1乃至請求項3のいずれか1項記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the concave portion of the concave-convex portion is a lattice-like groove in a plan view. 前記凹凸部の凹部は、平面視にて複数の穴であることを特徴とする請求項1乃至請求項3のいずれか1項記載の半導体装置。   The semiconductor device according to claim 1, wherein the concave portion of the concave and convex portion is a plurality of holes in a plan view. 樹脂モールドで覆われた半導体チップを有する半導体装置の製造方法であって、
前記半導体チップの裏面に凹凸部を形成する工程と、
前記半導体チップをリードフレームのタブ上に接着剤を介して固着する工程と、
前記半導体チップとインナーリードとをワイヤボンドする工程と、
前記半導体チップと前記インナーリードと前記ワイヤボンド用のワイヤとを覆うように樹脂封止する工程と、からなり、
前記固着する工程は減圧雰囲気で行うことを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device having a semiconductor chip covered with a resin mold,
Forming an uneven portion on the back surface of the semiconductor chip;
Fixing the semiconductor chip on the tab of the lead frame via an adhesive;
Wire bonding the semiconductor chip and the inner lead;
A step of resin sealing so as to cover the semiconductor chip, the inner lead, and the wire for wire bonding,
The method of manufacturing a semiconductor device, wherein the fixing step is performed in a reduced pressure atmosphere.
前記凹凸部を形成する工程は、ダイシングブレードによる溝形成工程と等方性シリコンエッチング工程とからなることを特徴とする請求項7記載の半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 7, wherein the step of forming the concavo-convex portion includes a groove forming step using a dicing blade and an isotropic silicon etching step. 前記凹凸部を形成する工程は、レーザー加工による穴形成工程と飛散した溶融シリコン除去工程とからなることを特徴とする請求項7記載の半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 7, wherein the step of forming the concavo-convex portion includes a hole forming step by laser processing and a scattered molten silicon removing step. 前記凹凸部を形成する工程は、異方性シリコンエッチング工程と等方性エッチング工程とからなることを特徴とする請求項7記載の半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 7, wherein the step of forming the uneven portion includes an anisotropic silicon etching step and an isotropic etching step.
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