JP2010178229A - Solid-state image sensor - Google Patents

Abstract

Even when a high gain is obtained when processing a pixel signal to be read, variations in gain are suppressed without increasing the time required for signal sampling.
A signal processing unit 16 includes an input capacitor Ci to which a signal from a pixel is input, and an operational amplifier OP to which an input capacitor Ci is connected to an inverting input terminal and a predetermined potential Vref is applied to a non-inverting input terminal. And a feedback circuit FB connected between the inverting input terminal and the output terminal of the operational amplifier OP. The feedback circuit FB includes a plurality of connection states in which two or more capacitors are connected in series between the inverting input terminal and the output terminal of the operational amplifier OP and between the inverting input terminal and the output terminal of the operational amplifier OP. It is composed of a plurality of capacitors Cf11, Cf21, Cf31, Cf32 and one or more switches SW0 to SW3 so that the connection state can be switched.
[Selection] Figure 2

Description

  The present invention relates to a solid-state imaging device.

  FIG. 8 of Patent Document 1 below discloses a solid-state imaging device using a switched capacitor type integration circuit for a pixel signal readout circuit. Since this switched capacitor type integration circuit is the same as the signal processing unit 116 (see FIG. 4) employed in the solid-state imaging device according to the comparative example described later, see also the description of the comparative example described later.

  In the switched capacitor type integrating circuit employed in this conventional solid-state imaging device, a feedback circuit of a differential amplifier (operational amplifier) is composed of a plurality of switches and a plurality of capacitors. The gain can be changed by changing the capacitance value of the entire feedback circuit depending on the on / off state of each switch. Then, any capacitor constituting the feedback circuit is connected in parallel between the inverting input terminal and the output terminal of the differential amplifier when the corresponding switch is turned on. Therefore, when obtaining a high gain, only a capacitor having a small capacitance value is connected between the inverting input terminal and the output terminal of the differential amplifier. For this reason, the higher the gain, the smaller the capacitance required.

  However, the capacitance value of the capacitance is proportional to the area of the capacitance, and the variation in the capacitance value increases as the capacitance area decreases. Therefore, a capacitance with a small capacitance value has a significant variation in capacitance value, resulting in a variation in gain. As described above, in the switched capacitor integration circuit employed in the solid-state imaging device disclosed in FIG. 8 of Patent Document 1, the gain variation increases particularly when a high gain is obtained.

Therefore, in the solid-state imaging device disclosed in FIG. 1 and FIG. 2 of Patent Document 1, a signal output from a pixel is sampled a plurality of times per pixel, and the signal sampled a plurality of times is added and output. A readout circuit is employed. According to this solid-state imaging device, even when a high gain is obtained, it is not necessary to use a capacitor having a small capacitance value, so that variations in gain can be suppressed.
JP 2005-269471 A

  However, in the solid-state imaging device disclosed in FIG. 1 and FIG. 2 of Patent Document 1, in order to obtain a high gain, a signal output from the pixel must be sampled a plurality of times per pixel, and the gain is As the size increases, the number of samplings must be increased. Therefore, according to this conventional solid-state imaging device, in order to obtain a high gain, a relatively long time is required for many times of sampling, resulting in a disadvantage that the frame rate is lowered.

  The present invention has been made in view of such circumstances, and even when a high gain is obtained when processing a pixel signal to be read out, a solid state that can suppress variations in gain without reducing the frame rate. An object is to provide an imaging device.

  The following aspects are presented as means for solving the problems. The solid-state imaging device according to the first aspect includes (i) a pixel that photoelectrically converts incident light, (ii) an input capacitor to which a signal from the pixel or a signal corresponding thereto is input, and (iii) a first An operational amplifier in which the input capacitor is connected to the input terminal and a predetermined potential is applied to the second input terminal; and (iv) a short circuit between the first input terminal and the output terminal of the operational amplifier. One individual circuit, a second individual circuit having a plurality of capacitors connected in series between the first input terminal and the output terminal, and provided in the first individual circuit. And a feedback circuit having at least one switch for turning on and off between the input terminal and the output terminal.

  The solid-state imaging device according to a second aspect is the solid state imaging device according to the first aspect, wherein the second individual circuit is at least one connected in series to the plurality of capacitors between the first input terminal and the output terminal. A capacitor having a capacitance value larger than a capacitance value formed by the plurality of capacitors connected in series in the second individual circuit; and the first input terminal. And a third individual circuit having at least one switch connected in series with the capacitor having the large capacitance value between the output terminal and the output terminal.

  In the solid-state imaging device according to the third aspect, in the first or second aspect, the capacitance values of the plurality of capacitors connected in series in the second individual circuit are substantially the same.

  In the second aspect, the solid-state imaging device according to the fourth aspect includes the capacitance values of the plurality of capacitors connected in series in the second individual circuit and the capacitances in the third individual circuit. The capacitance value is substantially the same.

  The solid-state imaging device according to a fifth aspect is the solid-state imaging device according to the second aspect, wherein the feedback circuit connects the second individual circuit and the third individual circuit, and the second individual circuit is the third element. When the connection switch is turned on and the second individual circuit and a part of the third individual circuit are shared with each other circuit Further, the feedback circuit forms the second individual circuit in which the plurality of capacitors are connected in series between the first input terminal and the output terminal.

  In the solid-state imaging device according to the sixth aspect, in the fifth aspect, when the connection switch is turned off and the second individual circuit and the third individual circuit are disconnected, the feedback circuit is The third individual circuit to which a capacitor having a capacitance value larger than a capacitance value formed by the plurality of capacitors connected in series in the second individual circuit is connected to the first input terminal and the It is formed between the output terminals.

  A solid-state imaging device according to a seventh aspect includes (i) a pixel that photoelectrically converts incident light, (ii) an input capacitor to which a signal from the pixel or a signal corresponding thereto is input, and (iii) a first An operational amplifier having the input capacitor connected to the input terminal and a predetermined potential applied to the second input terminal; and (iv) at least one switch and a plurality of capacitors. A first connection state in which a terminal is short-circuited between the terminal and the output terminal of the operational amplifier, and a predetermined number of capacitors among the plurality of capacitors are connected in series, and between the first input terminal and the output terminal And a feedback circuit that switches a second connection state that forms a predetermined capacitance value by the at least one switch.

  The solid-state imaging device according to an eighth aspect is the seventh aspect, wherein the feedback circuit has a capacitance value different from the predetermined capacitance value by the first input by at least one of the plurality of capacitors. A third connection state formed between the terminal and the output terminal is provided.

  In the seventh or eighth aspect, the solid-state imaging device according to the ninth aspect is the first input terminal and the output terminal by the feedback circuit only when the predetermined number of capacitors are connected in series to each other. Can contribute to the formation of a capacitance value between the two.

  The solid-state imaging device according to a tenth aspect is the seventh or eighth aspect, wherein the predetermined number of capacitors are connected to the first input terminal and the output terminal by the feedback circuit even when they are not connected in series with each other. It can contribute to the formation of a capacitance value between.

  According to the present invention, it is possible to provide a solid-state imaging device capable of suppressing gain variation without reducing the frame rate even when a high gain is obtained when processing a pixel signal to be read.

  Hereinafter, a solid-state imaging device according to the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a circuit diagram showing a solid-state imaging device 1 according to the first embodiment of the present invention. The solid-state image sensor 1 according to the present embodiment is configured as a CMOS solid-state image sensor.

  As shown in FIG. 1, a solid-state imaging device 1 according to the present embodiment has a plurality of pixels 11 (in FIG. 1) that are arranged two-dimensionally and photoelectrically convert incident light, like a general CMOS solid-state imaging device. Only the 2 × 2 pixels 11 are shown.), The vertical scanning circuit 12, the horizontal scanning circuit 13, and the output signal of the pixel 11 in the corresponding column provided corresponding to each column of the pixel 11 is supplied. Vertical signal lines 14 and constant current sources 15 connected to the vertical signal lines 14. Needless to say, the number of pixels 11 is not limited. In FIG. 1, Vdd is a power supply potential.

  Each pixel 11, like a general CMOS type solid-state imaging device, receives a photodiode PD as a photoelectric conversion unit that generates and accumulates a charge according to incident light, and converts the charge into a voltage by receiving the charge. Floating diffusion FD as a charge-voltage conversion unit, amplification transistor AMP as an amplification unit that outputs a signal corresponding to the potential of the floating diffusion FD, and transfer as a charge transfer unit that transfers charges from the photodiode PD to the floating diffusion FD A transistor TX, a reset transistor RES as a reset unit for resetting the potential of the floating diffusion FD, and a selection transistor SEL as a selection unit for selecting the pixel 11 are connected as shown in FIG. Yes.

  The gates of the transfer transistors TX are commonly connected to each row, and a control signal φTX for controlling the transfer transistors TX is supplied from the vertical scanning circuit 12 to the transfer transistors TX. The gates of the reset transistors RES are commonly connected to each row, and a control signal φRES for controlling the reset transistors RES is supplied from the vertical scanning circuit 12 to the reset transistors RES. The gates of the selection transistors SEL are commonly connected to each row, and a control signal φSEL for controlling the selection transistors SEL is supplied from the vertical scanning circuit 12 to the selection transistors SEL.

  The photodiode PD generates an electric charge according to the amount of incident light (subject light). The transfer transistor TX is turned on during the high level period of the transfer pulse (control signal) φTX, and transfers the charge accumulated in the photodiode PD to the floating diffusion FD. The reset transistor RES is turned on during a high level period of the reset pulse (control signal) φRES to reset the floating diffusion FD.

  The amplification transistor AMP has a drain connected to the power supply potential Vdd, a gate connected to the floating diffusion FD, a source connected to the drain of the selection transistor SEL, and a source follower circuit having the constant current source 15 as a load. is doing. The amplification transistor AMP outputs a read current to the vertical signal line 14 via the selection transistor SEL according to the voltage value of the floating diffusion FD. The selection transistor SEL is turned on during the high level period of the selection pulse (control signal) φSEL, and connects the source of the amplification transistor AMP to the vertical signal line 14.

  The vertical scanning circuit 12 receives a driving pulse (not shown) from the outside and outputs a selection pulse φSEL, a reset pulse φRES, and a transfer pulse φTX for each row of the pixels 11. The horizontal scanning circuit 13 receives a driving pulse (not shown) from the outside and outputs a horizontal scanning signal φH for each column.

  Further, the solid-state imaging device 1 according to the present embodiment includes a plurality of signal processing units 16, and the signal processing units 16 are provided corresponding to the respective vertical signal lines 14. FIG. 2 is an enlarged circuit diagram showing one signal processing unit 16 in FIG. The signal processing unit 16 includes an input capacitor Ci, an operational amplifier OP, and a feedback circuit FB, and outputs a signal corresponding to the signal on the corresponding vertical signal line 14 from the output terminal of the operational amplifier OP.

  A signal of the vertical signal line 14 (and therefore a signal from the pixel 11) is input to the input capacitor Ci. If necessary, for example, the signal of the vertical signal line 14 may be amplified by an amplifier and then input to the input capacitor Ci. An electrode of the input capacitor Ci opposite to the vertical signal line 14 side is connected to an inverting input terminal (−input terminal) as a first input terminal of the operational amplifier OP. A predetermined potential Vref is applied to a non-inverting input terminal (+ input terminal) as a second input terminal of the operational amplifier OP. The operational amplifier OP is configured using a differential amplifier circuit or the like.

  The feedback circuit FB is connected between the inverting input terminal of the operational amplifier OP and the output terminal of the operational amplifier OP. The feedback circuit FB is connected between the inverting input terminal and the output terminal of the operational amplifier OP in a short-circuited connection state (hereinafter referred to as a short-circuit connection state) and a connection state in which a capacitor is connected (hereinafter referred to as a capacitance connection state). It is composed of a plurality of capacitors Cf11, Cf21, Cf31, Cf32 and one or more switches SW0 to SW3 so that they can be switched. In the capacitor connection state, the capacitors Cf11, Cf21, Cf31, Cf32 and the plurality of switches SW0 to SW3 are configured to be appropriately switchable so as to obtain a desired gain. As a result, the feedback circuit FB can take a plurality of capacitive connection states, and one of the capacitive connection states is selected according to the required gain. In at least one of the capacitor connection states, capacitors Cf31 and Cf32 are connected in series. In the present embodiment, the feedback circuit FB includes four individual circuits connected in parallel to each other between the inverting input terminal and the output terminal of the operational amplifier OP. Specifically, the feedback circuit FB includes a first individual circuit configured by the switch SW0, a second individual circuit configured by a series circuit of the switch SW1 and the capacitor Cf11, and a switch SW2 and the capacitor Cf21. A third individual circuit configured by a series circuit and a fourth individual circuit configured by a series circuit of the switch SW3 and the two capacitors Cf31 and Cf32 are included. In the following description, each capacity and its capacity value are represented by the same reference numerals. The capacitance value of each capacitor of the feedback circuit FB is not particularly limited and may be appropriately different. In this embodiment, Cf11 = Ci / 2 and Cf21 = Cf31 = Cf32 = Ci / 4 are set. It shall be. Therefore, the capacitance value of the second individual circuit is Ci / 2, the capacitance value of the third individual circuit is Ci / 4, and the capacitance value of the fourth individual circuit is Ci / 8. Among the values, the capacitance value of the fourth individual circuit is the smallest. Here, the capacitance value of the individual circuit refers to the capacitance value of the entire individual circuit when the switch of the individual circuit is closed.

  In the present embodiment, the individual circuit configured by the switch SW0 is an individual circuit that short-circuits between the inverting input terminal and the output terminal of the operational amplifier OP, and the individual circuit includes the operational amplifier OP. At least one switch SW0 that turns on and off between the inverting input terminal and the output terminal is provided. In the present embodiment, the individual circuit configured by the series circuit of the switch SW3 and the two capacitors Cf31 and Cf32 includes a plurality of capacitors connected in series between the inverting input terminal and the output terminal of the operational amplifier OP. It is an individual circuit having Cf31 and Cf32. Further, in the present embodiment, the individual circuit configured by the series circuit of the switch SW1 and the capacitor Cf11 is formed by the plurality of capacitors Cf31 and Cf32 connected in series in the individual circuit having the plurality of capacitors Cf31 and Cf32. The capacitor Cf11 having a capacitance value larger than the capacitance value to be generated, and at least one switch SW1 connected in series with the capacitor Cf11 between the inverting input terminal and the output terminal of the operational amplifier OP. Furthermore, in the present embodiment, the individual circuit configured by the series circuit of the switch SW2 and the capacitor Cf21 is constituted by the plurality of capacitors Cf31 and Cf32 connected in series in the individual circuit having the plurality of capacitors Cf31 and Cf32. The capacitor Cf21 having a capacitance value larger than the capacitance value to be formed, and at least one switch SW2 connected in series with the capacitor Cf21 between the inverting input terminal and the output terminal of the operational amplifier OP.

  The feedback circuit FB is in a connection state in which the inverting input terminal and the output terminal are short-circuited by turning on the switch SW0. Further, the feedback circuit FB has a total of seven connection states depending on which one or more of the switches SW1 to SW3 are turned on while the switch SW0 is turned off. In accordance with these seven connection states, the capacitance value CF (hereinafter referred to as “feedback capacitance value”) CF between the inverting input terminal and the output terminal of the operational amplifier OP formed by the feedback circuit FB is 7. Different types of values. In the present embodiment, the switches SW0 to SW3 are each composed of a MOS transistor. Control signals φSW0 to φSW3 are supplied from the outside to the gates of the switches SW0 to SW3, respectively. These control signals φSW0 to φSW3 serve as gain setting signals for setting the gain of the signal processing unit 16. In the present embodiment, the switches SW0 to SW3 are turned on when the corresponding control signals φSW0 to φSW3 are at the high level, and are turned off when the corresponding control signals φSW0 to φSW3 are at the low level.

  In the present embodiment, when the switch SW3 is turned on with the switch SW0 turned off, the connection state of the feedback circuit FB is such that the two capacitors Cf31 and Cf32 are connected in series between the inverting input terminal and the output terminal of the operational amplifier OP. The capacitors Cf31 and Cf32 contribute to the formation of the feedback capacitance value CF. On the other hand, when the switch SW3 is turned off, the two capacitors Cf31 and Cf32 are both disconnected from the inverting input terminal and the output terminal of the operational amplifier OP and do not contribute to the formation of the feedback capacitance value CF.

  According to the signal processing unit 16, when the signal φSW0 becomes high level, the switch SW0 is turned on, the inverting input terminal and the output terminal of the operational amplifier OP are short-circuited, and the output terminal of the operational amplifier OP is set to the predetermined potential Vref. To be clamped. Thereafter, when the voltage of the vertical signal line 14 changes by ΔV in a state where the signal φSW0 is set to the low level, the switch SW0 is turned off, and one or more of the switches SW1 to SW3 is turned on, the operational amplifier The signal at the output terminal of OP is {Vref− (Ci / CF) × ΔV}. As described above, when the switch SW0 is turned off, an inversion gain (−Ci / CF) is obtained as the gain of the signal processing unit 16 by the ratio of the capacitance value of the input capacitance Ci and the feedback capacitance value CF. In this embodiment, since Cf11 = Ci / 2 and Cf21 = Cf31 = Cf32 = Ci / 4 as described above, this inversion gain is, for example, -2 when only the switch SW1 is on, and the switch SW2. When only the switch SW3 is on, the magnification is -4 times.

  Further, the solid-state imaging device 1 according to the present embodiment includes a sample hold unit 17 provided corresponding to each vertical signal line 14. Each sample and hold unit 17 samples a signal corresponding to the signal of each vertical signal line 14 (in this embodiment, a signal at the output terminal of each operational amplifier OP of the signal processing unit 16) according to the sampling control signals φTVN and φTVS. The held signal is supplied to the horizontal signal lines 18N and 18S according to the horizontal scanning signal φH.

  In the present embodiment, the sample hold unit 17 includes optical signal storage capacitors CS and reset signal storage capacitors CN provided corresponding to the respective vertical signal lines 14, and optical information photoelectrically converted by the pixels 11. An optical signal sampling switch TVS for storing the optical signal in the optical signal storage capacitor CS according to the optical signal sampling control signal φTVS, and a reset signal including a noise component to be subtracted from the optical signal is reset according to the reset signal sampling control signal φTVN. A reset signal sampling switch TVN for storing in the signal storage capacitor CN, and an optical signal horizontal transfer switch for supplying the optical signal stored in the optical signal storage capacitor CS to the optical signal horizontal signal line 18S in accordance with the horizontal scanning signal φH. THS and reset signal stored in reset signal storage capacitor CN are horizontal And a horizontal transfer switch THN reset signal supplied to the horizontal signal line 18N reset signal in accordance with scanning signal No. .phi.H. In the present embodiment, transistors RTHN and RTHS are provided for resetting the horizontal signal lines 18N and 18S to a predetermined potential Vref at a predetermined timing, respectively. The transistors RTHN and RTHS receive an external control signal φRTH and turn on when the control signal φRTH is at a high level, and turn off when the control signal φRTH is at a low level. Output amplifiers APN and APS are connected to the horizontal signal lines 18N and 18S, respectively. In the present embodiment, the switches TVS, TVN, THS, THN, RTHN, and RTHS are MOS transistors.

  As shown in FIG. 1, corresponding to each vertical signal line 14, the output terminal of the operational amplifier OP is connected to one end of the optical signal sampling switch TVS and one end of the reset signal sampling switch TVN of the sample hold unit 17. ing. As a result, the signal at the output terminal of each operational amplifier OP corresponding to the signal on each vertical signal line 14 is supplied to the sampling switches TVN and TVS as signals to be turned on / off.

  The gates of the reset signal sampling switches TVN provided corresponding to the vertical signal lines 14 are connected in common, and a reset signal sampling control signal φTVN is supplied from the outside to the gates. The reset signal sampling switch TVN is turned on when the reset signal sampling control signal φTVN is at a high level, and turned off when the reset signal sampling control signal φTVN is at a low level. When the reset signal sampling switch TVN is turned on in response to the reset signal sampling control signal φTVN, the reset signal at the output terminal of the operational amplifier OP is stored in the corresponding reset signal storage capacitor CN.

  The gates of the optical signal sampling switches TVS provided corresponding to the vertical signal lines 14 are connected in common, and an optical signal sampling control signal φTVS is supplied to the gate from the outside. The optical signal sampling switch TVS is turned on when the optical signal sampling control signal φTVS is at a high level, and is turned off when the optical signal sampling control signal φTVS is at a low level. When the optical signal sampling switch TVS is turned on in response to the optical signal sampling control signal φTVS, the optical signal at the output terminal of the operational amplifier OP is stored in the corresponding optical signal storage capacitor CS.

  For each column, the gates of the horizontal transfer switch for optical signal THS and the horizontal transfer switch for reset signal THN are connected in common, and the horizontal scanning signal φH of the corresponding column is supplied from the horizontal scanning circuit 13 thereto. When the horizontal transfer switches THS, THN of each column are turned on in accordance with the horizontal scanning signal φH of each column, the optical signals stored in the optical signal storage capacitor CS and the reset signal storage capacitor CN of the corresponding column, The reset signal is output to the optical signal horizontal signal line 18S and the reset signal horizontal signal line 18N, respectively, and is output to an external signal processing unit (not shown) via the output amplifiers APS and APN, respectively. Although not shown in the drawing, the external signal processing unit obtains a difference between outputs of the output amplifiers APS and APN by a differential amplifier or the like. Thus, correlated double sampling is realized, and an optical information signal from which fixed pattern noise and the like are removed is obtained as an image signal from the external signal processing unit. A differential amplifier or the like that obtains such a difference may be mounted on the solid-state imaging device 1.

  FIG. 3 is a timing chart showing an example of the reading operation of the solid-state imaging device 1 according to the present embodiment.

  In the present embodiment, a mechanical shutter (not shown) is opened for a predetermined exposure period, and charges are accumulated in the charge accumulation layer of the photodiode PD of each pixel 11. The same operation is sequentially performed on the rows. FIG. 3 mainly shows the operation when the pixel 11 in the nth row is selected and the pixel 11 in the (n + 1) th row is subsequently selected.

  The period T1 is a horizontal scanning period of the output of the pixels 11 in the (n-1) th row and corresponds to a period T3 described later. A period T2 after the period T1 is a horizontal blanking period of the output of the pixels 11 in the n-th row.

  In the period T2, the vertical scanning circuit 12 selects the pixel 11 in the n-th row, the n-th row reset pulse φRES (n) changes to the low level, and the n-th row reset transistor RES is turned off. Further, in the period T2, the selection pulse φSEL (n) in the nth row changes to a high level, and the selection transistor SEL in the nth row is turned on. When the selection transistor SEL in the nth row is turned on, the source of the amplification transistor AMP in the nth row is connected to the vertical signal line 14. The amplification transistor AMP in the n-th row operates as a source follower circuit by the constant current source 15.

  In the period from the start of the period T2 to the start of the period T12, the n-th row selection transistor SEL is turned on, and at the same time, the n-th row reset transistor RES is turned off. The gate voltage of the amplification transistor AMP becomes a floating state, and the reset level of the pixel 11 in the n-th row appears on the vertical signal line 14. At this time, in the period T10 after the period T2 is started, the control signal φSW0 becomes a high level and the switch SW0 is turned on, so that the signal processing unit 16 uses the reset level of the vertical signal line 14 as an input reference. In this state, the level of the output terminal of the operational amplifier OP is clamped to the predetermined potential Vref. In the period T11 in the period T2, the reset signal sampling pulse (control signal) φTVN changes to the high level, and the reset signal sampling switch TVN is turned on. Thereby, the reset signal of the pixels 11 in the n-th row is accumulated in the reset signal storage capacitor CN. This operation is performed simultaneously in parallel on the pixels in each column of the nth row.

  Next, in the period T12 in the period T2, the transfer pulse φTX (n) in the nth row changes to a high level, and the transfer transistor TX in the nth row is turned on. When the transfer transistor TX in the n-th row is turned on, the signal charge photoelectrically converted and accumulated by the photodiode PD of the pixel 11 in the n-th row is transferred to the corresponding floating diffusion FD. As a result, the voltage of the floating diffusion FD becomes a voltage corresponding to the transferred charge amount, and this voltage is applied to the gate electrode of the amplification transistor AMP. As a result, a level including optical information of the pixels 11 in the nth row appears on the vertical signal line 14. At this time, the change due to the optical signal appears at the output terminal of the operational amplifier OP as a voltage inverted and amplified by the gain (−Ci / CF) with reference to Vref. As described above, the gain (−Ci / CF) is set by the control signals φSW1 to φSW3. In a period T13 after the period T12, the optical signal sampling pulse (control signal) φTVS changes to a high level, and the optical signal sampling switch TVS is turned on. As a result, the optical signal of the pixel in the n-th row is accumulated in the optical signal storage capacitor CS. This operation is performed simultaneously in parallel on the pixels in each column of the nth row.

  In this manner, in the period T2, the output signal of the pixel 11 in the n-th row is sampled, and the reset signal for the pixel 11 in the n-th row is accumulated in the reset signal storage capacitor CN for each column. The optical signal storage capacitor CS stores the optical signal of the pixel 11 in the n-th row.

  A period T3 after the period T2 is a horizontal scanning period of the output of the pixels 11 in the n-th row. In the period T3, the horizontal transfer switch THN for reset signal and the horizontal transfer switch THS for optical signal are sequentially turned on and stored for each corresponding to each vertical signal line 14 by horizontal scanning by the horizontal scanning signal φH from the horizontal scanning circuit 13. The reset signal and the optical signal respectively stored in the capacitors CN and CS are sequentially read out to the reset signal horizontal signal line 18N and the optical signal horizontal signal line 18S for each corresponding to each vertical signal line 14, and output. The signals are output to an external signal processing unit (not shown) via the amplifiers APN and APS, respectively. By taking the difference between the outputs of the output amplifiers APS and APN with the differential amplifier or the like of this external signal processing unit, an image output from which fixed pattern noise or the like is removed can be obtained.

  Next, in the periods T4 and T5, the same operation as that performed in the periods T2 and T3 for the nth row is performed for the (n + 1) th row, and the same operation is repeated thereafter.

  Here, a solid-state image sensor according to a comparative example compared with the solid-state image sensor 1 according to the present embodiment will be described. FIG. 4 is an enlarged circuit diagram showing one signal processing unit 116 used in the solid-state imaging device according to this comparative example, and corresponds to FIG. 4, elements that are the same as or correspond to those in FIG. 2 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The solid-state imaging device according to this comparative example differs from the solid-state imaging device 1 according to the present embodiment only in that a signal processing unit 116 is provided in place of each signal processing unit 16. The signal processing unit 116 is different from the signal processing unit 16 only in that one capacitor Cf33 is provided instead of the serial connection portion of the two capacitors Cf31 and Cf32. The signal processing unit 116 employed in this comparative example has the same configuration as the switched capacitor type integration circuit employed in the solid-state imaging device disclosed in FIG.

  In both the signal processing unit 16 and the signal processing unit 116, Cf11 = Ci / 2 and Cf21 = Ci / 4. In the signal processing unit 16, Cf31 = Cf32 = Ci / 4, whereas Cf33 = Ci / 8. . However, since the combined capacitance value of the serially connected portion of the two capacitors Cf31 and Cf32 is Ci / 8, the capacitance value of the individual circuit configured by the series circuit of the switch SW3, the capacitor Cf31, and the capacitor Cf32 in the signal processing unit 16. In addition, the capacitance value of the individual circuit configured by the series circuit of the switch SW3 and the capacitor Cf33 in the signal processing unit 116 is also Ci / 8. Therefore, when only the switch SW3 is turned on, the signal processing unit 16 and the signal processing unit 116 can obtain a high gain of −8 times.

  However, in the signal processing unit 116 of this comparative example, in order to obtain a high gain of -8 times, the capacitance Cf33 having a capacitance value as small as Ci / 8 is used. On the other hand, in the signal processing unit 16 of the present embodiment, two capacitors Cf31 and Cf32 having a capacitance value Ci / 4 that is twice that of the capacitor Cf33 are used in order to obtain a gain of -8 times. When the capacitance value of one capacitor is reduced, the variation in the capacitance value increases. Therefore, while the variation of the capacitance Cf33 is large, the variation of the capacitances Cf31 and Cf32 is small and the variation of the combined capacitance of the serially connected portions of the capacitors Cf31 and Cf32 is also small. Therefore, when obtaining a high gain, the gain variation obtained by the signal processing unit 116 of this comparative example increases, whereas the gain variation obtained by the signal processing unit 16 of the present embodiment is suppressed.

  In the signal processing unit 16 of the present embodiment, the signal processing unit 116 according to the comparative example and the switched capacitor type integration circuit employed in the solid-state imaging device disclosed in FIG. Unlike the readout circuit employed in the solid-state imaging device disclosed in FIG. 1 and FIG. 2 of Patent Document 1 described above, one pixel is sampled a plurality of times, and the signal sampled a plurality of times is added and output. Because it does not do, it has not sampled many times to obtain a high gain. Therefore, in the signal processing unit 16 of the present embodiment, as in the case of the signal processing unit 116 according to the comparative example, even when a high gain is obtained, it is not necessary to increase the time required for signal sampling.

  As described above, according to the present embodiment, even when a high gain is obtained when processing a pixel signal to be read, variation in gain can be suppressed without increasing the time required for signal sampling.

[Second Embodiment]
FIG. 5 is an enlarged circuit diagram showing one signal processing unit 26 used in the solid-state imaging device according to the second embodiment of the present invention, and corresponds to FIG. 5, elements that are the same as or correspond to those in FIG. 2 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The solid-state imaging device according to the present embodiment is different from the solid-state imaging device 1 according to the first embodiment only in that a signal processing unit 26 is provided in place of each signal processing unit 16.

  The signal processing unit 26 of the present embodiment is different from the signal processing unit 16 of the first embodiment in that one capacitor Cf34 is provided instead of the serial connection portion of the two capacitors Cf31 and Cf32. The switch SW5 is connected between the electrode on the opposite side of the switch SW2 of the capacitor Cf21 and the output terminal of the operational amplifier OP, the connection midpoint between the capacitor Cf21 and the switch SW5, the switch SW3 and the capacitor Cf34. This is only the point where the switch SW4 is connected to the midpoint of connection. The switches SW4 and SW5 are also composed of MOS transistors, and control signals φSW4 and φSW5 are supplied from the outside to the gates of the switches SW4 and SW5, respectively. In the present embodiment, the switches SW4 and SW5 are turned on when the corresponding control signals φSW4 and φSW5 are at a high level, and are turned off when the corresponding control signals φSW4 and φSW5 are at a low level. In the present embodiment, the control signals φSW4 and φSW5 are gain setting signals together with the control signals φSW0 to φSW3.

  In the signal processing unit 26 of the present embodiment and the signal processing unit 16 of the first embodiment, Cf11 = Ci / 2 and Cf21 = Ci / 4, but in the signal processing unit 16, Cf31 = Cf32 = Ci / 4. On the other hand, in the signal processing unit 26, Cf34 = Ci / 4. The gains of −2 times, −4 times, and −8 times obtained in the signal processing unit 16 of the first embodiment turn on only the switch SW1 in the signal processing unit 26 of the present embodiment. Can be obtained by turning on only the switch SW3 (or only the switches SW2 and SW5) and turning on only the switches SW2 and SW4, respectively.

  In the signal processing unit 26 of the present embodiment, by turning on only the switches SW2 and SW4, the two capacitors Cf21 and Cf34 are connected in series between the inverting input terminal and the output terminal of the operational amplifier OP. These capacitors Cf21 and Cf34 contribute to the formation of the feedback capacitance value CF. Further, by turning on only the switch SW3 in the signal processing unit 26, only Cf34 contributes to the formation of the feedback capacitance value CF. Further, by turning on only the switches SW2 and SW5 in the signal processing unit 26, only Cf21 contributes to the formation of the feedback capacitance value CF.

  Also in the present embodiment, as in the first embodiment, even when a high gain is obtained when processing a pixel signal to be read out, gain variation without increasing the time required for signal sampling. Can be suppressed.

  In the signal processing unit 26 according to the present embodiment, two switches SW3 and SW4 are increased as compared with the signal processing unit 16 according to the first embodiment, but one capacitance value Ci / 4 is provided. Capacity is decreasing. If the capacitance value Ci / 4 is relatively large, the area occupied by one capacitance of the capacitance value Ci / 4 is larger than the area occupied by the two switches SW3 and SW4. Therefore, in the signal processing unit 26 according to the present embodiment, the occupied area can be suppressed as compared with the signal processing unit 16 according to the first embodiment.

  In the present embodiment, an individual circuit having a plurality of capacitors Cf21 and Cf34 in which the switch SW2, the capacitor C21, the switch S4, and the capacitor Cf34 are connected in series between the inverting input terminal and the output terminal of the operational amplifier OP. It is composed. In the present embodiment, the switch SW1 and the capacitor Cf11 have a capacitance value larger than the capacitance value formed by the plurality of capacitors Cf21 and Cf34 connected in series in the individual circuit having the plurality of capacitors Cf21 and Cf34. An individual circuit having a capacitor Cf11 and at least one switch SW1 connected in series with the capacitor Cf11 is formed between the inverting input terminal and the output terminal of the operational amplifier OP. Further, in the present embodiment, the switch SW2, the capacitor Cf21, and the switch SW5 are larger than the capacitance value formed by the plurality of capacitors Cf21 and Cf34 connected in series in the individual circuit having the plurality of capacitors Cf21 and Cf34. An individual circuit having a capacitance Cf21 having a capacitance value and at least one switch SW2, SW5 connected in series with the capacitance Cf21 between the inverting input terminal and the output terminal of the operational amplifier OP is configured. Furthermore, in the present embodiment, the switch SW3 and the capacitor Cf34 are larger in capacitance value than the capacitance value formed by the plurality of capacitors Cf21 and Cf34 connected in series in the individual circuit having the plurality of capacitors Cf21 and Cf34. And an at least one switch SW3 connected in series with the capacitor Cf34 between the inverting input terminal and the output terminal of the operational amplifier OP.

[Third Embodiment]
FIG. 6 is an enlarged circuit diagram showing one signal processing unit 36 used in the solid-state imaging device according to the third embodiment of the present invention, and corresponds to FIG. 6, elements that are the same as or correspond to those in FIG. 2 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The solid-state imaging device according to the present embodiment is different from the solid-state imaging device 1 according to the first embodiment only in that a signal processing unit 36 is provided in place of each signal processing unit 16.

  The signal processing unit 36 of the present embodiment is different from the signal processing unit 16 of the first embodiment in that a capacitor Cf41 and a capacitor Cf42 are used instead of the switches SW1 to SW3 and the capacitors Cf11, Cf21, Cf31, and Cf32. The only difference is that the series circuit is connected between the inverting input terminal and the output terminal of the operational amplifier OP.

  Therefore, the signal processing unit 16 of the first embodiment can obtain a variable gain, whereas the signal processing unit 36 of the present embodiment can obtain a fixed gain.

  However, also in the present embodiment, as in the first embodiment, the feedback circuit FB is connected between the inverting input terminal and the output terminal of the operational amplifier OP. A plurality of capacitors so that the connection state can be switched to a plurality of connection states including a connection state in which a short circuit is established and a connection state in which two or more capacitors Cf41 and Cf42 are connected in series between the inverting input terminal and the output terminal. Cf41, Cf42 and one or more switches SW0.

  Therefore, also in the present embodiment, as in the first embodiment, even when a high gain is obtained when processing a pixel signal to be read out, the gain is not increased without increasing the time required for signal sampling. The variation of can be suppressed.

  In the present embodiment, the individual circuit configured by the series circuit of the two capacitors Cf41 and Cf42 includes a plurality of capacitors Cf41 and Cf42 connected in series between the inverting input terminal and the output terminal of the operational amplifier OP. It has an individual circuit.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

1 is a circuit diagram showing a solid-state imaging device according to a first embodiment of the present invention. It is an enlarged circuit diagram which shows one signal processing part in FIG. 2 is a timing chart illustrating an example of a reading operation of the solid-state imaging device illustrated in FIG. 1. It is an enlarged circuit diagram which shows one signal processing part used with the solid-state image sensor by a comparative example. It is an enlarged circuit diagram which shows one signal processing part used with the solid-state image sensor by the 2nd Embodiment of this invention. It is an enlarged circuit diagram which shows one signal processing part used with the solid-state image sensor by the 3rd Embodiment of this invention.

DESCRIPTION OF SYMBOLS 1 Solid-state image sensor 11 Pixel 14 Vertical signal line 16, 26, 36 Signal processing part Ci Input capacity OP Operational amplifier FB Feedback circuit Cf11, Cf21, Cf31, Cf32, Cf34, Cf41, Cf42 Capacity SW0-SW3 switch

Claims (10)

A pixel that photoelectrically converts incident light;
An input capacitance to which a signal from the pixel or a signal corresponding thereto is input;
An operational amplifier having the input capacitor connected to the first input terminal and a predetermined potential applied to the second input terminal;
A first individual circuit that short-circuits between the first input terminal and the output terminal of the operational amplifier; and a plurality of capacitors connected in series between the first input terminal and the output terminal. And a feedback circuit having at least one switch provided in the first individual circuit and configured to turn on and off between the first input terminal and the output terminal. A solid-state imaging device. The second individual circuit has at least one switch connected in series to the plurality of capacitors between the first input terminal and the output terminal,
The feedback circuit includes a capacitor having a capacitance value larger than a capacitance value formed by the plurality of capacitors connected in series in the second individual circuit, and between the first input terminal and the output terminal. The solid-state imaging device according to claim 1, further comprising a third individual circuit including at least one switch connected in series with the capacitor having the large capacitance value.   3. The solid-state imaging device according to claim 1, wherein the capacitance values of the plurality of capacitors connected in series in the second individual circuit are substantially the same.   3. The capacitance values of the plurality of capacitors connected in series in the second individual circuit and the capacitance values of the capacitors in the third individual circuit are substantially the same. The solid-state imaging device described. The feedback circuit includes a connection switch that connects the second individual circuit and the third individual circuit, and that is turned on and off so that the second individual circuit shares a part of the third individual circuit. Have
When the connection switch is turned on and a part of the second individual circuit and the third individual circuit is shared, the feedback circuit is connected between the first input terminal and the output terminal. The solid-state imaging device according to claim 2, wherein the second individual circuit in which a plurality of capacitors are connected in series is formed. When the connection switch is turned off and the second individual circuit and the third individual circuit are disconnected, the feedback circuit is:
In the second individual circuit, the third individual circuit to which a capacitor having a capacitance value larger than a capacitance value formed by the plurality of capacitors connected in series is connected to the first input terminal and the output. The solid-state imaging device according to claim 5, wherein the solid-state imaging device is formed between the terminals. A pixel that photoelectrically converts incident light;
An input capacitance to which a signal from the pixel or a signal corresponding thereto is input;
An operational amplifier having the input capacitor connected to the first input terminal and a predetermined potential applied to the second input terminal;
A first connection state having at least one switch and a plurality of capacitors, and short-circuiting between the first input terminal and the output terminal of the operational amplifier; and a predetermined number of the plurality of capacitors A feedback circuit that switches a second connection state in which a predetermined capacitance value is formed between the first input terminal and the output terminal by the at least one switch.
A solid-state imaging device comprising:   The feedback circuit has a third connection state in which a capacitance value different from the predetermined capacitance value is formed between the first input terminal and the output terminal by at least one of the plurality of capacitors. The solid-state imaging device according to claim 7, comprising:   8. The predetermined number of capacitors can contribute to the formation of a capacitance value between the first input terminal and the output terminal by the feedback circuit only in a state where they are connected in series with each other. Or the solid-state image sensor of 8.   The predetermined number of capacitors can contribute to the formation of a capacitance value between the first input terminal and the output terminal by the feedback circuit even when they are not connected in series with each other. 8. The solid-state image sensor according to 8.

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