JP2010165794A - Semiconductor memory device - Google Patents

Abstract

There is provided a semiconductor memory device capable of suppressing the potential of an electrode layer functioning as a control gate of a memory cell from affecting other regions.
A semiconductor memory device according to the present invention includes a stacked body in which a plurality of electrode layers WL1 to WL5 and a plurality of insulating layers 24 are alternately stacked, which are provided over a memory cell region and a peripheral circuit region on a semiconductor substrate 11. , Charge accumulation provided between the semiconductor layer 21 provided in the hole formed through the stacked body in the memory cell region and extending in the stacking direction of the stacked body, and between the semiconductor layer 21 and the electrode layers WL1 to WL5. Layer 17 and a transfer transistor provided below the stacked body in the peripheral circuit region and transferring the potential to the electrode layers WL1 to WL5, and provided between the transfer transistor and the lowermost electrode layer WL1, and diffusion of the transfer transistor And a lower shield wiring layer SL1 to which a shield potential corresponding to the potential of the layer is applied.
[Selection] Figure 5

Description

  The present invention relates to a semiconductor memory device.

In a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type nonvolatile semiconductor memory device using a silicon nitride film as a data storage layer (charge storage layer), memory cells may be stacked on a substrate in order to increase the storage density. Has been done. For example, Patent Document 1 discloses a technique related to a nonvolatile semiconductor memory device having a structure in which a columnar semiconductor is provided in a direction perpendicular to a main surface of a substrate and a plurality of memory cells are connected in series in that direction.
When an electrode layer that functions as a control gate of a memory cell is provided to extend to the peripheral circuit region, depending on the potential of the electrode layer, the diffusion layer of the transistor formed in the peripheral circuit region has a high resistance and performs a desired operation. There is concern about the problem of being unable to do so.

JP 2007-180389 A

  The present invention provides a semiconductor memory device capable of suppressing the potential of an electrode layer functioning as a control gate of a memory cell from affecting other regions.

According to one embodiment of the present invention, a semiconductor substrate having a memory cell region and a peripheral circuit region, and a plurality of electrode layers and a plurality of insulating layers provided over the memory cell region and the peripheral circuit region on the semiconductor substrate. And a semiconductor layer that extends in the stacking direction of the electrode layer and the insulating layer, and is provided in a hole formed through the stack in the memory cell region. A charge storage layer provided between the semiconductor layer and the electrode layer; a transfer transistor provided under the stacked body in the peripheral circuit region; for transferring a potential to the electrode layer; and A lower shield wiring layer provided between the lower electrode layer and provided with a shield potential corresponding to the potential of the diffusion layer of the transfer transistor; That the semiconductor memory device is provided.
According to another aspect of the present invention, a semiconductor substrate having a memory cell region and a peripheral circuit region, a plurality of electrode layers provided over the memory cell region and the peripheral circuit region on the semiconductor substrate, A stacked body in which a plurality of insulating layers are alternately stacked, and provided in a hole formed through the stacked body in the memory cell region, and extends in a stacking direction of the electrode layer and the insulating layer. A semiconductor layer, a charge storage layer provided between the semiconductor layer and the electrode layer, a transfer transistor provided under the stacked body in the peripheral circuit region and transferring a potential to the electrode layer; A lower shield wiring layer provided between the transfer transistor and the lowermost electrode layer, to which a first shield potential according to the potential of the diffusion layer of the transfer transistor is applied; Provided on the electrode layer, and the upper shield wiring layer a second shield potential corresponding to the potential of the electrode layer is provided, a semiconductor memory device characterized by comprising a are provided.
According to yet another aspect of the present invention, a semiconductor substrate having a memory cell region and a peripheral circuit region, and a plurality of electrode layers provided over the memory cell region and the peripheral circuit region on the semiconductor substrate. And a plurality of insulating layers stacked alternately, and a hole formed through the stacked body in the memory cell region, and in the stacking direction of the electrode layer and the insulating layer An extended semiconductor layer, a charge storage layer provided between the semiconductor layer and the electrode layer, and an upper portion provided on the uppermost electrode layer and provided with a shield potential corresponding to the potential of the electrode layer There is provided a semiconductor memory device comprising a shield wiring layer.

  According to the present invention, there is provided a semiconductor memory device capable of suppressing the potential of an electrode layer functioning as a control gate of a memory cell from affecting other regions.

1 is a schematic diagram showing a planar positional relationship of main elements in a semiconductor memory device according to an embodiment of the present invention. The schematic diagram corresponding to the AA cross section of FIG. The schematic diagram corresponding to the BB cross section of FIG. The schematic diagram corresponding to the CC cross section of FIG. The schematic diagram corresponding to the DD cross section of FIG. The schematic diagram corresponding to the EE cross section of FIG. The schematic diagram corresponding to the FF cross section of FIG. Sectional drawing similar to FIG. 2 in other embodiment. Sectional drawing similar to FIG. 7 in other embodiment. Furthermore, sectional drawing similar to FIG. 7 in other embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Elements common to the drawings are given the same reference numerals.
FIG. 1 is a schematic diagram showing a planar positional relationship of main elements in a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a diagram corresponding to the AA cross section in FIG. 1.
FIG. 3 is a view corresponding to the BB cross section in FIG. 1.
FIG. 4 is a view corresponding to the CC cross section in FIG. 1.
FIG. 5 is a diagram corresponding to the DD cross section in FIG. 1.
FIG. 6 is a diagram corresponding to the EE cross section in FIG. 1.
FIG. 7 is a diagram corresponding to the FF cross section in FIG. 1.

  In this specification, for convenience of explanation, an XYZ orthogonal coordinate system is introduced. In this coordinate system, two directions parallel to the upper surface (main surface) of the semiconductor substrate and orthogonal to each other are defined as an X direction and a Y direction, and a direction perpendicular to the main surface of the semiconductor substrate is defined as Z direction. The direction.

  The semiconductor memory device according to the present embodiment includes a memory cell array 10 in which a plurality of memory cells are three-dimensionally arranged, a peripheral circuit 50 that performs operations such as writing data into the memory cells and reading data stored in the memory cells. On the same semiconductor substrate. FIG. 1 shows a row decoder that selects an electrode layer that functions as a control gate of a memory cell, among other peripheral circuits 50.

  First, a memory cell will be described with reference to FIG.

For example, n ⁻ type diffusion layers 12 and 13 and an n ⁺ type diffusion layer 14 are selectively formed on the surface of a p-type silicon substrate (or p-type well layer) 11. The diffusion layer 14 is connected to the cell source CS. On the surface of the substrate 11 between the diffusion layer 12 and the diffusion layer 13, a source-side selection gate SGS is provided via an insulating film 15. The source side select gate SGS is made of, for example, amorphous or polycrystalline silicon. The diffusion layers 12 to 14, the insulating film 15, and the source side selection gate SGS constitute a source side selection transistor.

  On the diffusion layer 12, a memory string MS configured by connecting a plurality of memory cells MC in series in the Z direction is provided. By controlling the gate voltage applied to the source side select gate SGS, the memory string MS and the cell source CS can be turned on and off.

  An interlayer insulating layer 19 is provided on the substrate 11, and a lower shield wiring layer SL <b> 1 (hereinafter also simply referred to as a shield wiring layer) is provided on the interlayer insulating layer 19. On the shield wiring layer SL1, a stacked body in which a plurality of insulating layers 24 and a plurality of electrode layers WL1 to WL5 are alternately stacked is provided. The number of electrode layers WL1 to WL5 is arbitrary, but in the present embodiment, for example, a case of five layers is illustrated.

  The shield wiring layer SL1 and the electrode layers WL1 to WL5 are made of, for example, amorphous or polycrystalline silicon. Alternatively, the shield wiring layer SL1 may be made of metal silicide or metal having a lower resistance.

  A drain-side selection gate SGD is provided on the uppermost insulating layer 24 on the stacked body, and insulating layers 25 and 26 are provided thereon. The drain side select gate SGD is made of, for example, amorphous or polycrystalline silicon. The upper surface of the insulating layer 26 is covered with the insulating film 18.

  A through hole extending in the Z direction and reaching the diffusion layer 12 is formed in the stacked body, and an insulating film 16, a charge storage layer 17, an insulating film 18, and a semiconductor layer 21 are provided on the side wall of the through hole. .

For example, the insulating film 16 is a silicon oxide film, the charge storage layer 17 is a silicon nitride film, and the insulating layer 18 is a silicon oxide film, and these constitute a so-called ONO (Oxide-Nitride-Oxide) film. The semiconductor layer 21 is, for example, n ⁻ type silicon. The semiconductor layer 21 is in contact with the diffusion layer 12 at the bottom of the through hole.

  A portion where the semiconductor layer 21 and each of the electrode layers WL1 to WL5 face each other with the ONO film interposed therebetween constitutes a memory cell MC. The semiconductor layer 21 functions as a channel in the memory cell MC, and each of the electrode layers WL1 to WL5 is a control gate. The charge storage layer 17 functions as a data storage layer that stores charges injected from the semiconductor layer 21.

  The memory cell MC is a memory cell having a charge trap structure, and the charge storage layer 17 has a large number of traps for trapping charges (electrons), and is made of, for example, a silicon nitride film. The insulating film 18 between the charge storage layer 17 and the semiconductor layer 21 diffuses the charge stored in the charge storage layer 17 into the semiconductor layer 21 when charges are injected from the semiconductor layer 21 into the charge storage layer 17. It becomes a potential barrier. The insulating film 16 between the charge storage layer 17 and the electrode layers WL1 to WL5 prevents the charges stored in the charge storage layer 17 from diffusing into the electrode layers WL1 to WL5. A plurality of memory cells MC corresponding to the number of electrode layers WL1 to WL5 are connected in series in the Z direction to form a memory string MS.

A p ⁻ type semiconductor layer 22 and an n ⁺ type semiconductor layer 23 are provided on the semiconductor layer 21 by ion implantation, respectively. The drain side select gate SGD faces the semiconductor layer 22 with the insulating film 18 interposed therebetween, and thereby a drain side select transistor is configured.

  A portion of the semiconductor layer 23 provided on the upper surface of the insulating film 18 is converted into metal silicide, and the portion is connected to the bit line BL. By controlling the gate voltage applied to the drain side select gate SGD, on / off between the memory string MS and the bit line BL can be controlled.

  An insulating layer 28 is embedded inside the semiconductor layers 21 to 23, and an interlayer insulating layer 27 is also provided on the insulating layer 28 and around the cell source CS. Further, in the shield wiring layer SL1, the electrode layers WL1 to WL5, and the drain side selection gate SGD, the opposite end portion of the memory string MS is formed into a metal silicide to reduce the resistance.

  The stacked body including the shield wiring layer SL1, the insulating layer 24, and the electrode layers WL1 to WL5 described above extends to the peripheral circuit region. These stacked bodies are shown as word lines WL in the plan view of FIG.

  In the peripheral circuit region, transfer transistors that transfer potentials to the electrode layers WL1 to WL5 and the shield wiring layer SL1 are provided. For example, FIG. 1 shows a region where a transfer transistor 20 that transfers a potential to the electrode layer WL2, a transfer transistor 30 that transfers a potential to the electrode layer WL1, and a transfer transistor 40 that transfers a potential to the shield wiring layer SL1 are formed. Is shown.

  FIG. 5 corresponding to the DD cross section in FIG. 1 shows a cross sectional structure of a portion where the transfer transistor 20 is formed.

The transfer transistor 20 includes n ⁻ type diffusion layers 33 a and 33 b selectively formed on the surface of the substrate 11, n ⁺ type diffusion layers 34 a and 34 b, and the substrate 11 between the diffusion layers 33 a and 33 b. A gate insulating film 32 provided on the surface and a gate electrode 31 provided thereon are provided. The region in which they are formed is shown as an active region 60 of the transfer transistor 20 in FIG. The aforementioned diffusion layer formed on the surface of the substrate 11 is separated from the diffusion layers of other transistors and elements by, for example, an insulating layer 35 having an STI (Shallow Trench Isolation) structure.

  A wiring 39 is provided on the stacked body through an insulating layer 29, and the diffusion layer 34 a of the transfer transistor 20 is connected to the wiring 39 through a contact portion 36. The diffusion layer 34b is connected to the electrode layer WL2 via the contact portions 38 and 41.

  As shown in FIG. 4 corresponding to the CC cross section in FIG. 1, each of the electrode layers WL1 to WL5 and the shield wiring layer SL1 is formed in a staircase pattern in the peripheral circuit region. Each of the electrode layers WL1 to WL5 and the shield wiring layer SL1 is a stepped portion and is connected to a corresponding transfer transistor via a contact portion.

  For example, the electrode layer WL2 is connected to the diffusion layer 34b of the transfer transistor 20 via the contact part 41 and the contact part 38 shown in FIG. The electrode layer WL1 is connected to the diffusion layer 34b of the transfer transistor 30 via the contact part 42 and the contact part 38 shown in FIG. The shield wiring layer SL1 is connected to the diffusion layer 34b of the transfer transistor 40 via the contact portion 43 and the contact portion 38 shown in FIG.

  In each of the electrode layers WL1 to WL5 and the shield wiring layer SL1, the stepped portion connected to the transfer transistor is converted into a metal silicide to reduce the resistance.

  In the transfer transistor 20 shown in FIG. 5, when a predetermined gate voltage is applied to the gate electrode 31 through the gate wiring 37, the diffusion layers 34 a and 34 b become conductive, and are given to the diffusion layer 34 a through the wiring 39 and the contact portion 36. The applied potential is transferred to the diffusion layer 34b. Then, the potential of the diffusion layer 34b is transferred to the electrode layer WL2 via the contact portions 38 and 41.

  FIG. 6 corresponding to the section EE in FIG. 1 shows a cross-sectional structure of a portion where the transfer transistor 30 is formed.

Similarly, the transfer transistor 30 includes n ⁻ type diffusion layers 33 a and 33 b selectively formed on the surface of the substrate 11, n ⁺ type diffusion layers 34 a and 34 b, diffusion layers 33 a and 33 b. A gate insulating film 32 provided on the surface of the substrate 11 in between and a gate electrode 31 provided thereon. The region in which they are formed is shown as an active region 60 of the transfer transistor 30 in FIG.

  In this transfer transistor 30, when a predetermined gate voltage is applied to the gate electrode 31 via the gate wiring 37, the diffusion layers 34 a and 34 b become conductive, and the potential applied to the diffusion layer 34 a via the wiring 39 and the contact portion 36. Is transferred to the diffusion layer 34b. Then, the potential of the diffusion layer 34b is transferred to the electrode layer WL1 via the contact portions 38 and 42.

  FIG. 7 corresponding to the FF cross section in FIG. 1 shows a cross sectional structure of a portion where the transfer transistor 40 is formed.

Similarly, the transfer transistor 40 includes n ⁻ -type diffusion layers 33 a and 33 b selectively formed on the surface of the substrate 11, n ⁺ -type diffusion layers 34 a and 34 b, diffusion layers 33 a and 33 b. A gate insulating film 32 provided on the surface of the substrate 11 in between and a gate electrode 31 provided thereon. The region in which they are formed is shown as an active region 60 of the transfer transistor 40 in FIG.

  In this transfer transistor 40, when a predetermined gate voltage is applied to the gate electrode 31 through the gate wiring 37, the diffusion layers 34 a and 34 b become conductive, and the potential applied to the diffusion layer 34 a through the wiring 39 and the contact portion 36. Is transferred to the diffusion layer 34b. The potential of the diffusion layer 34b is transferred to the shield wiring layer SL1 through the contact portions 38 and 43.

  The semiconductor memory device according to this embodiment is a nonvolatile semiconductor memory device that can electrically erase and write data freely and can retain the memory contents even when the power is turned off.

  Here, a memory cell (write target cell) having one of the electrode layers (in this example, the electrode layer WL2) in a block (selected block) surrounded by a dotted line in FIGS. A case where data is written by injecting electrons into the charge storage layer will be described.

  0 V is applied to the selected bit line BL connected to the write target cell (including the memory string), and Vdd (for example, about several volts) is applied to the other non-selected bit lines BL. The drain side select transistor connected to the write target cell is turned on, and the source side select transistor connected to the write target cell is turned off. Vdd is given to the cell source. 0V is applied to the substrate 11 or the p-type well layer. Vpgm (for example, about 20V) is applied to the electrode layer WL2 that is the control gate of the write target cell, and Vpass (for example, about 10V) is applied to the other electrode layers. That is, the write potential Vpgm given to the wiring 39 is transferred and applied to the electrode layer WL2 of the selected block by the transfer transistor 20 shown in FIG.

  As a result, 0 V of the selected bit line BL propagates to the channel (semiconductor layer 21) of the write target cell, and the electric field strength applied to the ONO film between that channel and the electrode layer WL2 of the write target cell increases. Then, electrons are injected into the charge storage layer 17 of the writing target cell, and data writing is performed.

  A desired shield potential corresponding to the potential of the diffusion layers 34a and 34b of the transfer transistor below the shield wiring layer SL1 and the potential of the lowermost electrode layer WL1 is applied to the shield wiring layer SL1. Table 1 shows an example of the potentials of the electrode layers WL1 to WL5 and the potential of the shield wiring layer SL1.

  Vpgm is a voltage sufficient to perform data writing (electron injection) to the cell to be written, and is about 20 V, for example. Vpass is a voltage that prevents writing to a non-write target cell, and the channel region of the cell so that writing is not performed to a memory cell that has an electrode layer to which Vpgm in the unselected bit line is applied as a control gate. The voltage is sufficient to boost the voltage, for example, about 10V.

  In the semiconductor memory device according to the present embodiment, a transfer transistor is provided under a portion extending to the peripheral circuit region in the electrode layers WL1 to WL5 in order to effectively use the substrate area. That is, as shown in FIG. 1, the word line WL including the electrode layers WL1 to WL5 extends so as to cross over the active region 60 of the transfer transistor.

In the case of such a structure, depending on the potential of the electrode layer existing above the active region 60, the n ⁻ type diffusion layers 33a and 33b of the transfer transistor therebelow increase in resistance. It may occur that charge transfer cannot be performed.

In contrast, in the present embodiment, a shield wiring layer SL1 is provided between the lowermost electrode layer WL1 and the transfer transistor, and a desired shield potential is applied to the shield wiring layer SL1. As a result, the influence of the electrode layer potential on the n ⁻ type diffusion layers 33a and 33b of the transfer transistor can be blocked, and an increase in resistance of the n ⁻ type diffusion layers 33a and 33b can be suppressed.

  Table 1 described above shows potential examples of the electrode layers WL1 to WL5 and the shield wiring layer SL1 above the transfer transistor when the transfer transistor transfers, for example, Vpgm to an arbitrary electrode layer.

For example, when Vpgm is transferred to the lowermost electrode layer WL1 by the transfer transistor, the same Vpgm is applied to the shield wiring layer SL1. Thereby, the reduction of the electron density or the formation of the inversion layer, particularly on the surface side, of the n ⁻ type diffusion layers 33a and 33b of the transfer transistor can be suppressed, and the resistance increase of the diffusion layers 33a and 33b can be suppressed.

  For example, when Vpgm is transferred to the electrode layer WL2 by the transfer transistor and the potential applied to the lowermost layer WL1 is Vpass, the shield layer SL1 is applied to the shield wiring layer SL1 in order to suppress the resistance of the diffusion layers 33a and 33b as described above. Gives Vpgm. Alternatively, in order to ensure the withstand voltage of the insulating layer between the lowermost electrode layer WL1 to which Vpass is applied and the shield wiring layer SL1, VpgmL lower than Vpgm is shielded to such an extent that resistance in the diffusion layers 33a and 33b does not become a problem. You may give to wiring layer SL1.

  For example, when Vpgm is transferred to the electrode layer WL3 by the transfer transistor and the potential applied to the lowermost electrode layer WL1 is 0 V, the shield wiring layer is suppressed in order to suppress the high resistance of the diffusion layers 33a and 33b as described above. Vpgm is given to SL1. Also in this case, in order to ensure the withstand voltage of the insulating layer between the lowermost electrode layer WL1 to which 0V is applied and the shield wiring layer SL1, the resistance in the diffusion layers 33a and 33b is less than Vpgm to the extent that the resistance does not become a problem. The lowered VpgmL may be applied to the shield wiring layer SL1.

  Since the shield wiring layer SL1 does not function as a control gate of the memory cell, it can be designed only for the purpose of reducing the resistance without considering transistor characteristics such as a threshold value. From such a viewpoint, the shield wiring layer SL1 is not limited to a semiconductor, and may be composed of a compound of a metal and a semiconductor, or a metal.

Next, another embodiment of the present invention will be described with reference to FIGS.
8 is a cross-sectional view of the memory cell array portion corresponding to FIG. 2 of the above-described embodiment, and FIG. 9 is a cross-sectional view of the row decoder portion corresponding to FIG.

  In the present embodiment, an upper shield wiring layer SL2 (hereinafter also simply referred to as a shield wiring layer) is provided between the uppermost electrode layer WL5 and the drain-side selection gate SGD. A desired shield potential applied to the wiring 39 is transferred to the shield wiring layer SL2 via the contact portions 36, 38, and 44 by the transfer transistor 70 shown in FIG.

  For example, when writing is performed by applying a high voltage Vpgm to the uppermost electrode layer WL5, the selected bit line connected to the memory string including the write target cell is set to 0V, and the 0V is applied to the channel of the write target cell and the write is performed. Is done.

  In a non-selected memory string that does not include a write target cell, the connection with the bit line is cut by turning off the drain side selection gate, the channel potential is raised by the boost ratio, and the electrode layer WL5 to which Vpgm is applied. An electric field that causes electron injection does not act, so that writing into unselected cells is not performed. At this time, a high voltage is applied between the source and drain of the drain-side selection gate in the non-selected memory string, and there is a concern that erroneous writing to the non-selected cell due to the GIDL (Gate Induced Drain Leakage) phenomenon occurs.

  On the other hand, in the present embodiment, a shield wiring layer SL2 is provided between the uppermost electrode layer WL5 and the drain-side selection gate SGD, and the shield wiring layer SL2 corresponds to the potential of the uppermost electrode layer WL5. By applying a desired potential, the potential difference between the source and drain of the drain side select gate SGD can be relaxed, and erroneous writing due to GIDL can be suppressed.

  Table 2 shows potential examples of the electrode layers WL1 to WL5 and the upper shield wiring layer SL2 in the non-selected memory string.

  When the potential of the uppermost electrode layer WL5 is 0V, no high voltage is applied between the source and drain of the drain-side selection gate SGD. Therefore, GIDL does not occur, and the potential applied to the shield wiring layer SL2 is sufficient. .

  When Vpass (for example, about 10 V) is applied to the electrode layer WL5, several V to VpassL lower than Vpass are shielded to reduce the electric field between the source and drain of the drain side selection gate SGD and suppress the generation of GIDL. Give to SL2. At this time, the potential applied to the shield wiring layer SL2 can be lowered to such an extent that the electrode layer WL5 is not deteriorated by GIDL.

  When Vpgm (for example, about 20 V) is applied to the electrode layer WL5, in the same manner as described above, in order to reduce the electric field between the source and the drain of the drain side selection gate SGD and suppress the generation of GIDL, a number V˜ VpgmL is applied to the shield wiring layer SL2. In this case, since GIDL is more likely to occur than when the electrode layer WL5 is Vpass, it is desirable to apply a higher potential to the shield wiring layer SL2 than when the electrode layer WL5 is Vpass. However, if the potential of the shield wiring layer SL2 is too high, GIDL is generated in the vicinity of the shield wiring layer SL2, and the resulting characteristic deterioration cannot be ignored. Therefore, the upper limit of the shield potential must be set appropriately.

  Since the shield wiring layer SL2 does not function as a control gate of the memory cell, it can be designed only for resistance reduction without taking into consideration transistor characteristics such as a threshold value. From such a viewpoint, the shield wiring layer SL2 is not limited to a semiconductor, and may be composed of a compound of a metal and a semiconductor, or a metal.

  Further, as shown in FIG. 10 which is a cross-sectional view of the row decoder portion similar to FIG. 7, both the shield wiring layer SL1 and the shield wiring layer SL2 described above may be provided.

  That is, by providing the lower shield wiring layer SL1 between the lowermost electrode layer WL1 and the transfer transistor and applying the desired first shield potential, the resistance of the diffusion layer of the transfer transistor can be prevented from increasing, and the uppermost layer By providing the upper shield wiring layer SL2 between the electrode layer (electrode layer WL4 in the case of FIG. 10) and the drain-side selection gate SGD and applying a desired second shield potential, erroneous writing to unselected cells can be suppressed. .

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to them, and various modifications can be made based on the technical idea of the present invention.

  In the above-described embodiment, an example in which the write potential Vpgm is transferred by the transfer transistor has been described. However, the transfer transistor also transfers the potential, for example, Vpass or 0 V in accordance with the potential applied to the corresponding electrode layer. For example, when the transfer transistor is transferring Vpass, Vpass may be applied to the shield wiring layer SL1 thereon. However, even in such a case, as described above, it is possible to provide the shield wiring layer SL1 with a potential as high as possible to ensure a breakdown voltage between the shield wiring layer SL1 and the lowermost electrode layer WL1. It is advantageous for restraining the rise.

  In the above-described embodiment, silicon is exemplified as the semiconductor, but a semiconductor other than silicon may be used. Further, the film structure including the charge storage layer 17 between each of the electrode layers WL1 to WL5 and the semiconductor layer 21 is not limited to the ONO (Oxide-Nitride-Oxide) structure, and for example, 2 of the charge storage layer and the gate insulating film. It may be a layered structure.

  DESCRIPTION OF SYMBOLS 10 ... Memory cell array, 17 ... Charge storage layer, 20, 30, 40 ... Transfer transistor, 21 ... Semiconductor layer, 50 ... Peripheral circuit, CS ... Cell source, SGS ... Source side selection transistor, SGD ... Drain side selection transistor, MC ... Memory cell, MS ... Memory string, WL1 to WL5 ... Electrode layer, SL1 ... Lower shield wiring layer, SL2 ... Upper shield wiring layer

Claims (5)

A semiconductor substrate having a memory cell region and a peripheral circuit region;
A stacked body provided over the memory cell region and the peripheral circuit region on the semiconductor substrate, wherein a plurality of electrode layers and a plurality of insulating layers are alternately stacked;
A semiconductor layer provided in a hole formed through the stacked body in the memory cell region and extending in a stacking direction of the electrode layer and the insulating layer;
A charge storage layer provided between the semiconductor layer and the electrode layer;
A transfer transistor provided under the stacked body in the peripheral circuit region and transferring a potential to the electrode layer;
A lower shield wiring layer provided between the transfer transistor and the lowermost electrode layer, to which a shield potential according to the potential of the diffusion layer of the transfer transistor is applied;
A semiconductor memory device comprising: A semiconductor substrate having a memory cell region and a peripheral circuit region;
A stacked body provided over the memory cell region and the peripheral circuit region on the semiconductor substrate, wherein a plurality of electrode layers and a plurality of insulating layers are alternately stacked;
A semiconductor layer provided in a hole formed through the stacked body in the memory cell region and extending in a stacking direction of the electrode layer and the insulating layer;
A charge storage layer provided between the semiconductor layer and the electrode layer;
A transfer transistor provided under the stacked body in the peripheral circuit region and transferring a potential to the electrode layer;
A lower shield wiring layer provided between the transfer transistor and the lowermost electrode layer, to which a first shield potential according to the potential of the diffusion layer of the transfer transistor is applied;
An upper shield wiring layer provided on the uppermost electrode layer and provided with a second shield potential according to the potential of the electrode layer;
A semiconductor memory device comprising:   3. The semiconductor memory device according to claim 1, wherein the lower shield wiring layer is supplied with the same potential as the potential of the diffusion layer of the transfer transistor located under the lower shield wiring layer.   The lower shield wiring layer is provided with an intermediate potential between the potential of the diffusion layer of the transfer transistor located below the lower shield wiring layer and the potential of the lowermost electrode layer. The semiconductor memory device according to claim 1. A semiconductor substrate having a memory cell region and a peripheral circuit region;
A stacked body provided over the memory cell region and the peripheral circuit region on the semiconductor substrate, wherein a plurality of electrode layers and a plurality of insulating layers are alternately stacked;
A semiconductor layer provided in a hole formed through the stacked body in the memory cell region and extending in a stacking direction of the electrode layer and the insulating layer;
A charge storage layer provided between the semiconductor layer and the electrode layer;
An upper shield wiring layer provided on the uppermost electrode layer and provided with a shield potential according to the potential of the electrode layer;
A semiconductor memory device comprising:

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