JP2010161438A - Piezoelectric oscillator - Google Patents

Abstract

A piezoelectric oscillator is provided with a sleep mode.
An oscillation circuit 110 that outputs an oscillation signal Vp that oscillates a piezoelectric vibrator 100, a current source circuit 120 that supplies a current Id to the oscillation circuit 110, and an oscillation signal Vp output from the oscillation circuit 110 are shaped. A buffer circuit 130 for outputting the output signal OUT, and a control terminal 140 for receiving a control signal SL for switching between the sleep mode and the normal mode. The current source circuit 120 is normal when the control signal SL is in the sleep mode. The first switching unit 124 that switches the current Id supplied to the oscillation circuit 110 to be smaller than that in the mode is included, and the buffer circuit 130 is an element constituting the buffer circuit 130 when the control signal SL is in the sleep mode. The second switching unit 132 for stopping the supply of the current of the oscillation signal Vp when the control signal SL is in the sleep mode. The piezoelectric oscillator 1 includes a third switching unit 133 for switching so as not to be outputted, the.
[Selection] Figure 1

Description

  The present invention relates to a piezoelectric oscillator having a sleep mode for reducing power consumption.

  Piezoelectric oscillators mounted on many electronic devices have a problem that current consumption cannot be suppressed because it is necessary to constantly drive the piezoelectric vibrator in order to obtain a stable oscillation frequency.

  In order to solve this problem, for example, Patent Document 1 describes a method of a piezoelectric oscillator having a sleep mode in order to reduce power consumption during standby. FIG. 4 is a circuit diagram showing a configuration of the piezoelectric oscillator 4 described in Patent Document 1. As shown in FIG. The piezoelectric oscillator 4 enters the sleep mode when the sleep signal SL applied from the external terminal 440 is at the H level, and enters the normal mode when the sleep signal SL is at the L level. In the normal mode, the normal mode current source 424 is connected to the current source 402, and a large current flows through the current sources 401 and 420 connected by the current mirror, so that a large current is supplied to the amplifiers 421 and 422. On the other hand, in the sleep mode, the resistor 426 is connected to the current source 402, and the current flowing through the current sources 401 and 420 connected by the current mirror is reduced from the current of the normal mode current source 424 and supplied to the amplifier 421. The amount of current to be reached is the minimum level necessary to keep the piezoelectric vibrator oscillating. Further, the output terminal of the amplifier 422 is connected to the ground potential line because the transistor 427 is turned on.

JP-A-6-125222 (FIG. 1)

  However, in the conventional method, since the transistor 427 is turned on in the sleep mode, a current flows from the current source 420 via the transistor 427, and thus there is a problem that wasteful current is consumed.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

[Application Example 1]
A piezoelectric vibrator; an oscillation circuit that excites the piezoelectric vibrator to output an oscillation signal; a current source circuit that supplies current to the oscillation circuit; and an output obtained by shaping the oscillation signal output from the oscillation circuit A buffer circuit for outputting a signal, and a control terminal for inputting a control signal for switching between a sleep mode and a normal mode, and the current source circuit is compared with the normal mode when the control signal is in the sleep mode. A first switching unit that switches so as to reduce a current supplied to the oscillation circuit, and the buffer circuit supplies a current to an element constituting the buffer circuit when the control signal is in the sleep mode. A second switching unit that stops, and a third switching unit that switches the output of the oscillation signal to the outside when the control signal is in the sleep mode. The includes a piezoelectric oscillator, characterized in that.

  According to this configuration, during the sleep mode, the amount of current supplied to the oscillation circuit can be set to the minimum level necessary for the piezoelectric vibrator to continue to oscillate, and the buffer circuit can be stopped without wasting current. A stable frequency can be output even when the mode is changed from the sleep mode to the normal mode.

  Hereinafter, embodiments of a piezoelectric oscillator will be described with reference to the drawings.

(First embodiment)
<Configuration of piezoelectric oscillator>
First, the configuration of the piezoelectric oscillator according to the first embodiment will be described with reference to FIG. FIG. 1 is a circuit diagram showing the configuration of the piezoelectric oscillator according to the first embodiment.

  As shown in FIG. 1, the piezoelectric oscillator 1 includes a piezoelectric vibrator 100, an oscillation circuit 110, a current source circuit 120, and a buffer circuit 130.

  The oscillation circuit 110 includes an inverter 111 and a resistor 112 connected in parallel between both terminals of the piezoelectric vibrator 100, and capacitors 113 and 114 respectively connected to both terminals of the piezoelectric vibrator 100. . An oscillation signal Vp is output from the output terminal of the inverter 111.

  The current source circuit 120 is connected between the Pch transistor 121 and the current source 125 connected in series between the power supply potential line VDD and the ground potential line, and between the power supply potential line VDD and the current supply terminal 115 of the inverter 111. Pch transistor 122, Pch transistor 123 connected in series between power supply potential line VDD and current supply terminal 115 of inverter 111, and Pch transistor 124 serving as a first switching unit.

  In the Pch transistor 121, the gate terminal and the drain terminal are connected, and the current I0 flows from the current source 125. The Pch transistor 122 is current mirror connected to the Pch transistor 121, and a current I0 flows. The Pch transistor 123 is connected to the Pch transistor 121 as a current mirror. The Pch transistor 124 is connected to the gate terminal and the external terminal 140, and is switched on or off by the control signal SL.

  Control signal SL is set to H level in the sleep mode and set to L level in the normal mode. Therefore, in the sleep mode, since the H level is applied to the gate terminal of the Pch transistor 124, the Pch transistor 124 becomes non-conductive and the current I0 does not flow through the Pch transistor 123. On the other hand, since the L level is applied to the gate terminal of the Pch transistor 124 in the normal mode, the Pch transistor 124 becomes conductive, and the current I1 (> I0) flows through the Pch transistor 123. That is, in the current source circuit 120, the current Id supplied to the current supply terminal 115 of the inverter 111 is I0 in the sleep mode, and the current Id supplied to the current supply terminal 115 of the inverter 111 is in the normal mode. I0 + I1. If the current I0 is set to a minimum amount of current that allows the oscillation circuit 110 to excite the piezoelectric vibrator 100 and maintain the oscillation state, the oscillation circuit 110 is set to a current amount less than half that in the normal mode in the sleep mode. It can be operated.

  The buffer circuit 130 includes a buffer 131, a Pch transistor 132 that is a second switching unit, and an Nch transistor 133 that is a third switching unit.

  The Pch transistor 132 is connected between the power supply potential line VDD and the current supply terminal 135 of the buffer 131, and the gate terminal is connected to the external terminal 140. The buffer 131 shapes the oscillation signal Vp output from the oscillation circuit 110 into a rectangular wave, for example, and outputs the output signal OUT from the external terminal 141. The Nch transistor 133 is connected between the output terminal of the buffer 131 and the ground potential line, and the gate terminal is connected to the external terminal 140.

  The Pch transistor 132 is in a non-conductive state in the sleep mode (the control signal SL is at the H level), and interrupts the current supply to the buffer 131. On the other hand, Pch transistor 132 is conductive when in normal mode (control signal SL is at L level), and supplies current to buffer 131. The Nch transistor 133 becomes conductive when in the sleep mode (the control signal SL is at the H level), and fixes the output signal OUT at the L level. On the other hand, Nch transistor 133 is non-conductive in normal mode (control signal SL is at L level) and does not fix output signal OUT at L level.

  According to the present embodiment described above, the following effects can be obtained.

  In the present embodiment, in the sleep mode, the amount of current supplied to the oscillation circuit 110 is set to the minimum level necessary for the piezoelectric vibrator 100 to continue to oscillate, and the current supply to the buffer circuit 130 is interrupted to be useless. A stable frequency can be output even when the power consumption is stopped and the system is stopped and the sleep mode is changed to the normal mode.

  While the embodiments of the piezoelectric oscillator have been described above, the present invention is not limited to these embodiments, and can be implemented in various forms without departing from the scope of the invention. Hereinafter, a modification will be described.

  (Modification 1) Modification 1 of the piezoelectric oscillator will be described. FIG. 2 is a circuit diagram illustrating a configuration of the piezoelectric oscillator according to the first modification. As shown in FIG. 2, the piezoelectric oscillator 2 includes a buffer circuit 230 and an inverter 235 instead of the buffer circuit 130 of the first embodiment. Buffer circuit 230 includes Pch transistors 231 and 232 and Nch transistors 233 and 234 connected in series between power supply potential line VDD and ground potential line. The gate terminal of the Pch transistor 231 and the gate terminal of the Nch transistor 234 are each connected to the output of the inverter 111, and the gate terminal of the Pch transistor 232 and the gate terminal of the Nch transistor 233 are respectively connected via the external terminal 140 and the inverter 235. Connected. The Pch transistor 232 is a second switching unit, and the Nch transistor 233 is a third switching unit.

  In the sleep mode (the control signal SL is at the H level), the Pch transistor 232 and the Nch transistor 233 are in a non-conductive state, so that the external terminal 141 is in a high impedance state. On the other hand, in the normal mode (the control signal SL is at L level), the Pch transistor 232 and the Nch transistor 233 are in a conductive state, and the buffer circuit 230 functions as an inverting amplifier circuit.

  (Modification 2) Modification 2 of the piezoelectric oscillator will be described. FIG. 3 is a circuit diagram showing a configuration of the piezoelectric oscillator according to the second modification. As shown in FIG. 3, the piezoelectric oscillator 3 includes a NOR circuit 330 instead of the buffer circuit 130 of the first embodiment. In the NOR circuit 330, one input terminal is connected to the external terminal 140, and the oscillation signal Vp is input to the other input terminal. When the NOR circuit 330 is composed of CMOS, a Pch transistor (not shown) connected to the external terminal 140 is a second switching unit, and an Nch transistor (not shown) connected to the external terminal 140 is a third. Switching unit.

  In the sleep mode (the control signal SL is at the H level), the output of the NOR circuit 330 is fixed at the L level, so that the output signal OUT is fixed at the L level. On the other hand, in the normal mode (the control signal SL is at L level), the NOR circuit 330 functions as an inverting amplifier circuit.

1 is a circuit diagram showing a configuration of a piezoelectric oscillator according to a first embodiment. The circuit diagram which shows the structure of the piezoelectric oscillator which concerns on the modification 1. FIG. FIG. 6 is a circuit diagram showing a configuration of a piezoelectric oscillator according to Modification 2. The circuit diagram which shows the structure of the conventional piezoelectric oscillator.

  DESCRIPTION OF SYMBOLS 1-3 ... Piezoelectric oscillator, 100 ... Piezoelectric vibrator, 110 ... Oscillator circuit, 111 ... Inverter, 112 ... Resistor, 113, 114 ... Capacitor, 115 ... Current supply terminal, 120 ... Current source circuit, 121-124 ... Pch transistor , 125 ... current source, 130 ... buffer circuit, 131 ... buffer, 132 ... Pch transistor, 133 ... Nch transistor, 135 ... current supply terminal, 140 ... external terminal, 141 ... external terminal, 230 ... buffer circuit, 231, 232 ... Pch transistor, 233, 234... Nch transistor, 235... Inverter, 330.

Claims (1)

A piezoelectric vibrator;
An oscillation circuit for exciting the piezoelectric vibrator and outputting an oscillation signal;
A current source circuit for supplying current to the oscillation circuit;
A buffer circuit for outputting an output signal obtained by shaping the oscillation signal output from the oscillation circuit;
A control terminal for inputting a control signal for switching between the sleep mode and the normal mode;
Including
The current source circuit includes a first switching unit that switches so that the current supplied to the oscillation circuit is reduced when the control signal is in the sleep mode compared to when in the normal mode;
The buffer circuit includes a second switching unit that stops supply of current to elements constituting the buffer circuit when the control signal is in the sleep mode, and the oscillation signal when the control signal is in the sleep mode. A third switching unit that switches to shut off the output to the outside,
A piezoelectric oscillator characterized by that.

Images