JP2010152960A - Error correction circuit and storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve error correction capability in error correction technology of a storage device. <P>SOLUTION: The storage device is provided with error correction circuits (30, 34, 36, 38) for calculating a syndrome value of data and correcting errors from the syndrome value; a circuit (46) in which real data is read out, when error correction cannot be performed, mirror data is read out, while when correction is failed, read out data of real data and mirror data are compared, and an error place is specified; compensating circuits (48, 50) compensating the syndrome value by taking out successively error positions and information of magnitude from the specified one; and a compensating circuit (40) compensating data further with specified error position and magnitude. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an error correction circuit for data including an error correction code used in a storage device or a communication device, and to a storage device, and more particularly to an error correction circuit for error correction of a data block provided with ECC (Error Correction Code). And a storage device.

  In the field of storage devices such as magnetic disk devices and communication systems, error correction techniques using error correction codes (ECC) are used to correct data errors that occur in the recording / reproduction process and transmission path. Widely popular.

  As this ECC code, a Reed Solomon (RS) code is used. The RS code performs RS encoding on recorded data in advance, performs RS decoding on a bit string reproduced through a recording / reproducing process, and detects and corrects an error included in the bit string. That is, the RS code is excellent in symbol unit correction capability, and in particular, is excellent in burst error detection and correction capability.

  As an error correction code technique, an iterative decoding format is used. Error detection / correction capability can be improved by combining iterative decoding and ECC (see, for example, Patent Document 1).

  FIG. 16 is an explanatory diagram of an error correction circuit using a conventional RS code. Data (read signal) read from a storage disk 100 such as a magnetic disk by a read element 102 such as a magnetic head is demodulated by a data demodulation circuit 110. The data demodulating circuit 110 includes, for example, a PR channel circuit and an iterative decoder.

  The error correction circuit 130 is composed of an ECC decoder. An error correction circuit (hereinafter referred to as an ECC decoder) 130 includes a syndrome calculation circuit 120, an error position decoding circuit 122, an error magnitude decoding circuit 124, a data correction circuit 128, and a decoding error determination circuit 126. .

  The syndrome calculation circuit 120 receives the decoded sequence from the decoder of the data demodulation circuit 110 and calculates a syndrome value of the decoded sequence. The error position decoding circuit 122 calculates simultaneous equations of error positions from the calculated syndrome values and identifies the error positions. The error magnitude decoding circuit 124 calculates an error magnitude simultaneous equation from the calculated syndrome, and decodes the error magnitude.

  The decoding error determination circuit 126 determines whether the correction capability is exceeded from the error position of the error position decoding circuit 122 and the error size of the error size decoding circuit 124, and outputs a determination result. If the correction capability is not exceeded, the data correction circuit 128 corrects the data according to the specified error position and error magnitude, and outputs error correction data.

In such error correction, for example, in the Reed-Solomon (15, 11) code, the number of code blocks n is “15”, the number of information blocks k is “11”, and the number of check blocks (n−k) is “4”. The maximum number of correctable symbols is (n−k) / 2 = 2.
JP-A-11-330985

  In the prior art, if the error cannot be corrected by reading, the data is read again to correct the error. Further, when correction fails, these are read again and error correction is repeated.

  If the data error is a random error, the position and the number are changed by reading again, and therefore the data can be reproduced when the number of errors is equal to or less than the ECC correction number.

  However, if the recording density rises and the medium defect cannot be ignored, the data will be erroneous at the medium defect portion every time even if it is read again. When an error due to a medium defect exceeds the ECC correction capability, an abnormal situation occurs in which data disappears. The same applies when the communication speed increases.

  Therefore, an object of the present invention is to provide an error correction circuit and a storage device for improving error correction performance.

  Another object of the present invention is to provide an error correction circuit and a storage device for improving error correction capability for a medium defect.

  To achieve this object, the storage device includes a storage medium in which the same data is recorded at a plurality of locations, a head for reading the data of the storage medium, a demodulation circuit for demodulating a read signal of the head, and the demodulation An error correction circuit that calculates a syndrome value of read data from the circuit, specifies an error position from the syndrome value, corrects read data at the specified error position, and outputs error correction data; and read operation of the head And a control circuit for controlling.

  The error correction circuit includes a circuit that corrects the syndrome value and a circuit that corrects the corrected data, and the control circuit reads data at a first location, and reads the data at the first location. In response to the error correction failure of the read data from the error correction circuit, the same data at the second location is read, and the error correction circuit performs error correction on the read data at the second location, and the second In response to failure in error correction from the error correction circuit of the read data at the location, the error correction circuit is instructed to correct the error, and the error correction circuit responds to the correction instruction and the first location and the second location. The error location is identified by comparing the read data at the location, the syndrome value is corrected based on the identified error position and size information, error correction is performed, and the error location and size are corrected. , To correct the error-corrected data.

  The error correction circuit also includes a syndrome calculation unit that calculates a syndrome value of the input data, specifies an error position from the syndrome value, corrects read data at the specified error position, and outputs error correction data. An error correction unit, a circuit that receives the same mirror data as the data, and compares the data to identify an error location; a circuit that corrects the syndrome value of the identified error location; and the corrected data And a circuit for correcting.

  If this data is read and error correction is impossible, the mirror data is read. When both corrections fail, the read data of this data and the mirror data are compared to identify the error location. From the specified information, error position and size information is sequentially taken out, the syndrome value is corrected, and error correction is performed. Further, when data can be corrected normally by ECC, the data is further corrected at a specific error position and size, so that the error correction capability is apparently improved.

  Hereinafter, embodiments of the present invention will be described in the order of a storage device, data read / correction, data read / correction processing, and other embodiments. However, the present invention is not limited to this embodiment.

(Storage device)
1 is a block diagram of a storage device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a Galois field as the data format of FIG. 1, and FIG. 3 is an explanatory diagram of addition in the Galois field of FIG. 4 is an explanatory diagram of multiplication in the Galois field of FIG. 2, FIG. 5 is an explanatory diagram of the error position decoding circuit of FIG. 1, and FIG. 6 is an explanatory diagram of the error magnitude decoding circuit of FIG. . In FIG. 1, a magnetic disk device is shown as a storage device.

  In the magnetic disk 10, data is recorded on each track in units of sectors. In this embodiment, the same data is recorded at a plurality of locations on the magnetic disk 10. For example, data 11A is recorded, and mirror data 11B of data 11A is written at a position rotated 180 degrees on the magnetic disk. The mirror data 11B is the same data as the data 11A.

  This data is recorded as follows. The recording data is added with a CRC code (Cyclic Redundancy Code) and then converted into a data string that satisfies a constraint condition such as an MTR code (Maximum Transition Run Code) or an RLL (Run Length Limited) code. Then, an RS (Reed Solomon) parity string is added to the data string as an ECC code.

  The ECC-encoded data string is subjected to a compensation process that slightly widens the inversion interval at a position where the magnetization inversion is adjacent. A write current of a recording head (write head) (not shown) is generated according to the recording-compensated data string, and the recording head is driven to perform recording on the magnetic disk 10.

  Next, playback will be described. At the time of reproduction, the reproduction head (read head) 12 reads the data 11 A and 11 B of the magnetic disk 10 and outputs an analog voltage (read signal) to the demodulation circuit 20. The demodulation circuit 20 demodulates the read signal into read data. The demodulating circuit 20 includes, for example, a variable gain amplifier (VGA), a low-pass filter, an A / D converter, an FIR filter, and an iterative decoder.

  The variable gain amplifier adjusts the amplitude of the read signal, and the low-pass filter (LPF) cuts the high frequency range of the read signal whose amplitude has been adjusted, and converts the analog output of the A / D converter (ADC) into a digital signal. Thereafter, a FIR (Finite Impulse Response) filter performs PR (Partial Response) waveform equalization, and then outputs the result to the iterative decoder.

  The iterative decoder performs iterative decoding using likelihood. For example, Max-log-MAP (Maximum A Posteriori) algorithm, SOVA (Soft-Output Viterbi Algorithm), SOVA with noise prediction function (NPSOVA: Noise Predictive SOVA), and the like are used.

  The iteratively decoded determination output is input to the ECC decoder 70, and the ECC decoder 70 performs error correction using the ECC. The ECC decoder 70 includes a syndrome calculation unit 30, an error position polynomial decoding unit 34, an error magnitude decoding unit 36, a data correction unit 38, and a decoding error determination circuit 42.

The ECC decoder 70 performs a Galois field operation known as a cyclic code. The Galois field will be described with reference to FIG. FIG. 2 shows the relationship between a power representation of a Galois field GF (2 ⁴ ) with primitive polynomial F (x) = x ⁴ + x + 1, a corresponding vector representation, and a corresponding decimal representation. In other words, the decimal representation corresponds to the value of “0” to “15” with respect to the 4-bit vector representation (binary representation). On the other hand, the power expression (Galois field expression) is “0” to “α ¹⁴ ” and corresponds to each vector expression.

Next, addition in a Galois field will be described. FIG. 3 shows an example of Galois field addition in decimal display. For example, “3” (= α ⁴ ) + “3” (= α ⁴ ) in decimal display is “0” (= 0) in decimal display, and “3” (= α ^{4 in} decimal display). ) + “4” (= α ² ) is “7” (= α ¹⁰ ) in decimal notation.

In addition, multiplication in a Galois field will be described. FIG. 4 shows an example of multiplication of a Galois field in decimal display. For example, “3” (= α ⁴ ) × “3” (= α ⁴ ) in decimal display is “5” (= α ⁸ ) in decimal display, and “3” (= α in decimal display) ⁴ ) + “4” (= α ² ) is “12” (= α ⁶ ) in decimal notation.

Returning to FIG. 1, the syndrome value calculation unit 30 calculates the syndromes S _{0 to} Sn _k−1 of the decoded sequence from the demodulation circuit 20 and stores the calculated syndrome values (coefficients). For example, in the Reed-Solomon (15, 11) code, the number n of code blocks is “15”, the number of information blocks k is “11”, the number of check blocks (n−k) is “4”, and the maximum correctable symbol Since the number is (n−k) / 2 = 2, syndromes So to S3 are calculated.

The error position decoding unit 34 calculates an error position polynomial of simultaneous equations related to the error position shown in FIG. 5 from the generated syndrome polynomials S _{0 to} S _n−k−1 . Simultaneous legal expression for the error position in Figure 5, has indicated in the general formula, the left side of the syndrome _{S (n-k) / 2-1} ~S n-k-1, the syndromes _S 0 _{~S n-k- 2} and simultaneous equations represented by the product of the coefficients σ1 to σ _{(n−k) / 2} with respect to the position X.

The simultaneous equations are solved, the error polynomial is factored, the coefficients σ1 to σ _{(n−k) / 2} are calculated, the position X is sequentially substituted into the following equation (1), and σe (X) = The position X that becomes 0 is decoded as an error position. This position X corresponds to, for example, a block number.

Next, the error magnitude decoding unit 36 decodes the error magnitude (numerical value) in the block. The error magnitude decoding unit 36 is a relational expression between the created syndrome polynomials S _{0 to} S _n−k−1 , the position X, and the error magnitude value e, as shown in FIG. The simultaneous equations are solved, and the error magnitudes (values in the block) e _{1 to} e _{(n−k) / 2} are calculated by the following equation (2). For example, if the error magnitude e corresponds to the data value in the block and one block is “0” to “255” (8 bits), the error magnitude is “1” to “255”. ”.

  The decoding error determination circuit 42 receives the error position and the error size from the error position decoding unit 34 and the error size decoding unit 36, and determines whether the correction capability is exceeded. Then, the control circuit 60 is notified that correction is possible or impossible.

  If correction is possible, the data correction circuit 38 corrects the magnitude (value) of the error at the specified error position, and outputs error correction data.

  In the present embodiment, the read buffer 22 that holds data from the demodulation circuit 20, the difference calculator 46 that calculates the difference between the mirror data 11B from the demodulation circuit 20 and the data 11A of the read buffer 22, An error specifying unit 48 for specifying the error position / size from the difference calculation result of the difference calculator 46 is provided.

Furthermore, a syndrome correction unit 50 that corrects the syndrome values S _{0 to} S _n−k−1 from the syndrome calculation unit 30 according to the error position / size of the error specifying unit 48, the syndrome calculation unit 30, and the syndrome correction unit 50. The first switch 32 for switching the output of the data, the data correction unit 40 for correcting the correction data from the data correction unit 40 according to the error position / size of the error specifying unit 48, the data correction unit 38, and the data correction unit And a second switch 44 for switching the output to the output 40.

  The control circuit 60 controls the reading operation and the ECC decoding operation, as will be described with reference to FIG.

(Data reading / correction)
FIG. 7 is a relationship diagram of the main data 11A, the mirror data 11B, the difference, and the syndrome correction value. FIG. 8 is a relationship diagram of the syndrome of the mirror data 11B and the corrected syndrome. The error correction operation according to FIG. 1 will be described with reference to FIGS.

  FIG. 7 shows an example of the Reed-Solomon (15, 11) code. The number of code blocks n is “15”, the number of information blocks k is “11”, and the number of check blocks (n−k) is “4”. That is, four blocks with block numbers “0” to “3” are inspection blocks, and 11 blocks with block numbers “4” to “14” are information blocks.

Assume that the main data constituting each block has a Galois field notation as shown in FIG. 7 and the mirror data has a Galois field notation as shown in FIG. In the example of FIG. 7, it is assumed that an error is detected in the seventh, tenth, and thirteenth blocks of this data, and the data values are α ⁷ , α ⁴ , and α ² , respectively. That is, the maximum number of correctable symbols exceeds (n−k) / 2 = 2.

Next, since the correctable range of this data is exceeded, the mirror data 11B is read out. In the example of FIG. 7, it is assumed that an error is detected in the fourth, seventh, and tenth blocks of the mirror data and the data values are α ¹⁰ , α ⁷ , and α ² , respectively. That is, the maximum number of correctable symbols exceeds (n−k) / 2 = 2.

  In the present embodiment, when this data is compared with mirror data, there are the following three cases except when errors of the same position and the same size occur.

  (1) Only this data has an error. FIG. 7 shows an example of information block number 13.

  (2) The mirror data and the main data have errors of different sizes at the same position. FIG. 7 shows an example of information block number 10.

  (3) An error occurred only in the mirror data. FIG. 7 shows an example of information block number 4.

  In the case of (1), the detected error position and size are irrelevant to error correction of the mirror data. In the case of (2), the magnitude of the detected error is the difference between the two. In the case of (3), the detected error position and size are errors themselves in the mirror data.

  Therefore, when error correction is not possible for both this data and mirror data, the case of (3) is detected, the error syndrome of (3) is removed from the syndrome of the mirror data, and correction is performed. Reduce errors in mirror data. This improves the ECC error correction capability.

  Further, since the error position and size of only the mirror data are specified, the data at that position is corrected separately after the ECC correction.

Referring to the configuration of FIG. 1, the difference calculator 46 calculates a difference (see also FIG. 7) between the mirror data 11B and the data 11A of the read buffer 22. Then, the error specifying unit 48 detects the case where there is a difference and the case (3), and the error position (block number 4 in FIG. 7) and size (in FIG. 7, Galois field notation α ¹⁰ ). Are output to the syndrome correction circuit 50 and the data correction circuit 40.

FIG. 7 shows a syndrome value corresponding to the error position and size, and is composed of four terms. Here, there are four syndrome values of α ¹⁰ , α ¹⁰ α ⁴ , α ¹⁰ α ^{2 * 4} , and α ¹⁰ α ^{3 * 4} for block number 4 and size α ¹⁰ . At this time, under the control of the control circuit 60, the first switch 32 selects the syndrome correction circuit 50, and the second switch 44 selects the data correction circuit 40.

  The syndrome correction circuit 50 corrects the syndrome of the mirror data from the received error position and size. As shown in FIG. 8, when the syndrome of the mirror data is S0 to S3, the syndrome correction circuit 50 adds the four syndrome values of FIG. 7 to the syndromes S0 to S3 to correct the corrected syndrome S. Create '0-S'3.

  By this Galois field addition, as shown in FIG. 8, the syndrome values corresponding to the fourth block are added to the syndromes S0 to S3 of the mirror data, so that the corrected syndromes S′0 to S′3 are 4 blocks. The syndrome value corresponding to the eye is canceled and only the seventh and tenth blocks in FIG. For this reason, since the ECC error correction range is not exceeded, ECC correction can be performed from the syndrome in which the mirror data is corrected.

  Since the error of the fourth block is not ECC corrected, the correction circuit 40 corrects the error of the fourth block with the notified position and size.

  In this way, the same data is written on the storage medium at a plurality of equal division angles at a plurality of positions, the main data is read, and if error correction is impossible, the mirror data is read, and when both corrections fail. The error data is identified by comparing the read data of this data with the mirror data. From the specified information, error position and size information is sequentially taken out, the syndrome value is corrected, and error correction is performed.

  Further, when data can be corrected normally by ECC, the data is further corrected at a specific error position and size, so that the error correction capability is apparently improved.

(Data read / correction processing)
Next, read / correction processing executed by the control circuit 60 will be described. 9 and 10 are read / correction processing flowcharts according to the embodiment of the present invention, and FIGS. 11 to 15 are explanatory diagrams of error correction operation examples.

  The processing of FIGS. 9 and 10 will be described with reference to FIGS.

  (S10) First, in the reading process, the first switch 32 selects “a” on the syndrome calculation unit 30 side, and the second switch 44 selects “a” on the data correction unit 38 side. . The control circuit 60 reads the current sector position and cylinder position of the active head 12. As is well known, servo information of the magnetic disk 10 (not shown) is read by the head 12, and a read signal is demodulated by a servo demodulation circuit (not shown) to obtain a sector position and a cylinder position. The control circuit 60 calculates the sector to be read and the cylinder position, the sector position of this data, the distance to the cylinder position, and the sector to be read and the cylinder position and the distance to the sector position of the mirror data and the cylinder position. To do.

  (S12) The control circuit 60 seeks to the data position closest to the current position of the head 12 by comparing the distances. Therefore, the data at the first seek position is regarded as the main data. As described above, since the data close to the current position of the head is accessed from the two data 11A and 11B in FIG. 1, the access time can be shortened as an effect of providing the mirror data.

  (S14) The control circuit 60 instructs the head 12 to read data. The read signal of the main data 11 </ b> A read by the head 12 is demodulated by the demodulation circuit 20 and stored in the read buffer 22. At the same time, the syndrome calculation unit 30 calculates the syndrome from the demodulated read data and outputs it to the error position decoding unit 34. As described with reference to FIG. 5, the error position decoding unit 34 solves simultaneous equations relating to the error position and decodes the error position. Further, the error size decoding unit 36 decodes the error size as described with reference to FIG. The decoding error determination circuit 42 receives the error position and the error size from the error position decoding unit 34 and the error size decoding unit 36, and determines whether the correction capability is exceeded. Then, the control circuit 60 is notified that correction is possible or impossible.

  (S16) When correction is possible, the data correction circuit 38 performs error correction from the decoded error position and size, and outputs the result to the control circuit 60 via the switch 44. When the control circuit 60 receives a notification that correction is possible, the control circuit 60 takes in the error correction data of the data correction circuit 38 and ends normally.

  (S18) On the other hand, when a correction impossible notification is received in step S14, the control circuit 60 seeks the position of the head 12 to the position of the mirror data 11B. Therefore, the data at the second seek position is regarded as mirror data.

  (S20) The control circuit 60 instructs the head 12 to read data. The read signal of the mirror data 11B read by the head 12 is demodulated by the demodulation circuit 20, and the syndrome calculation unit 30 calculates the syndrome from the read data demodulated, and outputs the syndrome to the error position decoding unit 34. As described with reference to FIG. 5, the error position decoding unit 34 solves simultaneous equations relating to the error position and decodes the error position. Further, the error size decoding unit 36 decodes the error size as described with reference to FIG. The decoding error determination circuit 42 receives the error position and the error size from the error position decoding unit 34 and the error size decoding unit 36, and determines whether the correction capability is exceeded. Then, the control circuit 60 is notified that correction is possible or impossible. If correction is possible, the process proceeds to the normal end of step S16.

(S22) On the other hand, when a correction impossible notification is received in step S20, the first switch 32 selects “b” on the syndrome correction unit 50 side according to the instruction of the control circuit 60, and the second switch 44 Then, “b” on the data correction unit 40 side is switched. Then, the difference calculator 46 calculates the difference (see FIG. 11) between the mirror data 11B of the demodulation circuit 20 and the data 11A of the read buffer 22. Then, the error specifying unit 48 detects the case of the difference (3) described above, and detects the error position (block number 4 in FIG. 11) and size (α ¹⁰ = 7 in FIG. 11). (Decimal notation)) is output to the syndrome correction circuit 50 and the data correction circuit 40.

(S24) The syndrome correction circuit 50 sequentially extracts the error position and size, and corrects the mirror data syndrome. FIG. 11 shows a syndrome value corresponding to the error position and size, and is composed of four terms. Here, for block number 4 and size α ¹⁰ = 7 (decimal notation), α ¹⁰ = 7 (decimal notation), α ¹⁰ α ⁴ = 9 (decimal notation), α ¹⁰ α ^{2 * 4} = The four syndrome values are 8 (decimal notation) and α ¹⁰ α ^{3 * 4} = 11 (decimal notation). Hereinafter, for the understanding of the explanation, the Galois field notation and the corresponding decimal notation are used together. As shown in FIG. 12, when the syndrome of the mirror data 11B is S _{0 to} S ₃ , the syndrome correction circuit 50 adds the four syndrome values of FIG. 11 to the syndromes S _{0 to} S ₃ . The corrected syndromes S ′ _{0 to} S ′ ₃ are created.

By this Galois field addition, as shown in FIG. 8, since the syndrome value corresponding to the fourth block is added to the syndromes S0 to S3 of the mirror data, the corrected syndromes S ′ _{0 to} S ′ ₃ are 4 blocks. The syndrome value corresponding to the eye is canceled, and only the seventh and tenth blocks in FIG. For this reason, since the ECC error correction range is not exceeded, ECC correction can be performed from the syndrome in which the mirror data is corrected.

(S26) The corrected syndromes S ′ _{0 to} S ′ ₃ are output to the error position decoding unit 34 via the switch 50. As described with reference to FIG. 5, the error position decoding unit 34 solves simultaneous equations relating to the error position and decodes the error position. FIG. 13 shows the simultaneous error position equations of the example of FIG. That is, the error position simultaneous equations are as shown in the following equation (3).

この連立方程式を解き、σ_１とσ_２とを、図１３のように、計算する。更に、図５で説明した式（２）は、この例では、図１４に示すように、下記式（４）である。

The simultaneous equations are solved, and σ ₁ and σ ₂ are calculated as shown in FIG. Further, in this example, the expression (2) described in FIG. 5 is the following expression (4) as shown in FIG.

図１４に示すように、（４）式に、計算したσ１、σ２を代入し、且つＸ１を、「１」から順に代入すると、σ（１）〜σ（１４）の値が得られる。この値が、「０」の場合の位置Ｘのべき乗表記の指数が、誤り位置として、解読される。この例では、１０進表記Ｘ＝７，１１のべき乗表記α^１０、α^７の指数である「１０」、「７」が、誤り位置として、解読される。

As shown in FIG. 14, when the calculated σ1 and σ2 are substituted into the equation (4) and X1 is substituted in order from “1”, values of σ (1) to σ (14) are obtained. The exponent in the power notation of the position X when this value is “0” is decoded as the error position. In this example, exponents “10” and “7” which are exponents of the decimal notation X = 7,11 and exponents α ¹⁰ and α ⁷ are decoded as error positions.

The error magnitude decoding unit 36 decodes the error magnitude as described with reference to FIG. As shown in FIG. 15, when the decoded error position X1 = 11 (power notation = α ⁷ ) and X2 = 7 (= power notation α ¹⁰ ), as shown in FIG. Calculate That is, the simultaneous equations of the magnitude of the error are changed from the equation (2) to the following equation (5).

Equation (5) is solved to calculate Δ, and error magnitudes e1 and e2 are calculated as shown in FIG. The obtained results are e1 = 11 (power notation = α ⁷ ) and e2 = 4 (power notation = α ² ), which is consistent with FIG. 11. The decoding error determination circuit 42 includes an error position decoding unit 34, an error The error position from the size decoding unit 36 and the size of the error are received, and it is determined whether the correction capability is exceeded, and the control circuit 60 is notified of whether correction is possible or not.

  (S28) If correction is possible, the data correction circuit 38 performs error correction from the decoded error position and size, and outputs the result to the data correction unit 40 via the switch 44. The correction circuit 40 corrects the data of the block excluded from the correction (the fourth block in FIG. 11) with the notified position and size. When the control circuit 60 receives a notification that correction is possible, the control circuit 60 takes in the error correction data of the data correction circuit 38 and ends normally.

  (S30) On the other hand, if error correction is impossible, the control circuit 60 determines whether all error candidates have been extracted. If the control circuit 60 determines that all error candidates have not been extracted, the control circuit 60 returns to step S24.

  (S32) When the control circuit 60 determines that all error candidates have been extracted, the control circuit 60 determines whether the number of readings exceeds the allowable number. If the number of readings does not exceed the allowable number, the process returns to step S18 in FIG. That is, the mirror data is read again and corrected. On the other hand, if the number of readings exceeds the allowable number, the process ends abnormally.

  In this way, the same data is written in a plurality of locations on the storage medium, the main data is read, and if the error cannot be corrected, the mirror data is read. The read data is compared to identify the error location. From the specified information, error position and size information is sequentially taken out, the syndrome value is corrected, and error correction is performed. Further, when data can be corrected normally by ECC, the data is further corrected at a specific error position and size, so that the error correction capability is apparently improved.

(Other embodiments)
In the above-described embodiment, the Reed-Solomon code has been described as the ECC code, but other codes such as a BCH (Bose Chaudhari Hocquengham) code can be used. Further, the error position decoding unit 34 may calculate a syndrome polynomial by a burrecamp Massi (BM) method. In the Burrekamp Massi method, as is well known, an error locator polynomial is calculated by repeating the update of the polynomial as many times as the order of the generator polynomial, starting from the initial value of the polynomial.

  Furthermore, although the example of the application of the storage device of the magnetic disk device has been described, the present invention can also be applied to other medium storage devices such as an optical disk device and a communication device.

  As mentioned above, although this invention was demonstrated by embodiment, this invention can be variously deformed within the range of the meaning, and this is not excluded from the scope of the present invention.

  (Appendix 1) A head that reads data of a storage medium in which the same data is recorded at a plurality of locations, a demodulation circuit that demodulates a read signal of the head, and a syndrome value of read data from the demodulation circuit are calculated, An error correction circuit that specifies an error position from the syndrome value, corrects read data at the specified error position, and outputs error correction data; and a control circuit that controls a read operation of the head; The correction circuit includes a circuit that corrects the syndrome value and a circuit that corrects the corrected data, and the control circuit reads data at a first location and reads the data at the first location. In response to an error correction failure from the error correction circuit, the same data at the second location is read out, and the read data at the second location is read out by the error correction circuit. In addition to performing error correction, upon receiving an error correction failure from the error correction circuit of the read data at the second location, the error correction circuit is instructed to correct, and the error correction circuit responds to the correction instruction. The error location is identified by comparing the read data of the first location and the second location, the syndrome value is corrected based on the identified error position and size information, error correction is performed, and the error A storage device, wherein the error-corrected data is corrected by a position and a size.

  (Additional remark 2) The memory | storage device of Additional remark 1 characterized by the circuit which correct | amends the said syndrome value correct | amends the syndrome value of the read-out data of said 2nd location.

  (Additional remark 3) The said error correction circuit has an error specific circuit which specifies the error location only of the data of said 2nd location by comparing the read data of said 1st location and 2nd location. The storage device of appendix 1.

  (Supplementary Note 4) The error correction circuit includes: a circuit that calculates a syndrome value of read data; a decoding circuit that specifies an error position from the syndrome value; and correction of read data at the specified error position, and error correction data And a data correction circuit for outputting the data.

  (Supplementary note 5) The storage device according to supplementary note 1, wherein the data is Reed-Solomon encoded data including a check block and an information block.

  (Supplementary Note 6) The error correction circuit includes a read buffer that holds the read data of the first location, a comparison circuit that compares the read data of the first location and the second location, and an output of the comparison circuit And the error specifying circuit for specifying the error location of only the data at the second location.

  (Supplementary note 7) The control circuit receives the error correction success of the error correction circuit of the read data of the first location, takes in the error correction data of the error correction circuit, and reads the data of the second location The storage device according to appendix 1, wherein processing is prohibited.

  (Supplementary Note 8) The control circuit receives error correction of the error correction circuit of the read data at the second location, takes in the error correction data of the error correction circuit, and prohibits the correction instruction. The storage device according to appendix 7.

  (Additional remark 9) The syndrome calculation part which calculates the syndrome value of the input data, The error correction part which pinpoints an error position from the said syndrome value, corrects the read data of the specified error position, and outputs error correction data And receiving the same mirror data as the data and comparing the two data, a circuit for identifying an error location, a circuit for correcting the syndrome value of the identified error location, and correcting the corrected data And an error correction circuit.

  (Supplementary note 10) The error correction circuit according to supplementary note 9, wherein the circuit for correcting the syndrome value corrects the syndrome value of the mirror data.

  (Additional remark 11) The said error correction circuit has an error specific circuit which specifies the error location of only the said mirror data by the comparison of both said data, The error correction circuit of Additional remark 9 characterized by the above-mentioned.

  (Supplementary Note 12) The error correction circuit includes: a circuit that calculates a syndrome value of the data; a decoding circuit that specifies an error position from the syndrome value; The error correction circuit according to claim 9, further comprising a data correction circuit for outputting

  (Supplementary note 13) The error correction circuit according to supplementary note 9, wherein the data is Reed-Solomon encoded data including a check block and an information block.

  (Supplementary Note 14) The error correction circuit specifies an error location of only the mirror data from a read buffer that holds the data, a comparison circuit that compares the buffer data with the mirror data, and an output of the comparison circuit And the error correction circuit.

  (Supplementary note 15) The output side of the circuit for calculating the syndrome value is connected to one of the circuit for correcting the syndrome value and the error correction unit, and the output side of the error correction unit The error correction circuit according to appendix 9, further comprising a second switch selectively connected to the data correction circuit.

  (Supplementary note 16) The error correction circuit according to supplementary note 9, further comprising a control circuit which receives error correction of the error correction unit of the input data and takes in the error correction data of the error correction unit.

  (Supplementary note 17) The error correction circuit according to supplementary note 16, wherein the control circuit receives error correction success of the error correction unit of the mirror data and takes in the error correction data of the error correction unit.

  If this data is read and error correction is impossible, the mirror data is read. When both corrections fail, the read data of this data and the mirror data are compared to identify the error location. From the specified information, error position and size information is sequentially taken out, the syndrome value is corrected, and error correction is performed. Further, when data can be corrected normally by ECC, the data is further corrected at a specific error position and size, so that the error correction capability is apparently improved.

It is a block diagram of the reproducing | regenerating system of the memory | storage device which shows one Embodiment of this invention. It is explanatory drawing of the Galois field notation used for FIG. It is explanatory drawing of the Galois field addition of FIG. It is explanatory drawing of the Galois field multiplication of FIG. It is explanatory drawing of the error position decoding part of FIG. It is explanatory drawing of the magnitude | size decoding part of the error of FIG. It is explanatory drawing of the error specific operation | movement of the error correction circuit of this invention. It is explanatory drawing of the syndrome correction | amendment operation | movement of this invention. FIG. 3 is a flowchart (No. 1) of a reading process of the control circuit of FIG. FIG. 3 is a flowchart (No. 2) for reading processing of the control circuit in FIG. It is explanatory drawing of the error specific operation | movement of FIG.9 and FIG.10. It is explanatory drawing of the syndrome correction | amendment operation | movement of FIG.9 and FIG.10. It is explanatory drawing of the simultaneous equations of the error position decoding of FIG.9 and FIG.10. It is explanatory drawing of the error position specification of FIG.9 and FIG.10. It is explanatory drawing of the magnitude | size decoding of the error of FIG.9 and FIG.10. It is explanatory drawing of the conventional error correction circuit.

Explanation of symbols

10 Magnetic disk (storage medium)
11A Main data 11B Mirror data 12 Head 20 Demodulation circuit 22 Read buffer 30 Syndrome operation unit 32 First switch 34 Error position decoding unit 36 Error size decoding unit 38 Data correction unit 40 Data correction unit 42 Decoding error determination circuit 46 Comparison Circuit 48 error identification circuit 50 syndrome correction circuit 60 control circuit 70 ECC decoder

Claims (5)

A head for reading data of a storage medium in which the same data is recorded in a plurality of places;
A demodulation circuit for demodulating the read signal of the head;
Calculating a syndrome value of read data from the demodulation circuit, specifying an error position from the syndrome value, correcting the read data at the specified error position, and outputting error correction data; and
A control circuit for controlling the read operation of the head,
The error correction circuit is
A circuit for correcting the syndrome value;
A circuit for correcting the corrected data,
The control circuit reads data at a first location, receives an error correction failure from the error correction circuit for the read data at the first location, reads the same data at a second location, and the error correction circuit The error correction of the read data of the second location is performed, and the error correction failure of the read data of the second location from the error correction circuit is received, and the error correction circuit is instructed to correct,
In accordance with the correction instruction, the error correction circuit specifies an error location by comparing read data of the first location and the second location, and uses the syndrome value based on the specified error position and size information. And correcting the error, and correcting the error-corrected data with the error position and size. The circuit for correcting the syndrome value is:
The storage device according to claim 1, wherein a syndrome value of the read data at the second location is corrected. The error correction circuit is
2. The storage device according to claim 1, further comprising an error specifying circuit that specifies an error location of only the data at the second location by comparing the read data at the first location and the second location. A syndrome calculator for calculating the syndrome value of the input data;
An error correction unit that specifies an error position from the syndrome value, corrects read data of the specified error position, and outputs error correction data;
A circuit that receives the same mirror data as the data and identifies an error location by comparing the two data;
A circuit for correcting the syndrome value of the identified error location;
An error correction circuit comprising: a circuit for correcting the corrected data. The error correction circuit is
A circuit for calculating a syndrome value of the data;
A decoding circuit for identifying an error position from the syndrome value;
The error correction circuit according to claim 4, further comprising: a data correction circuit that corrects read data at the specified error position and outputs error correction data.

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