JP2010152778A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain improvement in writing speed and a longer life in a multivalue flash memory. <P>SOLUTION: In the semiconductor storage device, a nonvolatile memory includes a plurality of blocks, each of the blocks includes a plurality of pages, and each of the pages includes a plurality of cells. The page is writable in a first mode for recording a plurality of bits in one cell, and the page is also writable in a second mode for recording bits smaller in number of the plurality of bits in one sell in a time shorter than the time required for writing in the first mode. A controller writes data to a first page by use of the second mode in response to a write request of data from the outside of the semiconductor storage device, and writes a part of data in the first page to the second page by use of the first mode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a method for caching user data to be written using a multi-value flash memory as a nonvolatile memory.

  Patent Document 1 includes a nonvolatile memory having a binary flash memory area capable of recording 1 bit in one memory cell and a multi-value flash memory area capable of recording a plurality of bits in one memory cell. A semiconductor memory device is described in which address mapping data for user data stored in the value flash memory area is stored in the binary flash memory area to improve the write operation performance.

JP 2008-84316 A

  Patent Document 1 discloses a mapping management method that uses different recording methods depending on the type of stored data, and a storage device equipped with the mapping management method. However, there has not been proposed a storage device equipped with a cache management method that uses different recording methods depending on whether or not the stored data is written as a cache. The multi-level flash memory has the advantage that the bit unit price is lower than that of the binary flash memory, but has the disadvantage that the write time is long and the number of erasable times is small. In designing a semiconductor memory device configured using a multi-level flash memory with priority on bit cost reduction, it is a problem to improve the host write performance and the rewrite life as much as possible.

  A semiconductor memory device according to the present invention includes a nonvolatile memory and a controller that controls the nonvolatile memory. The nonvolatile memory includes a plurality of blocks, each of which includes a plurality of pages, and each page includes The page is writable in a first mode that records multiple bits in one cell, and the page can also write fewer bits than the multiple bits in the first cell Writing is possible in the second mode in which recording is performed in a time shorter than the time required for writing in the mode. In response to a data write request from the outside of the semiconductor memory device, the controller writes data on the first page using the second mode, and then uses the first mode to write the data in the first page. A part of the data is written on the second page.

  According to the present invention, it is possible to improve the writing speed and extend the life of a semiconductor memory device.

  Hereinafter, a first embodiment of the present invention will be described.

  FIG. 1 shows an embodiment of a storage device SSD (Solid State Drive) according to the present invention. The SSD 1000 has a large number of multi-value (four-value) nonvolatile memories (flash memories) mounted in one package, and a file having a storage capacity for a plurality of pages as an HDD (hard disk drive) compatible storage device. Configure storage.

  The SSD 1000 has, for example, the same outer size (70.0 × 100.0 × 9.5 mm) as a 2.5-inch HDD device or the same outer size (101.6 × 146.146) as a 3.5-inch HDD device. A connector pin mounted in a package of 0 × 25.4 mm and connected to the interface with the external host 1500 is the same as the 2.5 inch HDD device or the 3.5 inch HDD device. As a result, the SSD 1000 is an HDD compatible storage device.

  A multi-level (4-level) flash memory can store a maximum of 2 bits in one memory cell. Basically, a multi-level (4-level) flash memory is one of four types of threshold voltage distributions according to 2-bit write information. The threshold voltage corresponding to one is held. Such a memory cell capable of storing a plurality of bits is generally called an MLC (Multi Level Cell). In this SSD 1000, 2 units (8 chips) such as 1100 to 1107 are mounted as a minimum unit with a configuration in which four flash memory chips that input and output data with a 22 MHz clock are arranged in parallel.

  The quaternary flash memory can store 2 bits in one memory cell, but 2 bits stored in one memory cell are allocated as data of different pages. For example, in a NAND flash memory, data is written and read out for each page unit such as 4 kilobytes. However, when storing 2 bits, 1 bit of each of two row addresses (page addresses) is stored in one memory cell. Corresponding data is stored in multiple. Each such page pair is divided into two, such as a lower page and an upper page. Depending on the product, it may be called A page or B page.

  The SSD 1000 is also provided with means for accessing the flash memory only with the lower page for the quaternary flash memory. When the flash memory is accessed only in the lower page, it can be used as a binary memory cell (generally called SLC (Single Level Cell)). It is known that when a memory cell is operated to write in binary, the operation speed is reduced to about 20% compared to the case of recording in four values (recording using lower page and upper page). ing. For example, the write time with 4 values is 1 millisecond, and the write time with 2 values is 200 microseconds.

  In the SSD 1000, a semiconductor volatile memory is also provided. The semiconductor volatile memory is composed of, for example, an SDRAM (Synchronous Dynamic Random Access Memory) 1252 that operates at 66 MHz × 16 bits. In order to improve the rewrite endurance of the multi-level flash memory, write data from the host 1500 is written. , And non-host data that manages them, and is used for caching.

  A portion 1020 surrounded by a dotted line in FIG. 1 is configured by one semiconductor integrated circuit device (system LSI) as a dedicated SSD controller. That is, the SSD 1000 includes one controller chip 1020, one SDRAM chip 1252, a plurality of multi-value flash memory chips 1100 to 1107, a switch SW1040, and a capacitor CP1030.

  Although not particularly limited, the controller chip 1020 inputs and outputs data to and from the external host 1500 through an interface 1010 such as SATA (Serial AT Attachment). The controller chip 1020 includes a central processing unit CPU 1270 and logic circuits (SATA control unit 1200, register unit 1210, ECC unit 1220, routing unit 1230, FLASH control unit 1240, SDRAM control unit 1250, SRAM (static random access memory). ) Control unit 1260), power source detection unit 1280, and the like.

  The multi-value flash memory chips 1100 to 1107 are connected to the controller chip 1020 through a semiconductor nonvolatile memory I / F (interface). Note that most of the multi-value flash memory chips 1100 to 1107 are used as an area for storing an amount of file data corresponding to the storage capacity of the HDD compatible storage device, but the other part is the host 1500. It is also used to temporarily cache the data written from above.

  In general, a multi-level flash memory is a device that is premised on that error bits are generated more frequently than other memory devices. As data rewrite and erase are repeated, the data storage characteristics of the memory cell may deteriorate, and normal data may not be read at the time of reading. Therefore, when an SSD using a semiconductor nonvolatile memory is configured as a storage medium, an error detection / correction circuit is essential. The ECC unit 1220, which is an error detection / correction circuit, generates parity to be attached to data to be written to the multilevel flash memory chips 1100 to 1107 by encoding / decoding such as a Hamming code / Reed-Solomon code / BCH code. And error detection / correction of the read data.

  The SSD 1000 further includes a power supply detection unit 1280, a capacitor CP1030 and a switch SW1040 for securing an operating voltage when the power is shut off. The capacitor CP1030 has a controller chip 1020, a SATA-I / F 1010, a multi-value flash memory chip 1100 to 1107, and a multi-value flash memory chip 1100 to 1107 even when an unexpected power interruption occurs in power supply from the host 1050 through the SATA interface 1010. The operation voltage Vdd is supplied to the SDRAM chip 1252 to ensure the operation up to the normal end state including the read / write interruption processing of the multi-value flash memory chip, and the data to be saved in the SDRAM chip 1252 is stored in the multi-value flash memory chip. It acts to ensure a sufficient time for retreating to 1100 to 1107. Capacitor CP1030 is configured to have a capacitance value necessary for securing an operating voltage such that the above interruption processing and data saving are performed.

  The power detection unit 1280 receives a power supply voltage from a host 1500 such as a microcomputer, and detects power on and power off. In response to the detected power-on or power-off, switching control of the switch SW1040 and data transfer operation between the multi-value flash memory chips 1100 to 1107 and the SDRAM chip 1252 are performed.

  The switch SW1040 can be switched on and off by a detection signal. When power is turned on from the host 1500, the capacitor CP1030 performs a charging operation using the power supply voltage, and performs an operation of supplying the held voltage as an operating voltage for each component of the SSD 1000. The operation voltage formed by the capacitor CP1030 is prevented from flowing back to the host 1500 side so that the holding voltage of the capacitor CP1030 can be used effectively. In the simplest configuration, the power supply voltage from the host 1500 side is charged up to the capacitor CP1030 through the switch SW1040 as the power supply voltage of the SSD 1000 through a unidirectional element such as a diode, and the controller chip 1020, SATA-I / F1010. The multi-value flash memory chips 1100 to 1107 and the SDRAM chip 1252 are transmitted.

  In the case where a power shutdown or the like occurs on the host 1500 side, the controller chip 1020 and the multi-value flash memory chips 1100 to 1107 are prevented from backflow in which the operating voltage is maintained from the capacitor CP1030 and the SATA-I / F 1010 is connected to the host 1500 Is controlled so as not to respond to a signal (command or the like) from the side, and when saved data exists in the SDRAM chip 1252, the saved data related to a predetermined saved area of the multilevel flash memory chips 1100 to 1107 is saved. . If the power is cut off during the write operation to the multi-level flash memory chips 1100 to 1107, a reset command is issued to each multi-level flash memory chip, and the write operation is interrupted. Similarly, if the multilevel flash memory chips 1100 to 1107 are being erased, a reset command is issued and the erase operation is also interrupted.

  The routing unit 1230 is a circuit provided to realize high speed / stabilization of data transfer inside the SSD 1000, and a FLASH control unit 1240 for controlling reading / writing / erasing of the multilevel flash memory chips 1100 to 1107. Specially for simple, high-speed and stable data transfer between the SDRAM control unit 1250 for controlling data input / output of the SDRAM 1252, the SRAM control unit 1260 for controlling data input / output of the SRAM 1261, the ECC unit 1220, and the SATA control unit 1200. Responsible for integrated route control. On the other hand, the central processing unit CPU 1270 is in charge of complicated control although speed stability is not so required, such as determination of ATA commands input from the external host 1500 and overall management as a storage device.

  The FLASH control unit 1240 includes an interface circuit for four channels and data buffers BUF0 to BUF3. Each channel has an 8-bit data bus. The FLASH control unit 1240 inputs / outputs data by connecting the eight multi-level flash memory chips 1100 to 1107 in a parallel form of 4 channels × 2 enables. Chips 0 and 4, Chips 1 and 5, Chips 2 and 6, and Chips 3 and 7 share data buses with data buffers BUF0, 1, 2, and 3, respectively, and assert one of the two enable signals. As a result, the chip that can use the data buffer or the data bus is switched to {0, 1, 2, 3} or {4, 5, 6, 7}. The data stream read from the flash memory is accumulated up to the sector size (512 B) in the buffers BUF 0 to 3 of the FLASH control unit 1240 and then output to the routing unit 1230.

  The routing unit 1230 has a plurality of data bus selector circuits, and switches the selectors as necessary through the register unit 1210 by firmware recorded in the central processing unit CPU 1270. Thus, a signal path for directly transferring data between the SDRAM and the flash memory, a signal path for sending data from the SDRAM to the ECC unit, adding the generated parity to the data, and transferring the data to the flash memory. A signal path for sending data (with parity) read from the flash memory to the ECC unit and transferring the error-detected / corrected data to the SDRAM, or directly via the SATA-I / F A signal path to be output to an external host is formed. Each part on the path is provided with a buffer, and data is exchanged through the buffer. The routing unit 1230 receives a processing end flag and an error presence / absence notification from each unit connected thereto. When the transfer process is interrupted for some reason, an interrupt signal is transmitted to each unit. The processing end or error notification from the routing unit 1230 to the central processing unit CPU 1270 is performed by register polling of the register unit 1210 by the central processing unit CPU. The register unit 1210 is connected to the routing unit 1230 and each unit on the path through the management signal bus 1290, and the above-described signal path selection and transfer state notification are performed by writing and reading the register accessible from the firmware of the central processing unit CPU 1270. It is comprised so that it can do.

  The power supply detection unit 1280 is configured to notify the central processing unit CPU 1270 and the routing unit 1230 of an interrupt signal and a trigger signal for performing the power supply cutoff process when the power supply voltage drops below a certain value.

  Applying a small capacity to the SDRAM chip 1252 can reduce the amount of data saved (ie, necessary power) when the power is shut down, so that the capacity value of the mounted capacitor CP can be reduced and the SSD 1000 can be downsized. And cost reduction.

  The central processing unit CPU 1270 is connected to other parts by a CPU bus 1271 indicated by the hatched arrows in FIG. The central processing unit CPU 1270 receives a command such as a user data read / write operation instruction from the host 1500 via the register unit 1210, acquires a logical address of the user data, and executes a read / write operation of the user data according to the command.

  The SRAM 1261 basically operates as a work memory for the central processing unit CPU 1270. Information written in the SRAM 1261 from the central processing unit CPU 1270 can be read out from the routing unit 1230 via the SRAM control unit 1260. As a result, the central processing unit CPU 1270 can transmit information to be written to the SDRAM chip 1252 and the multilevel flash memory chips 1100 to 1107 via the routing unit 1230. The information includes, for example, a logical address of user data, the number of block erases of the flash memory, and the like.

  Next, the block configuration, page configuration, and access method of the multilevel flash memory chips 1100 to 1107 will be described with reference to FIG.

  As shown in FIG. 2A, each of the multi-value flash memory chips 1100 to 1107 includes a large number, for example, 4096 blocks 2100 to 2111. Each block is numbered from 0 to 4095. A block is a minimum unit for erasing the multi-level flash memory. The size is, for example, 512 KB. Note that the time spent for erasing the block is, for example, 2 milliseconds. In the multi-level flash memory chip, a part of the block (for example, 3% of the whole) includes a congenital defective block that cannot be used at all. For each of the other (normal blocks), block erasure is guaranteed only a limited number of times, for example, up to 10,000 times. If more times are erased, the memory cell may deteriorate and erasure may be incomplete. A block that is incompletely erased (failed) cannot be rewritten thereafter. Such a phenomenon is called acquired block failure.

  Each of the blocks 2100 to 2111 includes a plurality of, for example, 128 pages 2120 as shown in FIG. Each page is numbered 0-127. A block is a minimum unit for reading from and writing to a multilevel flash memory. The size is, for example, 4 KB. When data is written in units of pages as MLC in one block, it must be performed on an unwritten page after block erasure, and must be performed in ascending order of page numbers (0 → 1 →... → 127). In addition, when data is written in one block as an SLC in page units (2 pages in terms of MLC), it must be performed on an unwritten page after block erasure, and in ascending order of page pair numbers. Don't be. There are 64 page pairs in one block (128 pages). Which page is associated with which page and the order of page pair numbering depends on the flash memory chip product. There are various. Here, as an example, a flash memory chip in which page 2Y and page 2Y + 1 (Y = 0 to 63) are in a pair relationship and the page pair number is Y is assumed. In that case, data must be written in the order of page write as SLC and arrows 2130, 2131,.

  Regardless of the two write methods (MLC method / SLC method), if data is to be written again on a written page, the block itself must be erased before that. In addition, in a block where the number of erases exceeds the guaranteed value, the memory cell may deteriorate and writing may be incomplete. Blocks that are incompletely written (failed) are not allowed to be rewritten thereafter. This phenomenon is also one of acquired block failures.

  The multi-level flash memory has a function of two page simultaneous writing and two block simultaneous erasing in order to perform page writing and block erasing at high speed. As shown in FIG. 2C, with X being an integer from 0 to 2047, two pages (for example, 2200) of the same number can be written simultaneously (but as MLC) for 2X number and 2X + 1 number 2 blocks 2300. is there. Further, two blocks having an adjacent relationship such as 2300 can be erased simultaneously.

  Next, physical management specifications of blocks and pages of a flash memory for storing user data in the SSD 1000 will be described with reference to FIGS. 3 and 8A.

  As shown in FIG. 3, memory blocks 0 to 2A and 2A + 1, 2 blocks 3210 and 3220 are selected with A being an integer from 0 to 2047, and B is an integer from 0 to 2047, and memory chips 1 to 2B are selected. 2B + 1 No. 2 blocks 3211 and 3221, C is an integer from 0 to 2047, 2C No. 2C and 2C + 1 No. 2 blocks 3212 and 3222 are selected, and D is an integer from 0 to 2047 Select 2 blocks 3213 and 3223 from chip 3 to 2D and 2D + 1, select 2 blocks 3214 and 3224 from memory chip 4 to 2E and 2E + 1, and set E to an integer from 0 to 2047, and set F to 0 As an integer of 2047, 2 blocks 3215 and 3225 of memory chip 5 to 2F and 2F + 1 are selected, and G is set to 0 to 2047. As an integer, 2 blocks 3216 and 3226 of memory chip 6 to 2G and 2G + 1 are selected, and 2 blocks 3217 and 3227 of memory chip 7 to 2H and 2H + 1 are selected as an integer of 0 to 2047, An erase unit EU3200 is formed by collecting these 16 blocks. The size is, for example, 8 MB. A large number of such EU sets are created using all normal blocks (blocks that are not inherently defective) on the multilevel flash memory chips 1100 to 1107. When executing block erase in the SSD 1000, this EU is used as a unit.

  EUs on the multi-level flash memory chips 1100 to 1107 are classified into five types according to their usage. FIG. 8A shows their type names and distribution.

  The 16 sets of EUs from the youngest block address are assigned to the save & table 8110 type. Here, user data saved from the SDRAM chip 1252 when the power is shut down, address information of the data, and the like, and a table including other EU allocation states and user data storage states are recorded. The allocation destination of these EUs is fixed at 8110, but the allocation destinations of other EUs vary between 8120 and 8140 in accordance with the data rewrite in the SSD 1000.

  Of the other EUs, three sets of EUs are assigned to the type of secondary cache 8120. Further, at least 1884 EUs are assigned to the type of data & tertiary cache 8130. Also, at most 145 sets of EUs are assigned to a type of free 8140.

  When the erase unit EU3200 is allocated as the secondary cache 8120, the EU is used as a temporary storage location for user data. However, reading and writing of the data is performed by the SLC method. Therefore, the substantial storage capacity of the EU1 set is 4 MB, which is half of 8 MB.

  When the erase unit EU3200 is allocated as the data & tertiary cache 8130, the memory space is divided into two areas 3231 and 3232 and managed as shown in FIG. They are called a data area 3231 and a tertiary cache area 3232, respectively. In both areas, data is read and written by the MLC method. The data area 3231 is a collection of page numbers 0 to 119 of each constituent block, and the tertiary cache area 3232 is a collection of page numbers 120 to 127 of each constituent block. The data area 3231 has a size of 7680 KB and user data static is used as a storage location, and the tertiary cache area 3232 has a size of 512 KB and is used as a temporary storage location for user data. The data area 3231 is further divided into 60 sub-areas. Each of them is a 128 KB area configured by collecting two pages from each component block, as indicated by the hatched portion 3240 in FIG. These are called physical management units PMU. The number of EU groups allocated as the data & tertiary cache 8130 varies according to the data rewrite performed in the SSD 1000.

  When the erasing unit EU3200 is allocated as free 8140, the EU becomes a spare for the EU allocated as 8120 or 8130. The number of EU groups allocated as free 8140 changes according to the execution of data rewriting in the SSD 1000. The EU is also used as a spare when the EU assigned as 8120 or 8130 is acquired later. If there is no congenital bad block in the flash memory chip, 145 EU groups are allocated as free 8140 in the initial state. The number of EU groups allocated as free 8140 also decreases every time an acquired failure occurs. When the number of sets becomes a small value (for example, zero), the SSD 1000 loses tolerance for acquired block failure, and therefore changes to a mode in which it operates as a read-only storage device. For example, an error is returned without writing data in response to a write command from the host.

  Next, a user data storage method in the erase unit EU 3200 allocated as the data & tertiary cache 8130 will be described with reference to FIG.

  FIG. 4A shows how a logical address space (LBA space) for managing user data by the host 1500 is allocated to the physical address space.

  As shown in FIG. 4A, the LBA space 4000 of user data is first divided into logical blocks of 7680 KB units such as 4010, 4020, and 4030. Next, each logical block is equally divided into 60 sub-regions (128 KB each). These are called logical management units LMU. User data is stored in the flash memory by allocating the LMU and the PMU in a one-to-one relationship. For example, LMU 4110 data is stored in the PMU 4210, LMU 4120 data is stored in the PMU 4220, and LMU 4130 data is stored in the PMU 4230. As shown in the figure, the correspondence from the LMU to the PMU may be random and not necessarily in the address order.

  As shown in FIG. 4A, the state in which 60 LMUs in the logical block 4020 are allotted to one of 60 PMUs in the data area 3231 in one EU 3200 is the initial state of the SSD 1000. Or it is limited to the state immediately after the garbage collection. By writing user data from the host 1500, a state in which 60 LMU groups 4020 are allocated to PMUs across two EUs 3200 and 3201 as shown in FIG. 4B is generated. For example, a case where user data included in the LMU 4120 is updated (written) twice by the host 1500 will be described. In the first update, the EU 3201 is procured from among the EUs allocated as free 8140, and the allocation destination of the LMU 4120 is invalidated by the PMU 4220 that records the state before the update, and the PMU 4221 that records the state after the update is valid. become. Next, in the second update, the PMU 4221 that records the state before the update is invalidated, and the PMU 4222 that records the state after the update becomes valid. EU 3201 newly procured by such data update is referred to as update EU. The update EU3201 is affected by the LMU address pattern of data written from the host 1500, and the LMU and the PMU are not necessarily allocated in a one-to-one relationship. Hereinafter, the EU 3200 in which the LMU and the PMU are allocated in a one-to-one relationship is referred to as a basic EU, and the two are distinguished.

  When there are N LMU allocation states as shown in FIG. 4B, the number of EU groups allocated as data & tertiary cache 8130 is increased by N groups to 1884 + N groups, and EUs allocated as free 8140 The number of sets decreases by N sets to 145-N sets. In general, if user data is continuously written from the host 1500, N increases monotonously and the free 8140 EU is exhausted. Therefore, garbage collection is a process performed to increase the number of free 8140 EU groups. This is because the central processing unit CPU 1270 determines that the allocation state as shown in FIG. 4B is forcibly changed to the allocation state as shown in FIG. This is a process in which a logical block (7680 KB) created by collecting only these is moved to one unwritten EU and made a basic EU.

  Next, the procedure by which the SSD 1000 stores write data from the host 1500 will be described with reference to FIGS. 5 and 6. FIG.

  The SSD 1000 secures two types of cache areas on the SDRAM chip 1252 in order to temporarily store write data in a volatile manner. One is an LMU cache having a capacity of 128 KB, and the other is a random primary cache having a capacity of 128 KB. When the data received by the write command from the host 1500 is larger than 16 KB, it is cached in the LMU cache, and when it is 16 KB or less, it is cached in the random primary cache.

  The write process when the write data is larger than 16 KB will be described with reference to FIG.

  Data is cached in the LMU cache 5000 so that the logical management unit LMU including the address range of the write data can be accommodated without deviation. That is, the first sector (00h) in the LMU is arranged in the first sector of the LMU cache 5000, and the last sector (FFh) in the LMU is arranged in the last sector of the LMU cache 5000. Since the logical management unit LMU divides the LBA space by 128 KB, that is, by 256 sectors, as shown in FIG. 5B, the upper 40 bits are the LMU address and the lower 8 bits are the LMU address in the LMU as shown in FIG. Represents a sector address. Therefore, the lower 8 bits of the LBA specified by the write command are the head sector address when the write data is cached in the LMU cache 5000.

  The 128 KB data stored in the LMU cache 5000 will eventually be written to one of the PMUs on the flash memory. At that time, the writing is performed four times by 32 KB. Since the FLASH control unit 1240 performs simultaneous writing of two pages (8 KB) to four chips using four channels simultaneously (see FIG. 2C), the size of one write is 8 × 4 = 32 KB. Become. When the LMU cache 5000 is divided into four 32 KB areas 5010 to 5040, each area is written to the PMU of the flash memory as a unit. This light is an MLC method.

  For example, it is assumed that the lower 8 bits of the LBA specified by the write command are 30h (= 48) and the write data size is 130 sectors. At this time, the write data is temporarily stored in the sector range 5110 in the LMU cache 5000 (5220). As described above, since writing to the PMU of the flash memory is performed in units of 32 KB, data of 48 sectors (address range 5100) from the head is insufficient to perform the writing 5240 of the area 5010. Therefore, the current PMU storing the data is read to supplement the area 5010 with the data (5210). Thereafter, the write 5240 of the area 5010 to the new PMU is performed. The states of the current PMU and the new PMU at this time are equal to the state immediately before the invalidation of 4221 and the validation of 4222 occur in FIG. 4B. Next, the write 5241 of the area 5020 without data shortage is performed. Next, the write 5242 of the area 5030 is executed, but the data in the rear 14 sectors is insufficient. There are two methods for replenishing the missing data. One is a method of replenishing data after waiting for the next write command of the host 1500 (5230). Empirically, there is a possibility that the host 1500 is continuing the sequential write, and data write in the address range 5120 can be expected. Therefore, such a method is applied. The other is a method (5231) of reading the current PMU storing the data and replenishing the data in the area 5030 in the same way as the area 5010 when the former expectation is lost. Finally, the light 5243 in the area 5040 is similarly executed to complete the 128 KB light to the new PMU. In FIG. 4B, this means that the invalidation of 4221 and the validation of 4222 have been established.

  With the write cache method that expects LBA continuity as described above, the ratio of the host write data to the flash memory write data increases, and the rewrite efficiency of the SSD 1000 is improved.

  In the above description, a write cache method has been described in which when the insufficient data is replenished in the 32 KB area, the write cache method is immediately written to the flash memory. The method may be used. This alternative method is effective when there is an overlap in the LBA range specified by a plurality of write commands. The SDRAM is a memory that can be overwritten and updated and has a substantially unlimited rewrite life. If the LMU cache 5000 is overwritten for each write command and only the latest data is left, the number of writes to the PMU on the flash memory can be reduced as a result, and the rewrite life of the SSD 1000 is improved.

  The write process when the write data is 16 KB or less will be described with reference to FIG.

  The random primary cache 6000 has eight areas 6010 to 6080 in which write data can be cached in units of 16 KB. A data cache method for this area will be described below. For example, it is assumed that the write data size specified by the write command is 20 sectors (10 KB). At this time, if the area 6020 in the random primary cache 6000 is empty, the write data is temporarily stored in the 10 KB range (for example, 6120) in the area (6420). The area 6020 lacks data of 12 sectors (address range 6110) from the beginning. Therefore, the memory (including not only the flash memory but also the SDRAM) storing the latest data in the range is read and the data is replenished to the address range 6110 (6410).

  As described above, when data is cached in the random primary cache 6000 and there is no free space, 16 KB data with the lowest access frequency is expelled from the random primary cache 6000 to secure free space. The evicted data moves to one of the random secondary caches 6300 on the flash memory.

  The random secondary cache 6300 is allocated to three sets of EUs on the flash memory as indicated by 8120 in FIG. The LBA space 4000 is divided into three sections, and each section is configured to use a random secondary cache 6300 one by one. These pages in the EU are recorded by the SLC method. Therefore, the effective capacity of each random secondary cache is 4 MB, and is composed of 256 16 KB areas 6210 to 6250.

  For example, when the data stored in the area 6070 has the lowest access frequency in the past 32 accesses, the stored data is written to the unwritten 16 KB area (for example, 6220) in the random secondary cache 6300 by the SLC method. (6430).

  As described above, when data is cached in the random secondary cache 6300 and there is no free space, all 16 KB data is expelled from the random secondary cache 6300 and the EU is deleted to secure 256 free spaces. To do. The evicted data (only the latest data when the LBA overlaps) moves to the PMU of the update EU (see 3201 in FIG. 4) or the random tertiary cache of the basic EU (see 3200 in FIG. 4). The movement depends on conditions, and details will be described later with reference to the flowchart of FIG.

  The random tertiary cache indicates a 512 KB tertiary cache area (for example, 6312) in the EU (for example, 6310) allocated as data & tertiary cache such as 8130 in FIG. 8A. When writing data in the tertiary cache area, the FLASH control unit 1240 uses 4 channels simultaneously, and each page is 4 pages (4 KB) for each even-numbered block of 4 chips or each odd-numbered block of 4 chips. Since writing is performed, the size of one write is 4 × 4 = 16 KB. This light is an MLC method. According to this write size, the tertiary cache area is composed of 32 16 KB areas.

  Of the data evicted from the random secondary cache 6300, a method of evicting to the random tertiary cache will be described with respect to 16 KB data included in the area 6240, for example. First, the logical block (such as 4020 in FIG. 4) to which the logical address of the eviction data belongs is examined. Next, the EU (such as 3200 in FIG. 4) in which the PMU to which the LMU of the logical block is allocated exists is examined. In addition, when it is assigned across two EUs as in 3200 and 3201 in FIG. 4B, the basic EU (3200 in FIG. 4) is selected. If the selected EU is 6310 in FIG. 6, the eviction data is recorded in a free area in the tertiary cache area 6312 in the EU (6460).

  Of the data evicted from the random secondary cache 6300, for example, the evicting method to the PMU will be described with respect to 16 KB data included in the area 6240. First, the logical block (such as 4020 in FIG. 4) to which the logical address of the eviction data belongs is examined. Next, the EU (such as 3200 in FIG. 4) including the PMU to which the LMU of the logical block is allocated is examined. In addition, when it is assigned across two EUs as in 3200 and 3201 in FIG. 4B, the update EU (3201 in FIG. 4) is selected. If the selected EU is 6320 in FIG. 6, the LMU data including the eviction data is recorded in the unwritten PMU 6321 in the EU (6440). The range (112 KB) other than the eviction data in the LMU data (128 KB) is replenished by reading the memory (including not only the flash memory but also the SDRAM) storing the latest data in the range (6450). . The PMU 6321 becomes a new PMU assigned to the LMU as indicated by 4222 in FIG.

  As a result of expelling data from the random secondary cache to the random tertiary cache, if the free area in the tertiary cache area (for example, 6312) becomes zero, the expelled data will be ejected to the next random tertiary cache. The third cache area is re-allocated by performing garbage collection of the logical block including Specifically, one set is obtained as a candidate for a new basic EU from EUs allocated as free, and 60 latest LMU data of the logical block are written in the data area (for 60 PMUs). The latest LMU data is configured by collecting data in the original basic EU data area and tertiary cache area, an updated EU data area, and cache data on the SDRAM. As a result, since the tertiary cache area of the new basic EU is 16 KB × 32 free areas, data can be evicted from the random secondary cache to the random tertiary cache again. The original basic EU and updated EU are deleted and assigned as free. As shown in FIG. 4B, the LMU allocation state immediately before garbage collection often spans two EUs, and there are two EUs to be erased. Therefore, one set of free EU is consumed → 2 sets are generated by garbage collection, and as a result, one set of free EU can be increased.

  For the SSD 1000, the frequent occurrence of garbage collection is a cause of a decrease in write performance. Garbage collection is a process that requires 240 page writes (moving to the data area) and 2 erasures (free EU generation) even if 8 flash memory chips are operated in parallel. It is. This requires at least 240 × 1 milliseconds + 2 × 2 milliseconds = 244 milliseconds. Therefore, not performing garbage collection as much as possible reduces the command response time and improves the write performance. Further, reducing the number of occurrences of garbage collection (that is, the occurrence frequency) for a certain amount of host write as much as possible delays the deterioration of memory cells and improves the rewrite life. Although details will be described later, the SSD 1000 to which the present embodiment is applied uses a random secondary cache to suppress the occurrence of garbage collection as compared with a conventional SSD that does not have this.

  Next, referring to FIG. 7, in the host write of 16 KB or less, the eviction process executed by the central processing unit CPU 1270 when the data eviction from the random secondary cache becomes necessary (selection of 6440/6460 in FIG. 6). Details).

  First, the central processing unit CPU 1270 determines whether there is a vacancy in the tertiary cache area of the basic EU (7010). If the result is true, the eviction data is added to the tertiary cache area of the basic EU (7060), and the process ends.

  On the other hand, if the result of step 7010 is false, the allocation destination PMU group of the logical block to which the data evicted from the random secondary cache belongs extends over two erase units EU, that is, the update EU is given to the logical block. (7020).

  If the result of step 7020 is true, it is determined whether there is an empty PMU in the data area of the updated EU (7030). If the result is false, it is impossible to record the eviction data in the updated EU. Therefore, a set of EUs is obtained from the EUs allocated as free (7040), and the EUs are designated as data destinations. The garbage collection process is executed (7050), and the process ends. Thereafter, the destination EU becomes the new basic EU of the logical block. In step 7050, the original basic EU and the updated EU are deleted and allocated as free.

  On the other hand, if the result of step 7020 is false, a set of EUs is acquired from the EUs allocated as free, set as the update EU of the logical block (7070), and the process proceeds to the following step 7080.

  If the result of the above step 7030 is true, in order to record the eviction data in the update EU, the update EU is obtained by merging the eviction data 16 KB with the latest data (112 KB) of its peripheral address and expanding it to 128 KB. (7080). This is the end of the process.

  Next, the transition (life cycle) of the allocation destination type of the erasing unit EU will be described with reference to FIG.

  Along with data write from the host, EU allocated as free may be procured as updated EU. In such a case, the EU type changes as indicated by an arrow 8220.

  When garbage collection occurs, the basic EU and update EU allocated as data & tertiary cache are erased, and the EU allocated as free is procured as a new basic EU. In such a case, the new basic EU type transitions as indicated by arrow 8220 and the erased EU type changes as indicated by arrow 8230.

  When an EU allocated as data & tertiary cache becomes an acquired defect during access, an EU allocated as free is procured as an alternative destination. In such a case, the type of the substitution destination EU transitions as indicated by an arrow 8220, and the failed EU changes to a discarding EU as indicated by an arrow 8240.

  After the EU allocated as a random secondary cache is appended to the last page, the EU is deleted, and the EU allocated as free is procured as a new random secondary cache. In such a case, the procured EU type changes as indicated by an arrow 8221, and the deleted EU type changes as indicated by an arrow 8231.

  When an EU allocated as a random secondary cache becomes an acquired defect during access, an EU allocated as free is procured as an alternative destination. In such a case, the type of the substitution destination EU changes as indicated by an arrow 8221, and the defective EU changes to a discarding EU as indicated by an arrow 8241.

  Next, referring to FIG. 9, the SSD 1000 uses a random secondary cache to give a specific example that the write performance is improved and the rewrite life is improved as compared with a conventional SSD that does not have it. Show.

  For example, a write cache operation in the SSD 1000 is considered when a large amount of data is randomly written in units of 16 KB (32 sectors) from the host 1500 within a range of 0000h to 01FFh (512 sectors from the head) in LBA.

  First, since the write data in this example is a unit of 16 KB, it always enters the random primary cache. Since the capacity of the random primary cache is 128 KB (256 sectors), which is half the address range, the hit rate is 50% on average. That is, about half of the write data is evicted to the random secondary cache.

  The size of the address range of data transferred from the random primary cache is 256 KB, that is, 16 pieces of 16 KB data. In addition, up to 256 16 KB data can be added to the random secondary cache. Therefore, of the 256 entries recorded when the random secondary cache vacancy becomes zero, the entries including the latest data are, on average, 16/16. For example, as shown in FIG. 9A, there are 16 entries including the latest data such as entries 9011, 9012, and 9014, and 240 entries including old data such as entries 9010 and 9013. When the random secondary cache is full, 16 entries of data need to be moved further, but the remaining 240 entries of data need not be moved.

  The SLC write is generated 256 times in units of 16 KB until the random secondary cache is completely written from the unwritten state. Further, every time 256 KB latest data is expelled from the random secondary cache, the MLC write is generated 8 times in 32 KB units, and the random secondary cache EU is erased once.

  The latest data of 256 KB evicted from the random secondary cache is first moved to the tertiary cache area of the basic EU as indicated by arrows 9020 and 9030 in FIG. 9A, but is moved twice because the capacity is 512 KB. Then the space becomes zero. Thereafter, as shown by an arrow 9040 in FIG. 9B, the data is moved to the data area of the update EU. However, since the capacity is 7680 KB, the space becomes zero after 30 movements.

  Garbage collection is performed when there is no destination for the latest 256 KB data evicted from the random secondary cache. At this time, 256 KB data is moved from the random secondary cache to the data area of the new basic EU as indicated by an arrow 9050 in FIG. 9C, and from the original basic EU at LBA as indicated by an arrow 9060 in FIG. 9C. Data in the range of 0200h to 3BFFh is moved to the new basic EU data area.

  If random writing is continued as it is, a series of write cache operations as described above are repeated with one interval from the occurrence of garbage collection to the next occurrence of garbage collection as one segment. In this one segment, since the random secondary cache has 32 times of data eviction, the total number of writes to the random secondary cache is 256 × 32 = 8192 times. If the random primary cache hit rate is 50%, the number of writes from the host is 8192 / 0.5 = 16384 times.

  In one garbage collection segment, the random secondary cache EU is erased 32 times, and the basic EU and the update EU are erased once, resulting in a total of 34 erases. The number of EU erases per host write is about 0.002.

  Consider the total host write processing time in one segment. The SLC write time is 256 × 32 × 0.2 milliseconds = 1638.4 milliseconds, the MLC write time is (32 × 8 + 240) × 1.0 milliseconds = 496 milliseconds, and the erase time is 34 Since x 2 milliseconds = 68 milliseconds, the total is 2202.4 milliseconds. The processing time per host light is about 0.134 milliseconds.

  Next, the same consideration is given to an SSD that does not have a random secondary cache. In this case, the data evicted from the random primary cache is directly moved to the basic EU or the update EU.

  In one garbage collection segment, 32 evictions occur in 16 KB increments to the tertiary cache area of the basic EU, and 60 evictions occur in 128 KB increments (with 112 KB replenishment) in the update EU data area. If the random primary cache hit rate is 50%, the number of writes from the host is (32 + 60) /0.5=184 times.

  In this one division, the basic EU and the update EU are erased once, so that a total of two erasures occur. The number of EU erases per host write is about 0.01.

  Consider the total host write processing time in one segment. Since the MLC write time is (32 + 60 × 4 + 240) × 1.0 milliseconds = 512 milliseconds and the erase time is 2 × 2 milliseconds = 4 milliseconds, the total time is 516 milliseconds. The processing time per host write is about 2.8 milliseconds.

  To summarize the above results, the SSD 1000 equipped with a random secondary cache that records write data by the SLC method has about 20 times the write of a local address random write compared to a conventional SSD that does not have it. It has performance and the frequency of erasure is about 1/5 times. In other words, the erase frequency is about 1/5 times, which means that the rewrite life is about 5 times. As described above, the effect of the present embodiment was quantitatively shown.

  The address local random write is an access pattern often seen in updating the cluster management table when rewriting a file when the host 1500 uses the OS standard file system to handle file data on the storage device. is there. Therefore, the effects enjoyed by this embodiment are not stochastically unique.

  Hereinafter, a second embodiment of the present invention will be described.

  The present embodiment is obtained by changing a part of the specifications of the first embodiment, and the parts not particularly mentioned are the same as those of the first embodiment. The changed part will be described with reference to FIG.

  This embodiment is effective when it is clear that the write access of the host 1500 to the SSD increases in a certain logical address range FWR as shown in FIG.

  In the LBA space 4000, only within this FWR range 10010 to 10030, as shown in FIG. 10B, the logical block size is reduced to 3840 KB, for example, and address division is performed. ) Is composed of 30 LMUs.

  The SSD of this embodiment creates an erase unit EU10100 having 30 PMUs to which these 30 LMUs are allocated. The EU 10100 is a kind of EU assigned to the type 8130 in FIG. 8, but the distribution ratio between the data area and the tertiary cache area is special. That is, 60 pages of pages 0 to 59 of each constituent block constitute a data area 10200, and 68 pages of remaining pages 60 to 127 constitute a tertiary cache area 10300. In this way, the EU that has expanded the tertiary cache area can accumulate a large amount of data evicted from the random secondary cache. Under the access conditions as shown in FIG. 10A, the write data in the FWR range is frequently evicted from the random secondary cache, but the evicted data is recorded in the extended tertiary cache area. Thus, the time until the free space becomes zero is longer than that in the first embodiment (8.5 times in this example). As a result, the occurrence frequency of garbage collection can be further reduced as compared with the first embodiment. That is, the write performance is further improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. . For example, the flash memory may be a NAND flash memory or a NOR flash memory. The capacity of the SDRAM and the page size, block size, and number of blocks of the flash memory vary depending on the memory product employed. The input / output bus widths of these memory chips are also different. The number of bits that can be recorded in one memory cell is 2 bits in the MLC method and 1 bit in the SLC method, but the present invention is not limited to these recordable bits. Any flash memory may be used as long as it has a write method for recording a plurality of bits in one cell and a write method for recording fewer bits in one cell in a shorter time than the former.

The storage device of this embodiment is one that is mounted in a package equivalent to the HDD package having an outer size smaller than 2.5 or 3.5 inches, such as 1 inch or 1.8 inches, or originally developed. Various embodiments such as a simple package or simply mounted on a mounting substrate can be adopted.
As described above, according to the embodiment of the present invention, in a semiconductor memory device configured using a multi-level flash memory, when data of a small size is randomly written from a host within a partial address range, The host write performance is improved by performing writing in an average shorter time than the normal writing time of the multi-level flash memory, and reducing the frequency of block erasing when the block data of the multi-level flash memory is transferred. It is possible to achieve the effect of improving the rewrite life.

It is a figure which shows the internal structure of SSD which applied embodiment of this invention. It is a figure which shows the physical structure and access specification of a multi-value flash memory. It is a figure which shows the structure of the erasing unit EU used when erasing a flash memory block in SSD. It is a figure which shows the method to allocate the data of logical address space to the physical page in erase unit EU in SSD. It is a figure which shows the data storage processing method of SSD with respect to the data write exceeding 16KB by a host. It is a figure which shows the data storage processing method of SSD with respect to the data write of 16KB or less by a host. It is a flowchart which shows the data eviction processing method from a random secondary cache with respect to the data write of 16KB or less by a host. It is a figure which shows the allocation type of the erasing unit EU in the flash memory mounted in SSD, and its life cycle. It is a figure which shows the change of the data storage condition in SSD in 16KB random write of a 256KB address range. It is a figure which shows the method to allocate the data of a part of logical address space to the physical page in erase unit EU in SSD which is the 2nd Embodiment of this invention.

Explanation of symbols

1000 ... SSD, 1020 ... controller chip, 1100 to 1107 ... flash memory chip, 1252 ... SDRAM chip, 1270 ... central processing unit CPU, 1500 ... host, 3200 ... erase unit EU, 3231 ... data area, 3232 ... tertiary cache area 6000 ... random primary cache, 6300 ... random secondary cache.

Claims (4)

A semiconductor memory device including a controller for controlling a nonvolatile memory,
The nonvolatile memory includes a plurality of blocks, each of the blocks includes a plurality of pages, each of the pages includes a plurality of cells,
The page can be written in a first mode that records multiple bits in one cell, and the page can also write fewer bits than the multiple bits in one cell in the first mode. Can be written in the second mode for recording in a time shorter than the time required for
In response to a data write request from the outside of the semiconductor memory device, the controller writes the data to the first page of the nonvolatile memory using the second mode, and then The semiconductor memory device, wherein a part of the data in the first page is written into a second page of the nonvolatile memory using a mode. The semiconductor memory device according to claim 1,
After writing a portion of the data in the first page to the second page using the first mode,
The semiconductor memory device, wherein the first block including the first page is erased. The semiconductor memory device according to claim 1, wherein
The second block including the second page includes a third page other than the second page;
The semiconductor memory device, wherein the third page stores data in a first address range including a first logical address corresponding to a part of the data written in the second page . The semiconductor memory device according to claim 3,
The controller is
In response to a data write request from the outside of the semiconductor memory device,
After writing the data to the fourth page using the second mode,
Writing a portion of the data in the fourth page to a fifth page using the first mode;
The third block including the fifth page includes a sixth page other than the fifth page, and the sixth page corresponds to a part of the data written in the fifth page. Storing data in a second address range including a second logical address
If the frequency of the write request for the second address range is greater than the frequency of the write request for the first address range,
The semiconductor memory device, wherein the number of the fifth pages included in the third block is greater than the number of the second pages included in the second block.

Images