JP2010141569A - Information processor and data transmission method - Google Patents

Abstract

The content of communication data is prevented from being obtained without concealing the communication procedure.
A first information processing module and a second information processing module are connected to each other by a signal line, the first information processing module sends a clock signal to the signal line, and a data signal. The second information processing module superimposes on the rising edge of the clock signal and superimposes a delivery confirmation signal for the data signal received via the signal line on the falling edge of the clock signal. The data signal is superimposed on the rising edge of the clock signal sent to the signal line by the information processing module, and the delivery confirmation signal for the data signal received via the signal line is set on the falling edge of the clock signal. An information processing apparatus for superimposing is provided.
[Selection] Figure 8

Description

  The present invention relates to an information processing apparatus and a data transmission method.

  In general, security related to information technology refers to maintaining the confidentiality, integrity, and availability of programs and data. Among them, examples of the security risk in communication include data eavesdropping, falsification, or impersonation. Further, for example, from the viewpoint of copyright protection, unauthorized copying of content data flowing on the communication path can be a security risk.

  In order to maintain security in information communication, encryption technology is often used. For example, impersonation or falsification of data can be detected by giving an electronic signature based on a public key cryptosystem to communication data. Further, for example, by encrypting a communication path through mutual authentication between communication devices, it is possible to conceal communication data to prevent eavesdropping, or to protect content data from illegal copying by an unauthorized device.

  However, even if the communication path is encrypted, an attack may be made by, for example, acquiring encrypted communication data by monitoring the communication path and diverting the acquired data for impersonation. . Moreover, the encryption algorithm currently used may be estimated by analyzing the data acquired by monitoring. Therefore, conventionally, as an approach for improving security, technological development has been advanced in the direction of concealing communication procedures and / or increasing the strength of encryption.

  Such a situation is generally the same when any communication technology is used. For example, Patent Literature 1 below discloses a technique that can simplify wiring between devices using a serial transmission method. According to the technique described in Patent Document 1 below, data is transmitted using an AMI code, which is a typical example of a bipolar code. At this time, the data clock is represented by an intermediate value of the signal level, and the data clock is reproduced on the receiving side based on the signal level.

Japanese Patent Laid-Open No. 3-109984

  However, if the communication procedure is concealed or the encryption strength is increased, the circuit scale and processing amount required for the communication processing inevitably increase. This is a negative factor for communication devices that are required to be smaller and consume less power in many cases.

  Therefore, the present invention has been made in view of the above problems, and the object of the present invention is to make it impossible to know the contents of communication data without concealing the communication procedure. It is an object of the present invention to provide a new and improved information processing apparatus and data transmission method.

  In order to solve the above-described problem, according to an aspect of the present invention, a first information processing module and a second information processing module are connected to each other by a signal line, and the first information processing module includes a clock. A signal is sent to the signal line, a data signal is superimposed on the rising edge of the clock signal, and a delivery confirmation signal for the data signal received via the signal line is superimposed on the falling edge of the clock signal. The second information processing module superimposes a data signal on the rising edge of the clock signal sent to the signal line by the first information processing module, and the data signal received via the signal line An information processing apparatus is provided that superimposes a delivery confirmation signal on the falling edge of the clock signal.

  Further, the first information processing module or the second information processing module may superimpose a dummy data signal on the rising edge of the clock signal at any time when there is no data signal to be transmitted.

  The dummy data signal may be a signal having the same bit pattern as a data signal received in the past.

  The dummy data signal may be a signal having a predetermined bit pattern defined in advance.

  In addition, when the first information processing module or the second information processing module does not detect a collision of data signals, the continuous data signal is set to the rising edge of the clock signal with a predetermined time interval. It may be superimposable.

  The first information processing module may supply power to the second information processing module using the signal line.

  In addition, when the first information processing module and the second information processing module detect a data signal collision, the first information processing module and the second information processing module output a cancel signal having a voltage that cancels a fluctuation in the voltage of the signal line due to the collided data signal. It may be superimposed on the rising edge of the clock signal.

  In addition, the delivery confirmation signal may have a voltage that cancels the fluctuation of the voltage of the signal line due to the received data signal.

  In order to solve the above problem, according to another aspect of the present invention, in the information processing apparatus including the first information processing module and the second information processing module connected to each other via a signal line, The information processing module superimposes the data signal on the rising edge of the clock signal, the first information processing module sends the clock signal to the signal line, and the second information processing module Receiving the data signal superimposed on the clock signal, superimposing a delivery confirmation signal for the received data signal on the falling edge of the clock signal by the second information processing module, Receiving the delivery confirmation signal by one information processing module. Transmission method is provided.

  As described above, according to the information processing apparatus and the data transmission method according to the present invention, it is possible to prevent the contents of communication data from being acquired without concealing the communication procedure.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

The “best mode for carrying out the invention” will be described in the following order.
1. 1. Description of communication method related to the present invention 1-1. Overview of communication method 1-2. 1. Configuration for serial transmission system 2. Description of information processing apparatus according to one embodiment 2-1. Outline of information processing apparatus 2-2. Configuration of information processing apparatus 2-3. Amplitude values of data signal and delivery confirmation signal 2-4. Collision detection process 2-5. 2. Further security improvements 3. Description of communication processing flow 3-1. Flowchart 3-2. Example of signal pattern Summary

<1. Description of Communication System Related to the Present Invention>
[1-1. Overview of communication method]
First, an outline of a communication method related to the present invention will be described with reference to FIG. Note that the communication method described in this section communicates between two information processing modules of an information processing apparatus by superimposing a data signal on a clock signal, and the second information processing module does not require a PLL circuit. It is intended to realize directed communication.

  FIG. 1 is a schematic diagram showing an example of an information processing apparatus to which a communication method related to the present invention can be applied. FIG. 1 shows a portable terminal 400 as an example of an information processing apparatus.

  Referring to FIG. 1, the mobile terminal 400 mainly includes a display unit 12, a connection unit 16, and an operation unit 18. In addition, the display unit 12 is provided with an imaging unit 402 and operation switches 404.

  The display unit 12 of the portable terminal 400 has a screen (not shown) such as a liquid crystal display. For example, an arbitrary image transmitted from the operation unit 18 to the display unit 12 is displayed on the screen of the display unit 12.

  The imaging unit 402 provided in the display unit 12 provides a camera function for shooting a subject. The operation switch 404 is used as, for example, a shutter switch when photographing an object using the imaging unit 402. The operation switch 404 may be used for switching to the manner mode, for example. Here, for example, when the user operates the operation switch 404, an operation signal is transmitted from the display unit 12 to the operation unit 18. Then, an imaging start command is output from the operation unit 18 to the imaging unit 402 of the display unit 12, and subject imaging processing by the imaging unit 402 is executed. Thereafter, image data captured by the imaging unit 402 is transmitted from the display unit 12 to the operation unit 18.

  That is, in an electronic device such as the portable terminal 400, bidirectional data transmission is performed between the operation unit 18 (first information processing module) and the display unit 12 (second information processing module). Here, for example, if the movable range of the connection portion 16 that connects two information processing modules is expanded, the risk of damage to the signal line due to the movement increases. Therefore, in order to achieve both the freedom of the movable member and the reliability of the signal line, a serial transmission method can be adopted as a communication method between the two information processing modules.

[1-2. Configuration for serial transmission system]
The configuration of the apparatus for the serial transmission method will be described with reference to FIGS. FIG. 2 is an explanatory diagram showing the overall configuration of the mobile terminal 400. FIG. 3 is an explanatory diagram showing a more detailed configuration for realizing bidirectional communication among various functions of the mobile terminal 400.

(Overall functional configuration)
Referring to FIG. 2, the display unit 12 of the mobile terminal 400 includes a liquid crystal unit 14, an imaging unit 402, an operation switch 404, and a serializer / deserializer 408 (SER / DES). The operation unit 18 of the portable terminal 400 is provided with a baseband processor 19 and a serializer / deserializer 406 (SER / DES). In the following description, the serializer / deserializer 406 provided in the operation unit 18 may be referred to as SER / DES (M). Further, the serializer / deserializer 408 provided in the display unit 12 may be referred to as SER / DES (D).

  First, the flow of signals from the operation unit 18 toward the display unit 12 will be described. A parallel signal of image data displayed on the liquid crystal unit 14 is generated by the baseband processor 19. The parallel signal generated by the baseband processor 19 is converted into a serial signal by the serializer / deserializer 406. The signal serialized by the serializer / deserializer 408 is input to a serializer / deserializer 408 provided in the display unit 12 via a serial signal line passing through the connection unit 16. The serializer / deserializer 408 converts the serial signal input via the serial signal line into a parallel signal and inputs the parallel signal to the liquid crystal unit 14.

  Next, the flow of signals from the display unit 12 toward the operation unit 18 will be described. As described above, examples of the signal from the display unit 12 to the operation unit 18 include a signal of image data captured by the imaging unit 402 and an operation signal generated by the operation switch 404. Here, as an example, a case where a signal of image data captured by the imaging unit 402 is transmitted will be described. The parallel signal output from the imaging unit 402 is converted into a serial signal by the serializer / deserializer 408 and input to the serializer / deserializer 406 of the operation unit 18 via a serial transmission line passing through the connection unit 16. The serializer / deserializer 406 converts the serial signal input via the serial signal line into a parallel signal and inputs the parallel signal to the baseband processor 19.

  With the above-described flow, the mobile terminal 400 realizes bidirectional data transmission between the display unit 12 and the operation unit 18. Hereinafter, the functional configuration of the serializers / deserializers 406 and 408 for realizing such bidirectional communication will be described in more detail.

(Details of functional configuration)
Referring to FIG. 3, a functional configuration of the mobile terminal 400 centering on the serializer / deserializer 406 and 408 is shown. In addition, the portable terminal 400 employs a form in which a signal is transmitted by being superimposed on a DC power source. Of course, the application range of the technology described in this specification is not limited to an example in which a signal is transmitted by being superimposed on a DC power source.

  As described above, the mobile terminal 400 includes the serializer / deserializer 406 (SER / DES (M)) and the serializer / deserializer 408 (SER / DES (D)). The serializer / deserializers 406 and 408 are connected by a single signal line (for example, a coaxial cable or the like). This signal line is also used as a power line for supplying DC power from the operation unit 18 to the display unit 12. In the following description, SER / DES (M) may be simply expressed as (M) and SER / DES (D) may be simply expressed as (D).

  As illustrated in FIG. 3, the serializer / deserializer 406 (M) includes an encoder 412, a driver 414, a combiner / distributor 416, a superimposing unit 418, a receiver 420, and a decoder 422. The serializer / deserializer 408 (D) includes a separator 432, a combiner / distributor 434, a receiver 436, a clock detector 438, a decoder 440, a bandpass filter 442 (BPF), an encoder 444, and a driver 446. Have

  First, processing for transmitting data (TX DATA1) from the serializer / deserializer 406 (M) to the serializer / deserializer 408 (D) will be described.

  As illustrated in FIG. 3, transmission data (TX DATA1) and a clock signal (TX CLK1) are input to the serializer / deserializer 406 (M). It is assumed that the transmission data (TX DATA1) is serialized when it is input to the encoder 412. The clock signal (TX CLK1) is input to the encoder 412 and the decoder 422. When transmission data (TX DATA1) and a clock signal (TX CLK1) are input, the encoder 412 first encodes transmission data (TX DATA1) by a predetermined modulation method such as ASK (Amplitude Shift Keying). Convert to signal. Then, the encoder 412 superimposes the data signal on the clock signal (TX CLK1). The data signal may be, for example, a signal obtained by encoding transmission data using an AMI (Alternate Mark Inversion) code applying amplitude modulation.

  The clock signal on which the data signal is superimposed by the encoder 412 is input to the combiner / distributor 416 via the driver 414. The combiner / distributor 416 distributes the signal line leading to the encoder 412 and the signal line leading to the decoder 422 in order to realize bidirectional communication. At the time of data transmission, the combiner / distributor 416 inputs the input signal to the superimposing unit 418.

  In the superimposing unit 418, the DC power is superimposed on the clock signal, and a superimposed signal is generated. Then, the superimposed signal generated by the superimposing unit 418 is input to the separation unit 432 of the serializer / deserializer 408 (D) via a coaxial cable. The separation unit 432 separates the input superimposed signal into a DC power source and a clock signal on which a data signal is superimposed. The DC power source separated by the separation unit 432 is supplied to the display unit 12.

  On the other hand, the signal separated by the separation unit 432 is input to the combiner / distributor 434. The combiner / distributor 434 is means for distributing the signal line leading to the decoder 440 and the signal line leading to the encoder 444 in order to realize bidirectional communication. In the case of data reception, the signal input to the combiner / distributor 434 is input to the clock detection unit 438 and the decoder 440 via the receiver 436. The clock detection unit 438 detects a clock from the input signal. At this time, the clock detection unit 438 can detect the clock component based on, for example, the period of polarity inversion of the amplitude of the clock signal.

  The clock detected by the clock detection unit 438 is supplied to, for example, the liquid crystal unit 14 and input to the decoder 440. The decoder 440 uses the clock (RX CLK2) input from the clock detection unit 438, performs decoding processing on the input signal, and generates reception data (RX DATA2). The reception data (RX DATA2) thus generated by the decoder 440 is input to the liquid crystal unit 14.

  The processing for transmitting data (TX DATA1) from the serializer / deserializer 406 (M) to the serializer / deserializer 408 (D) has been described above. Next, processing for transmitting data (TX DATA2) from the serializer / deserializer 408 (D) to the serializer / deserializer 406 (M) will be described.

(SER / DES (D) → SER / DES (M))
As described above, in order to transmit data (TX DATA2) from the serializer / deserializer 408 (D) to the serializer / deserializer 406 (M), a clock is required on the serializer / deserializer 408 (D) side. However, if a PLL (Phase-Locked Loop) circuit is provided on the serializer / deserializer 408 (D) side in order to generate a clock signal, power consumption increases.

  Therefore, a contrivance is made so that a clock signal is supplied from the serializer / deserializer 406 (M) to the serializer / deserializer 408 (D). For example, the serializer / deserializer 406 (M) continues to transmit the clock signal to the serializer / deserializer 408 (D) even in a time zone in which the serializer / deserializer 406 (M) does not transmit data. The serializer / deserializer 408 (D) transmits data by superimposing the data signal on the clock signal received from the serializer / deserializer 406 (M) when transmitting data. The clock signal transmitted from the serializer / deserializer 406 (M) is input to the clock detector 438 via the separator 432, the combiner / distributor 434, and the receiver 436. Therefore, the clock detection unit 438 detects a clock signal from the input signal and inputs the clock signal to the bandpass filter 442. Normally, the clock signal detected by the clock detection unit 438 contains a lot of jitter. Therefore, the jitter of the clock signal detected by the clock detection unit 438 is suppressed by the band pass filter 442.

  The clock signal whose jitter is suppressed by the band pass filter 442 is input to the encoder 444. Further, transmission data (TX DATA2) is input to the encoder 444. Then, the encoder 444 converts transmission data (TX DATA2) into an encoded data signal by a predetermined modulation method such as ASK. The data signal encoded by the encoder 444 is input to the combiner / distributor 434 through the driver 446 in accordance with the clock signal. The combiner / distributor 434 generates a superimposed signal by superimposing the data signal input from the encoder 444 on the clock signal transmitted from the serializer / deserializer 406 (M). Then, the superimposed signal is sent to the coaxial cable via the separation unit 432 and transmitted to the serializer / deserializer 406 (M).

  In the serializer / deserializer 406 (M), the superimposed signal transmitted through the coaxial cable is input to the decoder 422 via the superimposing unit 418, the combiner / distributor 416, and the receiver 420. When the code is amplitude-modulated, the decoder 422 decodes data based on the amplitude value of the input code. At this time, the decoder 422 decodes the data using the clock signal (TX CLK1) used for transmitting the transmission data (TX DATA1).

  Note that the clock used by the serializer / deserializer 408 (D) for data transmission is the transmission clock (TX CLK1) transmitted from the serializer / deserializer 406 (M). Therefore, the decoder 422 does not need to detect the clock from the input code. The data (RX DATA1) decoded by the decoder 422 and the clock (RX CLK1) are input to the baseband processor 19.

  The processing for transmitting data (TX DATA2) from the serializer / deserializer 408 (D) to the serializer / deserializer 406 (M) has been described above. In this way, data transmission from the serializer / deserializer 408 (D) to the serializer / deserializer 406 (M) is realized without using a PLL.

[1-3. Issues in serial transmission system]
In the serial transmission method described above, since one signal line is shared in two-way communication, a mechanism for avoiding signal collision or a mechanism for detecting a signal collision and enabling signal retransmission is required. Thus, for example, a time division transmission (TDD) method may be adopted to divide the time slots into forward transmission and reverse transmission. However, when the time division transmission method is adopted, the definition of the time slot is known to an unauthorized user or a third party (hereinafter collectively referred to as an unauthorized user including a malicious third party). The content of communication data may be easily read. In addition, if the data is to be encrypted in order to keep the communication data confidential, additional encryption / decryption processing is required, resulting in disadvantages such as an increase in circuit scale and power consumption. On the other hand, according to the new transmission method according to the embodiment of the present invention described in detail in the next section, it is possible to improve the security of communication between the information processing modules.

<2. Description of Information Processing Apparatus According to One Embodiment>
[2-1. Overview of information processing equipment]
First, an outline of an information processing apparatus according to an embodiment of the present invention will be described with reference to FIG. FIG. 4 is a schematic diagram schematically illustrating the information processing apparatus 100 according to an embodiment. Referring to FIG. 4, two examples (information processing apparatuses 100a and 100b) of the information processing apparatus 100 are shown.

  The information processing device 100a is a terminal device similar to the mobile phone 400 described with reference to FIG. The information processing apparatus 100a includes an operation unit 102a and a display unit 104a that are connected to each other by a connection unit 103a (see FIG. 4A). In the information processing apparatus 100a, the operation unit 102a and the display unit 104a each have a semiconductor chip (not shown) as a processor inside, and a serial transmission method via a signal line (not shown) provided in the connection unit 103a. Two-way communication with.

  On the other hand, the information processing apparatus 100b is a recording / reproducing apparatus including a recording module 102b and a display module 104b that are configured separately from each other and connected to each other through a signal line 103b (see FIG. 4B). In the information processing apparatus 100b, each of the recording module 102b and the display module 104b has a semiconductor chip (not shown) as a processor therein, and performs bidirectional communication by a serial transmission method via the signal line 103b.

  Note that the information processing apparatus 100 according to the present embodiment is not limited to the terminal device or the recording / reproducing apparatus illustrated in FIG. The information processing apparatus 100 may be an arbitrary apparatus that performs two-way communication between two information processing modules using a serial transmission method. Further, in this specification, when there is no need to distinguish between the information processing apparatus 100a and the information processing apparatus 100b, they are collectively referred to as the information processing apparatus 100. Similarly, in this specification, the operation unit 102a and the recording module 102b illustrated in FIG. 4 are collectively referred to as the first information processing module 102, and the display unit 104a and the display module 104b are collectively referred to as the second information processing module 104.

[2-2. Configuration of information processing apparatus]
Next, an example of the configuration of the information processing apparatus 100 will be described with reference to FIG. FIG. 5 is an explanatory diagram showing a more detailed configuration for realizing bidirectional communication among various functions of the information processing apparatus 100.

  Referring to FIG. 5, the configuration of the information processing apparatus 100 is shown, centering on the serializer / deserializer 106 included in the first information processing module 102 and the serializer / deserializer 108 included in the second information processing module 104.

  The serializer / deserializer 106 and 108 are connected to each other by a signal line (for example, a coaxial cable or the like). This signal line can also be used as a power supply line for supplying DC power from the first information processing module 102 to the second information processing module 104. Further, the serializer / deserializers 106 and 108 may be further connected by a ground line (GND) that supplies a reference voltage when measuring the voltage of the signal line.

  As illustrated in FIG. 5, the serializer / deserializer 106 (M) includes an encoder 112, a driver 114, a combiner / distributor 116, a superimposing unit 118, a receiver 120, and a decoder 122. The encoder 112 includes a transmission control unit 128. Furthermore, the decoder 122 includes a delivery confirmation unit 124 and a collision detection unit 126. On the other hand, the serializer / deserializer 108 (D) includes a separator 132, a combiner / distributor 134, a receiver 136, a clock detector 138, a decoder 140, a bandpass filter 142, an encoder 144, and a driver 146. In addition, the encoder 144 includes a transmission control unit 152. Further, the decoder 140 includes a delivery confirmation unit 148 and a collision detection unit 150.

  One of the main differences between the information processing apparatus 100 according to the present embodiment and the mobile phone 400 shown in FIG. 3 is that the configuration of the first information processing module 102 includes a delivery confirmation unit 124, a collision detection unit. 126 and a transmission control unit 128 are added. Similarly, a delivery confirmation unit 148, a collision detection unit 150, and a transmission control unit 152 are added to the configuration of the second information processing module 104. Each added processing block may be configured independently of the encoder 112 or the decoder 122, or the encoder 144 or the decoder 140, for example. Next, the flow of signals transmitted and received between the first information processing module 102 and the second information processing module 104 in the configuration of the information processing apparatus 100 will be described.

[2-2-1. Signal flow (SER / DES (M) → SER / DES (D))]
Similar to the example of FIG. 3, the transmission data (TX DATA1) and the clock signal (TX CLK1) are input to the serializer / deserializer 106 (M). It is assumed that the transmission data (TX DATA1) is serialized when it is input to the encoder 112. The clock signal (TX CLK1) is input to the encoder 112 and the decoder 122. When the transmission data (TX DATA1) and the clock signal (TX CLK1) are input, the encoder 112 first converts the transmission data (TX DATA1) into a data signal modulated to a special amplitude value which will be described in more detail later. To do. Then, the encoder 112 superimposes the data signal on the rising edge of the clock signal (TX CLK1).

  The clock signal on which the data signal is superimposed by the encoder 112 is input to the combiner / distributor 116 via the driver 114. The combiner / distributor 116 distributes the signal line leading to the encoder 112 and the signal line leading to the decoder 122 in order to realize bidirectional communication. At the time of data transmission, the combiner / distributor 116 inputs the input signal to the superimposing unit 118.

  In this embodiment, the encoder 112 superimposes the data signal on the clock signal, and then notifies the collision detection unit 126 of the decoder 122 that the data signal has been output. Then, the collision detection unit 126 monitors a signal returned from the second information processing module 104, and detects a collision when a signal collision occurs. The collision detection process performed by the collision detection unit 126 will be further described later.

  The superimposing unit 118 superimposes a DC power source on the clock signal to generate a superimposed signal. Then, the superimposed signal generated by the superimposing unit 118 is input to the separation unit 132 of the serializer / deserializer 108 (D) via, for example, a coaxial cable. The separation unit 132 separates the input superimposed signal into a DC power source and a clock signal on which a data signal is superimposed. The DC power source separated by the separation unit 132 is supplied to the second information processing module 104.

  On the other hand, the signal separated by the separation unit 132 is input to the combiner / distributor 134. The synthesizer / distributor 134 is means for distributing the signal line leading to the decoder 140 and the signal line leading to the encoder 144 in order to realize bidirectional communication. In the case of data reception, the signal input to the combiner / distributor 134 is input to the clock detector 138 and the decoder 140 via the receiver 136. The clock detection unit 138 detects a clock from the input signal. At this time, the clock detection unit 138 can detect the clock component, for example, based on the period of the amplitude value polarity inversion when the DC component of the signal is removed.

  The clock detected by the clock detection unit 138 is input to the decoder 140 and the band pass filter 142. The decoder 140 performs a decoding process on the input signal in accordance with the rising edge of the clock (RX CLK2) from the clock detection unit 138 to generate reception data (RX DATA2). The reception data (RX DATA2) generated by the decoder 140 is input to a control unit (not shown) of the second information processing module 104. Also, the delivery confirmation unit 148 of the decoder 140 matches the delivery confirmation signal corresponding to the signal value of the reception data (RX DATA2) with the falling edge of the clock (RX CLK2) from the clock detection unit 138 via the encoder 144. To send. The delivery confirmation signal transmitted by the delivery confirmation unit 148 will be further described later.

  The processing for transmitting data (TX DATA1) from the serializer / deserializer 106 (M) to the serializer / deserializer 108 (D) has been described above. Next, processing for transmitting data (TX DATA2) from the serializer / deserializer 108 (D) to the serializer / deserializer 106 (M) will be described.

[2-2-2. Signal flow (SER / DES (D) → SER / DES (M))]
Similar to the example of FIG. 3, the serializer / deserializer 106 (M) continues to transmit the clock signal to the serializer / deserializer 108 (D) even when it does not transmit data. Then, when transmitting data, the serializer / deserializer 108 (D) transmits data by superimposing the data signal on the clock signal received from the serializer / deserializer 106 (M). The clock signal transmitted from the serializer / deserializer 106 (M) is input to the clock detector 138 via the separator 132, the combiner / distributor 134, and the receiver 136. The clock detection unit 138 detects a clock signal from the input signal and inputs it to the bandpass filter 142 in order to suppress jitter.

  The clock signal whose jitter is suppressed by the band pass filter 142 is input to the encoder 144. In addition, transmission data (TX DATA2) is input to the encoder 144. Then, the encoder 144 converts the transmission data (TX DATA2) into a data signal modulated to a special amplitude value that will be described in more detail later. The data signal encoded by the encoder 144 is input to the combiner / distributor 134 via the driver 146 in accordance with the rising edge of the clock signal. The synthesizer / distributor 134 superimposes the data signal input from the encoder 144 on the rising edge of the clock signal transmitted from the serializer / deserializer 106 (M) to generate a superimposed signal. Then, the superimposed signal is sent to the coaxial cable via the separation unit 132 and transmitted to the serializer / deserializer 106 (M).

  Furthermore, in this embodiment, the encoder 144 superimposes the data signal on the clock signal, and then notifies the collision detection unit 150 of the decoder 140 that the data signal has been output. Then, the collision detection unit 150 monitors the signal returned from the first information processing module 102 and detects the collision when a signal collision occurs. The collision detection process performed by the collision detection unit 150 will be further described later.

  In the serializer / deserializer 106 (M), the superimposed signal transmitted through the coaxial cable is input to the decoder 122 via the superimposing unit 118, the combiner / distributor 116, and the receiver 120. The decoder 122 decodes data based on the amplitude value of the input code. At this time, the decoder 122 decodes the data using the clock signal (TX CLK1) used for transmission of the transmission data (TX DATA1).

  Note that the clock used by the serializer / deserializer 108 (D) for data transmission is the transmission clock (TX CLK1) transmitted from the serializer / deserializer 106 (M). Therefore, the decoder 122 does not need to detect the clock from the input code. The data (RX DATA1) decoded by the decoder 122 and the clock (RX CLK1) are input to a control unit (not shown) of the first information processing module 102 or the like. Further, the delivery confirmation unit 124 of the decoder 122 transmits a delivery confirmation signal corresponding to the signal value of the reception data (RX DATA1) through the encoder 112 in accordance with the falling edge of the clock (TX CLK1). The delivery confirmation signal transmitted by the delivery confirmation unit 124 will be further described later.

  The processing for transmitting data (TX DATA2) from the serializer / deserializer 108 (D) to the serializer / deserializer 106 (M) has been described above. Next, in this embodiment, the amplitude value of the data signal and the delivery confirmation signal superimposed on the clock signal transmitted / received between the serializer / deserializer 106 (M) and the serializer / deserializer 108 (D) will be described.

[2-3. Amplitude values of data signal and delivery confirmation signal]
FIG. 6 is an explanatory diagram for explaining an example of amplitude values of the data signal and the delivery confirmation signal.

  Referring to FIG. 6, an example of an amplitude value for each signal value when the reference voltage (DC component voltage) is 5.0 V is shown for three types of signals, a clock signal, a data signal, and an acknowledgment signal. ing. FIG. 6 also shows whether each signal is superimposed on the rising edge or falling edge of the clock signal.

  First, a signal value is not specified for the clock signal. The clock signal becomes 6.0V, which is 1.0V higher than the reference voltage at the rising edge, and becomes 4.0V which is 1.0V lower than the reference voltage at the falling edge. The amplitude value of the clock signal here is an amplitude value in a state where the data signal is not superimposed.

  Next, the data signal is superimposed on the rising edge of the clock signal for both “1” and “0” signal values. At this time, the amplitude value of the data signal with the signal value “1” is set to 6.2 V by further superimposing the shift value 0.2 V on the amplitude value 6.0 V of the rising edge of the clock signal. On the other hand, the amplitude value of the data signal with the signal value “0” is superimposed on the amplitude value 6.0V of the rising edge of the clock signal and a shift value −0.2V, which is inverted from positive to negative, to be 5.8V. The data signal superimposed on such a clock signal is compared with an amplitude threshold given in advance in a comparator provided in the decoder 122 of the first information processing module 102 or the decoder 140 of the second information processing module 104. And decoded into each signal value.

  On the other hand, the delivery confirmation signal is superimposed on the falling edge of the clock signal in the case of the delivery confirmation signal for any signal value of “1” and “0”. At this time, the amplitude value of the delivery confirmation signal with respect to the data signal having the signal value “1” is superimposed on the amplitude value 4.0V of the falling edge of the clock signal by superimposing a positive / negative inverted shift value −0.2V to obtain 3.8V. And Similarly, the amplitude value of the delivery confirmation signal for the data signal having the signal value “0” is set to 4.2 V by superimposing the shift value 0.2 V on the amplitude value 4.0 V of the falling edge of the clock signal. Transmission of such a delivery confirmation signal (amplitude value control) is performed via the encoder 112 or 144 by the delivery confirmation unit 124 or 148 of any information processing module that has received the data signal, for example. Thus, the information processing module that has transmitted the data signal can know that the transmitted signal value has been correctly delivered to the counterpart module. In addition, even when a signal value of “1” or “0” is transmitted as a data signal, the fluctuation of the voltage of the signal line due to the data signal is canceled by the delivery confirmation signal (the average of the amplitude values is changed to the reference voltage). Therefore, fluctuation of the DC component of the signal is prevented.

[2-4. Collision detection process]
Even when the data signal is transmitted with the amplitude value shown in FIG. 6 superimposed on the clock signal, if the first information processing module 102 and the second information processing module 104 transmit signals simultaneously, the rising edge of the clock signal is transmitted. In this case, a signal collision occurs and communication fails. Therefore, in the present embodiment, signal collision is detected by the collision detection unit 126 of the first information processing module 102 and the collision detection unit 150 of the second information processing module 104.

  FIG. 7 is an explanatory diagram for explaining the collision detection processing by the collision detection unit 126 of the first information processing module 102 and the collision detection unit 150 of the second information processing module 104. Here, the description will be made on the assumption that the data signal superimposed on the clock signal takes the amplitude value described with reference to FIG.

  Referring to FIG. 7A, the amplitude value of a signal when a signal collision occurs is shown for each combination of signal values of a data signal transmitted from each module. For example, when the signal value “1” is transmitted simultaneously from both modules, the signal amplitude value (signal line voltage) is shifted to the voltage value 6.0 V of the clock signal by two modules (0.2 V). X2 = 0.4V) is added to obtain 6.4V. For example, when a signal value “1” is transmitted from one module and a signal value “0” is transmitted from the other module, the amplitude value of the signal is changed to a voltage value 6.0 V of the clock signal and a shift value 0.2 V. -0.2V is added and it becomes 6.0V. Also, for example, when the signal value “0” is transmitted from both modules simultaneously, the amplitude value of the signal is shifted to the voltage value 6.0 V of the clock signal (−0.2 V × 2 = -0.4V) is added to 5.6V.

  That is, when a signal collision occurs, the amplitude value of the data signal when the collision does not occur is always different from 6.2V or 5.8V. Using this, the collision detection unit 126 of the first information processing module 102 and the collision detection unit 150 of the second information processing module 104 make a determination using a comparator that compares the amplitude value of the received signal with a predetermined threshold value. Then, the occurrence of signal collision is detected.

  Further, when the collision detection unit 126 and the collision detection unit 150 detect the collision of the signals, the collision detection unit 126 and the collision detection unit 150 send a cancel signal having a voltage that cancels the fluctuation of the voltage of the signal line due to the collision through the encoder 112 or the encoder 144 to the next clock signal. Superimposed on the rising edge.

  Referring to FIG. 7B, the amplitude value of the cancel signal that cancels the voltage fluctuation caused by the signal collision is shown for each combination of the signal values of the data signal transmitted from each module. For example, when the signal value “1” is transmitted from both modules at the same time, the voltage fluctuation due to signal collision is 0.4 V, so the amplitude value of the cancel signal is 6.0 V−0.4 V = 5. .6V is required. Therefore, the voltage of the signal line is set to 5.6 V by transmitting a cancel signal in which the shift value −0.2 V is superimposed on the clock signal from both modules.

  Further, for example, when the signal value “0” is transmitted from both modules at the same time, the fluctuation of the voltage due to the collision of the signals is −0.4V, so the amplitude value of the cancel signal is set to 6.0V + 0.4V = It needs to be 6.4V. Therefore, the signal line voltage is set to 6.4V by transmitting a cancel signal in which the shift value + 0.2V is superimposed on the clock signal from both modules.

  For example, when a signal value “1” is transmitted from one module and a signal value “0” is transmitted from the other module, the voltage at the time of signal collision is the rising edge of the clock signal on which the data signal is not superimposed. Is equal to 6.0V. Therefore, the collision detection units 126 and 150 do not have to transmit a cancel signal. Instead, the collision detection units 126 and 150 are -0.2V when the signal value “1” is transmitted from the own module, and the signal value “0” is transmitted from the own module. May transmit a cancel signal of + 0.2V. Thereby, the amplitude values of the cancel signals from both modules cancel each other.

  By such collision detection by the collision detection units 126 and 150 and transmission of the cancel signal, even if the data signal of any signal value collides, the fluctuation of the voltage of the signal line due to the signal collision is canceled out. This prevents the DC component of the signal from fluctuating.

  When the collision detection units 126 and 150 detect a signal collision, the encoders 112 and 144 wait for a randomly determined time, respectively, and then superimpose the data signal that could not be normally transmitted due to the collision on the clock signal again. To do. This is a process generally referred to as random back-off, which prevents the retransmitted signals from colliding again.

  Further, by the collision detection processing described in this section, bidirectional communication is realized in the information processing apparatus 100 without adopting, for example, a time division transmission method. This eliminates the need to conceal the definition of the time slot of the time division transmission method, for example, in order to avoid a decrease in security.

[2-5. Further security improvements]
By providing the collision detection processing described in the previous section, two-way communication between the first information processing module 102 and the second information processing module 104 is possible. At this time, even if an unauthorized user monitors the voltage of the signal line, no one other than the sender and the receiver (that is, each module) can know which module the voltage is from. Therefore, it is difficult for an unauthorized user to interpret the signal contents if the signals from both modules are constantly transmitted. However, if data transmission / reception occurs only sporadically, or if data is transmitted from only one module, the risk of interpreting the data content remains. As a countermeasure against this, in the present embodiment, the security of inter-module communication of the information processing apparatus 100 is further improved by backoff processing at the time of non-collision and dummy data transmission processing described below.

[2-5-1. Non-collision back-off process]
First, the transmission control unit 128 of the first information processing module 102 and the transmission control unit 152 of the second information processing module 104 send continuous data signals for a predetermined time even when no collision of data signals is detected. It can be superimposed on the rising edge of the clock signal at intervals. In this specification, the process of transmitting such continuous data signals with a predetermined time interval is referred to as a back-off process at the time of non-collision. Accordingly, it becomes difficult for an unauthorized user to correctly recognize a group of data transmitted from one module and correctly assemble a series of data signals.

[2-5-2. Dummy data transmission process]
Furthermore, the transmission control units 128 and 152 transmit dummy data signals between data signal transmissions. As will be described later with reference to FIG. 11, the dummy data signal is superimposed on the rising edge of the clock signal at any time when there is no data signal to be transmitted. The amplitude value of the signal when the dummy data signal is superimposed is equal to one of the amplitude values when the normal data signal is superimposed on the clock signal (for example, 6.2 V or 5.8 V shown in FIG. 6). Shall. The dummy data signal may be, for example, a signal having a predetermined bit pattern defined in advance. In that case, a predetermined bit pattern defined in advance is stored in advance in a memory provided in each of the first information processing module 102 and the second information processing module 104. Then, the decoders 122 and 140 of each module compare the stored bit pattern with the bit pattern of the received signal and distinguish the dummy data signal from the normal data signal. The dummy data signal may be, for example, a signal (echo back signal) having the same bit pattern as the data signal received in the past. In that case, the dummy data signal can be distinguished from the normal data signal without storing a predefined bit pattern.

  Even if the transmission / reception of data occurs only sporadically by such back-off processing and / or dummy data transmission processing at the time of non-collision, the contents of communication data are kept confidential without concealing the communication procedure. It can be prevented from being learned. Note that if the transmission interval of the dummy data signal is narrowed, the possibility that the dummy data signal and the data signal or the dummy data signal collide with each other increases. Therefore, it is preferable that the dummy data signal is transmitted at a time interval that does not adversely affect normal communication due to signal collision.

<3. Explanation of communication processing flow>
Next, a flow of communication processing by the first information processing module 102 and the second information processing module 104 of the information processing apparatus 100 according to the present embodiment will be described.

[3-1. flowchart]
FIG. 8 is a flowchart illustrating an example of the flow of communication processing by the information processing apparatus 100 according to the present embodiment. Note that the flowchart of FIG. 8 can be applied to both the first information processing module 102 and the second information processing module 104 of the information processing apparatus 100. Here, the flowchart will be described with the first information processing module 102 as a main component.

  Referring to FIG. 8, first, the clock signal (TX CLK1) is supplied to the encoder 112 of the first information processing module 102, and the rising edge of the clock signal is detected (S102).

  Next, the encoder 112 determines whether or not there is transmission data (TX DATA1) (S104). If the transmission data is supplied to the encoder 112, the process proceeds to S106. On the other hand, if transmission data is not supplied, the process proceeds to S116.

  In S104, when transmission data is supplied to the encoder 112, it is further determined whether or not the back-off is currently waiting (S106). Here, the back-off may include a back-off when the collision detection unit 126 detects a signal collision and a back-off at the time of non-collision by the transmission control unit 128. If it is currently waiting for backoff, the process proceeds to S116. On the other hand, if not waiting for backoff, the process proceeds to S108.

  S108 to S114 are processes on the signal transmission side. In S106, if not waiting for back-off, the data signal superimposed on the rising edge of the clock signal from the encoder 112 via the driver 114, the combiner / distributor 116, and the superimposing unit 118 is the second information processing module 104. (S108).

  Thereafter, the collision detection unit 126 of the decoder 122 measures the voltage of the falling edge of the clock signal and determines whether or not a delivery confirmation signal has been received (S110). If a delivery confirmation signal is received here, the process proceeds to S114. On the other hand, if the delivery confirmation signal has not been received, the process proceeds to S112.

  For example, when signals are transmitted simultaneously from two information processing modules, signal collision occurs. In that case, the collision detection unit 126 measures the voltage value shown in FIG. 6A, for example, and detects the occurrence of the collision. Then, the collision detection unit 126 superimposes a cancel signal for canceling voltage fluctuation due to signal collision on the next rising edge of the clock signal (S112).

  Next, the transmission control unit 128 determines a back-off time for waiting for transmission of the data signal (S114). Here, the back-off time can include both back-off at the time of signal collision and back-off at the time of non-collision. Then, the process returns to S102.

  On the other hand, when transmission data is not supplied to the encoder 112 in S104, or when waiting for backoff in S106, the signal reception processing in S116 to S120 is performed.

  First, in S116, the voltage at the rising edge of the clock signal is measured by the decoder 122 (S116). Then, it is determined whether or not received data (RX DATA1) exists (S118). If the received data does not exist here, the process returns to S102. On the other hand, if the received data exists, the process proceeds to S120.

  In S120, the reception data is demodulated by the decoder 122, and a delivery confirmation signal having an amplitude corresponding to the signal value of the reception data is transmitted by the delivery confirmation unit 124 to the encoder 112, the driver 114, the synthesizer / distributor 116, and the superimposition unit 118. Sent through. Thereafter, the process returns to S102.

  Note that the dummy data transmission process described in the previous section is performed instead of the signal reception process of S116 to S120 at a time interval that does not adversely affect normal communication due to the collision of the signals. Communication security between modules is improved.

[3-2. Example of signal pattern]
9 to 11 are explanatory diagrams illustrating an example of signal patterns transmitted and received between the first information processing module 102 and the second information processing module 104 in the present embodiment. In each figure, the transition of the amplitude value of the signal for each edge is indicated by a solid line along the time axis, with the reference voltage of 5.0V as the center and the edge interval of the clock signal as one unit of time T. Of these, the edges T = 1, 3, 5,... Are the rising edges of the clock signal, and the edges T = 2, 4, 6,... Are the falling edges of the clock signal.

  First, referring to FIG. 9, only the clock signal is supplied from the first information processing module 102 to the second information processing module 104 during a period of T = 1 to 4. The amplitude value of the rising edge of the clock signal is 6.0V, and the amplitude value of the falling edge is 4.0V.

  Next, the data signal (TX DATA1) is superimposed by the first information processing module 102 on the rising edge of the clock signal at T = 5, 7, and 9. The signal values here are “1”, “0”, and “1”. The amplitude value of the signal value “1” is 6.2V, and the amplitude value of the signal value “0” is 5.8V. On the other hand, the delivery confirmation signal (ACK) is superimposed by the second information processing module 104 on the falling edges of the clock signals of T = 6, 8, and 10. The amplitude value of the delivery confirmation signal with respect to the signal value “1” of the data signal is 3.8 V, and the amplitude value of the delivery confirmation signal with respect to the signal value “0” of the data signal is 4.2 V.

  Next, only the clock signal is supplied from the first information processing module 102 to the second information processing module 104 again during a period of T = 11 to 14.

  Next, the data signal (TX DATA2) is superimposed by the second information processing module 104 on the rising edge of the clock signal at T = 15, 17, and 19. The signal values here are “0”, “1”, and “0”. The amplitude value of the signal value “1” is 6.2V, and the amplitude value of the signal value “0” is 5.8V. On the other hand, the delivery confirmation signal (ACK) is superimposed by the first information processing module 102 on the falling edges of the clock signals of T = 16, 18, and 20. The amplitude value of the delivery confirmation signal with respect to the signal value “1” of the data signal is 3.8 V, and the amplitude value of the delivery confirmation signal with respect to the signal value “0” of the data signal is 4.2 V.

  Since the fluctuation of the DC component of the signal voltage is canceled by such control of the amplitude value, the power supply line that supplies power from the first information processing module 102 to the second information processing module 104 is used as the signal line. Becomes easy. Even if an unauthorized user monitors the voltage of a signal line, it is difficult to interpret the content of the signal because it cannot know which module is transmitting the signal.

  Next, referring to FIG. 10, an example of a signal pattern when a signal collision occurs is shown.

  First, the data signal (TX DATA1) is superimposed on the rising edge of the clock signal of T = 1, 3 by the first information processing module 102. On the other hand, a delivery confirmation signal (ACK) is superimposed by the second information processing module 104 on the falling edge of the clock signal of T = 2, 4. Thereafter, the data signal from the first information processing module 102 and the data signal from the second information processing module 104 are simultaneously superimposed on the rising edge of T = 5. That is, a signal collision occurs at T = 5, and the voltage of the signal line is 6.4V. Therefore, at the falling edge of T = 6, no acknowledgment signal is transmitted from either module, and the voltage of the signal line remains 4.0 V, which is the falling edge of the clock signal. Then, the cancel signal is superimposed on the rising edge of T = 7 by the first information processing module 102 and the second information processing module 104 that have detected the signal collision. In this case, the amplitude value of the clock signal on which the cancel signal is superimposed is 5.6V.

  Thereafter, the first information processing module 102 and the second information processing module 104 perform random backoff in order to avoid collision of signals to be retransmitted. For example, in the example of FIG. 10, the first information processing module 102 waits for signal transmission during T = 9-12. On the other hand, the second information processing module 104 stands by for signal transmission during T = 9-16.

  Then, the data signal is superimposed on the rising edge of the clock signal at T = 13 by the first information processing module 102 that has finished the back-off period. On the other hand, the delivery confirmation signal is superimposed by the second information processing module 104 on the falling edge of the clock signal of T = 14. Further, the data signal is superimposed on the rising edge of the clock signal of T = 17 by the second information processing module 104 whose back-off period has ended with a delay. On the other hand, the delivery confirmation signal is superimposed from the first information processing module 102 on the falling edge of the clock signal of T = 18.

  Next, referring to FIG. 11, an example of a signal pattern related to dummy data signal transmission processing is shown. Here, a case where only the transmission control unit 128 of the first information processing module 102 executes the dummy data transmission function will be described as an example.

  First, the data signal (TX DATA1) is superimposed on the rising edge of the clock signal of T = 1, 3 by the first information processing module 102. The signal values here are “1” and “1”. On the other hand, a delivery confirmation signal (ACK) is superimposed by the second information processing module 104 on the falling edge of the clock signal of T = 2, 4.

  Next, only the clock signal is supplied from the first information processing module 102 to the second information processing module 104 during a period of T = 5 to 8.

  Next, the data signal (TX DATA2) is superimposed by the second information processing module 104 on the rising edge of the clock signal at T = 9. The signal value here is “1”. On the other hand, a delivery confirmation signal (ACK) is superimposed by the first information processing module 102 on the falling edge of the clock signal of T = 10. Further, a dummy data signal is superimposed by the first information processing module 102 on the rising edge of the clock signal at T = 11. Here, as the dummy data signal, a signal having the same bit pattern as the data signal received immediately before (that is, an echo back of the signal value “1”) is used. On the other hand, the delivery confirmation signal (ACK) is superimposed by the second information processing module 104 on the falling edge of the clock signal of T = 12. At this time, the second information processing module 104 can identify that the received signal is a dummy data signal by comparing the bit pattern of the received signal with the bit pattern of the signal transmitted immediately before.

  Thereafter, only the clock signal is supplied from the first information processing module 102 to the second information processing module 104 again during a period of T = 13 to 16.

  In such a signal pattern, it is assumed that an unauthorized user who knows the definition of the amplitude value of the amplitude modulation according to the present embodiment shown in FIG. 6 reads the voltage of the signal line. In this case, the read signal pattern is “1”, “1”, “1”, “1”. However, it is difficult for an unauthorized user to know from which module each signal value of the signal pattern is transmitted, a data signal, or a dummy data signal mainly for the following two reasons. First, as a first reason, the voltage value of the signal line is the same for both the dummy data signal and the normal data signal. Therefore, for example, in FIG. 11, there is an appearance between a 2-bit data signal transmitted / received at T = 1 to 4 and a 1-bit data signal and 1-bit dummy data signal transmitted / received at T = 9-12. There is no difference in the voltage values above. As a second reason, for example, in FIG. 11, only the clock signal is transmitted at T = 5 to 8, but this may be due to back-off at the time of non-collision. That is, for example, even when the first information processing module 102 attempts to transmit a data signal having a signal pattern of signal values “1”, “1”, “1”, “1”, the same signal as in FIG. Patterns may be observed. As a result, an unauthorized user cannot accurately know the signal separation itself, and it becomes difficult to analyze the observed data using the signal separation as a hint.

  In FIGS. 9 to 11, for the sake of clarity of explanation, a simple signal pattern with a small number of bits has been described as an example. However, the number of bits and the signal pattern of a signal such as a data signal, an acknowledgment signal, a cancel signal, or a dummy data signal transmitted and received in the information processing apparatus 100 according to the present embodiment are not limited to this example, and any It may be a value.

<4. Summary>
So far, the information processing apparatus 100 according to an embodiment of the present disclosure has been described with reference to FIGS. 1 to 11.

  According to the information processing apparatus 100 according to the present embodiment, the data signal and the delivery confirmation signal are superimposed on the rising edge and the falling edge of the clock signal between the two information processing modules, respectively. Two-way communication is realized without adopting it. This eliminates the need to conceal the definition of the time slot of the time division transmission method, for example, in order to avoid a decrease in security.

  In addition, at any time when there is no data signal to be transmitted, the dummy data signal is superimposed on the rising edge of the clock signal by any information processing module. This makes it difficult for an unauthorized user to interpret the contents of communication data even when data transmission / reception occurs only sporadically.

  Even when no collision of data signals is detected, continuous data signals can be superimposed on the rising edge of the clock signal with a predetermined time interval. Thus, it becomes difficult for an unauthorized user to correctly recognize a group of data to be transmitted and correctly assemble a series of data signals.

  Further, in the information processing apparatus 100, power is supplied from the first information processing module 102 to the second information processing module 104 using a signal line that is common to the clock signal. The direct current component of the power is maintained at a constant value by the definition of the amplitude value shown as an example in the present embodiment. Further, since the power line and the signal line are shared, it is possible to prevent a security attack in which, for example, the current flowing in the signal line between the information processing modules is detected to know the signal content.

  Due to such improved communication security between information processing modules, the information processing apparatus 100 can be omitted from having additional circuits for encryption and decryption in the apparatus. Instead, for example, by providing an additional encryption unit in the information processing apparatus 100, communication security between information processing modules can be further strengthened.

  Needless to say, the features of the information processing apparatus 100 described in the present specification other than those described above also contribute to improving communication security between information processing modules in the information processing apparatus 100.

  Here, a series of processing by the information processing apparatus 100 described in this specification may be realized by hardware or may be realized by software. When a series of processes or a part thereof is executed by software, for example, a program constituting the software is stored in advance in the ROM, read into the RAM at the time of execution, and executed by the CPU.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  For example, the present invention can also be applied when the information processing apparatus 100 performs communication between three or more information processing modules.

  Further, for example, the communication process described with reference to FIG. 8 does not necessarily have to be executed in the order described in the flowchart. Each processing step may include processing executed in parallel or individually independently.

It is a schematic diagram which shows an example of the information processing apparatus with which the communication system relevant to this invention can be applied. It is explanatory drawing which shows the whole structure of the information processing apparatus shown in FIG. It is explanatory drawing which shows the more detailed structure of the principal part of the information processing apparatus shown in FIG. It is a mimetic diagram showing roughly about an information processor concerning one embodiment. It is explanatory drawing which shows the more detailed structure of the principal part of the information processing apparatus which concerns on one Embodiment. It is explanatory drawing for demonstrating the amplitude value of a data signal and a delivery confirmation signal. It is explanatory drawing for demonstrating the collision detection process which concerns on one Embodiment. It is a flowchart which shows an example of the flow of the communication process which concerns on one Embodiment. It is explanatory drawing which shows an example of the signal transmitted / received between information processing modules. It is explanatory drawing which shows the other example of the signal transmitted / received between information processing modules. It is explanatory drawing which shows the other example of the signal transmitted / received between information processing modules.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Information processing apparatus 102 1st information processing module 103 Connection part 104 2nd information processing module 106 Serializer / deserializer (M)
108 Serializer / Deserializer (D)
112 Encoder 114 Driver 116, 134 Synthesizer / Distributor 118 Superimposition unit 120, 136 Receiver 122, 140 Decoder 124, 148 Delivery confirmation unit 126, 150 Collision detection unit 128, 152 Transmission control unit 132 Separation unit 138 Clock detection unit 142 Band pass filter (BPF)

Claims (9)

A first information processing module and a second information processing module connected to each other by a signal line include:
The first information processing module;
Send a clock signal to the signal line, and superimpose a data signal on the rising edge of the clock signal;
In addition, a delivery confirmation signal for the data signal received via the signal line is superimposed on the falling edge of the clock signal,
The second information processing module;
Superimposing a data signal on the rising edge of the clock signal sent to the signal line by the first information processing module;
And superimposing a delivery confirmation signal for the data signal received via the signal line on the falling edge of the clock signal,
Information processing device.   2. The first information processing module or the second information processing module superimposes a dummy data signal on a rising edge of the clock signal at any time when there is no data signal to be transmitted. Information processing device.   The information processing apparatus according to claim 2, wherein the dummy data signal is a signal having the same bit pattern as a data signal received in the past.   The information processing apparatus according to claim 2, wherein the dummy data signal is a signal having a predetermined bit pattern defined in advance.   The first information processing module or the second information processing module can superimpose a continuous data signal on the rising edge of the clock signal with a predetermined time interval when no collision of data signals is detected. The information processing apparatus according to claim 1, wherein   The information processing apparatus according to claim 5, wherein the first information processing module supplies power to the second information processing module using the signal line.   When the first information processing module and the second information processing module detect a data signal collision, the first information processing module and the second information processing module receive a cancel signal having a voltage that cancels the fluctuation of the voltage of the signal line due to the collided data signal as the next clock. The information processing apparatus according to claim 6, wherein the information processing apparatus is superimposed on a rising edge of a signal.   The information processing apparatus according to claim 6, wherein the delivery confirmation signal has a voltage that cancels a variation in the voltage of the signal line due to the received data signal. In an information processing apparatus comprising a first information processing module and a second information processing module connected to each other via a signal line:
Superimposing a data signal on a rising edge of a clock signal by the first information processing module;
Sending the clock signal to the signal line by the first information processing module;
Receiving the data signal superimposed on the clock signal by the second information processing module;
Superimposing a delivery confirmation signal for the received data signal on the falling edge of the clock signal by the second information processing module;
Receiving the delivery confirmation signal by the first information processing module;
A data transmission method including:

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