JP2010039812A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer capable of shortening the starting time. <P>SOLUTION: When a cold/warm start signal indicating a cold start state like a power-on reset is given from a cold/warm start signal circuit 13, a reset signal is validated by a reset validating/invalidating selection circuit 14, and a flash ROM control register 21 is initialized, and chain data stored in a chain data area 20b is copied to the flash ROM control register 21. When the cold/warm start signal indicating a warm start state like a restart reset is given from the cold/warm start signal circuit 13, the reset signal is invalidated by the reset validating/invalidating selection circuit 14, and the flash ROM control register 21 is not initialized, and copying the chain data from the chain data area 20b is eliminated. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a microcomputer equipped with a nonvolatile memory such as a flash memory.

  The flash ROM built in the microcomputer (hereinafter sometimes referred to as “microcomputer”) is designed to keep individual performance constant at the time of product testing in order to minimize the production impact caused by variations in manufacturing characteristics. Adjustment data (hereinafter sometimes referred to as “tune data”) is stored in a storage unit configured by a nonvolatile memory (see, for example, Patent Document 1).

  When the flash ROM is reset, the flash ROM control circuit and the flash ROM control register in the flash ROM are initialized. When the reset is released, the tune data stored in the storage unit is copied to the flash ROM control register. Is done. In the microcomputer of the prior art, the tune data is copied from the storage unit to the flash ROM control register every time the reset is released.

  Further, for example, a PLL (Phase Locked Loop) circuit is built in the microcomputer as an oscillation circuit. When the PLL circuit is reset, the PLL control circuit and the PLL control register in the PLL circuit are initialized, and the PLL circuit enters a self-excited oscillation state. In order to obtain an oscillation frequency with a desired multiplication rate, it is necessary to change the multiplication rate setting of the PLL control register after reset is released.

JP 2006-48304 A

  In the above-described prior art microcomputer, the flash ROM control register of the flash ROM is initialized each time it is reset, and tune data is copied from the storage unit to the flash ROM control register. Therefore, even when tune data has already been copied to the flash ROM control register as in the case of resetting, the tune data is copied to the flash ROM control register. The time required for copying such tuned data depends on the amount of information and the transfer speed, and it is not a problem if only one copy time is considered. When reset is repeated, there is a problem that the overall time required for copying becomes long, and the time until the program is executed (hereinafter referred to as “microcomputer activation time”) becomes long.

  If the microcomputer has a built-in PLL circuit, changing the multiplication rate of the PLL control register after releasing the reset causes a transition from the current oscillation frequency to the oscillation frequency of the desired multiplication rate and waits for the PLL oscillation to stabilize. Time is needed. In the conventional microcomputer, the PLL control register is initialized every time it is reset, and the multiplication rate of the PLL control register is changed. Therefore, every time the reset is released, a PLL oscillation stabilization wait time is required.

  The PLL oscillation stabilization wait time is not a problem if only one time is considered. However, when the reset is frequently repeated, for example, in a non-defective product test, the overall time is long. Thus, for example, when the program is configured to be executed after the PLL oscillation stabilization wait time, there is a problem that the startup time of the microcomputer becomes long.

  An object of this invention is to provide the microcomputer which can shorten starting time.

  The microcomputer of the present invention is based on a storage unit that stores a predetermined program and adjustment data, a memory control register that stores the adjustment data provided from the storage unit, and the adjustment data that is stored in the memory control register. Memory means including a memory control circuit that controls the memory unit, and processing means that can execute the program stored in the memory unit of the memory unit, and the memory control register stores the memory control register. When a memory reset signal instructing erasure of the adjustment data stored in the memory control register is input in a memory erasure state where adjustment data needs to be erased, the adjustment stored in the memory control register Data is erased, and the adjustment data newly given from the storage unit is stored in the memory control register. The adjustment data stored in the memory control register is input when the memory reset signal is input when the adjustment data stored in the memory control register is not required to be erased. And a memory reset control means for controlling the storage means.

  According to the microcomputer of the present invention, the microcomputer includes the storage means, the processing means, and the memory reset control means. The storage means includes a storage unit, a memory control register, and a memory control circuit, and a predetermined program and adjustment data are stored in the storage unit. The program stored in the storage unit is executed by the processing means, and the adjustment data is given to the memory control register and stored. Based on the adjustment data stored in the memory control register, the memory control circuit controls the storage unit. When the memory reset signal is input when the memory erasing state is required, the storage unit erases the adjustment data stored in the memory control register and stores the adjustment data newly given from the storage unit in the memory control register. When a memory reset signal is input when the memory erasure is unnecessary, the memory reset control means controls the adjustment data stored in the memory control register. As a result, it is not necessary to provide adjustment data from the storage unit to the memory control register after inputting the memory reset signal when the memory erasing is unnecessary, and the time for supplying the adjustment data to the memory control register can be omitted. . Therefore, it is possible to reduce the startup time of the microcomputer, which is the time from when the memory reset signal is input until the processing means executes the program.

<Prerequisite technology>
Before describing the microcomputer of the present invention, a microcomputer (hereinafter sometimes referred to as a “microcomputer”) as a premise of the present invention will be described. FIG. 1 is a block diagram showing a configuration of a flash ROM 1 built in a microcomputer as a premise of the present invention. The flash ROM 1 includes a storage unit 2, a flash ROM control register 3, and a flash ROM control circuit 4. The storage unit 2 is configured by a nonvolatile memory. The flash ROM control register 3 is constituted by a volatile memory. The flash ROM control circuit 4 is connected to the storage unit 2 and the flash ROM control register 3.

  The storage unit 2 includes a user data area 2a and a tune data area 2b. In the tune data area 2b, adjustment data (hereinafter referred to as “tune data”) for keeping individual performances constant during product testing in order to minimize the influence on production due to characteristic variations in the manufacture of the flash ROM 1 May be stored). User data such as a program is stored in the user data area 2a.

  When the flash ROM 1 is reset and a reset signal is given, the flash ROM control register 3 and the flash ROM control circuit 4 are initialized. When the reset is released, the flash ROM 1 is stored in the tune data area 2b of the storage unit 2. Tune data is copied to the flash ROM control register 3. Therefore, it takes a tune data copy time after reset release until the flash ROM 1 is accessed.

  The reason why the tune data needs to be copied is that the flash ROM control register 3 is a volatile memory, and therefore it is necessary to store the tune data in the storage unit 2 which is a non-volatile memory. This is because a large number of signals cannot be connected to the flash ROM control circuit 4 at the same time while being stored in the tune data area 2b of No. 2, so that it is necessary to connect to the flash ROM control register 3.

  The tune data is not changed once it is set at the time of the test. If the power is supplied, the value of the flash ROM control register 3 is also retained. If it is just copied, there is no need to re-copy at the time of reset. However, if the tune data is copied when the reset is released as described above, the tune data is copied to the flash ROM control register 3 every time the reset is released. Become.

  If copying of the tune data in the flash ROM 1 is performed every reset as described above, the startup time of the microcomputer, specifically, the CPU startup time of the microcomputer becomes a problem. The time required for copying the tune data depends on the amount of information and the transfer speed. If only one copy time is considered, there is no problem. However, if the reset is frequently repeated, the entire time required for copying There is a problem that the time required for the microcomputer becomes longer and the startup time of the microcomputer becomes longer. In addition, in the non-defective product test, since the reset is frequently repeated, it takes a long time to add up each copy time over the entire test time. Considering shortening of test time while reducing product cost, copy time during testing becomes a problem.

  On the other hand, in the flash ROM 1 in the base technology, the flash ROM control circuit 4 enables copying of the tune data to the flash ROM control register 3 based on a copy valid / invalid selection signal given from the outside of the flash ROM 1. Select whether to disable or disable. If the copy valid / invalid selection signal is a valid signal, the tune data is copied to the flash ROM control register 3 by reset release. If the copy valid / invalid selection signal is a signal indicating invalidity, the tune data is not copied while the flash ROM control register 3 is initialized to the default value even if the reset is released.

  Thus, when the copy valid / invalid selection signal is a signal indicating invalidity, it is possible to omit the tune data copy time after reset release, but the flash ROM control register 3 is reset to the default value. Will remain initialized. If the flash ROM control register 3 is left at the default value, it is impossible to adjust the characteristic variation during the manufacture of the flash ROM 1 that is originally required, so that the original performance cannot be exhibited. Therefore, the copy valid / invalid selection signal can be used as means for omitting copying of the tune data at the time of reset release, but cannot be used for adjustment at the time of testing the flash ROM 1 and is actually used. Since the above is not used for purposes other than evaluation, there is no effect of shortening the test time.

  The prerequisite technology microcomputer incorporates a PLL circuit as an oscillation circuit. FIG. 2 is a block diagram showing the configuration of the PLL circuit 5 built in the microcomputer as a premise of the present invention. When a PLL (Phase Locked Loop) circuit 5 is reset and a reset signal is given, the PLL control register 6 and the PLL control circuit 7 are initialized to enter a self-excited oscillation state. After the reset is released, in order to obtain an oscillation frequency with a desired multiplication rate, for example, the multiplication rate setting of the PLL control register 6 is changed by software. In the PLL circuit 5 in the base technology, the PLL control register 6 is initialized every time it is reset, and the multiplication factor of the PLL control register 6 is changed. A PLL oscillation stabilization wait time, which is a wait time until transition and stable oscillation at an oscillation frequency with a desired multiplication factor, is necessary.

  However, in actual use, the multiplication factor of the PLL circuit 5 stored in the PLL control register 6 (hereinafter sometimes referred to as “PLL multiplication factor”) is used in one way so as to maximize the CPU processing capacity. However, the PLL multiplication rate is hardly changed in many ways. After setting a desired PLL multiplication ratio once, there are many usage methods in which operation and stop are repeated at the same PLL multiplication ratio. Therefore, the PLL does not need to be in the self-excited oscillation state at the time of reset release, and if the PLL circuit 5 has a desired oscillation frequency when the CPU in the microcomputer executes the program, the PLL oscillation stabilization wait time is not necessary. . In most product tests, the operation is confirmed with the same PLL multiplication rate. When resetting, the oscillation is stable at the desired PLL multiplication rate from the start of the CPU. No waiting time is required.

  The microcomputer of the base technology operates, for example, with a clock signal output from the PLL circuit 5 (hereinafter sometimes referred to as “PLL clock”) during high-speed CPU operation, and operates in a PLL self-oscillation state when reset is released. Configured to do. In this case, the CPU operates with the PLL clock even when the PLL oscillation frequency is changed by changing the PLL multiplication rate by software. Therefore, if the PLL multiplication rate is changed so that the CPU clock operates at the highest speed of the upper limit of the standard value, the CPU operates at a frequency outside the standard value when the PLL circuit 5 oscillates beyond a desired frequency at the time of frequency transition. There is a problem that it ends up.

  As described above, in the microcomputer of the base technology, even when the PLL multiplication rate is fixed for a certain application, the PLL control register 6 is initialized at every reset, so the PLL multiplication rate is changed after the CPU is started. Therefore, there is a problem that a PLL oscillation stabilization wait time is required. In the base technology microcomputer, when the clock is set so that the CPU operates at the highest speed when the PLL multiplication rate is changed after the CPU is started, the CPU clock is changed while the PLL oscillation frequency transitions from the low speed to the high speed. There is a problem that the oscillation frequency may exceed the standard.

  As for the latter problem, a software workaround, for example, when changing the PLL clock multiplication ratio after changing the CPU clock frequency division setting so that the frequency has a sufficient margin, or when changing the PLL clock multiplication ratio This can be dealt with by operating the CPU with a clock different from the PLL clock and switching to the PLL clock while the PLL oscillation is sufficiently stable. However, the problem is that there are more restrictions in the specifications for actual use.

  Regarding the former problem, the PLL oscillation stabilization waiting time is not a problem if only one time is considered, but if the reset is repeated frequently, the overall time becomes longer. For example, when the program is configured to be executed after a PLL oscillation stabilization waiting time, there is a problem that the startup time of the microcomputer becomes long. Further, for example, since the reset is frequently repeated in the non-defective product test, if the PLL oscillation stabilization wait time is totaled over the entire test time, it takes a long time. Considering shortening of test time while reducing product cost, PLL oscillation stabilization waiting time at the time of testing becomes a problem.

  In view of the above problems, the present invention employs the configurations of the following embodiments.

<First Embodiment>
FIG. 3 is a block diagram showing a configuration of the microcomputer 10 according to the first embodiment of the present invention. A microcomputer (hereinafter also referred to as “microcomputer”) 10 includes a central processing unit (abbreviated as CPU) 11, a flash ROM 12, a cold / warm start signal circuit 13, and a reset valid / invalid selection circuit 14. Configured. The flash ROM 12 corresponds to a storage unit, and the CPU 11 corresponds to a processing unit. The CPU 11, the cold / warm start signal circuit 13 and the reset valid / invalid selection circuit 14 function as memory reset control means. The cold / warm start signal circuit 13 corresponds to a memory cold / warm start signal circuit, and the reset valid / invalid selection circuit 14 corresponds to a memory reset valid / invalid selection circuit.

  The CPU 11 is connected to the flash ROM 12 and the cold / warm start signal circuit 13. The flash ROM 12 is connected to the CPU 11, a cold / warm start signal circuit 13 and a reset valid / invalid selection circuit 14. The cold / warm start signal circuit 13 is connected to the CPU 11, the flash ROM 12, and the reset valid / invalid selection circuit 14. The reset valid / invalid selection circuit 14 is connected to the flash ROM 12 and the cold / warm start signal circuit 13.

  The CPU 11 comprehensively controls the arithmetic processing and the flash ROM 12 and the cold / warm start signal circuit 13 constituting the microcomputer 10 according to a built-in control program. The flash ROM 12, the cold / warm start signal circuit 13, and the reset valid / invalid selection circuit 14 will be described later.

  FIG. 4 is a block diagram showing the configuration of the flash ROM 12. In FIG. 4, a cold / warm start signal circuit 13 and a reset valid / invalid selection circuit 14 are described together. The flash ROM 12 includes a storage unit 20, a flash ROM control register 21, and a flash ROM control circuit 22. The flash ROM control register 21 corresponds to a memory control register, and the flash ROM control circuit 22 corresponds to a memory control circuit.

  The flash ROM control circuit 22 is connected to the storage unit 20 and the flash ROM control register 21. The storage unit 20 is configured by a nonvolatile memory. The storage unit 20 includes a user data area 20a and a tune data area 20b. The user data area 20a stores a program processed by the microcomputer 10 and user-specific user data. The program stored in the user data area 20a is executed by the CPU 11. The tune data area 20b stores tune data, which is adjustment data for keeping individual performances constant at the time of product testing, in order to minimize the influence on production due to characteristic variations in the manufacture of the flash ROM 12.

  The flash ROM control register 21 is configured by a volatile memory. The flash ROM control register 21 stores setting values necessary for the flash ROM control circuit 22, such as tune data. The flash ROM control circuit 22 is adjusted based on the tune data stored in the flash ROM control register 21. By rewriting the contents of the flash ROM control register 21, the control method of the flash ROM 12 can be changed, the degree of control of the circuit can be changed according to manufacturing variations, and the characteristics of the flash ROM 12 can be controlled. In addition to the tune data, the flash ROM control register 21 may store data that is not used for controlling the flash ROM 12.

  The flash ROM control circuit 22 comprehensively controls the storage unit 20 and the flash ROM control register 21 constituting the flash ROM 12. The flash ROM control circuit 22 is supplied with the above-mentioned tune data from the flash ROM control register 21. The flash ROM control circuit 22 receives a reset signal from the outside of the microcomputer 10 and a cold / warm start signal from a cold / warm start signal circuit 13 described later. The reset signal corresponds to a memory reset signal that instructs erasure of tune data stored in the flash ROM control register 21.

  The cold / warm start signal circuit 13 constituting the microcomputer 10 is connected to the flash ROM control circuit 22 constituting the flash ROM 12 and the reset valid / invalid selection circuit 14 constituting the microcomputer 10. The cold / warm start signal circuit 13 outputs a cold / warm start signal that is a signal that can be identified as being in a cold start state or a warm start state. The cold / warm start signal corresponds to the memory cold / warm start signal.

  The cold start state is a state in which start-up is instructed or a state in which a start-up instruction is awaited when the setting of an electronic circuit such as the flash ROM 12 has not yet been set. It is initialized and activated by the first reset after power is supplied to (hereinafter referred to as “power-on reset”). The warm start state is a state in which start-up is instructed after completion of setting of the electronic circuit such as the flash ROM 12 and a state in which a start-up instruction is waited. For example, power is supplied. It means a state of being restarted after being reset again (hereinafter referred to as “restart / reset”). However, since the software may set the cold start state to the warm start state, it is not always the warm start state that is reset and restarted while the power is supplied. In other words, the power supply is supplied and the cold start state is performed several times from the first time, and then it is reset to the warm start state. The cold start state corresponds to a memory cold start state, and the warm start state corresponds to a memory warm start state. The configuration of the cold / warm start signal circuit 13 will be described later.

  The reset valid / invalid selection circuit 14 is connected to a flash ROM control register 21 constituting the flash ROM 12. The reset valid / invalid selection circuit 14 is supplied with a reset signal from outside the microcomputer 10. The reset valid / invalid selection circuit 14 uses the reset signal supplied from the outside of the microcomputer 10 in accordance with the value of the cold / warm start signal supplied from the cold / warm start signal circuit 13 as it is, specifically, the flash ROM 12. Is supplied to the flash ROM control register 21 of the flash ROM 12, or a signal (hereinafter referred to as "non-reset signal") that is not reset by cutting off the reset signal is supplied to the flash ROM 12, specifically, the flash ROM control register 21 of the flash ROM 12. Choose. The non-reset signal corresponds to a memory non-reset signal that blocks the reset signal that is the input memory reset signal and instructs the retention of the tune data stored in the flash ROM control register 21.

  More specifically, when the cold / warm start signal is a signal indicating a cold start state, the reset valid / invalid selection circuit 14 validates the reset signal from the outside of the microcomputer 10 and controls the reset signal as it is in the flash ROM. It is given to the register 21. The flash ROM control register 21 is initialized to a default state when a reset signal is given from the reset valid / invalid selection circuit 14. For example, if the flash ROM control register 21 stores tune data, the tune data is deleted. The cold start state corresponds to a memory erasure required state in which tune data stored in the flash ROM control register 21 needs to be erased.

  The reset valid / invalid selection circuit 14 invalidates the reset signal from the outside of the microcomputer 10 and sends a non-reset signal to the flash ROM control register 21 when the cold / warm start signal indicates a warm start state. give. When a non-reset signal is given from the reset valid / invalid selection circuit 14, the flash ROM control register 21 is not initialized to a default state but holds a stored value, for example, tune data. The warm start state corresponds to a memory erasure unnecessary state in which it is not necessary to erase the tune data stored in the flash ROM control register 21.

  When the cold / warm start signal supplied from the cold / warm start signal circuit 13 is a signal representing a cold start state, the flash ROM control circuit 22 uses the initialized flash data stored in the tune data area 20b. The value copied to the ROM control register 21 and the value stored in the flash ROM control register 21 are updated. That is, in the cold start state, when a reset signal is input, the flash ROM control register 21 is initialized and the tune data stored in the flash ROM control register 21 is erased, and a new tune data area 20b of the storage unit 20 is deleted. Tune data supplied to the flash ROM control register 21 is stored.

  The flash ROM control circuit 22 stores the tune data stored in the tune data area 20b in the flash ROM control register 21 when the cold / warm start signal supplied from the cold / warm start signal circuit 13 indicates a warm start state. The operation is continued without holding the value already stored in the flash ROM control register 21 without copying. That is, in the warm start state, even if a reset signal is input, the flash ROM control register 21 is not initialized, and the tune data stored in the flash ROM control register 21 is not erased. The tune data already stored in the flash ROM control register 21 is held without being copied.

  FIG. 5 is a block diagram showing the configuration of the cold / warm start signal circuit 13. The cold / warm start signal circuit 13 includes a cold / warm start flag circuit 25. The cold / warm start flag circuit 25 includes a circuit for detecting whether it is in a cold start state or a warm start state, and a flag register for storing a detection result as a flag value. The flag value is a cold / warm start signal. Output as. The change from the cold start state to the warm start state may be set by hardware or may be set by software. When set by software, it is initialized to a cold start state the first time power is supplied, and remains in the cold start state as long as it is not reset to the warm start state by software after being reset again and again. In other words, it remains in the cold start state unless changed to the warm start state by software. In the case of updating the flag by software, the update timing can be freely set, that is, the warm start state can be arbitrarily set.

  FIG. 6 is a block diagram showing a configuration of the reset valid / invalid selection circuit 14. The reset valid / invalid selection circuit 14 includes a selection circuit 26 and a non-reset value register 27. A cold / warm start signal circuit 13 constituting the microcomputer 10 is connected to the selection circuit 26. The non-reset value register 27 stores a value represented by the non-reset signal (hereinafter referred to as “non-reset value”).

  In response to the cold / warm start signal supplied from the cold / warm start signal circuit 13, the selection circuit 26 selects one of the reset signal from the outside of the microcomputer 10 and the non-reset value stored in the non-reset value register 27. Select either one. More specifically, when the cold / warm start signal supplied from the cold / warm start signal circuit 13 is a signal indicating a cold start state, the selection circuit 26 selects a reset signal supplied from the outside of the microcomputer 10 as a reset signal. It is given to the flash ROM control register 21 as it is. When the cold / warm start signal supplied from the cold / warm start signal circuit 13 is a signal indicating a warm start state, the selection circuit 26 selects a non-reset value stored in the non-reset value register 27, and reset signal Is given to the flash ROM control register 21 as follows.

  FIG. 7 is a timing chart showing the operation timing of the microcomputer 10. When power is supplied at time t1 and the state of the power supply is changed from OFF to ON, a reset signal is input and an initial reset after power supply, that is, a power-on reset is performed. At time t1, a signal indicating a cold start state, for example, a low signal is output as a cold / warm start signal.

  Next, when the reset is released at time t2, the initialization of the flash ROM 12 is initialized as a reset sequence. Specifically, the flash ROM control register 21 and the flash ROM control circuit 22 are initialized, and the tune data stored in the tune data area 20b of the storage unit 20 is copied to the initialized flash ROM control register 21. The

  Immediately after power is supplied, it is not known what state the potential of a node such as a register in the microcomputer 10 is, so the timing of power-on reset, that is, the reset sequence after power-on reset, The potential of the node is stabilized. As a result, all the registers such as the flash ROM control register 21 and the latches are erased and become the initial state. Therefore, in the reset sequence, data is read from the storage unit 20 of the flash ROM 12 and is stored in the registers and latches. New storage is required.

  Therefore, in the reset sequence after the power-on reset, it is necessary to copy the tune data stored in the tune data area 20b of the storage unit 20 to the flash ROM control register 21 as described above. When the reset sequence ends, the operation of the CPU 11, specifically, the execution operation of the program stored in the user data area 20 a of the storage unit 20 is started.

  After that, at time t3, when the CPU 11 executes the program execution operation, the flag of the cold / warm start flag circuit 25 of the cold / warm start signal circuit 13 is rewritten, and when the cold start state is changed to the warm start state, / As a warm start signal, a signal indicating a warm start state, for example, a high signal is output.

  Next, when a reset signal is input at time t4, restart / reset (hereinafter may be referred to as “re-reset”) is performed, and reset is released at time t5. At this time, since it is in a warm start state, the reset valid / invalid selection circuit 14 invalidates the reset signal and outputs a non-reset signal. Thereby, the reset sequence after reset release is omitted, and the operation of the CPU 11 is started.

  In the warm start state, the potential of the node in the microcomputer 10 is already stabilized by the reset sequence after the power-on reset. Therefore, it is necessary to stabilize the potential of the node such as the register in the microcomputer 10 again by the reset sequence. There is no. Further, since the value of the register or the like is held, it is not necessary to read the data from the storage unit 20 of the flash ROM 12 again in the reset sequence and store it in the register or the like. Since the tune data is also stored in the flash ROM control register 21, it is not necessary to copy the tune data stored in the tune data area 20b of the storage unit 20 again. That is, in the reset in the warm start state such as restart / reset, the reset sequence after the reset release is not necessary.

  Therefore, as described above, the reset sequence after reset release can be omitted, for example, copying of tune data can be omitted. Therefore, after the reset release, the operation of the CPU 11 is started immediately and the startup time of the microcomputer 10 is shortened. can do.

  As described above, according to the present embodiment, when a reset signal is input in the cold start state, the flash ROM control register 21 is initialized and tune data is copied to the flash ROM control register 21. Even if a reset signal is input in the warm start state, the flash ROM control register 21 is not initialized and holds the stored tune data.

  Specifically, when the cold / warm start signal output from the cold / warm start signal circuit 13 is a signal indicating a cold start state, when the reset signal is input, the reset valid / invalid selection circuit 14 resets the reset signal. Is supplied to the flash ROM control register 21 to initialize the flash ROM control register 21 and copy the tune data. When the cold / warm start signal output from the cold / warm start signal circuit 13 is a signal indicating the warm start state, the reset valid / invalid selection circuit 14 flushes the non-reset signal even if the reset signal is input. Since it is given to the ROM control register 21, the flash ROM control register 21 is not initialized, and holds the stored tune data.

  As described above, when resetting in the warm start state, the flash ROM control register 21 is not initialized, and the tune data is reflected in the flash ROM control register 21, that is, the tune data is held in the flash ROM control register 21. Therefore, copying of tune data from the tune data area 20b to the flash ROM control register 21 can be omitted. This eliminates the need to copy the tune data at the time of resetting, so that the startup time of the microcomputer 10 can be shortened when the resetting is frequently performed. In the case of a non-defective product test, the test time can be shortened. The effect of shortening the start-up time and test time of the microcomputer 10 can be calculated quantitatively simply by multiplying the tune data by one copy time, the number of copy skips, and the number of samples to be executed.

  In order to realize the microcomputer 10 of the present embodiment, it is necessary to change a part of the circuit of the microcomputer 1 of the premise technique shown in FIG. 1 described above. Can be realized. Therefore, the increase in hardware cost is small with respect to the above effect, and the feasibility is extremely high. Further, the configuration of the microcomputer 10 of the present embodiment is applicable to all products in which a flash ROM similar to the flash ROM 12 of the present embodiment is mounted.

<Reference form>
The configuration of the microcomputer 10 according to the first embodiment can be applied to an electronic circuit other than the flash ROM 12, for example, a microcomputer equipped with a PLL circuit. FIG. 8 is a block diagram showing a configuration of the microcomputer 30 of the reference form. The configuration of the microcomputer 30 shown in FIG. 8 is similar to the configuration of the microcomputer 10 of the first embodiment shown in FIG. 3 described above, so only the different parts will be described, and the corresponding parts have the same reference numerals. A common description is omitted.

  The microcomputer 30 includes a CPU 11, a cold / warm start signal circuit 13, a reset valid / invalid selection circuit 14, and a PLL circuit 31. The microcomputer 30 of this embodiment is different in that the microcomputer 30 includes a PLL circuit 31 instead of the flash ROM 12 included in the microcomputer 10 of the first embodiment. The CPU 11 is connected to the PLL circuit 31 and the cold / warm start signal circuit 13. The PLL circuit 31 is connected to the CPU 11, the cold / warm start signal circuit 13 and the reset valid / invalid selection circuit 14. The cold / warm start signal circuit 13 is connected to the CPU 11 and the reset valid / invalid selection circuit 14. The reset valid / invalid selection circuit 14 is connected to the cold / warm start signal circuit 13 and the PLL circuit 31. The CPU 11 comprehensively controls arithmetic processing and the cold / warm start signal circuit 13 and the PLL circuit 31 constituting the microcomputer 30 according to a built-in control program. The PLL circuit 31 will be described later.

  FIG. 9 is a block diagram showing a configuration of the PLL circuit 31. In FIG. 9, a cold / warm start signal circuit 13 and a reset valid / invalid selection circuit 14 are described together. The PLL circuit 31 includes a PLL control register 32 and a PLL control circuit 33. The PLL control register 32 corresponds to an electronic circuit control register, and the PLL control circuit 33 corresponds to an electronic circuit control circuit. The PLL control register 32 is connected to the PLL control circuit 33.

  The PLL control circuit 33 is an oscillation circuit that oscillates and outputs an input clock so as to have a set multiplication rate. The PLL control register 32 stores setting data which is data of setting values such as a PLL multiplication factor necessary for the PLL control circuit 33. The PLL control circuit 33 is configured to be able to set an operation based on setting data stored in the PLL control register 32. Specifically, the PLL control circuit 33 oscillates and outputs the input clock so that the set value of the PLL multiplication rate stored in the PLL control register 32 is obtained.

  In this embodiment, the reset valid / invalid selection circuit 14 validates the reset signal input from the outside of the microcomputer 30 according to the value of the cold / warm start signal supplied from the cold / warm start signal circuit 13, and the reset signal Select whether to output the value as it is or to always output the non-reset value as a non-reset signal regardless of the reset signal value.

  More specifically, when the cold / warm start signal is a signal representing a cold start state, the reset valid / invalid selection circuit 14 validates the reset signal from the outside of the microcomputer 30 and performs PLL control as it is. It is given to the register 32. The reset valid / invalid selection circuit 14 invalidates the reset signal from the outside of the microcomputer 30 and gives a non-reset signal to the PLL control register 32 when the cold / warm start signal is a signal representing a warm start state.

  When the cold / warm start signal is a signal indicating a cold start state and the reset valid / invalid selection circuit 14 is in a valid state, a reset signal is output from the reset valid / invalid selection circuit 14 and the PLL control register 32 Initialized to default state. As a result, the multiplication rate is also in the initial state. The initial state of the multiplication rate is, for example, a self-excited oscillation state. After that, the CPU 11 rewrites the multiplication rate of the PLL control register 32 so that the desired PLL oscillation frequency is obtained, and after the PLL oscillation stabilization wait time, the PLL oscillation stable state is entered.

  When the cold / warm start signal is a signal representing a warm start state and the reset valid / invalid selection circuit 14 is in an invalid state, a non-reset signal is output from the reset valid / invalid selection circuit 14. The control register 32 is not initialized, and the already set value is valid as it is. In that case, even if the PLL circuit 31 is reset again, the PLL oscillation frequency before the resetting is maintained. Therefore, when the desired PLL oscillation frequency has already been reached, the CPU 11 does not need to update the multiplication rate, and the PLL oscillation stabilization wait time can be omitted.

  As described above, according to the present embodiment, when a reset signal is input in the cold start state, the PLL control register 32 is initialized, the multiplication rate of the PLL control register 32 is set, and the oscillation of the PLL circuit 31 is performed. Although the waiting for stability is performed, even if a reset signal is input in the warm start state, the PLL control register 32 is not initialized and holds the stored set value.

  Specifically, when the cold / warm start signal output from the cold / warm start signal circuit 13 is a signal indicating a cold start state, when the reset signal is input, the reset valid / invalid selection circuit 14 resets the reset signal. Is supplied to the PLL control register 32, the multiplication rate of the PLL control register 32 is set, and the oscillation stabilization wait of the PLL circuit 31 is performed. When the cold / warm start signal output from the cold / warm start signal circuit 13 is a signal representing a warm start state, the reset valid / invalid selection circuit 14 outputs a non-reset signal to the PLL even if a reset signal is input. Since it is given to the control register 32, the PLL control register 32 is not initialized and holds the stored set value. Therefore, initialization of the PLL control register 32 and setting of the multiplication rate can be omitted, and the oscillation stabilization wait time of the PLL circuit 31 can be omitted.

  Thus, when the desired PLL oscillation frequency has already been reached, such as when resetting again in the warm start state, initialization of the PLL control register 32 and setting of the multiplication ratio are omitted, and the PLL oscillation stabilization wait time is omitted. Can be omitted. As a result, when the reset is frequently performed, for example, in the configuration in which the program is executed after the PLL oscillation stabilization waiting time, the startup time of the microcomputer 30 can be shortened. In addition, the test time can be shortened in the non-defective product test. The effect of shortening the startup time and the test time in the microcomputer 30 of this embodiment can be calculated quantitatively by simply multiplying the PLL oscillation stabilization wait time, the number of omitted PLL stabilization wait times, and the number of samples performed. .

  When the microcomputer 30 of this embodiment is realized, it is necessary to change a part of the circuit of the microcomputer of the base technology shown in FIG. 2 described above, but in any case, it is realized with a simple and extremely small circuit change. be able to. Therefore, the increase in hardware cost is small with respect to the above effect, and the feasibility is extremely high. The configuration of the microcomputer 30 of the present embodiment is applicable to all products that are mounted with a PLL circuit having the same configuration as the PLL circuit 31 of the present embodiment.

  In the above reference embodiment, the microcomputer 30 including the PLL circuit 31 is cited as a microcomputer to which the configuration of the microcomputer 20 of the first embodiment can be applied. However, the microcomputer 30 is not limited to the PLL circuit, and the electronic circuit control register and If the microcomputer includes an electronic circuit control circuit and includes an electronic circuit in which the operation of the electronic circuit control circuit is set based on setting data stored in the electronic circuit control register, the same effect is achieved. Can do. Examples of the electronic circuit other than the PLL circuit include a step-down circuit that generates an internal power supply voltage by dropping a power supply voltage supplied from the outside to a predetermined set value.

  Such a microcomputer includes an electronic circuit control register for storing predetermined setting data, and an electronic circuit control circuit capable of setting an operation based on the setting data stored in the electronic circuit control register. Circuit and a circuit reset signal for instructing erasure of the setting data stored in the electronic circuit control register when the setting data stored in the electronic circuit control register needs to be erased. Is input, the setting data stored in the electronic circuit control register is erased, the newly applied setting data is stored in the electronic circuit control register, and stored in the electronic circuit control register. When the circuit reset signal is input when the setting data is in a setting erasing unnecessary state that does not require erasing the setting data, the electronic circuit control To hold the setting data stored in the register, configured with a circuit reset control means for controlling the electronic circuit.

  In the reference embodiment described above, the CPU 11, the cold / warm start signal circuit 13 and the reset valid / invalid selection circuit 14 function as circuit reset control means. The cold / warm start signal circuit 13 corresponds to a circuit cold / warm start signal circuit, and the reset valid / invalid selection circuit 14 corresponds to a circuit reset valid / invalid selection circuit. The PLL control register 32 corresponds to an electronic circuit control register, and the PLL control circuit 33 corresponds to an electronic circuit control circuit. The cold start state corresponds to the setting data stored in the PLL control register 32, specifically, the circuit cold start state which is a necessary setting erasing state in which the setting value of the multiplication rate needs to be erased. This corresponds to a circuit warm start state that is a setting erasure unnecessary state that does not require erasure of the setting value of the multiplication rate that is the setting data stored in the PLL control register 32. The reset signal corresponds to a circuit reset signal for instructing erasure of setting data stored in the PLL control register 32, and the non-reset signal is a circuit non-reset for instructing retention of setting data stored in the PLL control register 32. Corresponds to the signal.

<Second Embodiment>
FIG. 10 is a block diagram showing a configuration of the microcomputer 40 according to the second embodiment of the present invention. Since the configuration of the microcomputer 40 shown in FIG. 10 is similar to the configuration of the microcomputers 10 and 30 of the first embodiment and the reference embodiment described above, only different parts will be described, and the same reference will be made to the corresponding parts. A common description is omitted by adding a symbol.

  The microcomputer 40 includes a CPU 11, a flash ROM 12, a cold / warm start signal circuit 13, a reset valid / invalid selection circuit 14, and a PLL circuit 31. The microcomputer 40 of the present embodiment is configured by further including a PLL circuit 31 in addition to the configuration of the microcomputer 10 of the first embodiment.

  The CPU 11, the cold / warm start signal circuit 13 and the reset valid / invalid selection circuit 14 function as memory reset control means and circuit reset control means. The cold / warm start signal circuit 13 corresponds to a memory cold / warm start signal circuit and a circuit cold / warm start signal circuit, and the reset valid / invalid selection circuit 14 is a memory reset valid / invalid selection circuit and circuit reset valid / invalid. This corresponds to a selection circuit.

  The CPU 11 is connected to the flash ROM 12, the cold / warm start signal circuit 13 and the PLL circuit 31. The flash ROM 12 is connected to the CPU 11, a cold / warm start signal circuit 13 and a reset valid / invalid selection circuit 14. The cold / warm start signal circuit 13 is connected to the CPU 11, the flash ROM 12, and the reset valid / invalid selection circuit 14. The reset valid / invalid selection circuit 14 is connected to the flash ROM 12, the cold / warm start signal circuit 13 and the PLL circuit 31. The PLL circuit 31 is connected to the CPU 11 and the reset valid / invalid selection circuit 14.

  FIG. 11 is a block diagram showing each configuration of the flash ROM 12 and the PLL circuit 31 constituting the microcomputer 40. In FIG. 11, a cold / warm start signal circuit 13 and a reset valid / invalid selection circuit 14 are described together.

  The microcomputer 40 is the same as the first embodiment and reference except that the reset signal or non-reset signal output from the reset valid / invalid selection circuit 14 is supplied to both the flash ROM control register 21 and the PLL control register 32. It operates similarly to the microcomputers 10 and 30 of the embodiment. The reset signal corresponds to a memory reset signal and a circuit reset signal, the non-reset signal corresponds to a memory non-reset signal and a circuit non-reset signal, and the cold / warm start signal includes a memory cold / warm start signal and a circuit cold / circuit Corresponds to the warm start signal. The cold start state corresponds to a memory cold start state and a circuit cold start state, and the warm start state corresponds to a memory warm start state and a circuit warm start state.

  More specifically, when the cold / warm start signal supplied from the cold / warm start signal circuit 13 is a signal indicating a cold start state, the reset valid / invalid selection circuit 14 receives a reset signal from the outside of the microcomputer 10. The reset signal is applied to the flash ROM control register 21 and the PLL control register 32 as it is.

  When a reset signal is given from the reset valid / invalid selection circuit 14, the flash ROM control register 21 is initialized to a default state, and, for example, tune data is erased. Similarly to the flash ROM control register 21, the PLL control register 32 is also initialized to the default state, and the multiplication rate is in the initial state. Thereafter, the tune data is copied in the flash ROM 12, and in the PLL circuit 31, the multiplication factor is updated by the CPU 11, and the PLL oscillation stabilization state is reached after the PLL oscillation stabilization wait time.

  The reset in the cold start state is performed, for example, as a power-on reset in the timing chart shown in FIG. 7, and in the reset sequence after the power-on reset, the flash ROM control register 21 is initialized and the tune data is copied. In addition, initialization of the PLL control register 32, updating of the multiplication rate, and waiting for PLL oscillation stabilization are performed.

  When the cold / warm start signal supplied from the cold / warm start signal circuit 13 is a signal indicating the warm start state, the reset valid / invalid selection circuit 14 invalidates the reset signal from the outside of the microcomputer 10 and does not reset. A signal is supplied to the flash ROM control register 21 and the PLL control register 32.

  When a non-reset signal is given from the reset valid / invalid selection circuit 14, the flash ROM control register 21 is not initialized to a default state but holds a stored value, for example, tune data. Similarly to the flash ROM control register 21, the PLL control register 32 is not initialized, and the already set value is valid as it is.

  The reset in the warm start state is performed, for example, as a restart / reset in the timing chart shown in FIG. In the reset in the warm start state, the flash ROM control register 21 and the PLL control register 32 are not initialized, and the tune data and the set value of the multiplication rate are held. Accordingly, since the reset sequence after reset can be omitted, the tune data copy time and the PLL oscillation stabilization wait time can be omitted.

  As described above, according to the present embodiment, as in the first embodiment and the reference embodiment, the tune data has already been copied to the flash ROM control register 21 as in the case of re-reset in the warm start state. When the oscillation frequency of the PLL circuit 31 is a desired oscillation frequency, the initialization of the flash ROM control register 21 and the PLL control register 32 is omitted, and the tune data copy time and the PLL oscillation stabilization wait time are omitted. be able to. As a result, the startup time of the microcomputer 40 can be shortened when frequent resetting is performed. In addition, the test time can be shortened in the non-defective product test.

  Further, the microcomputer 40 of the present embodiment can be realized by connecting the reset valid / invalid selection circuit 14 to the flash ROM 12 and the PLL circuit 31, and the flash ROM 12 and the PLL circuit 31 can be independently provided in circuit mounting. Since it can be realized, it can be realized with a simple and extremely small circuit change.

<Third Embodiment>
FIG. 12 is a block diagram showing a configuration of a microcomputer 50 according to the third embodiment of the present invention. The configuration of the microcomputer 50 shown in FIG. 12 is similar to the configuration of the microcomputer 40 of the second embodiment shown in FIG. 10 described above, so only the different parts will be described and the same reference numerals are used for the corresponding parts. A common description is omitted.

  The microcomputer 50 includes a CPU 11, a flash ROM 12, a cold / warm start signal circuit 13, a reset valid / invalid selection circuit 14, and a PLL circuit 51. The microcomputer 50 according to the present embodiment includes another PLL circuit 51 instead of the PLL circuit 31 provided in the microcomputer 40 according to the second embodiment.

  CPU 11 is connected to flash ROM 12, cold / warm start signal circuit 13 and PLL circuit 51. The flash ROM 12 is connected to the CPU 11, the cold / warm start signal circuit 13, the reset valid / invalid selection circuit 14, and the PLL circuit 51. The cold / warm start signal circuit 13 is connected to the CPU 11, the flash ROM 12, and the reset valid / invalid selection circuit 14. The reset valid / invalid selection circuit 14 is connected to the flash ROM 12, the cold / warm start signal circuit 13, and the PLL circuit 51. The PLL circuit 51 is connected to the CPU 11, the flash ROM 12, and the reset valid / invalid selection circuit 14. The PLL circuit 51 will be described later.

  FIG. 13 is a block diagram showing each configuration of the flash ROM 12 and the PLL circuit 51 that constitute the microcomputer 50. In FIG. 13, a cold / warm start signal circuit 13 and a reset valid / invalid selection circuit 14 are described together. The PLL circuit 51 according to the present embodiment includes a multiplication rate selection setting register 52 and a multiplication rate selection circuit 53 in addition to the PLL control register 32 and the PLL control circuit 33. The multiplication factor selection circuit 53 corresponds to a setting data selection circuit.

  The PLL control register 32 is connected to the multiplication factor selection circuit 53, and the multiplication factor selection circuit 53 is connected to the PLL control circuit 33. The multiplication factor selection circuit 53 is connected to the flash ROM control register 21 and the multiplication factor selection setting register 52 of the flash ROM 12, respectively.

  In the tune data area 20b of the storage unit 20 of the flash ROM 12 in the present embodiment, the set value of the multiplication rate of the PLL circuit 51 is stored together with the tune data. The set value of the multiplication rate of the PLL circuit 51 is copied together with the tune data and stored in the flash ROM control register 21.

  The multiplication rate selection circuit 53 determines the multiplication rate setting value from the PLL control register 32 and the multiplication rate setting value from the flash ROM control register 21 according to the register value stored in the multiplication rate selection setting register 52. Select one of these.

  The multiplication rate selection setting register 52 is initialized by a reset signal given from the outside of the PLL circuit 51. The initial value at the time of resetting the multiplication rate selection setting register 52 is selected as the setting value of the multiplication rate from the flash ROM control register 21 in this embodiment.

  The initial value at the time of resetting the multiplication rate selection setting register 52 is not limited to this, and a value indicating the setting value of the multiplication rate from the PLL control register 32 and the setting of the multiplication rate from the flash ROM control register 21 are not limited thereto. Either of the values representing the value may be used. Although different from the present embodiment, the multiplication rate selection setting register 52 may be configured to be initialized by a reset signal output from the reset valid / invalid selection circuit 14. It is desirable that the reset signal input to the multiplication rate selection setting register 52 and the initial value at the time of resetting the multiplication rate selection setting register 52 are mounted according to actual use. Further, if the register value of the multiplication rate selection setting register 52 is fixed and used, the multiplication rate selection circuit 53 may be fixed, and no new mounting is required.

  In the microcomputer 50 of the present embodiment, the setting value of the multiplication rate given to the PLL control circuit 33 is the setting value of the multiplication rate from the flash ROM control register 21 or the setting value of the multiplication rate from the PLL control register 32. Except for this, it operates in the same manner as the microcomputer 40 of the second embodiment.

  According to the present embodiment, both the flash ROM control register 21 and the PLL control register 32 already have the tune data and the multiplication rate set values stored in the flash ROM control register 21 as in the case of re-reset in the warm start state. When the included data is copied and the oscillation frequency of the PLL circuit 51 is the desired oscillation frequency, initialization is not performed, so that the PLL oscillation stabilization wait time can be omitted. As a result, the startup time of the microcomputer 50 can be shortened when frequent resetting is performed. In addition, the test time can be shortened in the non-defective product test.

  In the flash ROM control register 21, the setting value of the multiplication factor is copied together with the tune data after reset in the cold start state, and the setting of the multiplication factor is reflected. Therefore, the register value of the flash ROM control register 21 is set to the PLL multiplication factor. When the value is selected, there is an effect that the PLL control circuit 33 can be set to a desired PLL multiplication ratio before the CPU 11 is started even in the cold start state, that is, before the program is operated. In this case, it is not necessary to set the PLL multiplication rate by software, and there is a possibility that the PLL oscillation stabilization wait time can be reduced.

  In addition, as in this embodiment, if one of the register value of the flash ROM control register 21 and the register value of the PLL control register 32 can be selected as the setting value of the PLL multiplication ratio, the PLL multiplication ratio can be easily set in the middle. It is also possible to change to.

  Since the flash ROM control register 21 stores the tune data of the flash ROM 12, it is dangerous to rewrite the flash ROM control register 21 easily. However, as in the present embodiment, By making it possible to select the register value, such danger can be avoided.

  Further, by installing a multiplication rate selection circuit 53 and a multiplication rate selection setting register 52 so that either one of the register value of the flash ROM control register 21 and the register value of the PLL control register 32 can be selected, evaluation or the like can be performed. The application range of can be expanded.

  Further, the configuration in which the register value of the flash ROM control register 21 is used as the set value of the PLL multiplication ratio can be realized by connecting the flash ROM 12 and the PLL circuit 51 with wiring. Further, the configuration enabling selection of the register value of the PLL control register 32 is a new addition of the multiplication factor selection circuit 53 and the multiplication factor selection setting register 52 to the PLL circuit 31 and the addition of wiring in the above-described second embodiment. In addition, the implementation of newly added parts is also small. Therefore, the microcomputer 50 of the present embodiment can be realized by a simple circuit change.

  The microcomputers 10, 30, 40, 50 of the embodiments and reference embodiments described above each have a cold / warm start signal having the cold / warm start flag circuit 25 shown in FIG. 5 as a cold / warm start signal circuit. Although the circuit 13 is provided, the cold / warm start signal circuit is not limited to this, and may have other configurations shown below, for example.

  FIG. 14 is a block diagram showing a configuration of the cold / warm start signal circuit 60. The cold / warm start signal circuit 60 includes an external terminal setting unit 61. The external terminal setting unit 61 detects whether or not the value input from the external terminal of the microcomputer is an expected set value, and based on the detection result, the external terminal setting unit 61 is in a cold start state or in a warm start state. Judgment is made and a cold / warm start signal is output.

  Actually, when the value input from the external terminal of the microcomputer is the expected setting value, the external terminal setting unit 51 sets the input value from the external terminal (hereinafter referred to as “external terminal setting value”). Is determined to be a predetermined value, and whether the cold start state or the warm start state is determined based on the decoded value. Therefore, it is necessary to change the external pin setting value to distinguish whether it is in a cold start state or a warm start state when the microcomputer starts up, and peripheral systems other than the microcomputer must meet this specification. Cannot be realized. Here, after the power is supplied, it is not always necessary to set the warm start state after the second reset. The warm start state can be made after the convenient re-reset, which is equivalent to the cold / warm start flag circuit 13 shown in FIG.

  According to the cold / warm start signal circuit 60 shown in FIG. 14, it is possible to decode the external terminal setting value of the microcomputer and set the cold start state or the warm start state using the decoded value. That is, since it is possible to set the cold start state or the warm start state by using an external terminal of the microcomputer, the present invention can be realized without the dedicated circuits such as the cold / warm flag circuit 25 and the power-on reset circuit shown in FIG. be able to. Further, the cold start state and the warm start state can be set dynamically by a system outside the microcomputer, and can be set without depending on the software inside the microcomputer. As described above, since the timing for changing the external terminal setting is arbitrary, the cold start state and the warm start state can be arbitrarily set.

  Further, the cold / warm start signal circuit 60 shown in FIG. 14 only needs to decode the terminal signal as long as the external terminal specification meets the conditions, and is realized with a very simple circuit with a very high feasibility. Can do. Further, depending on the external terminal specification of the microcomputer, it can be realized relatively easily, so it may be used in combination with other realization methods.

  FIG. 15 is a block diagram showing a configuration of the cold / warm start signal circuit 62. The cold / warm start signal circuit 62 includes an external terminal setting unit 61 and a latch circuit 63. The latch circuit 63 latches the signal value decoded by the external terminal setting unit 61 at a certain point in time, and does not affect the cold / warm start signal even if the setting state of the external terminal is changed after latching. Circuit. The timing for latching may be when the external reset is released. If the external terminal setting unit 61 is fixed, the latch is unnecessary, and any timing may be used as long as the external terminal setting unit 61 is latched before the time when the external terminal setting unit 61 is changed.

  There are cases where the external terminals of a microcomputer must be used in combination with other terminal functions, such as when the number of terminals is small. In that case, if it is determined whether it is a cold start state or a warm start state at a certain point according to the terminal setting, if the terminal setting is changed when it is used as a terminal function of another specification, whether it is a cold start state as it is There is a problem that it is impossible to determine whether it is in a warm start state. As a countermeasure against this problem, a latch circuit 63 is provided as in the cold / warm start signal circuit 62 shown in FIG. 15, and the signal value obtained by decoding the terminal setting can be latched before using it as a terminal function of another specification. In this case, the above problem is solved.

  The cold / warm start signal circuit 62 shown in FIG. 15 is highly feasible if the external terminal specifications meet the conditions. The cold / warm start signal circuit 13 shown in FIG. 5 and the cold / warm start signal circuit 62 shown in FIG. This is effective when the start signal circuit 60 cannot be realized. Although it is necessary to be careful about the latching timing, the latching timing may be before it is used as a terminal function of another specification.

  FIG. 16 is a block diagram showing a configuration of the cold / warm start signal circuit 65. The cold / warm start signal circuit 65 includes a power-on reset circuit 66 and a cold / warm start flag register 67. The power-on reset circuit 66 outputs a signal indicating that power is supplied when power is supplied.

  The warm update signal is a write signal for changing from the cold start state to the warm start state. The generation of the warm update signal may be performed by any method of writing a value indicating the warm start state from the CPU 11, that is, software writing, and writing a signal value indicating the warm start state by hardware, that is, hardware writing. Good. In the case of generating a warm update signal by writing software, it is not always necessary to enter the warm start state after the second reset after the power is supplied. The warm start state can be made after the convenient re-reset, which is equivalent to the cold / warm start flag circuit 13 shown in FIG.

  The cold / warm start flag register 67 is a cold / warm start flag, and is an information register for identifying whether it is a cold start state or a warm start state. When a signal indicating that power is supplied from the power-on reset circuit 66 is supplied to the cold / warm start flag register 67, the cold / warm start flag register 67 is reset to a flag value indicating a cold start state. Output as a warm start signal. When a warm update signal is written, the cold / warm start flag register 67 becomes a flag value indicating a warm start state and outputs the flag value as a cold / warm start signal.

  As described above, the cold / warm start signal circuit 65 shown in FIG. 16 is initialized to the cold start state at the time of power-on reset, and receives a warm update signal as a write signal for changing to the warm start state. A cold / warm start flag register 67 is provided as a flag register for storing a cold start state or a warm start state so as to enter a start state. The generation of the warm update signal is realized by a circuit that can be updated by software rewriting by the CPU 11 or hardware.

  The difference between the cold / warm start flag register 67 and the cold / warm flag circuit 25 shown in FIG. 5 is that the cold / warm start flag register 67 or the cold / warm start flag circuit 25 is initialized by a power-on reset. The basic structure is the same. That is, the cold / warm start signal circuit 65 shown in FIG. 16 only has a cold / warm flag circuit mounted using the power-on reset circuit 66. The cold / warm start flag circuit 65 shown in FIG. 16 is used when the power-on reset circuit 66 is mounted and the cold / warm flag circuit 25 is not mounted, and when the conditions of the external terminal setting specifications are not met. This is useful when you cannot.

It is a block diagram which shows the structure of the flash ROM1 incorporated in the microcomputer used as the premise of this invention. It is a block diagram which shows the structure of the PLL circuit 5 incorporated in the microcomputer used as the premise of this invention. 1 is a block diagram showing a configuration of a microcomputer 10 according to a first embodiment of the present invention. 2 is a block diagram showing a configuration of a flash ROM 12. FIG. 3 is a block diagram showing a configuration of a cold / warm start signal circuit 13. FIG. 3 is a block diagram showing a configuration of a reset valid / invalid selection circuit 14. FIG. 3 is a timing chart showing the operation timing of the microcomputer 10. It is a block diagram which shows the structure of the microcomputer 30 of a reference form. 2 is a block diagram showing a configuration of a PLL circuit 31. FIG. It is a block diagram which shows the structure of the microcomputer 40 which is the 2nd Embodiment of this invention. 3 is a block diagram showing each configuration of a flash ROM 12 and a PLL circuit 31 constituting a microcomputer 40. FIG. It is a block diagram which shows the structure of the microcomputer 50 which is the 3rd Embodiment of this invention. 2 is a block diagram showing each configuration of a flash ROM 12 and a PLL circuit 51 that constitute a microcomputer 50. FIG. 4 is a block diagram showing a configuration of a cold / warm start signal circuit 60. FIG. 3 is a block diagram showing a configuration of a cold / warm start signal circuit 62. FIG. 3 is a block diagram showing a configuration of a cold / warm start signal circuit 65. FIG.

Explanation of symbols

  1,12 flash ROM, 2,20 storage unit, 3,21 flash ROM control register, 4,22 flash ROM control circuit, 5,31,51 PLL circuit, 6,32 PLL control register, 7,33 PLL control circuit, 10, 30, 40, 50 Microcomputer, 11 CPU, 13, 60, 62, 65 Cold / warm start signal circuit, 14 Reset valid / invalid selection circuit, 25 Cold / warm start flag circuit, 26 selection circuit, 27 Non-reset Value register, 52 multiplication rate selection setting register, 53 multiplication rate selection circuit, 61 external terminal setting unit, 63 latch circuit, 66 power-on reset circuit, 67 cold / warm start flag register.

Claims (5)

A storage unit for storing a predetermined program and adjustment data; a memory control register for storing the adjustment data provided from the storage unit; and an adjustment based on the adjustment data stored in the memory control register; Memory means including a memory control circuit for controlling
Processing means capable of executing the program stored in the storage unit of the storage means;
When a memory reset signal instructing erasure of the adjustment data stored in the memory control register is input when the adjustment data stored in the memory control register is in a memory-necessary state that requires erasure, The adjustment data stored in the memory control register is deleted, the adjustment data newly given from the storage unit is stored in the memory control register, and the adjustment data stored in the memory control register is not required to be deleted A memory reset control means for controlling the storage means so as to hold the adjustment data stored in the memory control register when the memory reset signal is input when the memory erasure is unnecessary. A microcomputer characterized by. The memory reset control means includes
Memory cold / warm start signal circuit for outputting a memory cold / warm start signal capable of discriminating whether the memory cold start state is the memory erasure required state or the memory warm start state is the memory erasure unnecessary state When,
When the memory cold / warm start signal is a signal representing the memory cold start state, the inputted memory reset signal is applied to the storage means, and the memory cold / warm start signal is a signal representing the memory warm start state. A memory reset valid / invalid selection circuit that shuts off the inputted memory reset signal and gives the memory means a memory non-reset signal instructing to hold the adjustment data stored in the memory control register; With
The storage means
When the memory reset signal is given from the memory reset valid / invalid selection circuit, the adjustment data stored in the memory control register is erased, and the adjustment data newly given from the storage unit is transferred to the memory control register 2. The microcomputer according to claim 1, wherein said adjustment data stored in said memory control register is held when said memory non-reset signal is given from said memory reset valid / invalid selection circuit. . An electronic circuit including an electronic circuit control register for storing predetermined setting data; and an electronic circuit control circuit capable of setting an operation based on the setting data stored in the electronic circuit control register;
When the setting data stored in the electronic circuit control register needs to be erased, a circuit reset signal is input to instruct the erasing of the setting data stored in the electronic circuit control register. Then, the setting data stored in the electronic circuit control register is deleted, the newly applied setting data is stored in the electronic circuit control register, and the electronic circuit control register is stored in the electronic circuit control register. When the circuit reset signal is input when the setting data is not required to be erased, the electronic circuit is controlled to hold the setting data stored in the electronic circuit control register. The microcomputer according to claim 1, further comprising a circuit reset control unit. The circuit reset control means includes
A circuit cold / warm start signal circuit for outputting a circuit cold / warm start signal capable of identifying whether the circuit is in a cold start state that is the setting erasure required state or a circuit warm start state in which the setting erasure is not required When,
When the circuit cold / warm start signal is a signal representing the circuit cold start state, the input circuit reset signal is applied to the electronic circuit, and the circuit cold / warm start signal is a signal representing the circuit warm start state. When it is, circuit reset valid / invalid selection which cuts off the inputted circuit reset signal and gives the electronic circuit a circuit non-reset signal instructing retention of the setting data stored in the electronic circuit control register With circuit,
The electronic circuit is
When the circuit reset signal is given from the circuit reset valid / invalid selection circuit, the setting data stored in the electronic circuit control register is erased, and the newly given setting data is transferred to the electronic circuit control register. 4. The setting data stored in the electronic circuit control register is held when the circuit non-reset signal is supplied from the circuit reset valid / invalid selection circuit. Microcomputer. The storage unit further stores the setting data,
The memory control register further stores the setting data,
The electronic circuit further includes a setting data selection circuit for selecting any one of the setting data given from the memory control register and the setting data given from the electronic circuit control register,
5. The microcomputer according to claim 3, wherein the electronic circuit control circuit is configured to be able to set an operation based on the setting data selected by the setting data selection circuit.

Images