JP2010034431A - Method of manufacturing semiconductor device - Google Patents

Abstract

The reliability of a semiconductor device is improved.
A controller chip 4 which is a solder bump electrode product manufactured by a different process and three memory chips (first DDR chip 1, second DDR chip and non-volatile memory chip), each of which is a gold bump electrode product, are mixedly mounted. In the assembly of the SIP 13, the three memory chips are sequentially mounted on the wiring board 7 first, and the controller chip 4 is mounted later, so that an oxide film is substantially formed on the solder material for gold-solder connection. In this state, the gold-solder connection can be performed, and the gold-solder connection of each of the three memory chips can be in a good connection state.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a semiconductor device in which a plurality of semiconductor chips are mounted flat on a substrate.

  In a semiconductor device, there is a technology having a structure including one microcomputer chip as a data processing device and two DDR2-SDRAMs as a plurality of memory devices on one surface of a module substrate (for example, Patent Document 1). reference).

Further, in an electronic device, one semiconductor chip (a semiconductor chip for connecting a stud bump) and two semiconductor chips (a semiconductor chip for connecting a solder bump) are mounted as electronic components on one main surface side of the wiring board. There is a technique having a structure in which a plurality of solder bumps are arranged as external connection terminals on the other main surface (back surface) side facing the main surface (see, for example, Patent Document 2).
JP 2007-213375 A JP 2003-7960 A

  As the functions of semiconductor devices increase, as shown in Patent Document 1, a memory system semiconductor chip (hereinafter also referred to as a memory chip) on one wiring board and a controller system for controlling the memory system semiconductor chip. SIP (System In Package) for building a system with a single semiconductor device (semiconductor package) has been developed by incorporating a semiconductor chip (hereinafter also referred to as a controller chip).

  The controller chip has an interface for inputting / outputting signals to / from the memory chip and an interface for inputting / outputting signals to / from an external device (external LSI). Compared to the number of pads. The types of memory chips to be mounted vary depending on the application and capacity of the product to be applied.

  Therefore, as shown in Patent Document 2, the controller chip is often manufactured by a process (or configuration) different from that of the memory chip.

  The inventor of the present application studied the manufacture of a SIP type semiconductor device using a memory chip and a controller chip manufactured by different processes (or configurations). Specifically, a SIP type semiconductor device using a semiconductor chip using a solder bump electrode and a semiconductor chip using a gold bump electrode was examined. As a result, the following problems became clear.

  In order to improve the bonding reliability between the gold bump electrode and the bonding lead (electrode) formed on the wiring board, the area where the gold bump electrode product is mounted on the wiring board before bonding the gold bump electrode. It is necessary to apply a solder material on the bonding lead.

  However, if the solder bump electrode product is mounted prior to the gold bump electrode product, the effect of heat for fixing the solder bump electrode product on the wiring board will cause the gold bump electrode product to be mounted on the bonding lead in the region where the gold bump electrode product is mounted in advance. The surface of the solder material applied to the surface is oxidized. For this reason, even when heat is applied to the solder material and melted, the solder wettability with respect to the gold bump electrode is lowered, and the bonding reliability between the gold bump electrode and the bonding lead is lowered.

  Therefore, the present inventor does not first apply the solder material for the gold bump electrode product, but after mounting the solder bump electrode product, the gold bump electrode product is mounted with the solder material for the gold bump electrode product. The application to the area to be applied was also examined.

  However, the mask used to apply the solder material only to the bonding leads on the wiring board interferes with the solder bump electrode product mounted in advance, and the mask can be placed on the wiring board. It turned out to be difficult.

  Note that Patent Document 1 does not describe that semiconductor chips manufactured by different processes (or configurations) such as solder bump electrode products and gold bump electrode products are mixedly mounted on one semiconductor device. .

  Moreover, since the said patent document 2 mounts a gold bump electrode product after mounting a solder bump electrode product on a wiring board, it improves the joining reliability of a gold bump electrode and the bonding lead of a wiring board. Therefore, it is difficult to apply the solder material for bonding onto the bonding lead of the wiring board.

  An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the heat dissipation of a semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the tamper resistance of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention includes the following steps. (A) an upper surface, a plurality of first bonding leads formed in a first region of the upper surface, a plurality of second bonding leads formed in a second region of the upper surface, and a lower surface opposite to the upper surface And a step of preparing a wiring board having a plurality of lands formed on the lower surface; (b) a step of applying a first bonding lead solder material to each of the plurality of first bonding leads. Furthermore, the following steps are included. (C) a first main surface, a plurality of first electrode pads formed on the first main surface, a plurality of gold bump electrodes respectively formed on the plurality of first electrode pads, and the first A step of disposing a first semiconductor chip having a first back surface opposite to the main surface on the first region of the wiring board such that the first main surface faces the upper surface of the wiring board. (D) applying heat to the wiring board to melt the solder material for the first bonding lead, and the plurality of gold bump electrodes of the first semiconductor chip and the plurality of first bonding leads of the wiring board. The process of electrically connecting each. Furthermore, the following steps are included. (E) a second main surface, a plurality of second electrode pads formed on the second main surface, a plurality of solder bump electrodes respectively formed on the plurality of second electrode pads, and the second Disposing a second semiconductor chip having a second back surface opposite to the main surface on the second region of the wiring substrate such that the second main surface faces the upper surface of the wiring substrate; (F) applying heat to the wiring board, melting the plurality of solder bump electrodes, and electrically connecting the plurality of solder bump electrodes of the second semiconductor chip and the plurality of second bonding leads of the wiring board, respectively. Step of connecting.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In the assembly of semiconductor devices in which solder bump electrode products and gold bump electrode products manufactured by different processes are mixed, the gold bump electrode product is first mounted on the substrate, and then the solder bump electrode product is mounted. The gold-solder connection can be performed in a state where the oxide film is not substantially formed on the solder material for gold-solder connection. Thereby, the mounting defect of a gold bump electrode product can be reduced and the reliability of a semiconductor device can be improved.

  In a semiconductor device in which a gold bump electrode product and a solder bump electrode product are mixedly mounted, a ring member surrounding the gold bump electrode product and the solder bump electrode product on the substrate, and a gold bump electrode product and a solder bump connected to the ring member. By providing a heat spreader that covers the electrode product and further connecting the solder bump electrode product to the heat spreader, the heat dissipation of the semiconductor device can be improved.

  In a semiconductor device in which a gold bump electrode product and a solder bump electrode product are mixedly mounted, a ring member surrounding the gold bump electrode product and the solder bump electrode product and a heat spreader covering the gold bump electrode product and the solder bump electrode product are provided on the substrate. As a result, the tamper resistance of the semiconductor device can be improved.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment)
FIG. 1 is a plan view showing an example of the structure of a semiconductor device according to an embodiment of the present invention through a heat spreader. FIG. 2 is a cross-sectional view showing an example of a structure cut along the line AA in FIG. 3 is an enlarged sectional view showing the detailed structure of FIG. 2, FIG. 4 is an enlarged plan view showing an example of the structure of the main surface of the DDR chip mounted on the semiconductor device shown in FIG. 1, and FIG. It is a partial expanded sectional view which shows an example of the structure cut | disconnected along A line. 6 is an enlarged plan view showing an example of the structure of the main surface of the FLASH chip mounted on the semiconductor device shown in FIG. 1, and FIG. 7 is an example of the structure cut along the line AA shown in FIG. FIG. 8 is an enlarged plan view showing an example of the structure of the main surface of the control chip mounted on the semiconductor device shown in FIG. 1, and FIG. 9 is an enlarged view of an example of the structure of part A shown in FIG. FIG. 10 is a partially enlarged sectional view showing an example of a structure cut along the line AA shown in FIG. 9, and FIG. 11 is a circuit block diagram showing an example of a circuit configuration of the semiconductor device shown in FIG.

  The semiconductor device of the present embodiment shown in FIGS. 1 to 3 is a semiconductor package in which a plurality of semiconductor chips are mounted on the wiring board 7 in a flat position. In the present embodiment, as an example of the semiconductor device, The SIP 13 in which three memory chips (first semiconductor chip) and one controller chip (second semiconductor chip) 4 are mounted on the wiring board 7 will be described.

  The three memory chips that are the first semiconductor chips mounted on the SIP 13 of the present embodiment are two DDR chips (first DDR chip 1 and second DDR chip 2) and one nonvolatile memory chip (FLASH chip). The case of 3 will be described as an example, but the number of mounted memory chips and each memory function are not limited to these. The DDR chip is, for example, a DDR-DRAM (Double Date Rate-Dynamic Random Access Memory) or the like, and a memory chip including a memory circuit that performs data transfer in synchronization with both rising and falling of an external clock signal. It is. The controller chip 4 controls these three memory chips.

  The configuration of the SIP 13 will be described. A wiring board 7 having an upper surface (surface, chip mounting surface) 7a and a lower surface 7b opposite to the upper surface 7a is flip-chip connected to the upper surface 7a of the wiring substrate 7 by face-down mounting. The first DDR chip 1, the second DDR chip 2, the nonvolatile memory chip 3 and the controller chip 4, and a plurality of BGA (Ball Grid Array) balls 11 which are external terminals provided on the lower surface 7 b of the wiring substrate 7. ing. As shown in FIG. 2, the plurality of BGA balls 11 are provided in a grid pattern on the lower surface 7 b of the wiring board 7, and therefore the SIP 13 is a BGA type semiconductor device.

  As shown in FIG. 3, a plurality of bonding leads (first bonding lead 7e and second bonding lead 7f) are formed on the upper surface 7a of the wiring board 7, and these bonding leads are not shown through the substrate in the substrate. A plurality of BGA balls 11 that are electrically connected to the corresponding land 7g on the lower surface 7b side through hole wiring, internal wiring, and the like, and are external terminals of the SIP 13, are connected to the corresponding land 7g.

  Further, four semiconductor chips (first DDR chip 1, second DDR chip 2, non-volatile memory chip 3 and controller chip 4) flip-chip connected on the wiring board 7 are rectangular wiring boards as shown in FIG. 7 are arranged on a diagonal line on the upper surface 7a. FIG. 1 shows the internal structure of the SIP 13 with the heat spreader 16 removed.

  In the SIP 13 of the present embodiment, the first DDR chip 1 and the second DDR chip 2 are arranged on both sides of the controller chip 4, and the nonvolatile memory chip 3 is arranged in the empty area. This is to equalize the arrangement distance between the controller chip 4 and the first DDR chip 1 and the arrangement distance between the controller chip 4 and the second DDR chip 2, so that the wiring lengths for both DDR chips are made equal.

  The nonvolatile memory chip 3 can also store the control program of the controller chip 4, and can write data that is not desired to be deleted when the power is turned off.

  A seal ring (ring member) 15 surrounding the four semiconductor chips and a heat spreader 16 connected to the seal ring 15 and covering the four semiconductor chips are provided on the upper surface 7a of the wiring board 7. ing. The heat spreader 16 may be a heat sink or the like. The seal ring 15 and the heat spreader 16 are joined together by an adhesive 18 as shown in FIG. That is, the four semiconductor chips mounted on the wiring board 7 are completely covered by the seal ring 15 and the heat spreader 16.

  The SIP 13 of this embodiment is mounted with the memory chip and the controller chip 4 manufactured by different processes (or configurations), and uses a gold bump electrode 8 as shown in FIG. Three memory chips each of which is a gold bump electrode product to which gold-solder connection is made and a controller chip 4 which is a solder bump electrode product to which solder connection is made using the solder bump electrode 9 are on the wiring board 7. It is mixed in.

  That is, each of the first DDR chip 1, the second DDR chip 2, and the nonvolatile memory chip 3 as the first semiconductor chip is applied to the wiring board 7 side using the gold bump electrode 8 as a gold bump electrode product. The solder material is flip-chip connected by gold-solder connection. On the other hand, the controller chip 4 which is the second semiconductor chip is flip-chip connected by solder connection to the solder material applied to the wiring board 7 side using the solder bump electrode 9 as a solder bump electrode product. Thereby, the memory chip (first semiconductor chip) and the controller chip (second semiconductor chip) 4 manufactured by different processes (or configurations) are mixedly mounted on the wiring board 7.

  Here, the detailed structure of each semiconductor chip mounted on the SIP 13 will be described.

  4 and 5 show an example of the structure of the first DDR chip 1 which is the first semiconductor chip. The first main surface 1a which is the surface of the silicon substrate 1d and the first back surface 1b on the opposite side are shown. The first main surface 1a and the first back surface 1b have a square shape that intersects the thickness. An integrated circuit such as a memory circuit is formed on the first main surface 1a side, and a plurality of first electrode pads 1c made of aluminum are formed in a row on the first main surface 1a. Yes. That is, the first DDR chip 1 has a center pad arrangement.

As shown in FIG. 5, an insulating SiO ₂ film 1e and a polyimide film 1f deposited on the SiO ₂ film 1e are formed on the first main surface 1a. Covering only the peripheral edge of one electrode pad 1c, the vicinity of the center is open. The gold bump electrodes 8 are connected to the exposed portions of the first electrode pads 1c through the openings.

  The second DDR chip 2 has the same structure as the first DDR chip 1. That is, as shown in FIG. 16 (f), it has a rectangular first main surface 2a and a first back surface 2b opposite to the first main surface 2a, and the first main surface 2a has a plurality of first electrodes in a center pad arrangement. Pads 2c are formed in a line, and a gold bump electrode 8 is connected to each first electrode pad 2c. Further, an integrated circuit such as a memory circuit is formed on the first main surface 2a side.

  Further, as shown in FIGS. 6 and 7, also for the non-volatile memory chip 3, as with the first DDR chip 1, the first main surface 3a which is the surface of the silicon substrate 3d and the first back surface 3b on the opposite side thereof. The first main surface 3a and the first back surface 3b have a square shape that intersects the thickness. An integrated circuit such as a memory circuit is formed on the first main surface 3a side, and a plurality of first electrode pads 3c made of aluminum are formed in two rows on the first main surface 3a. Yes. In other words, in the nonvolatile memory chip 3, a plurality of first electrode pads 3c are provided in two rows along each two opposite sides of the four sides of the first main surface 3a.

Further, as shown in FIG. 7, an insulating SiO ₂ film 3e is formed on the first main surface 3a, covering only the peripheral edge of each first electrode pad 3c, and opening in the vicinity of the center. is doing. The gold bump electrodes 8 are connected to the exposed portions of the first electrode pads 3c through the openings. Further, an integrated circuit such as a memory circuit is formed on the first main surface 3a side.

  The gold bump electrodes 8 connected to the first DDR chip 1, the second DDR chip 2, and the nonvolatile memory chip 3 are stud bump electrodes connected using a wire bonding tool, for example.

  The first DDR chip 1 and the second DDR chip 2 may also be formed in two rows of the first electrode pads 1c and the first electrode pads 2c as in the nonvolatile memory chip 3.

  As shown in FIGS. 8 to 10, the controller chip 4 also has a second main surface 4a that is the surface of the silicon substrate 4d and a second back surface 4b opposite to the second main surface 4a. As for the surface 4a and the 2nd back surface 4b, the planar shape which cross | intersects thickness consists of a square shape. Further, an integrated circuit such as a control circuit is formed on the second main surface 4a side, and on the second main surface 4a, as shown in FIG. 10, a plurality of second electrode pads 4c made of aluminum and The post leads 4f connected to and disposed immediately above these second electrode pads 4c are formed, and the plurality of second electrode pads 4c and post leads 4f are connected to the second main pads 4c as shown in FIG. Arranged in a staggered arrangement on the surface 4a. However, they may be arranged in a simple lattice arrangement.

  As shown in FIG. 10, an insulating film 4e is formed on the second main surface 4a. The insulating film 4e covers only the peripheral edge of each second electrode pad 4c and is open near the center. Post leads 4f are connected to exposed portions of the second electrode pads 4c through the openings, and solder bump electrodes 9 are connected to the post leads 4f. The solder bump electrode 9 is lead-free solder, for example, tin-silver solder.

  The controller chip 4 has an arithmetic processing function, and transmits / receives signals to / from each memory chip to control the operation of each memory chip, and also transmits / receives signals to / from the outside of the SIP 13. is there. Therefore, as shown in FIG. 8, the semiconductor chip has a large number of pins, and has a large driving force and a large amount of heat generation.

  Note that the gold bump electrode 8 for mounting the memory chip and the solder bump electrode 9 for mounting the controller chip 4 have a size (diameter) of the gold bump electrode 8 that is about ½ of the solder bump electrode 9.

  Therefore, as shown in FIG. 3, the height (R1) of the controller chip 4 from the upper surface 7a of the wiring board 7 in SIP 13 and the height (R2) from the upper surface 7a of the wiring board 7 of the first DDR chip 1 are For example, R1 = 0.085 mm and R2 = 0.04 mm. That is, the gap between the wiring board 7 and the controller chip 4 is about twice the gap between the wiring board 7 and the first DDR chip 1. In other words, the gap between the wiring board 7 and the first DDR chip 1 is about ½ of the gap between the wiring board 7 and the controller chip 4 and is very small.

  The gap between the controller chip 4 and the wiring board 7 having a relatively large gap is filled with an underfill resin 12, and the gap between the first DDR chip 1 and the controller chip 4 having a small gap is a non-conductive resin NCP (Non -Conductive Paste) 10 is filled.

  As for the chip thickness, the thickness (Q1) of the controller chip 4 is, for example, Q1 = 0.6 mm, and the thickness (Q2) of the first DDR chip 1 is, for example, Q2 = 0.4 mm. . Therefore, the mounting height of each semiconductor chip is, for example, R1 + Q1 = 0.585 mm for the controller chip 4 and R2 + Q2 = 0.44 mm for the first DDR chip 1, for example. Further, the gap between each semiconductor chip and the heat spreader 16 is, for example, P1 = 0.165 mm for the controller chip 4 and P2 = 0.41 mm for the first DDR chip 1.

  Since the controller chip 4 generates a large amount of heat as described above, connecting the controller chip 4 to the heat spreader 16 allows the heat generated from the controller chip 4 to escape to the heat spreader 16 and the seal ring 15 connected thereto. The heat dissipation effect of the controller chip 4 is enhanced.

  At that time, the second back surface 4b of the controller chip 4 is connected to the heat spreader 16 via an insulating resin. In the SIP 13 of the present embodiment, since the second back surface 4b of the controller chip 4 is at the GND potential, the connection is made through an insulating resin. The insulating resin is a silicone resin 17 as an example.

  On the other hand, a gap 19 is formed between the first DDR chip 1 and the heat spreader 16. That is, a gap 19 is formed between the first back surface 1 b of the first DDR chip 1 and the heat spreader 16. This is to prevent heat generated from the controller chip 4 from being transmitted to the first DDR chip 1 after being transmitted to the heat spreader 16 via the silicone resin 17. That is, this is to prevent the heat from adversely affecting the operation of the first DDR chip 1.

  Thus, in the SIP 13 of the present embodiment, the controller chip 4 and the heat spreader 16 are connected via the silicone resin 17 in order to enhance the heat dissipation effect of the controller chip 4, while the first DDR chip 1 has the first A gap 19 serving as a gap is formed between the back surface 1b and the heat spreader 16, and prevents heat generated from the controller chip 4 from being transmitted to the first DDR chip 1.

  Therefore, in the SIP 13, the mounting height of the controller chip 4 is preferably higher than the mounting height of the first DDR chip 1. In other words, the controller chip 4 is preferably close to the heat spreader 16 so as not to contact the heat spreader 16, while the first DDR chip 1 is preferably arranged away from the heat spreader 16. Further, since it is necessary to avoid the controller chip 4 from hitting the heat spreader 16, the thickness (height) including the adhesive 18 of the seal ring 15 must be higher than the mounting height of the controller chip 4.

  The separation of the first DDR chip 1 from the heat spreader 16 is the same for the other memory chips (the second DDR chip 2 and the non-volatile memory chip 3), and the second DDR chip 2 and the non-volatile memory chip 3 are also the heat spreader 16. It is preferable to arrange | position away from.

  Here, the seal ring 15 and the heat spreader 16 are preferably formed of a material having high thermal conductivity. The material is, for example, a copper alloy or an aluminum alloy, and the surface is subjected to, for example, nickel plating. May be.

  Next, the circuit operation in the SIP 13 will be described with reference to FIG. Here, a case where the first DDR chip 1, the second DDR chip 2, and the nonvolatile memory chip 3 are mounted as memory chips and the controller chip 4 for controlling these operations is provided in accordance with the present embodiment will be described. The number and type of memory chips are not limited to this example.

  One of the main roles of the controller chip 4 is to mediate between the external LSI 14 provided outside the system, the first DDR chip 1, the second DDR chip 2, and the nonvolatile memory chip 3 provided inside the system. In order to input / output data, there is an operation of converting a logical address (external address) for an external interface into a physical address of the first DDR chip 1, the second DDR chip 2, or the nonvolatile memory chip 3. Therefore, the controller chip 4 includes an interface for the first DDR chip 1, an interface for the second DDR chip 2, and an interface for the nonvolatile memory chip 3.

  When the controller chip 4 plays such a role, the controller chip 4 is provided with an external interface in addition to the number of pins necessary for the interface between the first DDR chip 1, the second DDR chip 2 and the nonvolatile memory chip 3. The electrode pad (pin) which comprises is needed. Therefore, the controller chip 4 has a larger number of electrode pads than the first DDR chip 1, the second DDR chip 2, and the nonvolatile memory chip 3 by the number of pins necessary for the external interface.

  The data output via the external interface is converted into various information via the external LSI 14 and output to a network device or a human interface device.

  On the other hand, the first DDR chip 1 and the second DDR chip 2 are provided with an interface with the controller chip 4 in order to perform data input / output with the external LSI 14 via the controller chip 4, but in addition to this, a clock (CK) is provided. A terminal, a DQS terminal, and the like. A current is applied to the CK terminal, and data is transmitted (or received) in synchronization with the rising edge (or falling edge) of the clock.

  The non-volatile memory chip 3 includes a chip select terminal (CE) in addition to the interface with the controller chip 4. Data can be written to or read from the nonvolatile memory chip 3 by enabling or disabling the chip select terminal.

  Next, the assembly of the SIP 13 of this embodiment will be described with reference to the flowchart shown in FIG.

  12 is a manufacturing flow diagram showing an example of the assembly procedure of the semiconductor device of FIG. 1, FIG. 13 is a plan view and a cross-sectional view showing an example of the states of steps S1 to S3 in FIG. 12, and FIG. FIG. 15 is a plan view and a sectional view showing an example of the state of each step of steps S4 and S5 in FIG. 12. 16 is a plan view and a cross-sectional view showing an example of the state of each step of steps S6 and S7 in FIG. 12, and FIG. 17 is a plan view and a cross-sectional view showing an example of the state of each step of steps S8 and S9 in FIG. 18 is a plan view and a cross-sectional view showing an example of the state of steps S10 and S11 in FIG. 12, and FIG. 19 is a plan view and a cross-sectional view showing an example of the state of step S12 in FIG. . Further, FIG. 20 is a manufacturing flow diagram showing the assembly procedure of the semiconductor device of the first modification of the embodiment of the present invention, and FIG. 21 shows the assembly procedure of the semiconductor device of the second modification of the embodiment of the present invention. It is a manufacturing flowchart.

  First, chip (memory) preparation in step S1 of FIG. 12 is performed. That is, the first DDR chip 1 shown in FIGS. 13A and 13C (the same applies to the second DDR chip 2) and the nonvolatile memory chip 3 shown in FIGS. 13B and 13D are prepared. As shown in the small process of step S1 in FIG. 12, after the wafer is prepared, the wafer is back-ground, that is, back-surface polished to reduce the wafer to a desired thickness.

  Thereafter, dicing is performed to obtain a memory chip of a desired size. Here, the first DDR chip 1 and the second DDR chip 2 in the center pad array, and the nonvolatile memory chip 3 in the two-row pad array are acquired.

  Thereafter, a gold stud bump is formed on each memory chip. That is, the gold bump electrode 8 is formed as shown in FIGS. 13A to 13D by using the stud bump technique for the electrode pad of each memory chip.

  Thereafter, chip (controller) preparation in step S2 of FIG. 12 is performed. Here, as an example, as shown in FIGS. 13 (e) and 13 (f), a controller chip 4 (chip with area bumps formed) to which a plurality of solder bump electrodes 9 are connected in advance in a staggered arrangement is prepared.

  Thereafter, substrate preparation in step S3 of FIG. 12 is performed. Here, as shown in FIGS. 13G and 13H, the upper surface 7a, the plurality of first bonding leads 7e formed in the first region 7c of the upper surface 7a, and the second region 7d of the upper surface 7a are formed. A wiring board 7 having a plurality of second bonding leads 7f, a lower surface 7b opposite to the upper surface 7a, and a plurality of lands 7g (see FIG. 3) formed on the lower surface 7b is prepared.

  As shown in FIG. 13G, in the first region 7c of the upper surface 7a, the memory chips (first semiconductor chips) of the first DDR chip 1, the second DDR chip 2, and the nonvolatile memory chip 3 are mounted. On the other hand, the second area 7d is an area where the controller chip (second semiconductor chip) 4 is mounted.

  FIG. 13 (h) shows an AA cross section of FIG. 13 (g).

  Further, in the chip mounting region including the first region 7c and the second region 7d on the upper surface 7a, a dam portion 7i shown in FIGS. 13 (g) and 13 (h) slightly protruding from the upper surface 7a is formed. This dam portion 7i divides the semiconductor chip mounting area to prevent the resin from flowing out during application of the resin such as the underfill resin 12 or NCP10, and is formed by, for example, silk printing. The amount of protrusion from the upper surface 7a is about 25 μm.

  In the example shown in FIGS. 13G and 13H, the dam portion 7i includes the mounting area (second area 7d) for the controller chip 4, the mounting area (first area 7c) for the first DDR chip 1, and the controller chip. 4 mounting region (second region 7d), second DDR chip 2 mounting region (first region 7c), second DDR chip 2 mounting region (first region 7c) and nonvolatile memory chip 3 mounting region (first region). The area 7c) is formed in each area, but is formed in the area that partitions the first DDR chip 1 mounting area (first area 7c) and the non-volatile memory chip 3 mounting area (first area 7c). Absent.

  This is because the adjacent chip mounting areas are separated to such an extent that the resin does not reach the bonding lead in the adjacent chip mounting area even if the resin flows out. The reason for this is that, as shown in FIGS. 1, 4, 6 and 8, the planar shape of each of the controller chip 4, the first DDR chip 1 and the second DDR chip 2 is almost a square. This is because the planar shape of the nonvolatile memory chip 3 is formed in a substantially rectangular shape having long sides longer than the long sides of the controller chip 4, the first DDR chip 1, and the second DDR chip 2. The nonvolatile memory chip 3 is mounted on the mounting area (first area 7c) of the nonvolatile memory chip 3 on the wiring board 7 so that the short side is adjacent to the second DDR chip 2. Therefore, the mounting area of the first DDR chip 1 and the mounting area of the non-volatile memory chip 3 are separated to such an extent that the resin does not reach the bonding leads, and the resin flows out to the respective areas without forming the dam portion 7i therebetween. The fear of doing is low. In this embodiment, the example in which the dam portion 7i is not formed between the first DDR chip 1 and the nonvolatile memory chip 3 has been described. However, even if the dam portion 7i is also formed in the region between the first DDR chip 1 and the nonvolatile memory chip 3. Good. Thereby, the outflow of resin can be suppressed more reliably.

  That is, the dam portion 7i does not have to be provided in an area between all adjacent chip mounting areas, and when the resin flows out, the chip mounting area is separated to the extent that it does not reach the bonding lead in the adjacent chip mounting area. If it is, it is not always necessary to provide it.

  Further, as shown in FIGS. 13G to 13J, the second bonding lead solder material 6 (solder precoat) is previously formed on the second bonding lead 7f in the second region 7d of the upper surface 7a of the wiring board 7. Is applied. On the other hand, no solder material is applied on the first bonding lead 7e in the first region 7c of the upper surface 7a. The second bonding lead solder material 6 is, for example, tin-silver-based lead-free solder.

  The first bonding lead 7e and the second bonding lead 7f formed on the upper surface 7a of the wiring substrate 7 are each covered with an insulating solder resist 7h, and the vicinity of the central portion thereof is covered with the solder resist. It is exposed through the 7h opening. The connection with the solder material is performed at the exposed portion.

  Thereafter, the solder material is applied in step S4 of FIG. Here, the first bonding lead solder material 5 is applied to each of the plurality of first bonding leads 7e in the mounting area of the three memory chips in the first area 7c of the upper surface 7a of the wiring board 7.

  In addition, since the plurality of first bonding leads 7e are arranged at a narrow pitch, it is preferable to form a thin solder material by adopting a solder forming method corresponding to the narrow pitch.

  Here, an example of a method for forming a solder material formed on the bonding leads arranged at a narrow pitch will be described. First, an adhesive liquid film is formed on the copper material constituting the bonding lead, and solder powder (solder particles) is sprinkled thereon, and then flux is applied to the solder powder and reflow is performed. . The solder powder is melted by reflow to form a thin solder material on the bonding lead. Alternatively, as shown in the small process of step S4 in FIG. 12, solder particles and flux are applied onto all the first bonding leads 7e in the three memory chip mounting regions of the first region 7c by the solder material printing method. Thereafter, reflow is performed and further cleaning is performed to remove the flux and the solder residue, whereby the first bonding lead solder material 5 is thinly formed on the plurality of first bonding leads 7e arranged at a narrow pitch. May be.

  When the first bonding lead solder material 5 is applied by a printing method, the first bonding lead solder material 5 on the plurality of second bonding leads 7f is formed as shown in FIGS. 14 (a) and 14 (b). The first bonding lead solder material 5 is applied onto the first bonding leads 7e of the wiring board 7 through the openings 20a of the mask 20 in this state.

  That is, the plurality of second bonding leads 7f formed with the solder bump electrodes 9 in the second region 7d of the upper surface 7a of the wiring board 7 are covered with the mask 20, and in this state, through the respective openings 20a of the mask 20. The first bonding lead solder material 5 is solidly applied on all the first bonding leads 7e in the first region 7c. At this time, since the above-described dam portion 7i and the solder material (second bonding lead solder material 6) provided in the second region 7d are formed on the upper surface 7a of the wiring substrate 7, the wiring substrate 7 A gap is generated between the mask 20 disposed on the upper surface 7 a of the wiring board 7 and the upper surface 7 a of the wiring substrate 7. Therefore, in this embodiment, as shown in FIG. 14B, by providing recesses 20b corresponding to these, the gap between the mask 20 and the upper surface 7a of the wiring board 7 is filled, and the solder material The application accuracy of the first bonding lead solder material 5 is improved. Thereafter, by performing reflow and cleaning, as shown in FIGS. 15A to 15D, the first bonding lead solder material 5 is thinly formed on the plurality of first bonding leads 7e arranged at a narrow pitch. To do. If the thickness of the solder material (second bonding lead solder material 6) provided in the dam portion 7i or the second region 7d is low, the recess 20b may not necessarily be formed in the mask 20.

  FIG. 14B shows the AA cross section of FIG.

  Here, as shown in FIGS. 15B to 15D, the thickness (S1) of the second bonding lead solder material 6 formed on the second bonding lead 7f and the first bonding lead 7e. Comparing the thickness (S2) of the formed first bonding lead solder material 5, S1 = 60 μm and S2 = 15 μm. That is, the thickness (S2) of the first bonding lead solder material 5 is about ¼ of the thickness (height) of the second bonding lead solder material 6 (S1). The amount of solder is about / 4.

  Therefore, if the thickness of the first bonding lead solder material 5 formed on the first bonding lead 7e can be reduced to, for example, about 15 μm, a solder material using a method other than the solder material forming method described above is used. Needless to say, it may be formed.

  FIG. 15B shows the AA cross section of FIG.

  Thereafter, flip chip bonding (1) in step S5 of FIG. 12 is performed. Here, as shown in FIGS. 15E to 15G, the flip chip bonding of the first DDR chip 1 is performed. First, as shown in the small process of step S5 in FIG. 12, baking (150 ° C./40 minutes) is performed to perform dehumidification processing, and further cleaning is performed by plasma processing. That is, the upper surface 7a of the wiring board 7 and the first bonding lead solder material 5 are cleaned by plasma cleaning, and thereby, it is possible to improve the bonding strength and the filling property of the NCP 10 in flip chip bonding.

  Here, FIG.15 (f) shows the AA cross section of FIG.15 (e).

  Thereafter, NCP 10 that is a nonconductive resin is applied to the chip mounting region of the first DDR chip 1 in the first region 7 c of the upper surface 7 a of the wiring substrate 7. Here, the NCP 10 is dropped and applied to the chip mounting area of the first DDR chip 1 in the first area 7c of the wiring board 7 through the nozzle.

  In flip chip bonding of the first DDR chip 1, the gap between the first DDR chip 1 and the wiring substrate 7 is narrow, so that it is difficult to inject the NCP 10 after mounting the first DDR chip. Therefore, before mounting the first DDR chip, the NCP 10 is first applied to the chip mounting area of the first DDR chip 1 in the first area 7c of the upper surface 7a of the wiring board 7, and after the application, mounting of the first DDR chip 1 is performed. Do.

  Thereby, even if the gap between the first DDR chip 1 and the wiring board 7 is narrow, the NCP 10 can be reliably embedded in the gap between the first DDR chip 1 and the wiring board 7 without forming a void.

  Note that, on the upper surface 7a of the wiring board 7, between the chip mounting area of the first DDR chip 1 in the first area 7c and the chip mounting area of the controller chip 4 in the second area 7d, FIG. Since the convex (projection) dam portion 7 i is formed as shown in f), it is possible to prevent the NCP 10 from flowing out to the second region 7 d side which is the chip mounting region of the controller chip 4.

  Thereafter, the first main surface 1a, the plurality of first electrode pads 1c formed on the first main surface 1a, the plurality of gold bump electrodes 8 respectively formed on the plurality of first electrode pads 1c, A first DDR chip 1 having a first rear surface 1b opposite to the first main surface 1a is prepared, and the first main surface 1a faces the upper surface 7a of the wiring board 7 as shown in FIG. In addition, the first DDR chip 1 is disposed on the first region 7 c of the wiring substrate 7. That is, the first DDR chip 1 is arranged on the chip mounting area of the first DDR chip 1 in the first area 7c shown in FIG.

  Thereafter, heat is applied to the wiring substrate 7 to melt the first bonding lead solder material 5 formed on the first bonding lead 7e and to form the first DDR chip 1 as shown in FIG. 15 (g). The plurality of gold bump electrodes 8 and the plurality of first bonding leads 7e of the wiring board 7 are electrically connected by the first bonding lead solder material 5 (flip chip bonding (1) is performed).

  Also in this case, on the upper surface 7a of the wiring substrate 7, between the chip mounting area of the first DDR chip 1 and the chip mounting area of the controller chip 4 in the second area 7d, FIG. Since the convex dam portion 7i is formed as shown in f), the NCP 10 can be prevented from flowing out to the second region 7d side which is the chip mounting region of the controller chip 4.

  Thereafter, as shown in the small process of step S5 in FIG. 12, the NCP 10 is cured by performing a curing bake (150 ° C./15 minutes), and as shown in FIGS. 15 (e) to 15 (g), the first DDR chip 1 Complete flip chip bonding. Note that the cure bake also serves as a dehumidifying treatment.

  Next, the flip chip bonding (2) in step S6 of FIG. 12 is performed. Here, as shown in FIGS. 16A to 16C, the nonvolatile memory chip 3 is flip-chip bonded. First, as shown in the small process of step S6 in FIG. 12, cleaning by plasma processing is performed. That is, the upper surface 7a of the wiring board 7 and the first bonding lead solder material 5 are cleaned by plasma cleaning, and thereby, it is possible to improve the bonding strength and the filling property of the NCP 10 in flip chip bonding.

  FIG. 16B shows the AA cross section of FIG.

  Thereafter, NCP 10 is applied to the chip mounting area of the nonvolatile memory chip 3 in the first area 7 c of the upper surface 7 a of the wiring board 7. Also here, the NCP 10 is dropped onto the chip mounting area of the nonvolatile memory chip 3 on the wiring substrate 7 through the nozzle and applied.

  In flip chip bonding of the nonvolatile memory chip 3, since the gap between the nonvolatile memory chip 3 and the wiring substrate 7 is narrow, the upper surface of the wiring substrate 7 is mounted before mounting the nonvolatile memory chip as in the case of the first DDR chip 1. The NCP 10 is first applied to the chip mounting area of the nonvolatile memory chip 3 of 7a, and the nonvolatile memory chip 3 is mounted after the application.

  Thereby, even if the gap between the nonvolatile memory chip 3 and the wiring board 7 is narrow, the NCP 10 can be reliably embedded in the gap between the nonvolatile memory chip 3 and the wiring board 7 without forming a void.

  Thereafter, the first main surface 3a, the plurality of first electrode pads 3c formed on the first main surface 3a, the plurality of gold bump electrodes 8 respectively formed on the plurality of first electrode pads 3c, A nonvolatile memory chip 3 having a first back surface 3b opposite to the first main surface 3a is prepared, and the first main surface 3a faces the upper surface 7a of the wiring substrate 7 as shown in FIG. As described above, the nonvolatile memory chip 3 is disposed on the first region 7 c of the wiring substrate 7. That is, the nonvolatile memory chip 3 is arranged on the chip mounting region of the nonvolatile memory chip 3 in the first region 7c shown in FIG.

  Thereafter, heat is applied to the wiring substrate 7 to melt the first bonding lead solder material 5 formed on the first bonding lead 7e and form it on the nonvolatile memory chip 3 as shown in FIG. The plurality of gold bump electrodes 8 and the plurality of first bonding leads 7e of the wiring board 7 are electrically connected to each other by the first bonding lead solder material 5 (flip chip bonding (2) is performed).

  Then, as shown in the small process of step S6 of FIG. 12, the NCP 10 is cured by performing a curing bake (150 ° C./15 minutes), and as shown in FIGS. 16A to 16C, the nonvolatile memory chip 3 Complete flip chip bonding. Note that the cure bake also serves as a dehumidifying treatment.

  Next, flip chip bonding (3) in step S7 of FIG. 12 is performed. Here, as shown in FIGS. 16D to 16F, the second DDR chip 2 is flip-chip bonded. In performing flip chip bonding (3), there are a total of two curing baking steps at the end of the flip chip bonding (1) and (2) steps. However, since the baking time of the memory chip is short, the curing baking step is performed. Even if it is included twice, the oxide film is not formed on the first bonding lead solder material 5 so much, and since the plasma cleaning is first performed in each process, the oxide film is removed although it is a small amount. Therefore, flip chip bonding (3) can be performed. The memory chip is baked at a temperature / time of 150 ° C./15 minutes, which is lower and shorter than the time / temperature (165 ° C./2 hours) of curing after the controller chip 4 is underfilled.

  In addition, FIG.16 (e) shows the AA cross section of FIG.16 (d).

  First, as shown in the small process of step S7 in FIG. 12, cleaning by plasma processing is performed. That is, the upper surface 7a of the wiring board 7 and the first bonding lead solder material 5 are cleaned by plasma cleaning, and thereby, it is possible to improve the bonding strength and the filling property of the NCP 10 in flip chip bonding.

  Thereafter, NCP 10 is applied to the chip mounting area of the second DDR chip 2 in the first area 7 c of the upper surface 7 a of the wiring board 7. Also here, the NCP 10 is dropped onto the chip mounting area of the second DDR chip 2 of the wiring substrate 7 through the nozzle and applied.

  Also in the flip chip bonding of the second DDR chip 2, the gap between the second DDR chip 2 and the wiring substrate 7 is narrow like the first DDR chip 1 and the nonvolatile memory chip 3, so that it is difficult to inject the NCP 10 after the second DDR chip is mounted. . Therefore, before mounting the second DDR chip, the NCP 10 is first applied to the chip mounting area of the second DDR chip 2 in the first area 7c of the upper surface 7a of the wiring board 7, and after the application, mounting of the second DDR chip 2 is performed. Do.

  Thereby, even if the gap between the second DDR chip 2 and the wiring board 7 is narrow, the NCP 10 can be reliably embedded in the gap between the second DDR chip 2 and the wiring board 7 without forming a void.

  Note that, on the upper surface 7a of the wiring board 7, between the chip mounting area of the second DDR chip 2 in the first area 7c and the chip mounting area of the controller chip 4 in the second area 7d, and the second DDR chip in the first area 7c. A convex dam 7i is formed between the chip mounting area 2 and the chip mounting area of the nonvolatile memory chip 3 as shown in FIGS. 16D and 16E. It is possible to prevent the controller chip 4 from flowing out to the second area 7 d side, which is the chip mounting area, or to the chip mounting area of the nonvolatile memory chip 3.

  Thereafter, the first main surface 2a, the plurality of first electrode pads 2c formed on the first main surface 2a, the plurality of gold bump electrodes 8 respectively formed on the plurality of first electrode pads 2c, A second DDR chip 2 having a first back surface 2b opposite to the first main surface 2a is prepared, and the first main surface 2a faces the upper surface 7a of the wiring board 7 as shown in FIG. In addition, the second DDR chip 2 is disposed on the first region 7 c of the wiring board 7. That is, the second DDR chip 2 is arranged on the chip mounting region of the second DDR chip 2 in the first region 7c shown in FIG.

  Thereafter, heat is applied to the wiring board 7 to melt the first bonding lead solder material 5 formed on the first bonding lead 7e and to form the second DDR chip 2 as shown in FIG. 16 (f). The plurality of gold bump electrodes 8 and the plurality of first bonding leads 7e of the wiring board 7 are electrically connected to each other by the first bonding lead solder material 5 (flip chip bonding (3) is performed).

  Also in this case, on the upper surface 7a of the wiring substrate 7, between the chip mounting area of the second DDR chip 2 in the first area 7c and the chip mounting area of the controller chip 4 in the second area 7d, and the first area 7c. A convex dam portion 7i is formed between the chip mounting area of the second DDR chip 2 and the chip mounting area of the nonvolatile memory chip 3 as shown in FIGS. Therefore, it is possible to prevent the NCP 10 from flowing out to the second region 7d side which is the chip mounting region of the controller chip 4 or the chip mounting region of the nonvolatile memory chip 3.

  After that, as shown in the small process of step S7 in FIG. 12, cure baking (150 ° C./40 minutes) is performed to cure the NCP 10, and as shown in FIGS. 16 (d) to (f), the second DDR chip 2 Complete flip chip bonding. Note that the cure bake also serves as a dehumidifying treatment.

  Next, flip chip bonding (4) shown in step S8 of FIG. 12 is performed. Here, as shown in FIGS. 17A to 17C, flip chip bonding of the controller chip 4 is performed. When performing flip chip bonding of the controller chip 4, the second bonding lead solder material 6 applied to each of the plurality of second bonding leads 7 f for the controller chip 4 has already been prepared at the stage of preparing the wiring board 7. It has been applied. That is, the wiring board 7 in which the second bonding lead solder material 6 is previously applied to each of the plurality of second bonding leads 7f is prepared.

  FIG. 17B shows the AA cross section of FIG.

  Thereafter, the wet back shown in the small process of S8 in FIG. 12 is performed. The wet back is flux application + reflow, and thereafter, the oxide film on the surface of the second bonding lead solder material 6 is removed by washing.

  In other words, since the three memory chips of the first DDR chip 1, the second DDR chip 2, and the nonvolatile memory chip 3 are already mounted, the second bonding lead solder material 6 of the wiring board 7 is also subjected to a plurality of times. Heat is applied, and the oxide film on the surface of the second bonding lead solder material 6 is previously removed before the controller chip 4 is arranged.

  As shown in FIGS. 15 (c) and 15 (d), the second bonding lead solder material 6 and the first bonding lead solder material 5 are thicker than the second bonding lead solder material 6. About 4 times thicker and more solder. Therefore, in the second bonding lead solder material 6, the oxide film can be removed (wet back) by flux application + reflow even at this stage. In other words, in the present embodiment, the mounting order of the controller chip 4 having a thick solder thickness (a large amount of solder) as in the second bonding lead solder material 6 is followed. As described above, a memory chip having a small solder thickness (a small amount of solder) is first mounted.

  Further, since the reflow process at the time of wet back is not preferable for the thin first bonding lead solder material 5 before chip mounting on the memory chip side, the flip chip bonding of the memory chip is completed first, and then the controller Flip chip bonding of the chip 4 is performed.

  In order to enhance the resistance to the wet back cleaning, the NCP 10 is hardened by a cure bake in each of the flip chip bonding (1), (2), and (3), thereby promoting the curing of the resin on the memory chip side. Keep it. That is, the resistance of the resin (NCP10) on the memory chip side during the wet-back of the flip chip bonding (4) is increased.

  After the wet back and cleaning, flip chip bonding (4) is performed.

  First, the second main surface 4a, the plurality of second electrode pads 4c formed on the second main surface 4a, the plurality of solder bump electrodes 9 respectively formed on the plurality of second electrode pads 4c, The controller chip (second semiconductor chip) 4 having the first back surface 2b opposite to the second main surface 4a is arranged so that the second main surface 4a faces the upper surface 7a of the wiring substrate 7 in the first state. It arrange | positions on 2 area | region 7d.

  Thereafter, heat is applied to the wiring board 7. At that time, the solder bump electrodes 9 on the controller chip 4 and the second bonding lead solder material 6 on the wiring substrate 7 are rubbed together in a heated state (this connection method is hereinafter also referred to as a mechanical scrub). (2) The bonding lead solder material 6 and the oxide film adhering to the surface of the solder bump electrode 9 on the controller chip 4 are removed and then connected.

  Further, by heating the wiring substrate 7, the plurality of solder bump electrodes 9 are melted, and the plurality of solder bump electrodes 9 of the controller chip 4 and the plurality of second bonding leads 7 f of the wiring substrate 7 are electrically connected to each other. To do.

  Thereby, as shown in FIGS. 17A to 17C, the flip chip bonding (4) of the controller chip 4 is completed.

  Thereafter, underfill application shown in step S9 of FIG. 12 is performed. That is, after the controller chip 4 is mounted, the underfill resin 12 is injected between the controller chip 4 and the wiring board 7. Since the solder bump electrode 9 of the controller chip 4 is high, the gap between the controller chip 4 and the wiring board 7 is wide (large). Therefore, the underfill resin 12 is applied after mounting the controller chip.

  Before underfill coating, first, baking (150 ° C./8 hours) shown in the small process of S9 in FIG. 12 is performed to surely cure NCP 10 applied by flip chip bonding (1) to (3). Let Thereafter, plasma is performed to clean the upper surface 7a of the wiring board 7, mainly between the wiring board 7 and the controller chip 4.

  Thereafter, underfill coating is performed. Here, the underfill resin 12 is dropped onto the outer peripheral portion of the controller chip 4 through the nozzle and penetrates into the gap between the wiring board 7 and the controller chip 4. Thereby, as shown in FIGS. 17D to 17F, the application of the underfill resin 12 is completed. Here, FIG. 17E shows the AA cross section of FIG.

  As shown in FIG. 17 (d), on the upper surface 7a of the wiring substrate 7, between the controller chip 4 in the second region 7d and the first DDR chip 1 in the first region 7c, and in the second region 7d. 4 and the second DDR chip 2 in the first region 7c, a convex dam portion 7i is formed, so that the underfill resin 12 can be prevented from flowing out toward the first region 7c. .

  Thereafter, appearance inspection and cure baking (165 ° C./2 hours) are performed to cure the underfill resin 12.

  The controller chip 4 according to the present embodiment has a wide gap between the controller chip 4 and the wiring board 7, and thus the case where the underfill resin 12 is applied after mounting the chip has been described. However, the gap between the controller chip 4 and the wiring board 7 is described. In the case of a narrow chip like a memory chip, it may be a pre-coating which is applied before mounting the chip. In particular, when the controller chip 4 is a chip with a small number of bump electrodes such as a one-row pad array (for example, center pad array), a flip chip mounting process (the main surface of the semiconductor chip faces the upper surface 7a of the wiring substrate 7). Thus, in the step of mounting the semiconductor chip on the wiring substrate), the mounting balance of the semiconductor chip becomes unstable, so that the first application (application before mounting the chip) is preferable in consideration of the stability of the semiconductor chip. .

  Thereafter, ring attachment shown in step S10 of FIG. 12 is performed. Here, as shown in FIGS. 18A and 18B, the seal ring 15 is disposed so as to surround the four semiconductor chips on the upper surface 7 a of the wiring substrate 7, and the seal ring 15 is bonded via the adhesive 18. To do. That is, four semiconductor chips are arranged inside the seal ring 15, and the seal ring 15 is bonded to the upper surface 7 a of the wiring substrate 7 with the adhesive 18. Here, FIG. 18B shows the AA cross section of FIG.

  At that time, an index mark 7j as shown in FIG. 1 is formed at one of the four corners of the upper surface 7a of the wiring board 7, and the seal ring 15 has a corner so that the index mark 7j can be seen. Has a tapered shape. The index mark 7j attached to the corner of the upper surface 7a of the wiring board 7 indicates, for example, a direction for unifying (recognizing) the chip arrangement or the like on the wiring board 7, or for positioning. All four corners of the seal ring 15 are tapered so that they can be seen after the seal ring is bonded.

  After bonding the seal ring, the four semiconductor chips are surrounded by the seal ring 15 on the upper surface 7a of the wiring board 7.

  Then, heat spreader shown in step S11 of FIG. 12 is performed. Here, as shown in FIGS. 18C to 18E, the seal ring 15 and the heat spreader 16 are bonded by the adhesive 18. As a result, the opening of the seal ring 15 is blocked by the heat spreader 16, and the upper part of the four semiconductor chips is covered by the heat spreader 16, so that the four semiconductor chips cannot be seen from the outside. Here, FIG.18 (d) shows the AA cross section of FIG.18 (c).

  When the heat spreader 16 is bonded, of the four semiconductor chips, only the controller chip 4 is bonded to the heat spreader 16 through the silicone resin 17 on the second back surface 4b as shown in FIG. . That is, since the controller chip 4 generates a large amount of heat as described above, the second back surface 4b of the controller chip 4 is bonded to the heat spreader 16 via the silicone resin 17 in order to improve heat dissipation.

  At this time, in order to prevent the heat generated by the controller chip 4 from being transmitted to the other three memory chips, a gap portion 19 is provided between each of the other three memory chips and the heat spreader 16 to define the heat spreader 16. Avoid contact.

  After the heat spreader is bonded, baking (150 ° C./4.5 hours) is performed to cure the adhesive 18 and the silicone resin 17.

  Thereafter, BGA ball attachment shown in step S12 of FIG. 12 is performed. Here, as shown in FIGS. 19A and 19B, the BGA balls 11 as a plurality of external terminals are connected to the lower surface 7b of the wiring board 7 in a grid pattern. FIG. 19B shows the AA cross section of FIG. After mounting the BGA ball, reflow and cleaning are performed to complete the assembly of the SIP 13.

  Next, a modification of the present embodiment will be described.

  FIG. 20 is a first modification of the present embodiment, and shows an assembly flow when flux cleaning is applied to the connection of the controller chip 4 instead of the mechanical scrub.

  That is, since the gap between the controller chip 4 and the wiring board 7 is wide, it is possible to allow the cleaning liquid for cleaning the flux to enter the gap, and thus it is possible to perform the flux cleaning. That is, in the flip chip bonding (4) process shown in step S8 of FIG. 20, not the mechanical scrub but flux cleaning is employed as the oxide film removal means of the solder material at the time of flip chip bonding of the controller chip 4. .

  In step S8 of FIG. 20, first, flux transfer is performed to apply the flux to the solder bump electrodes 9 on the controller chip 4. Thereafter, the wiring board 7 is arranged on the second bonding lead solder material 6 of the wiring board 7, and the wiring board 7 is heated to melt the solder bump electrodes 9 and perform solder connection. Thereafter, reflow and cleaning are performed, and the flip chip bonding of the controller chip 4 is completed.

  Of the steps shown in FIG. 20, the steps other than step S8 are the same as the steps other than step S8 shown in FIG.

  In addition, when the gap between the semiconductor chip and the wiring board 7 becomes narrower as the semiconductor device (SIP 13) becomes thinner in the future, the flux cleaning liquid (cleaning liquid) is not sufficiently supplied to the gap. There is a risk of voids. In such a case, it is preferable to employ a mechanical scrub.

  Further, when flux cleaning is employed at the time of solder connection, the solder pre-coating on the wiring substrate 7 side, that is, the application of the second bonding lead solder material 6 to the second bonding lead 7f of the wiring substrate 7 is not necessarily performed. Alternatively, the solder pre-coating on the wiring board 7 side may be omitted.

  Next, FIG. 21 shows a second modification of the present embodiment, in which flip chip bonding of each memory chip is performed collectively in one process. That is, underfill (NCP10) coating of each memory chip is performed after flip chip bonding of the three memory chips is completed (hereinafter, this is also referred to as post-coating). That is, when the underfill coating on each memory chip may be post-coating, the flip chip bonding of each memory chip to the wiring substrate 7 is performed first, and then the underfill coating on each memory chip is performed later. It is performed by application.

  Specifically, in step S25 of FIG. 21, after baking (150 ° C./40 minutes) and plasma processing, flip chip bonding (1) to (3) is continuously performed, and three memory chips are further formed. On the other hand, after applying underfill (NCP10), curing is performed collectively. Of the steps shown in FIG. 21, steps other than step S25 are the same as steps other than steps S5, 6, and 7 shown in FIG.

  As described above, when the underfill application to each memory chip can be performed after the application, the memory chip is mounted together and then the underfill application is performed to each memory chip by the post-application. Simplification can be achieved.

  In the assembly flow shown in FIG. 21, the removal of the oxide film of the solder material when the controller chip 4 is mounted may be either a mechanical scrub or a flux cleaning.

  Moreover, the assembly of the second modification shown in FIG. 21 is also a summary of the cure baking process. In other words, the cure baking process for each memory chip is not limited to the process performed every time one memory chip is mounted, but after all the memory chips (or up to the controller chip) are mounted, finally the final curing is performed. May be. However, when the process (apparatus) for mounting the memory chip and the process (apparatus) for mounting the controller chip are different, it is preferable to carry out a curing bake every time each chip is mounted because a transfer process is performed.

  According to the semiconductor device (SIP 13) and the manufacturing method of the present embodiment, the controller chip (solder bump electrode product) 4 using the solder bump electrodes 9 manufactured by different processes (or configurations), and the gold bumps In the assembly of the SIP 13 in which three memory chips (gold bump electrode products) using the electrodes 8 are mixedly mounted, the memory chip is first mounted on the wiring board 7 and then the controller chip 4 is mounted, -Gold-solder connection can be performed in a state where an oxide film is not substantially formed on the solder material for solder connection.

  Thereby, in flip chip bonding of each memory chip, the gold-solder connection can be brought into a good connection state, and as a result, the mounting failure of the memory chip can be reduced and the reliability of the SIP 13 can be improved. .

  Since the memory chip (gold bump electrode product) has a smaller bump electrode size (height) than the controller chip 4 (solder bump electrode product), the gap between the memory chip and the upper surface 7a of the wiring board 7 is narrow. Therefore, flux cleaning is difficult (the cleaning liquid is difficult to be supplied). In the case of a single row pad (for example, a center pad arrangement), the mounting balance is unstable before the NCP 10 is filled. Therefore, when mounting a one-row pad semiconductor chip, the NCP 10 is placed on the wiring substrate 7 in advance and then the semiconductor chip is mounted, so that the cleaning liquid is applied to the joint between the gold bump electrode 8 and the first bonding lead 7e. It becomes difficult to be supplied. Further, when the underfill resin 12 is filled after the memory chip is mounted without first arranging the NCP 10 on the wiring substrate 7, the connection step between the gold bump electrode 8 and the first bonding lead 7 e of the wiring substrate 7. It is necessary to carry out from the high temperature state to the process of curing the underfill resin 12. Therefore, if the cleaning process is performed before filling the underfill resin 12, the temperature of the joint between the gold bump electrode 8 and the first bonding lead 7e is lowered by the flux cleaning process and easily breaks ( (This is because the bonding area with the bonding lead is smaller than the solder bump electrode product).

  Because of the above reasons, flux cleaning is difficult (when an oxide film is formed on a solder material for gold-solder connection, it is not easy to remove the oxide film), so that the oxide film is not formed as in this embodiment. Thus, the memory chip is mounted on the wiring board 7 before the controller chip 4.

  Further, in the SIP 13 in which the memory chip that is a gold bump electrode product and the controller chip 4 that is a solder bump electrode product are mixedly mounted, a seal ring 15 that surrounds the memory chip and the controller chip 4 on the wiring substrate 7, and this seal ring 15 And the heat spreader 16 that covers the memory chip and the controller chip 4, and the controller chip 4 is connected to the heat spreader 16 via the silicone resin 17. The generated heat can be dissipated through the heat spreader 16.

  As a result, the heat dissipation of the SIP 13 can be improved.

  Further, in the SIP 13 in which the memory chip that is the gold bump electrode product and the controller chip 4 that is the solder bump electrode product are mixedly mounted, the seal ring 15 that surrounds the memory chip and the controller chip 4 on the wiring substrate 7, the memory chip and the controller By providing the heat spreader 16 that covers the chip 4, the three memory chips and the controller chip 4 can be hidden from the appearance.

  As a result, the tamper resistance of the SIP 13 can be improved.

  Further, on the upper surface 7 a of the wiring substrate 7, between the chip mounting area of the controller chip 4 and the chip mounting area of the first DDR chip 1, and between the chip mounting area of the controller chip 4 and the chip mounting area of the second DDR chip 2. Since the convex dam 7i is formed in each of the areas between the chip mounting area of the nonvolatile memory chip 3 and the chip mounting area of the second DDR chip 2, the NCP 10 and the underfill resin 12 are adjacent to each other. Outflow to the chip mounting area can be prevented. Thereby, it is possible to reduce the occurrence of mounting failure of each semiconductor chip.

  In order to improve the tamper resistance of the SIP 13, the periphery of the four semiconductor chips is surrounded by the seal ring 15, but this is related to reducing the distance between the chips. It is very beneficial to form the dam portion 7i between the chip mounting regions of each semiconductor chip for improvement.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the above-described embodiment, the case where the second bonding lead solder material 6 for the controller chip is applied to the second bonding lead 7f in advance when the wiring board 7 is prepared has been described. The lead solder material 6 is not limited to the one previously applied in the preparation stage of the wiring board 7, and may be applied after the wiring board 7 is prepared.

  In the above embodiment, the controller chip 4 has a plurality of second electrode pads 4c and post leads 4f connected and disposed directly above the second electrode pads 4c on the second main surface 4a. In the controller chip 4, the arrangement pitch of the second electrode pads 4c on the second main surface 4a and the arrangement pitch of the surface electrodes (post leads 4f) connected thereto are described. It may be a chip whose pitch is converted by a lead-out wiring (rewiring) that connects the two.

  Further, in the above-described embodiment, the case where the dam portion 7i formed on the upper surface 7a of the wiring substrate 7 has a convex shape (projection) made of silk printing or the like has been described, but the dam portion 7i has a convex shape (projection). However, the groove may be formed in the solder resist 7h (insulating film) formed on the upper surface 7a of the wiring board 7. However, the structure in the case of the groove does not cover the entire surface of the wiring board with the sealing body, so it is necessary to form the wiring so that the wiring is not exposed (to prevent corrosion of the exposed wiring and short circuit between the exposed wiring). ).

  In addition, the solder material applied to the region where the gold bump electrode product (memory chip) is mounted may be applied at the preparation stage of the wiring board 7, but is naturally oxidized if it is exposed to the atmosphere for a long time. Therefore, it is preferable to apply it immediately before mounting the gold bump electrode product.

  The present invention is suitable for an electronic device having a plurality of semiconductor chips.

It is a top view which permeate | transmits and shows an example of the structure of the semiconductor device of embodiment of this invention through a heat spreader. It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. It is an expanded sectional view which shows the detailed structure of FIG. FIG. 2 is an enlarged plan view illustrating an example of a structure of a main surface of a DDR chip mounted on the semiconductor device illustrated in FIG. 1. It is a partial expanded sectional view which shows an example of the structure cut | disconnected along the AA line shown in FIG. FIG. 2 is an enlarged plan view showing an example of a structure of a main surface of a FLASH chip mounted on the semiconductor device shown in FIG. 1. FIG. 7 is a partial enlarged cross-sectional view showing an example of a structure cut along line AA shown in FIG. 6. FIG. 2 is an enlarged plan view showing an example of a structure of a main surface of a control chip mounted on the semiconductor device shown in FIG. 1. It is the elements on larger scale which expand and show an example of the structure of the A section shown in FIG. FIG. 10 is a partial enlarged cross-sectional view showing an example of a structure cut along line AA shown in FIG. 9. FIG. 2 is a circuit block diagram illustrating an example of a circuit configuration of the semiconductor device illustrated in FIG. 1. FIG. 2 is a manufacturing flow diagram illustrating an example of an assembly procedure of the semiconductor device of FIG. 1. It is the top view and sectional drawing which show an example of the state of each process of step S1-S3 in the manufacturing flow shown in FIG. FIG. 13 is a plan view and a cross-sectional view showing an example of a solder material application state in step S4 in the manufacturing flow shown in FIG. It is the top view and sectional drawing which show an example of the state of each process of step S4 and S5 in the manufacturing flow shown in FIG. It is the top view and sectional drawing which show an example of the state of each process of step S6 and S7 in the manufacturing flow shown in FIG. It is the top view and sectional drawing which show an example of the state of each process of step S8 and S9 in the manufacturing flow shown in FIG. It is the top view and sectional drawing which show an example of the state of each process of step S10 and S11 in the manufacturing flow shown in FIG. It is the top view and sectional drawing which show an example of the state of the process of step S12 in the manufacturing flow shown in FIG. It is a manufacturing flowchart which shows the assembly procedure of the semiconductor device of the 1st modification of embodiment of this invention. It is a manufacturing flowchart which shows the assembly procedure of the semiconductor device of the 2nd modification of embodiment of this invention.

Explanation of symbols

1 First DDR chip (first semiconductor chip)
1a the first main surface 1b first back surface 1c first electrode pad 1d silicon substrate 1e SiO ₂ film 1f polyimide film 2 first 2DDR chip (first semiconductor chip)
2a 1st main surface 2b 1st back surface 2c 1st electrode pad 3 Nonvolatile memory chip (1st semiconductor chip)
3a first main surface 3b first back surface 3c first electrode pad 3d silicon substrate 3e SiO ₂ film 4 controller chip (second semiconductor chip)
4a Second main surface 4b Second back surface 4c Second electrode pad 4d Silicon substrate 4e Insulating film 4f Post lead 5 First bonding lead solder material 6 Second bonding lead solder material 7 Wiring substrate 7a Upper surface 7b Lower surface 7c First region 7d 2nd region 7e 1st bonding lead 7f 2nd bonding lead 7g Land 7h Solder resist 7i Dam part 7j Index mark 8 Gold bump electrode 9 Solder bump electrode 10 NCP (non-conductive resin)
11 BGA ball 12 Underfill resin 13 SIP (semiconductor device)
14 External LSI
15 Seal ring (ring member)
16 Heat spreader 17 Silicone resin (insulating resin)
18 Adhesive 19 Gap 20 Mask 20a Opening 20b Recess

Claims (18)

A method for manufacturing a semiconductor device comprising the following steps:
(A) an upper surface, a plurality of first bonding leads formed in a first region of the upper surface, a plurality of second bonding leads formed in a second region of the upper surface, and a lower surface opposite to the upper surface And a step of preparing a wiring board having a plurality of lands formed on the lower surface;
(B) applying a first bonding lead solder material to each of the plurality of first bonding leads;
(C) a first main surface, a plurality of first electrode pads formed on the first main surface, a plurality of gold bump electrodes respectively formed on the plurality of first electrode pads, and the first A step of disposing a first semiconductor chip having a first back surface opposite to the main surface on the first region of the wiring board such that the first main surface faces the upper surface of the wiring board. ;
(D) Heat is applied to the wiring board to melt the first bonding lead solder material, and the plurality of gold bump electrodes of the first semiconductor chip and the plurality of first bonding leads of the wiring board are respectively connected. Electrically connecting;
(E) a second main surface, a plurality of second electrode pads formed on the second main surface, a plurality of solder bump electrodes respectively formed on the plurality of second electrode pads, and the second Disposing a second semiconductor chip having a second back surface opposite to the main surface on the second region of the wiring substrate such that the second main surface faces the upper surface of the wiring substrate; ;
(F) Applying heat to the wiring board to melt the plurality of solder bump electrodes, and electrically connecting the plurality of solder bump electrodes of the second semiconductor chip and the plurality of second bonding leads of the wiring board, respectively. Connecting to.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second bonding lead solder material applied to each of the plurality of second bonding leads is applied at the stage of preparing the wiring board in the step (a). When mounting the second semiconductor chip, the oxide film adhering to the surface of the second bonding lead solder material is removed by an oxide film removing means and then mounted. Method.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the oxide film removing unit heats the solder bump electrodes on the second semiconductor chip and the second bonding lead solder material on the wiring board. A method of manufacturing a semiconductor device, characterized by being rubbed together.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the oxide film attached to the surface of the second bonding lead solder material is removed in advance by the oxide film removing means when the second semiconductor chip is mounted. A method of manufacturing a semiconductor device, wherein a flux is applied to a second bonding lead solder material, and an oxide film on the second bonding lead solder material is removed by reflow.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the oxide film removing means is flux cleaning.   2. The method of manufacturing a semiconductor device according to claim 1, wherein before the first semiconductor chip is disposed on the wiring substrate in the step (c), the upper surface of the wiring substrate and the first bonding lead are disposed by plasma cleaning. A method of manufacturing a semiconductor device, comprising: cleaning a solder material.   2. The method of manufacturing a semiconductor device according to claim 1, wherein a non-conductive resin is applied to the first region before the first semiconductor chip is disposed on the first region of the wiring board in the step (c). A method of manufacturing a semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, wherein after the step (f), an underfill resin is injected between the second semiconductor chip and the wiring board.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first bonding lead solder material is applied to each of the plurality of first bonding leads in the step (b). The second bonding lead solder material is coated on the first bonding lead of the wiring board through the opening of the mask in a state where the second bonding lead solder material is covered with a mask. A method for manufacturing a semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, wherein a mounting height of the second semiconductor chip is higher than a mounting height of the first semiconductor chip.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the plurality of first electrode pads are formed in a row on the first main surface of the first semiconductor chip. Method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first semiconductor chip includes two memory chips each including a memory circuit that performs data transfer in synchronization with both rising and falling edges of an external clock signal. A method of manufacturing a semiconductor device, wherein a nonvolatile memory chip is mounted.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first semiconductor chip includes three memory chips, and the second semiconductor chip includes one controller chip, and the three memory chips and the one semiconductor chip are provided. 2. A method of manufacturing a semiconductor device according to claim 1, wherein the controller chip is placed flat on the diagonal line on the upper surface of the rectangular wiring board.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are mounted flat on the wiring board, and surround the first semiconductor chip and the second semiconductor chip. And a heat spreader connected to the ring member and covering the first semiconductor chip and the second semiconductor chip is provided on the wiring board.   15. The method of manufacturing a semiconductor device according to claim 14, wherein the second back surface of the second semiconductor chip is connected to the heat spreader via an insulating resin.   16. The method of manufacturing a semiconductor device according to claim 15, wherein the insulating resin is a silicone resin.   15. The method of manufacturing a semiconductor device according to claim 14, wherein a gap is formed between the first semiconductor chip and the heat spreader.   2. The method of manufacturing a semiconductor device according to claim 1, wherein a dam portion for partitioning a semiconductor chip mounting region is formed on the upper surface of the wiring board.

Images