JP2010034234A - Semiconductor device - Google Patents

Abstract

A semiconductor device capable of suppressing leakage current is provided.
A semiconductor device includes an element region, a tunnel insulating film formed on the element region, a charge storage insulating film formed on the tunnel insulating film, and a charge storage insulating film. First and second memory cells each including a formed block insulating film 60 and a control gate electrode 70 formed on the block insulating film 60; an element region 20 of the first and second memory cells; An isolation region 20 formed between the tunnel insulating film 30 and the charge storage insulating film 40, and the block insulating film 60 includes a first insulating film 61 containing a metal element and oxygen as main components, The second insulating film 62 containing silicon and oxygen as main components is formed, and at least a part of the block insulating film 60 is formed on the element isolation region 50.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device.

  A nonvolatile semiconductor memory device using a charge storage insulating film capable of trapping charges as a charge storage layer has been proposed (see Patent Document 1). In this charge trap type nonvolatile semiconductor memory device, charges are accumulated in the charge storage insulating film by trapping the charge injected into the charge storage insulating film through the tunnel insulating film at the trap level in the charge storage insulating film. Is done. As a typical charge trap type nonvolatile semiconductor memory device, a MONOS type or SONOS type nonvolatile semiconductor memory device is known.

However, in the charge trap type nonvolatile semiconductor memory device, it can be said that the configuration and formation method of the block insulating film provided between the charge storage insulating film and the control gate electrode are not necessarily optimized. Absent.
JP 2004-158810 A

  An object of the present invention is to provide a semiconductor device having an optimized block insulating film.

  A semiconductor device according to one aspect of the present invention includes an element region, a tunnel insulating film formed on the element region, a charge storage insulating film formed on the tunnel insulating film, and the charge storage insulating film. First and second memory cell transistors each including a formed block insulating film and a control gate electrode formed on the block insulating film, an element region of the first memory cell transistor, and a tunnel insulating film And a charge storage insulating film and an element isolation region formed between the element region of the second memory cell transistor, the tunnel insulating film and the charge storage insulating film, and the first and second memories The block insulating film of each cell transistor is a product of a first insulating film containing a metal element and oxygen as main components and a second insulating film containing silicon and oxygen as main components. It is formed with a film, wherein at least a portion of said first and second memory cell transistors each of the block insulating film is characterized by being formed in the device isolation region.

  According to the present invention, it is possible to provide a semiconductor device having an optimized block insulating film.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following embodiments, a charge trap type nonvolatile semiconductor memory device using a charge storage insulating film for charge trapping as a charge storage layer will be described.

(First embodiment)
FIG. 1 is a cross-sectional view along the word line direction schematically showing the basic structure of the semiconductor device according to the present embodiment.

  First, a schematic configuration of the present embodiment will be described with reference to FIG.

  As shown in FIG. 1, an element region 20 is formed in a semiconductor substrate (silicon substrate) 10. A tunnel insulating film 30 is formed on the element region 20, and a charge storage insulating film 40 is formed on the tunnel insulating film 30. An element isolation region 50 is provided so as to isolate the element region 20, the tunnel insulating film 30, and the charge storage insulating film 40 of the memory cell transistors adjacent in the word line direction. A block insulating film 60 having a laminated structure is formed on the charge storage insulating film 40 and the element isolation region 50, and a control gate electrode 70 is formed on the block insulating film 60. That is, the block insulating films 60 of adjacent memory cell transistors are connected on the element isolation region 50.

  The tunnel insulating film 30 is formed of a film containing silicon oxide as a main component. The charge storage insulating film 40 is formed of a film mainly composed of a silicon nitride film. The element isolation region 50 is formed of a silicon oxide film. The block insulating film 60 is formed on the lower-layer insulating film 61 formed on the charge storage insulating film 40 and the element isolation region 50, the intermediate insulating film 62 formed on the lower-layer insulating film 61, and the intermediate insulating film 62. And an upper insulating film 63. The lower insulating film 61 is formed of a film containing a metal oxide, the intermediate insulating film 62 is formed of a film containing a silicon oxide film as a main component, and the upper insulating film 63 is formed of a film containing a metal oxide. ing. The control gate electrode 70 has a two-layer structure of a polycrystalline silicon layer and a tungsten silicide layer.

  According to the embodiment, the charge storage insulating film 40 of adjacent memory cell transistors is isolated by the element isolation region 50. Therefore, the charge accumulated in the charge storage insulating film 40 does not move between adjacent memory cell transistors. For this reason, it is possible to suppress the lateral leakage current caused by the charge storage insulating film 40.

  Further, the block insulating films 60 of adjacent memory cell transistors are connected on the element isolation region. For this reason, it is possible to suppress the leakage current in the vertical direction between the control gate electrode 70 and the semiconductor substrate 10. That is, since the block insulating film 60 is not isolated by the element isolation region 50, it is possible to reliably suppress the vertical leakage current having the interface of the element isolation region 50 as a leak path by the block insulating film 60.

  In the present embodiment, since the block insulating film is formed by the laminated structure of the metal oxide film and the silicon oxide film, the leakage current flowing through the block insulating film 60 can be effectively reduced as described below. Can do.

  A metal oxide film generally has a high dielectric constant and is excellent in leak resistance (high electric field leak resistance) when a high electric field (high voltage) is applied. However, since the metal oxide film has a higher trap level density than the silicon oxide film, the leak resistance (low electric field leak resistance) when a low electric field (low voltage) is applied is inferior to that of the silicon oxide film.

  The block insulating film 60 of this embodiment has a laminated structure of a lower insulating film 61 and an upper insulating film 63 formed of a metal oxide film, and an intermediate insulating film 62 formed of a silicon oxide film. Therefore, as can be seen from the energy band diagram of FIG. 2, high electric field leakage resistance can be ensured by the lower insulating film 61 and the upper insulating film 63, and low electric field leakage resistance can be ensured by the intermediate insulating film 62. Therefore, the leakage current of the block insulating film 60 can be effectively suppressed.

  3 to 8 are cross-sectional views schematically showing a basic manufacturing method of the semiconductor device according to this embodiment. 3A to 8A are cross-sectional views along the bit line direction (channel length direction), and FIGS. 3B to 8B are word line directions (channel width direction). FIG.

  As shown in FIG. 3, a silicon oxide film having a thickness of 5 nm to be a tunnel insulating film 30 is formed on the surface of a semiconductor substrate (silicon substrate) 10 doped with desired impurities in advance by a thermal oxidation method. Thereafter, a silicon nitride film having a thickness of 5 nm to be the charge storage insulating film 40 is deposited by a CVD (Chemical Vapor Deposition) method. Subsequently, an amorphous silicon film 41 serving as a mask material for element isolation processing is deposited on the charge storage insulating film 40 by a CVD method.

  Next, as shown in FIG. 4, the amorphous silicon film 41, the charge storage insulating film 40, and the tunnel insulating film 30 are sequentially etched by RIE (reactive ion etching) using a first resist mask (not shown). . Further, the semiconductor substrate 10 exposed by the etching is etched to form an element isolation trench 500 having a depth of 100 nm.

  Next, as shown in FIG. 5, a silicon oxide film for element isolation is deposited on the entire surface, and the element isolation trench 500 is filled with the silicon oxide film. Thereafter, the silicon oxide film on the surface portion is removed by a CMP (Chemical Mechanical Polishing) method, the surface is flattened, and the element isolation region 50 is formed. At this time, the amorphous silicon film 41 is exposed.

  Next, as shown in FIG. 6, the exposed amorphous silicon film 41 is selectively etched away with a chemical solution or the like. Next, the exposed surface of the silicon oxide film in the element isolation region 50 is etched to the same height as the charge storage insulating film 40 using a diluted hydrofluoric acid solution. Thereafter, a hafnium oxide film having a thickness of 4 nm is formed as the lower insulating film 61 of the block insulating film 60 by an ALD (Atomic Layer Deposition) method. Subsequently, a silicon oxide film having a thickness of 4 nm, which becomes the intermediate insulating film 62 of the block insulating film 60, is deposited on the lower insulating film 61 by the CVD method. Further, a hafnium oxide film to be the upper insulating film 63 of the block insulating film 60 is deposited on the intermediate insulating film 62 by the ALD method.

  Next, as shown in FIG. 7, a 100 nm thick conductive film 70 having a two-layer structure composed of a polycrystalline silicon layer / tungsten silicide layer to be the control gate electrode 70 is deposited by the CVD method. Subsequently, a silicon nitride film 80 serving as an RIE mask material is deposited by a CVD method. Thereafter, a silicon nitride film 80, a conductive film 70, a block insulating film 60, a charge storage insulating film 40, a RIE method using a second resist mask (not shown) having a pattern orthogonal to the first resist mask, The tunnel insulating film 30 is sequentially etched.

  Next, as shown in FIG. 8, using the gate structure obtained as described above as a mask, a dopant element such as arsenic is introduced into the exposed surface area of the semiconductor substrate 10 by ion implantation or the like. Then, the source / drain impurity diffusion layer 20 is formed by performing thermal annealing. Subsequently, an interlayer insulating film 90 is formed using a CVD method or the like. Further, a wiring layer or the like (not shown) is formed using a known technique to complete the nonvolatile semiconductor memory device.

  According to the embodiment, the element isolation region 50 is formed after the charge storage insulating film 40 is formed. Therefore, the charge storage insulating film 40 of the adjacent memory cell transistor is isolated in the word line direction by the element isolation region 50. For this reason, the movement of electric charge between adjacent memory cell transistors can be suppressed. As a result, it is possible to suppress the threshold fluctuation of the memory cell transistor.

  Further, since the block insulating film 60 is formed after the element isolation region 50 is formed, no element isolation trench is formed in the block insulating film 60. Therefore, the block insulating film 60 can suppress the leakage current at the interface of the element isolation region 50 based on the RIE processing damage when forming the element isolation trench. As a result, the charge retention characteristics of the memory cell transistor can be improved.

(Second Embodiment)
FIG. 9 is a cross-sectional view along the word line direction schematically showing the basic structure of the semiconductor device according to the present embodiment.

  The basic structure and the basic manufacturing method are the same as those in the first embodiment. Therefore, the description about the matter demonstrated in 1st Embodiment and the matter which can be easily guessed from 1st Embodiment is abbreviate | omitted.

  As shown in FIG. 9, an element region 20 is formed in a semiconductor substrate (silicon substrate) 10. A tunnel insulating film 30 is formed on the element region 20, and a charge storage insulating film 40 is formed on the tunnel insulating film 30. On the charge storage insulating film 40, a lower insulating film 61 that is a lower part of the block insulating film 60 is formed. An element isolation region 50 is provided so as to isolate the element region 20, the tunnel insulating film 30, the charge storage insulating film 40, and the lower insulating film 61 of adjacent memory cell transistors. An intermediate insulating film 62 and an upper insulating film 63 of the block insulating film 60 are provided on the lower insulating film 61 and the element isolation region 50, and a control gate electrode 70 is formed on the upper insulating film 63. That is, the intermediate insulating film 62 and the upper insulating film 63 of the block insulating film 60 of the adjacent memory cell transistor are connected on the element isolation region 50.

  The tunnel insulating film 30 is formed of a silicon oxide film. The charge storage insulating film 40 is formed of a silicon nitride film. The element isolation region 50 is formed of a silicon oxide film. The lower insulating film 61 of the block insulating film 60 is formed of a metal oxide film, the intermediate insulating film 62 is formed of a silicon oxide film, and the upper insulating film 63 is formed of a metal oxide film. The control gate electrode 70 has a two-layer structure of a polycrystalline silicon layer and a tungsten silicide layer.

  According to the above embodiment, as in the first embodiment, since the charge storage insulating film 40 is isolated by the element isolation region 50, threshold fluctuation due to charge movement between adjacent memory cell transistors is suppressed. I can do it. Further, since the intermediate insulating film 62 and the upper insulating film 63 of the block insulating film 60 are connected in the word line direction, the leakage current in the vertical direction using the interface of the element isolation region 50 as a leakage path, as in the first embodiment. Can be suppressed.

  The block insulating film 60 of the above embodiment has a laminated structure of a lower insulating film 61 and an upper insulating film 63 formed of a metal oxide film, and an intermediate insulating film 62 formed of a silicon oxide film. Yes. For this reason, as in the first embodiment, the lower insulating film 61 and the upper insulating film 63 can ensure high electric field leakage resistance, and the intermediate insulating film 62 can ensure low electric field leakage resistance. Therefore, the leakage current of the block insulating film 60 can be suppressed.

  10 to 15 are cross-sectional views schematically showing a basic manufacturing method of the semiconductor device according to this embodiment. 10A to 15A are cross-sectional views along the bit line direction, and FIGS. 10B to 15B are cross-sectional views along the word line direction.

  As shown in FIG. 10, a silicon oxide film having a thickness of 5 nm to be a tunnel insulating film 30 is formed on the surface of a semiconductor substrate (silicon substrate) 10 doped with a desired impurity in advance by a thermal oxidation method. Thereafter, a 5 nm thick silicon nitride film to be the charge storage insulating film 40 is deposited by CVD. Subsequently, a 4 nm-thick hafnium oxide film, which becomes the lower insulating film 61 of the block insulating film, is formed on the charge storage insulating film 40 by the ALD method. Thereafter, a silicon nitride film 42 serving as a mask material for element isolation processing is deposited by the CVD method.

  Next, as shown in FIG. 11, the silicon nitride film 42, the lower insulating film 61, the charge storage insulating film 40, and the tunnel insulating film 30 are sequentially etched by RIE using a first resist mask (not shown). . Further, the semiconductor substrate 10 exposed by the etching is etched to form an element isolation trench 500 having a depth of 100 nm.

  Next, as shown in FIG. 12, a silicon oxide film for element isolation is deposited on the entire surface, and the element isolation trench 500 is filled with the silicon oxide film. Thereafter, the silicon oxide film on the surface portion is removed by the CMP method, the surface is flattened, and the silicon nitride film 42 is exposed. Subsequently, using a dilute hydrofluoric acid solution, the silicon oxide film is etched to the same height as the surface of the lower insulating film 61 to form an element isolation region 50.

  Next, as shown in FIG. 13, the exposed silicon nitride film 42 is selectively removed by dry etching. Subsequently, a 4 nm-thick silicon oxide film to be an intermediate insulating film 62 is deposited on the element isolation region 50 and the lower insulating film 61 by a CVD method. Further, a hafnium oxide film to be the upper insulating film 63 is deposited on the intermediate insulating film 62 by the ALD method.

  Next, as shown in FIG. 14, a conductive film 70 having a two-layer structure of a polycrystalline silicon layer / tungsten silicide layer to be the control gate electrode 70 and having a thickness of 100 nm is deposited by the CVD method. Subsequently, a silicon nitride film 80 serving as an RIE mask material is deposited by a CVD method. Thereafter, by the RIE method using a second resist mask (not shown) having a pattern orthogonal to the first resist mask, the silicon nitride film 80, the conductive film 70, the block insulating film 60, the charge storage insulating film 40, and The tunnel insulating film 30 is sequentially etched.

  Next, as shown in FIG. 15, using the gate structure obtained as described above as a mask, a dopant element such as arsenic is introduced into the surface region of the exposed portion of the semiconductor substrate 10 by ion implantation or the like. Then, an impurity diffusion layer 20 for source / drain is formed by performing a thermal annealing process. Subsequently, an interlayer insulating film 90 is formed using a CVD method or the like. Further, a wiring layer or the like (not shown) is formed using a known technique to complete the nonvolatile semiconductor memory device.

  According to the above embodiment, the element isolation region 50 is formed after the charge storage insulating film 40 and the lower insulating film 61 are formed. Therefore, the charge storage insulating film 40 of the adjacent memory cell transistor is isolated in the word line direction by the element isolation region 50. For this reason, as in the first embodiment, the movement of charges between adjacent memory cell transistors can be suppressed.

  In addition, since the intermediate insulating film 62 and the upper insulating film 63 of the block insulating film 60 are formed after the element isolation region 50 is formed, no element isolation trench is formed in the intermediate insulating film 62 and the upper insulating film 63. Therefore, similarly to the first embodiment, the leakage current at the interface of the element isolation region 50 due to the RIE processing damage when forming the element isolation trench can be suppressed by the intermediate insulating film 62 and the upper insulating film 63. As a result, the charge retention characteristics of the memory cell transistor can be improved.

  Further, since the lower insulating film 61 is formed on the charge storage insulating film 40 when the silicon nitride film 42 used as the etching mask is removed, the charge storing insulating film 40 can be protected by the lower insulating film 61. it can. Therefore, it is possible to prevent the reliability of the charge storage insulating film 40 from being lowered.

  In this embodiment, the intermediate insulating film 62 and the upper insulating film 63 are connected between the memory cell transistors by performing element isolation after forming the lower insulating film 61. However, as shown in FIG. 16, even if element isolation processing is performed after the formation of the intermediate insulating film 62, the upper insulating film 63 is connected between the memory cell transistors, so that the same effect as in the above-described embodiment can be obtained. .

  Generally speaking, if the lower part of the block insulating film 60 is isolated in the element isolation region 50 and the upper part of the block insulating film 60 is connected on the element isolation region 50, the effect of this embodiment can be obtained. Is possible.

  In the present embodiment, the surface of the block insulating film 60 is flattened. However, if a part of the multilayer film constituting the block insulating film 60 is connected in the word line direction, for example, As shown in FIG. 17, the interface between the control gate electrode 70 and the upper insulating film 63 of the block insulating film 60 may protrude to the substrate side at the center of the memory cell transistor. In this case, since the electric field concentrates on the protruding portion of the control gate electrode 70, the control power of the control gate electrode 70 with respect to the channel increases, and as a result, the on-current of the memory cell transistor can be increased.

  In the first and second embodiments described above, the lower insulating film and the upper insulating film of the block insulating film are formed of a metal oxide film, and the intermediate insulating film is formed of a silicon oxide film. The upper insulating film may be formed of a silicon oxide film, and the intermediate insulating film may be formed of a metal oxide film.

  The block insulating film may have a two-layer structure. Specifically, the lower insulating film can be formed of a metal oxide film, and the upper insulating film can be formed of a silicon oxide film. It is also possible to form the lower insulating film with a silicon oxide film and the upper insulating film with a metal oxide film.

  Further, the block insulating film may have a laminated structure of four or more layers. For example, as a five-layer structure, a structure in which a metal oxide film, a silicon oxide film, a metal oxide film, a silicon oxide film, and a metal oxide film are sequentially stacked may be used.

  In each of the above-described embodiments, the metal oxide film is used as the upper insulating film and the lower insulating film of the block insulating film. In general, an insulating film containing a metal element and oxygen as main components is used. Can do. Therefore, an element such as silicon may be added to the metal oxide film. For example, as the metal oxide film, in addition to hafnium oxide, zirconium oxide, alumina, lanthanum oxide, hafnium aluminate, lanthanum aluminate, hafnium silicate, or the like may be used.

  In the embodiment described above, the silicon oxide film is used as the intermediate insulating film of the block insulating film. However, in general, an insulating film containing silicon and oxygen as main components can be used. Therefore, an element such as nitrogen may be added to the silicon oxide film.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed constituent elements. For example, even if several constituent requirements are deleted from the disclosed constituent requirements, the invention can be extracted as long as a predetermined effect can be obtained.

1 is a cross-sectional view schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 4 is a diagram illustrating an energy band structure during a write operation according to the first embodiment of the present invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which showed typically the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which showed typically the structure of the modification of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which showed typically the structure of the modification of the semiconductor device which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 20 ... Element region 30 ... Tunnel insulating film 40 ... Charge storage insulating film 50 ... Element isolation region 60 ... Block insulating film 61 ... Lower layer insulating film 62 ... Intermediate insulating film 63 ... Upper layer insulating film 70 ... Control gate electrode 80 ... Silicon nitride film 90 ... Interlayer insulating film

Claims (5)

An element region; a tunnel insulating film formed on the element region; a charge storage insulating film formed on the tunnel insulating film; a block insulating film formed on the charge storage insulating film; and the block insulation First and second memory cell transistors comprising a control gate electrode formed on the film;
An element isolation region formed between the element region, the tunnel insulating film, and the charge storage insulating film of the first memory cell transistor, and the element region, the tunnel insulating film, and the charge storage insulating film of the second memory cell transistor When,
Comprising
Each of the block insulating films of the first and second memory cell transistors includes a first insulating film containing a metal element and oxygen as main components and a second insulating film containing silicon and oxygen as main components. Formed of laminated film,
At least a part of the block insulating film of each of the first and second memory cell transistors is formed on the element isolation region. The lower part of the block insulating film of the first memory cell transistor and the lower part of the block insulating film of the second memory cell transistor are separated by the element isolation region,
2. The semiconductor device according to claim 1, wherein an upper portion of the block insulating film of each of the first and second memory cell transistors includes a portion formed on the element isolation region.   2. The semiconductor device according to claim 1, wherein an upper portion and a lower portion of the block insulating film of each of the first and second memory cell transistors include a portion formed on the element isolation region.   The block insulating film includes the first insulating film formed on the charge storage insulating film, the second insulating film formed on the first insulating film, and the second insulating film. The semiconductor device according to claim 1, further comprising: a third insulating film that is formed on the substrate and contains a metal element and oxygen as main components.   At least the first insulating film of the block insulating film of the first memory cell transistor and at least the first insulating film of the block insulating film of the second memory cell transistor are separated by the element isolation region. The semiconductor device according to claim 4.

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