JP2010034233A - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

A non-volatile semiconductor memory device in which electrical characteristics of a memory cell are improved is provided.
A non-volatile semiconductor memory device 1 is formed by stacking a semiconductor substrate 2 with a first insulating film 6 interposed therebetween, a charge storage layer 7, a second insulating film 13, a third insulating film 14, The fourth insulating film 15, the fifth insulating film 16, the sixth insulating film 17, and the control gate electrode 9 are used. The second insulating film 13 is made of a material containing silicon and oxygen. The fourth insulating film 15 is made of a material having a charge trap density higher than that of the third insulating film 14 and a relative dielectric constant higher than that of the second insulating film 13. The fifth insulating film 16 is made of a material having a charge trap density lower than that of the fourth insulating film 15. The sixth insulating film 17 has a relative dielectric constant lower than that of the fourth insulating film 15 and is made of a material containing silicon and oxygen.
[Selection] Figure 5

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof, and more particularly to a nonvolatile semiconductor memory device in which electrical characteristics of a memory cell are improved and a manufacturing method thereof.

In a normal nonvolatile memory, a plurality of memory cells are arranged along each of the word line direction (channel width direction) and the bit line direction (channel length direction). In recent years, along with the high integration of non-volatile memory, the size of memory cells and the distance between adjacent memory cells have been reduced, and a memory cell having a size and an interval of 100 nm or less between adjacent memory cells has been manufactured. It has come to be. However, as the memory cells become finer, the interference effect increases between adjacent memory cells. In order to suppress such an interference effect, it is necessary to reduce the height of the floating gate electrode by increasing the capacitance (C _ipd ) of the interelectrode insulating film by thinning the interelectrode insulating film. . However, simply thinning the interelectrode insulating film tends to cause an increase in leakage current and a deterioration in dielectric strength voltage, so that it is difficult to obtain desired memory cell characteristics.

As a solution to such a problem, for example, as disclosed in Patent Document 1 described later, a high dielectric film (high dielectric constant insulating film, high-k film) is formed between two upper and lower silicon oxide films. A technique for applying a laminated insulating film (silicon oxide film / high relative dielectric constant insulating film / silicon oxide film) having a three-layer structure sandwiching the electrode as an interelectrode insulating film has been studied. By applying an insulating film including a high dielectric constant insulating film as an interelectrode insulating film, the electric capacity (C _ipd ) of the interelectrode insulating film is increased while reducing the thickness of the interelectrode insulating film, and the floating gate electrode Can be reduced.

  However, if a material with many charge traps is used for the high dielectric constant insulating film, the leakage current is reduced due to the electrolytic relaxation effect due to the trapped charge, but charge detrapping is likely to occur due to the self electric field during charge retention. The charge retention characteristics of the memory cell will deteriorate. On the other hand, when a material with few charge traps is applied to the high dielectric constant insulating film, the charge retention characteristics of the memory cell can be improved, but the leakage current cannot be sufficiently reduced. In particular, when a material with few charge traps is applied to the high dielectric constant insulating film, the increase in leakage current due to electric field concentration at the corners of the floating gate electrode and control gate electrode becomes significant, and the writing speed and erasing speed of the memory cell Deterioration of memory cell characteristics such as a decrease in saturation or a decrease in saturation voltage is likely to occur.

Similarly, as a solution to the above-mentioned problem, there is currently a technique in which a laminated insulating film (ONO film) having a three-layer structure in which a silicon nitride film is sandwiched between two upper and lower silicon oxide films is applied as an interelectrode insulating film. well known. However, even if the ONO film is applied as an interelectrode insulating film, the above-described high relative dielectric constant depends on whether the intermediate nitride film is formed with a film quality with a lot of charge traps or a film quality with a few charge traps. The same problem as in the case of applying a laminated insulating film including an insulating film as an interelectrode insulating film arises.
JP 2006-310661 A

  An object of the present invention is to provide a nonvolatile semiconductor memory device in which the electrical characteristics of a memory cell are improved and a method for manufacturing the same.

  In order to solve the above problems, a nonvolatile semiconductor memory device according to one embodiment of the present invention is provided with a charge storage layer provided over a semiconductor substrate with a first insulating film interposed therebetween, and the charge storage layer. And a second insulating film made of a material containing silicon and oxygen, a third insulating film provided on the second insulating film, and provided on the third insulating film, A fourth insulating film made of a material having a charge trap density higher than that of the third insulating film and a relative dielectric constant higher than that of the second insulating film; and a fourth insulating film provided on the fourth insulating film. And a fifth insulating film made of a material having a charge trap density lower than that of the fourth insulating film, and a dielectric constant higher than that of the fourth insulating film, provided on the fifth insulating film. Low, and from materials containing silicon and oxygen A sixth insulating film and is characterized by comprising a control gate electrode provided on the sixth insulating film.

  In order to solve the above-described problem, a method for manufacturing a nonvolatile semiconductor memory device according to another aspect of the present invention includes a charge storage layer provided on a semiconductor substrate via a first insulating film, and the charge storage layer. A second insulating film made of a material containing silicon and oxygen is provided thereon, a third insulating film is provided on the second insulating film, and the third insulating film is formed on the third insulating film more than the third insulating film. A fourth insulating film made of a material having a high charge trap density and a higher dielectric constant than that of the second insulating film is provided, and a charge trap is formed on the fourth insulating film as compared with the fourth insulating film. A fifth insulating film made of a material having a low density is provided, and a sixth insulating film made of a material containing silicon and oxygen and having a dielectric constant lower than that of the fourth insulating film is provided on the fifth insulating film. And a control gate electrode is provided on the sixth insulating film. It is an.

  According to the present invention, it is possible to provide a nonvolatile semiconductor memory device in which the electrical characteristics of a memory cell are improved and a method for manufacturing the same.

  Embodiments according to the present invention will be described below with reference to the drawings.

(First embodiment)
The first embodiment relates to a technique for improving the performance of an interelectrode insulating film of a memory cell provided in, for example, a nonvolatile memory which is a kind of semiconductor device. In particular, the present invention relates to an interelectrode insulating film having an ideal film structure capable of realizing both a low leakage current characteristic and an excellent charge retention characteristic, and a manufacturing method thereof. Specifically, in the nonvolatile memory according to the present embodiment, an interelectrode insulating film having a structure in which silicon oxide films are stacked on upper and lower interfaces of a charge trapping layer made of a so-called high relative dielectric constant insulating film (high-k film). Form. Then, by locally increasing the charge trap density in the charge trap layer, the leakage current is reduced while maintaining the charge retention characteristics of the interelectrode insulating film. Hereinafter, the first embodiment according to the present invention will be described more specifically and in detail with reference to FIGS. 1 (a) and (b) to FIG.

  First, an outline of the structure of the memory cell portion of the nonvolatile memory 1 as the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. 1A and 1B schematically show a cross-sectional structure of a memory cell portion of a nonvolatile memory 1 using a floating gate electrode 7 as a charge storage layer. Specifically, FIG. 1A is a cross-sectional view taken along the longitudinal direction (channel length direction) of a bit line (not shown) included in the nonvolatile memory 1. FIG. 1B is a cross-sectional view taken along the longitudinal direction (channel width direction) of a word line (control gate electrode) 9 included in the nonvolatile memory 1. 1A is a cross-sectional view taken along the broken line X-X ′ in FIG. 1 (a) and 1 (b) are shown in FIG. 2 (a), (b) to FIG. 7 (a), (b), FIG. The same applies to (b) and FIGS. 13 (a) and 13 (b).

As shown in FIGS. 1A and 1B, in the nonvolatile memory 1, element formation areas (Active Area: AA) 3 are provided at a plurality of locations on the surface layer portion of the semiconductor substrate 2. As shown in FIG. 1A, impurity diffusion layers 4 serving as source / drain regions are formed in a plurality of locations in the surface layer portion of each element formation region 3. Further, as shown in FIG. 1B, each element formation region 3 is surrounded by an element isolation insulating film 5 embedded in a plurality of locations on the surface layer portion of the silicon substrate 2. Each element isolation insulating film 5 forms an element isolation region having an STI (Shallow Trench Isolation) structure. Further, as shown in FIG. _1A, a tunnel insulating film (gate insulation) _having a capacitance C _tnl is formed on the surface of the semiconductor substrate 2 so as to cover the surface of each element formation region 3 and each impurity diffusion layer 4. A plurality of membranes 6 are provided.

As shown in FIGS. 1A and 1B, above each element formation region 3, a floating gate electrode (FG) serving as a charge storage layer with each tunnel insulating film 6 interposed therebetween. ) 7 are provided. Then, the upper and upper surfaces of each floating gate electrode 7 exposed from each element isolation insulating film 5 and the surface of each element isolation insulating film 5 are covered, and the interelectrode insulating film (C _ipd ) Inter Poly Dielectric Film) 8 is provided. Further, a plurality of control gate electrodes (Control Gate: CG) 9 serving as word lines are provided above each floating gate electrode 7 with each interelectrode insulating film 8 interposed therebetween.

As described above, the nonvolatile memory 1 includes a plurality of tunnel insulating films 6, a floating gate electrode 7, an interelectrode insulating film 8, a control gate electrode 9 provided on the surface of the semiconductor substrate 2, and a semiconductor. A plurality of memory cells 10 including a plurality of impurity diffusion layers 4 formed on the surface layer portion of the substrate 2 are provided. The coupling ratio of each memory cell 10 is expressed as C _ipd / (C _tnl + C _ipd ). When a high voltage is applied between the surface of the semiconductor substrate 2 and the control gate electrode 9, a strong electric field is applied to the tunnel insulating film 6 according to the coupling ratio of each memory cell 10. Then, a tunnel current flows between the semiconductor substrate 2 and the floating gate electrode 7 via the tunnel insulating film 6, and the accumulated charge amount of the floating gate electrode 7 changes. As a result, a data write operation and an erase operation are performed on each memory cell 10. Although illustration of the whole is omitted, in the nonvolatile memory 1, a large number of memory cells 10 are arranged along each of the word line direction and the bit line direction.

  Next, a method of manufacturing the nonvolatile memory 1 will be described with reference to FIGS. 2 (a) and 2 (b) to FIGS. 7 (a) and 7 (b).

First, as shown in FIGS. 2A and 2B, a first insulating film 6 to be a tunnel insulating film (tunnel oxide film) is provided on the surface of a silicon substrate 2 as a semiconductor substrate. Here, as the first insulating film 6, a silicon oxide film (SiO ₂ film) having a film thickness of about 6 nm is formed by a thermal oxidation method. Prior to the formation of the silicon oxide film 6, the surface layer portion of the silicon substrate 2 is previously doped with a predetermined amount of impurities. Subsequently, a charge storage layer 7 serving as a floating gate electrode is provided on the surface of the silicon oxide film 6. Here, as the charge storage layer 7, a polycrystalline silicon layer (polysilicon layer) doped with phosphorus (P) having a thickness of about 100 nm is formed. Subsequently, a first mask material 11 for element isolation processing is provided on the surface of the phosphorus-doped polycrystalline silicon layer 7. Both the phosphorus-doped polycrystalline silicon layer 7 and the first mask material 11 are sequentially stacked and deposited on the surface of the phosphorus-doped polycrystalline silicon layer 7 by a CVD method (Chemical Vapor Deposition Method).

  Subsequently, a first resist mask (not shown) is provided on the first mask material 11, and the first resist mask is patterned to form a first resist pattern (not shown). Thereafter, based on the first resist pattern, the first mask material 11, the phosphorus-doped polycrystalline silicon layer 7, and the silicon oxide film 6 are sequentially etched and processed from above by the RIE method (Reactive Ion Etching Method). Further, the exposed region of the silicon substrate 2 exposed from the first resist mask, the first mask material 11, the phosphorus-doped polycrystalline silicon layer 7, and the silicon oxide film 6 is also etched and dug by the RIE method. Thereby, a plurality of element isolation grooves 12 having a depth of about 100 nm are formed in the surface layer portion of the silicon substrate 2. Here, the widths of the phosphorus-doped polycrystalline silicon layer 7, the silicon oxide film 6, and the silicon substrate 2 below these are left to be processed to about 50 nm without being cut. At the same time, the width of each element isolation groove 12 is processed to about 50 nm.

Next, as shown in FIGS. 3A and 3B, the element isolation insulating film 5 is embedded in each element isolation trench 12. Here, first, a silicon oxide film (SiO ₂ film) that becomes the element isolation insulating film 5 is filled with the inside of each element isolation groove 12 by, for example, a CVD method while covering the surface of the first mask material 11. It is deposited on the entire surface of the silicon substrate 2 until the thickness is reached. Subsequently, the element isolation silicon oxide film 5 is polished and removed by CMP (Chemical Mechanical Polish Method) until the surface of the first mask material 11 is exposed. As a result, the element isolation silicon oxide film 5 is embedded in each element isolation trench 12, and the surface of the first mask material 11 and the surface of the element isolation silicon oxide film 5 are planarized.

  Next, as shown in FIGS. 4A and 4B, the first mask material 11 exposed from the element isolation silicon oxide film 5 is selectively etched with a predetermined chemical solution, etc. It is removed from the surface of the crystalline silicon layer 7. Thereby, the surface (upper surface) of the phosphorus-doped polycrystalline silicon layer 7 is exposed. Subsequently, the element isolation silicon oxide film 5 embedded in each element isolation trench 12 is etched and dug using, for example, a diluted hydrofluoric acid solution. Thereby, the side wall surface of the phosphorus-doped polycrystalline silicon layer 7 is exposed. Here, of the side wall surface of the phosphorus-doped polycrystalline silicon layer 7 having an overall height of about 100 nm, a portion about 50 nm from the top, which is about half the height, is exposed. Thereby, element isolation regions 5 made of a silicon oxide film are formed at a plurality of locations on the surface layer portion of the silicon substrate 2.

  Next, as shown in FIGS. 5A and 5B, an interelectrode insulating film 8 is provided so as to cover the surface of the phosphorus-doped polycrystalline silicon layer 7 and the surface of each element isolation region 5. In FIGS. 1A and 1B referred to above, the interelectrode insulating film 8 is schematically described as a single-layer insulating film. However, in practice, a laminated insulating film in which an insulating film is stacked in a plurality of layers is used. The interelectrode insulating film 8 is formed by using this.

Specifically, first, a second insulating film 13 serving as a first inter-electrode insulating film is provided so as to cover the surface of the phosphorus-doped polycrystalline silicon layer 7 and the surface of each element isolation region 5. The second insulating film 13 is formed using a material containing silicon and oxygen. Here, as the second insulating film 13, a silicon oxide film (SiO ₂ film) having a thickness of about 3 nm is deposited on the surface of the phosphorus-doped polycrystalline silicon layer 7 and the surface of each element isolation region 5 by the CVD method. The film forming conditions for the silicon oxide film 13 are that nitrous oxide and dichlorosilane are used as the source gas, and the film forming temperature is set to about 800 ° C.

Subsequently, a third insulating film 14 serving as a second-layer interelectrode insulating film is provided on the silicon oxide film 13. Here, an alumina film (Al ₂ O ₃ film) having a film thickness of about 1.8 nm is deposited on the surface of the silicon oxide film 13 by the ALD method (Atomic Layer Deposition Method) as the third insulating film 14. The conditions for forming the alumina film 14 are that trimethylaluminum and water vapor are used as the source gas, and the film forming temperature is set to about 300 ° C. The alumina film 14 becomes a part of the charge trap layer 24 of the interelectrode insulating film 8 and functions as a sub charge trap layer.

Subsequently, a fourth insulating film 15 serving as a third-layer interelectrode insulating film is provided on the alumina film 14. The fourth insulating film 15 is made of a material having a charge trap density higher than that of the third insulating film (alumina film) 14 and a relative dielectric constant higher than that of the second insulating film (silicon oxide film) 13. Form. Here, as the fourth insulating film 15, a hafnium oxide film (HfO ₂ film) having a thickness of about 0.4 nm is deposited on the surface of the alumina film 14 by the ALD method. The film forming conditions for the hafnium oxide film 15 are that tetraethylmethylamino hafnium and water vapor are used as the source gas, and the film forming temperature is set to about 300.degree. The hafnium oxide film 15 becomes a part of the charge trap layer 24 included in the interelectrode insulating film 8 similarly to the alumina film 14 described above, and functions as a main charge trap layer capturing more charges than the alumina film 14.

  Subsequently, a fifth insulating film 16 serving as a fourth-layer interelectrode insulating film is provided on the hafnium oxide film 15. The fifth insulating film 16 is formed using a material having a charge trap density lower than that of the fourth insulating film (hafnium oxide film) 15. Here, as the fifth insulating film 16, an alumina film having the same thickness (about 1.8 nm) as the alumina film 14 serving as the second-layer interelectrode insulating film described above is used. It is deposited on the surface of the hafnium oxide film 15 by a film forming method and film forming conditions. The alumina film 16 becomes a part of the charge trap layer 24 of the interelectrode insulating film 8 like the alumina film 14 and the hafnium oxide film 15 described above, and functions as a sub charge trap layer like the alumina film 14. The charge trap layer 24 composed of the alumina film 14, the hafnium oxide film 15, and the alumina film 16 is also referred to as an intermediate layer of the interelectrode insulating film 8.

  Subsequently, a sixth insulating film 17 serving as a fifth-layer interelectrode insulating film is provided on the alumina film 16. The sixth insulating film 17 has a relative dielectric constant lower than that of the fourth insulating film (hafnium oxide film) 15 and is formed using a material containing silicon and oxygen. Here, as the sixth insulating film 17, a silicon oxide film having the same thickness (about 3 nm) as the silicon oxide film 13 serving as the first-layer interelectrode insulating film described above is used in the same manner as the silicon oxide film 13. The film is deposited on the surface of the alumina film 16 by the film forming method and film forming conditions.

  By the steps so far, the lower silicon oxide film 13, the lower alumina film (lower intermediate layer) 14, and the hafnium oxide film 15 (central intermediate layer) are formed on the surface of the phosphorus-doped polycrystalline silicon layer 7 and the surface of each element isolation region 5. Then, the base of the inter-electrode insulating film 8 composed of the laminated insulating film of five layers of the upper layer alumina film (upper intermediate layer) 16 and the upper layer silicon oxide film 17 is formed. The total film thickness of the interelectrode insulating film 8 is about 10 nm. As described above, in the present embodiment, the lower silicon oxide film 13 and the upper silicon oxide film 17, and the lower alumina film 14 and the upper alumina film 16 serving as the sub-charge trap layers are set to the same film thickness. Yes. For this reason, the hafnium oxide film 15 serving as the main charge trapping layer is located at the center of the interelectrode insulating film 8 in the film thickness direction. In other words, the hafnium oxide film 15 is located in the center between the floating gate electrode 7 and the control gate electrode 9, and maintains a substantially equal distance from each of the floating gate electrode 7 and the control gate electrode 9.

  Next, as shown in FIGS. 6A and 6B, a material for forming the control gate electrode 9 is provided on the interelectrode insulating film 8. Here, the control gate electrode 9 is formed in a structure in which first and second conductive layers 18 and 19 of different materials are laminated. Specifically, first, a polycrystalline silicon layer (polysilicon layer) 18 serving as a lower layer portion of the control gate electrode 9 is formed on the surface of the upper silicon oxide film 17. Subsequently, a tungsten silicide layer 19 serving as an upper layer portion of the control gate electrode 9 is formed on the surface of the polycrystalline silicon layer 18. Both the polycrystalline silicon layer 18 and the tungsten silicide layer 19 are sequentially stacked and deposited on the surface of the upper silicon oxide film 17 by the CVD method. The total thickness (height) of the control gate electrode 9 having a two-layer structure of the polycrystalline silicon layer 18 / tungsten silicide layer 19 is about 100 nm.

  Subsequently, a second mask material 20 for processing the gate structure is provided on the tungsten silicide layer 19. Here, as the second mask material 20, a silicon nitride film (SiN film) is deposited on the surface of the tungsten silicide layer 19 by the CVD method. Subsequently, a second resist mask (not shown) is provided on the silicon nitride film 20, and the second resist mask is patterned to form a second resist pattern (not shown) orthogonal to the first resist pattern described above. To do. Thereafter, based on the second resist pattern, the silicon nitride film 20, tungsten silicide layer 19, polycrystalline silicon layer 18, upper silicon oxide film 17, upper alumina film 16, hafnium oxide film 15, lower alumina film 14, lower layer The silicon oxide film 13, the phosphorus-doped polycrystalline silicon layer 7, and the silicon oxide film 6 are processed by being sequentially etched from above by the RIE method. Thus, as shown in FIG. 6A, the tunnel insulating film 6, the floating gate electrode 7, the interelectrode insulating film 8, the control gate electrode 9, and the silicon nitride film (second mask) processed into a desired shape. A plurality of gate structures 21 including the material 20 are formed on the surface of the silicon substrate 2. Here, the width of each gate structure 21 and the interval between adjacent gate structures 21 are both processed to about 50 nm.

Subsequently, as shown in FIGS. 7A and 7B, a seventh insulating film is formed so as to cover the upper surface and the side wall surface of each gate structure 21 and the surface of the silicon substrate 2 exposed from each gate structure 21. 22 is provided. Here, as the seventh insulating film 22, a silicon oxide film (SiO ₂ film) having a thickness of about 10 nm is formed by a combination of a thermal oxidation method and a CVD method. A portion of the silicon oxide film 22 provided on the side wall surface of each gate structure 21 becomes a so-called gate side wall oxide film. Subsequently, ion implantation and thermal annealing are performed using each gate structure 21 covered with the silicon oxide film 22 as a mask. As a result, a plurality of impurity diffusion layers 4 serving as source / drain regions are formed in the surface layer portion of the silicon substrate 2 (element formation region 3).

As a result, although the entire illustration is omitted, the memory cell 10 including the tunnel insulating film 6, the floating gate electrode 7, the interelectrode insulating film 8, the control gate electrode 9, and the impurity diffusion layer 4 has the word line direction and the bit line. A large number are arranged along each direction, and formed on the surface of the silicon substrate 2. Subsequently, an interlayer insulating film 23 is provided on the silicon substrate 2 while covering each gate structure 21 covered with the silicon oxide film 22 by using, for example, a CVD method. The interlayer insulating film 23 may be formed using, for example, a silicon oxide film (SiO ₂ film) or a TEOS film.

  Thereafter, although detailed and detailed description accompanying illustration is omitted, various wiring layers such as contact plugs and bit lines connected to the impurity diffusion layer 4 are formed inside the interlayer insulating film 23 using a known technique. To do. Thereby, the nonvolatile memory 1 of this embodiment having the memory cell structure shown in FIGS. 7A and 7B is manufactured.

  In the nonvolatile memory 1 of the present embodiment, as described above, the intermediate three layers that become the charge trap layer 24 in the interelectrode insulating film 8 having the five-layer structure have fewer charge traps, and A hafnium oxide layer 15 containing more charge traps is sandwiched between the central portions of the upper and lower alumina films 14 and 16 having substantially the same film thickness. As a result, the charge trap density along the thickness direction of the intermediate layer 24 has a maximum value at the center in the thickness direction. Further, the charge trap layer 24 itself has a structure sandwiched between the central portions of the upper and lower silicon oxide films 13 and 17 having substantially the same film thickness. Therefore, the charge trap density along the thickness direction of the interelectrode insulating film 8 takes the maximum value at the center in the thickness direction. Charges are trapped in the charge trap layer 24 having such a structure, particularly the hafnium oxide layer 15 which is the main charge trap layer, so that information (data) is written into the memory cell 10 or the memory cell Leakage current when erasing data can be reduced. In addition, the operation speed of the memory cell 10 can be further increased and the memory window can be widened.

  On the other hand, the hafnium oxide film 15 is located at the center between the floating gate electrode 7 and the control gate electrode 9 as described above, and is substantially equal from each of the floating gate electrode 7 and the control gate electrode 9. It is formed at a distance. For this reason, the charge detrapping phenomenon at the time of charge holding can be suppressed, and malfunction due to the threshold fluctuation of the memory cell 10 can also be suppressed.

  Next, referring to FIGS. 8A and 8B and FIGS. 9A and 9B, a hafnium oxide layer 15 is formed at the center of the upper and lower alumina films 14 and 16 to thereby provide a memory cell. The reason why the leakage current at the time of writing data to the memory cell 10 and at the time of erasing the data in the memory cell 10 can be reduced will be described. Although not shown in FIG. 8A, the energy state of the interelectrode insulating film at the time of writing data to a nonvolatile memory having an interelectrode insulating film having no charge trap in the intermediate layer is schematically shown. It is an energy band figure shown. FIG. 8B is a diagram schematically showing an energy state at the time of erasing data in a nonvolatile memory having an inter-electrode insulating film that does not have a charge trap in the intermediate layer. On the other hand, FIG. 9A shows the data stored in the nonvolatile memory 1 according to the present embodiment including the interelectrode insulating film 8 that forms the hafnium oxide layer 15 at the center of the upper and lower alumina films 14 and 16. It is a figure which shows typically the state of the energy band at the time of writing. FIG. 9B is a diagram schematically showing the state of the energy band when erasing data in the nonvolatile memory 1.

  As shown in FIGS. 8A and 8B, in the nonvolatile memory including the interelectrode insulating film in which the hafnium oxide layer is not formed at the center of the upper and lower alumina films, both at the time of data writing and at the time of data erasing. Electrons are not easily trapped in the intermediate layer, and an energy barrier is hardly formed in the intermediate layer. For this reason, it is difficult for the electric field to be relaxed on the floating gate electrode side or the control gate electrode side of the intermediate layer on the electron injection side. As a result, the tunneling probability of injected electrons is difficult to decrease during data writing and data erasing, and a leak current easily flows. On the other hand, as shown in FIGS. 9A and 9B, in the nonvolatile memory 1 according to the present embodiment, the centers of the upper and lower alumina films 14 and 16 are both written and erased. Electrons are easily trapped in the hafnium oxide layer 15 formed in the portion, and an energy barrier is easily formed in the intermediate layer 24. Therefore, the electric field is easily relaxed on the floating gate electrode 7 side or the control gate electrode 9 side of the intermediate layer 24 on the electron injection side. As a result, the tunneling probability of injected electrons decreases during data writing and data erasing, and leakage current does not flow easily.

  FIG. 10 is a graph showing a CV curve (threshold fluctuation) representing the relationship between the capacitance of the insulating film and the gate voltage applied to the insulating film for each type of insulating film. Specifically, FIG. 10 shows a case where an electric field stress equivalent to a data write operation is applied to a MIS capacitor (not shown) formed by depositing an insulating film having a relative dielectric constant higher than that of a silicon oxide film on a silicon substrate. The graph shows the shift state of the CV curve due to electrons trapped in the insulating film for each type of insulating film. As indicated by an arrow in FIG. 10, when an electric field stress equivalent to a data write operation is applied to the MIS capacitor, the CV curve (threshold value) shifts to the positive voltage side. As shown by the broken line graph in FIG. 10, when an insulating film having a small charge trap density is used for the MIS capacitor, the CV curve after application of the electric field stress to the initial state CV curve shown by the solid line graph in FIG. Does not shift to the positive voltage side too much. On the other hand, as shown by the dot-dash line graph in FIG. 10, when an insulating film having a large charge trap density is used for the MIS capacitor, compared to using an insulating film having a small charge trap density for the MIS capacitor, The CV curve after application of the electric field stress largely shifts to the positive voltage side with respect to the initial state CV curve shown by the solid line graph in FIG.

  As described above, according to the first embodiment, charges are concentrated and trapped locally in the central portion in the thickness direction of the charge trap layer 24. As a result, both the data trapped in the charge trap layer 24 and the floating gate electrode (charge storage layer) 7 and the control gate electrode 9 are written at the time of writing data into the memory cell 10 and at the time of erasing data in the memory cell 10. The distance can be stably maintained at substantially the same interval. As a result, in the nonvolatile memory 1 according to the present embodiment, the charge detrapping phenomenon while the memory cell 10 holds the charge, which has been almost impossible in the past, is suppressed, and the leakage current is reduced. Thus, it is possible to obtain desired memory cell characteristics. Therefore, according to the present embodiment, it is possible to provide the nonvolatile memory 1 in which the electrical characteristics of the memory cell 10 are improved and the manufacturing method thereof.

  Further, as described above, according to the present embodiment, it is possible to suppress or reduce an increase in leakage current and a deterioration in dielectric strength voltage while making the interelectrode insulating film 8 thinner. That is, according to the present embodiment, it is possible to reduce the size of the memory cell 10 and thus the nonvolatile memory 1 while improving the electrical characteristics.

(Second Embodiment)
Next, a second embodiment according to the present invention will be described with reference to FIGS. 11 (a), (b) and FIG. In addition, the same code | symbol is attached | subjected to the same part as 1st Embodiment mentioned above, and those detailed description is abbreviate | omitted.

  In the present embodiment, the structure of the interelectrode insulating film of the memory cell included in the nonvolatile semiconductor memory device is different from the structure of the interelectrode insulating film 8 according to the first embodiment, and the others are the same. Specifically, the interelectrode insulating film according to the present embodiment differs from the interelectrode insulating film 8 according to the first embodiment only in the structure of the three intermediate layers that are charge trap layers. This will be specifically described below.

  First, as shown in FIGS. 11A and 11B, until the step of forming element isolation regions 5 at a plurality of locations on the surface layer portion of the silicon substrate 2 as a pre-process of the step of forming the interelectrode insulating film 31, In the first embodiment, the same processes as those described with reference to FIGS. 2A and 2B to FIGS. 4A and 4B are performed. Subsequently, the interelectrode insulating film 31 according to this embodiment is provided so as to cover the surface of each phosphorus-doped polycrystalline silicon layer 7 and the surface of each element isolation region 5 by the same process as in the first embodiment.

  Specifically, as shown in FIGS. 11A and 11B, first, as in the first embodiment, the lower silicon oxide film 13 having a film thickness of about 3 nm is formed on the surface of each phosphorus-doped polycrystalline silicon layer 7 and each of the layers. A film is formed on the surface of the element isolation region 5. Subsequently, a lower alumina film 32 is formed on the surface of the lower silicon oxide film 13. However, while the lower alumina film 14 having a film thickness of about 1.8 nm is formed in the first embodiment, the lower alumina film 32 having a film thickness of about 1.1 nm is formed in this embodiment. Subsequently, a hafnium oxide film 15 having a film thickness of about 0.4 nm is formed on the surface of the lower alumina film 32 as in the first embodiment. Subsequently, an upper alumina film 33 is formed on the surface of the hafnium oxide film 15. However, the upper alumina film 16 having a film thickness of about 1.8 nm is formed in the first embodiment, whereas the upper alumina film 33 having a film thickness of about 2.5 nm is formed in this embodiment. Subsequently, an upper silicon oxide film 17 having a thickness of about 3 nm is formed on the surface of the upper alumina film 33 as in the first embodiment.

  By the steps so far, the lower silicon oxide film 13, the lower alumina film 32, the hafnium oxide film 15, the upper alumina film 33, and the upper silicon oxide film are formed on the surface of each phosphorus-doped polycrystalline silicon layer 7 and the surface of each element isolation region 5. The base of the interelectrode insulating film 31 composed of the five-layered insulating film of the film 17 is formed. The film thickness of the entire interelectrode insulating film 31 of this embodiment is about 10 nm, as is the film thickness of the entire interelectrode insulating film 8 of the first embodiment. Further, the intermediate layer (charge trap layer) 34 of the present embodiment is composed of the lower alumina film 32, the hafnium oxide film 15, and the upper alumina film 33.

  As described above, in the present embodiment, the lower silicon oxide film 13 and the upper silicon oxide film 17 are formed to the same film thickness as in the first embodiment. At the same time, the hafnium oxide film 15 is also formed to the same thickness as in the first embodiment. In contrast, the lower alumina film 32 of the present embodiment is formed to be approximately 0.7 nm thinner than the lower alumina film 14 of the first embodiment. At the same time, the upper alumina film 33 of this embodiment is formed to be approximately 0.7 nm thicker than the upper alumina film 16 of the first embodiment. For this reason, the hafnium oxide film 15 of this embodiment has a floating gate electrode of about 0.7 nm from the center in the film thickness direction of the interelectrode insulating film 31 and the intermediate layer 34 as compared with the hafnium oxide film 15 of the first embodiment. It is formed close to the 7 side.

  Subsequently, as shown in FIGS. 11A and 11B, a polycrystalline silicon layer (polysilicon layer) 18 is formed on the surface of the upper silicon oxide film 17 by the same process as in the first embodiment. . Subsequently, a tungsten silicide layer 19 is formed on the surface of the polycrystalline silicon layer 18 by the same process as in the first embodiment. Also in this embodiment, the total thickness (height) of the control gate electrode 9 having a two-layer structure of the polycrystalline silicon layer 18 / tungsten silicide layer 19 is about 100 nm as in the first embodiment.

  Thereafter, although a specific and detailed description accompanying illustration is omitted, an interlayer insulating film, a bit line, and the like are formed using a known technique as in the first embodiment. As a result, the nonvolatile memory of the present embodiment having the memory cell structure shown in FIGS. 11A and 11B is manufactured.

  As described above, the hafnium oxide film 15 of the present embodiment is about 0.7 nm from the central portion in the film thickness direction of the interelectrode insulating film 31 and the charge trap layer 34 as compared with the hafnium oxide film 15 of the first embodiment. It is formed close to the floating gate electrode 7 side. Therefore, the charge trap density of the present embodiment is approximately 0.7 nm from the center along the thickness direction of the interelectrode insulating film 31 and the charge trap layer 34 compared to the charge trap density of the first embodiment. The maximum value is obtained near the electrode 7. Charges are trapped in the charge trap layer 34 having such a structure, particularly the hafnium oxide layer 15 which is the main charge trap layer, so that data can be written into the memory cell or the memory as in the first embodiment. Leakage current at the time of erasing data in the cell can be reduced. In particular, the charge trap layer 34 of the present embodiment having the above-described structure has an increased leakage current at the corner of the floating gate electrode 7 when writing data to the memory cell, as compared to the charge trap layer 24 of the first embodiment. It can suppress more effectively. As a result, as in the first embodiment, the operating speed of the memory cell can be further increased and the memory window can be widened.

  Further, as described above, in the present embodiment, the hafnium oxide layer 15 serving as the main charge trap layer is formed at a distance of about 0.7 nm from the control gate electrode 9 as compared with the first embodiment. The Thereby, in the present embodiment, the charge detrapping phenomenon at the time of data retention after data is written to the memory cell can be further reduced as compared with the first embodiment. This is also effective in suppressing the threshold fluctuation of the memory cell.

  Next, referring to FIG. 12, the hafnium oxide layer 15 is formed closer to the floating gate electrode 7 side than the central portions of the upper and lower alumina films 32 and 33, so that the floating gate is written when writing data to the memory cell. The reason why the increase of the leakage current at the corner of the electrode 7 can be suppressed will be described. 12 is similar to FIG. 9A referred to in the first embodiment, between the electrodes forming the hafnium oxide layer 15 near the floating gate electrode 7 about 0.7 nm from the center of the upper and lower alumina films 14 and 16. It is a figure which shows typically the state of the energy band at the time of the data writing in the non-volatile memory which concerns on this embodiment provided with the insulating film 31. FIG.

  By trapping electrons in the hafnium oxide layer 15, the electric field is relaxed on the floating gate electrode 7 side, which is the electron injection side, when writing data to the memory cell. Here, as is clear from a comparison between FIG. 12 and FIG. 9A, the energy band of the hafnium oxide layer 15 which is the main charge trap layer (intermediate layer) of the present embodiment having the structure described above is the first. It can be seen that it is higher than the energy band of the hafnium oxide layer 15 of the embodiment. That is, it can be seen that the interelectrode insulating film 31 of this embodiment has a larger electric field relaxation effect on the floating gate electrode 7 side than the interelectrode insulating film 8 of the first embodiment. Therefore, according to the present embodiment, the electric field concentration at the corners of the floating gate electrode 7 at the time of writing data to the memory cell can be more relaxed than in the first embodiment. As a result, an increase in leakage current at the corner of the floating gate electrode 7 when data is written to the memory cell can be further suppressed as compared with the first embodiment.

  As described above, according to the second embodiment, the same effects as those of the first embodiment described above can be obtained. Further, charges are concentrated and trapped locally near the charge storage layer (floating gate electrode) 7 from the central portion in the thickness direction in the charge trap layer 34. As a result, in the present embodiment, as in the first embodiment, the charge storage layer 7 at the time of writing data to the memory cell is suppressed while suppressing the charge detrapping phenomenon while the memory cell holds the charge. Desired memory cell characteristics that a leakage current at the corners can be reduced can be obtained.

(Third embodiment)
Next, a third embodiment according to the present invention will be described with reference to FIGS. 13 (a), (b) and FIG. In addition, the same code | symbol is attached | subjected to the same part as each 1st and 2nd embodiment mentioned above, and those detailed description is abbreviate | omitted.

  This embodiment is similar to the second embodiment only in that the structure of the interelectrode insulating film of the memory cell included in the nonvolatile semiconductor memory device is different from the structure of the interelectrode insulating film 8 according to the first embodiment. Others are the same. Specifically, the interelectrode insulating film according to the present embodiment differs from the interelectrode insulating film 8 according to the first embodiment only in the structure of the three intermediate layers that are charge trap layers. This will be specifically described below.

  First, as shown in FIGS. 13A and 13B, until the step of forming element isolation regions 5 at a plurality of locations on the surface layer portion of the silicon substrate 2 as a pre-step of the step of forming the interelectrode insulating film 41, In the first embodiment, the same processes as those described with reference to FIGS. 2A and 2B to FIGS. 4A and 4B are performed. Subsequently, the interelectrode insulating film 41 according to this embodiment is provided so as to cover the surface of each phosphorus-doped polycrystalline silicon layer 7 and the surface of each element isolation region 5 by the same process as in the first embodiment.

  Specifically, as shown in FIGS. 13A and 13B, first, as in the first embodiment, the lower silicon oxide film 13 having a film thickness of about 3 nm is formed on the surface of each phosphorus-doped polycrystalline silicon layer 7 and each of the respective layers. A film is formed on the surface of the element isolation region 5. Subsequently, a lower alumina film 42 is formed on the surface of the lower silicon oxide film 13. However, while the lower alumina film 14 having a film thickness of about 1.8 nm is formed in the first embodiment, the lower alumina film 42 having a film thickness of about 2.5 nm is formed in this embodiment. Subsequently, a hafnium oxide film 15 having a thickness of about 0.4 nm is formed on the surface of the lower alumina film 42 as in the first embodiment. Subsequently, an upper alumina film 43 is formed on the surface of the hafnium oxide film 15. However, the upper alumina film 16 having a film thickness of about 1.8 nm is formed in the first embodiment, whereas the upper alumina film 43 having a film thickness of about 1.1 nm is formed in this embodiment. Subsequently, an upper silicon oxide film 17 having a thickness of about 3 nm is formed on the surface of the upper alumina film 33 as in the first embodiment.

  By the steps so far, the lower silicon oxide film 13, the lower alumina film 42, the hafnium oxide film 15, the upper alumina film 43, and the upper silicon oxide film are formed on the surface of each phosphorus-doped polycrystalline silicon layer 7 and the surface of each element isolation region 5. The base of the inter-electrode insulating film 41 made of the five-layer laminated insulating film of the film 17 is formed. The total film thickness of the interelectrode insulating film 41 of this embodiment is about 10 nm, as is the total film thickness of each of the interelectrode insulating film 8 of the first embodiment and the interelectrode insulating film of the second embodiment. Further, the intermediate layer (charge trap layer) 44 of the present embodiment is composed of the lower alumina film 42, the hafnium oxide film 15, and the upper alumina film 43.

  As described above, in the present embodiment, the lower silicon oxide film 13 and the upper silicon oxide film 17 are formed to have the same film thickness as in the first and second embodiments. At the same time, the hafnium oxide film 15 is also formed to have the same thickness as that of the first and second embodiments. In contrast, the lower alumina film 42 of the present embodiment is formed to be approximately 0.7 nm thicker than the lower alumina film 14 of the first embodiment, contrary to the lower alumina film 32 of the second embodiment. . At the same time, the upper alumina film 43 of the present embodiment is formed to be thinner by about 0.7 nm than the upper alumina film 16 of the first embodiment, contrary to the upper alumina film 33 of the second embodiment. For this reason, the hafnium oxide film 15 of the present embodiment is opposite to the hafnium oxide film 15 of the second embodiment, as compared with the hafnium oxide film 15 of the first embodiment. It is formed closer to the control gate electrode 9 side by about 0.7 nm from the center in the film thickness direction.

  Subsequently, as shown in FIGS. 11A and 11B, a polycrystalline silicon layer (polysilicon layer) 18 is formed on the surface of the upper silicon oxide film 17 by the same process as in the first embodiment. . Subsequently, a tungsten silicide layer 19 is formed on the surface of the polycrystalline silicon layer 18 by the same process as in the first embodiment. Also in this embodiment, the total thickness (height) of the control gate electrode 9 having a two-layer structure of the polycrystalline silicon layer 18 / tungsten silicide layer 19 is approximately the same as in the first and second embodiments. 100 nm.

  Thereafter, although a specific and detailed description accompanying illustration is omitted, an interlayer insulating film, a bit line, and the like are formed using a known technique as in the first and second embodiments. Thereby, the nonvolatile memory of this embodiment having the memory cell structure shown in FIGS. 13A and 13B is manufactured.

  As described above, the hafnium oxide film 15 of the present embodiment is opposite to the hafnium oxide film 15 of the first embodiment, as compared with the hafnium oxide film 15 of the first embodiment. The layer 34 is formed so as to approach the control gate electrode 9 side by about 0.7 nm from the center in the film thickness direction. Therefore, the charge trap density of the present embodiment is opposite to the charge trap density of the second embodiment, and the thickness direction of the interelectrode insulating film 31 and the charge trap layer 34 is larger than the charge trap density of the first embodiment. A maximum value is taken near the control gate electrode 9 about 0.7 nm from the central portion thereof. As the charge is trapped in the charge trap layer 44 having such a structure, particularly the hafnium oxide layer 15 which is the main charge trap layer, as in the first embodiment, when data is written in the memory cell or in the memory Leakage current at the time of erasing data in the cell can be reduced. In particular, the charge trap layer 44 of the present embodiment having the above-described structure is different from the charge trap layers 24 and 34 of the first and second embodiments in the control gate electrode 9 when erasing data in the memory cell. An increase in leakage current at the corner can be more effectively suppressed. As a result, similar to the first and second embodiments, the operation speed of the memory cell can be further increased and the memory window can be widened.

  Further, as described above, in the present embodiment, the hafnium oxide layer 15 serving as the main charge trap layer is about 0. 0 from the floating gate electrode 7 as compared with the first embodiment. It is formed at a distance of 7 nm. Thereby, in the present embodiment, the charge detrapping phenomenon at the time of data retention after erasing data in the memory cell can be further reduced as compared with the first and second embodiments. This is also effective in suppressing the threshold fluctuation of the memory cell.

  Next, referring to FIG. 14, the hafnium oxide layer 15 is formed closer to the control gate electrode 9 side than the central portions of the upper and lower alumina films 32 and 33, so that the floating gate is erased when data in the memory cell is erased. The reason why the increase of the leakage current at the corner of the electrode 7 can be suppressed will be described. 14 is similar to FIG. 9B referred to in the first embodiment, between the electrodes forming the hafnium oxide layer 15 near the control gate electrode 9 about 0.7 nm from the central portion of the upper and lower alumina films 14 and 16. It is a figure which shows typically the state of the energy band at the time of the erasure | elimination of the data in the non-volatile memory which concerns on this embodiment provided with the insulating film 41. FIG.

  By trapping electrons in the hafnium oxide layer 15, the electric field is relaxed on the side of the control gate electrode 9 that is the electron injection side when erasing data in the memory cell. Here, as apparent from the comparison between FIG. 14 and FIG. 9B, the energy band of the hafnium oxide layer 15 which is the main charge trapping layer of the present embodiment having the above-described structure is the hafnium oxide oxide of the first embodiment. It can be seen that it is higher than the energy band of the layer 15. That is, it can be seen that the interelectrode insulating film 41 of this embodiment has a larger electric field relaxation effect on the control gate electrode 9 side than the interelectrode insulating film 8 of the first embodiment. Therefore, according to the present embodiment, the electric field concentration at the corner of the control gate electrode 9 at the time of erasing data in the memory cell can be more relaxed than in the first embodiment. As a result, an increase in leakage current at the corners of the control gate electrode 9 when erasing data in the memory cell can be further suppressed as compared with the first embodiment.

  As described above, according to the third embodiment, the same effects as those of the first and second embodiments described above can be obtained. Further, charges are concentrated and trapped locally near the control gate electrode 9 from the central portion in the thickness direction in the charge trap layer 44. Thus, in this embodiment, as in the first and second embodiments, the charge detrapping phenomenon while the memory cell holds the charge is suppressed, and the data in the memory cell is erased. Desired memory cell characteristics that a leakage current at the corner of the control gate electrode 9 can be reduced can be obtained.

(Fourth embodiment)
Next, a fourth embodiment according to the present invention will be described with reference to FIGS. 15 (a) and 15 (b) to FIG. In addition, the same code | symbol is attached | subjected to the same part as each 1st-3rd embodiment mentioned above, and those detailed description is abbreviate | omitted. FIGS. 15A and 15B to 17 are cross-sectional views taken along the longitudinal direction (channel width direction) of the word line (control gate electrode) 9 included in the nonvolatile memory.

  In the present embodiment, the structure of the interelectrode insulating film of the memory cell included in the nonvolatile semiconductor memory device is different from the structure of the interelectrode insulating film 8 according to the first embodiment, as in the second and third embodiments. The rest is the same. Specifically, the interelectrode insulating film according to the present embodiment differs from the interelectrode insulating film 8 according to the first embodiment only in the structure of the three intermediate layers that are charge trap layers. This will be specifically described below.

  First, as shown in FIG. 15A, in the first embodiment, up to the step of forming element isolation regions 5 at a plurality of locations on the surface layer portion of the silicon substrate 2 as a pre-step of the step of forming the interelectrode insulating film. Steps similar to those described with reference to FIGS. 2A and 2B to FIGS. 4A and 4B are performed. Subsequently, the interelectrode insulating film according to the present embodiment is provided so as to cover the surface of each phosphorus-doped polycrystalline silicon layer 7 and the surface of each element isolation region 5.

  Specifically, as shown in FIG. 15A, first, the lower silicon oxide film 13 having a thickness of about 3 nm is formed on each phosphorus-doped polycrystalline silicon by the same process as that of the first embodiment. A film is formed on the surface of the layer 7 and the surface of each element isolation region 5. Subsequently, the lower alumina film 51 is formed on the surface of the lower silicon oxide film 13 by the same process as in the first embodiment. However, while the lower alumina film 14 having a uniform film thickness of about 1.8 nm is formed in the first embodiment, in the present embodiment, each recess of the lower silicon oxide film 13 is filled and the lower silicon oxide film 13 is filled. A lower alumina film 51 is deposited on the surface of the lower silicon oxide film 13 until reaching a height that covers the surface of each of the protrusions. Thereafter, the upper surface (surface) of the lower alumina film 51 is planarized by, for example, CMP. At this time, the thickness of the portion of the lower alumina film 51 located above the upper surface of each phosphorus-doped polycrystalline silicon layer 7 becomes about 1.8 nm after the planarization, as in the first embodiment. The CMP process is performed as described above.

  Subsequently, a third resist mask 52 for processing the lower layer alumina film 51 is provided on the upper surface of the planarized lower layer alumina film 51. Subsequently, the third resist mask is patterned to cover the upper surface of the lower alumina film 51 so as to cover the phosphorus-doped polycrystalline silicon layer 7 and to expose the upper portions of the element isolation regions 5. A pattern 52 is formed.

  Next, as shown in FIG. 15B, the lower alumina film 42 is etched based on the third resist pattern 52, and positions corresponding to the respective recesses of the lower silicon oxide film 13 inside the lower alumina film 51. A plurality of recesses 53 are formed. Specifically, a recess 53 having a reverse taper that becomes deeper from the upper surface of each phosphorus-doped polycrystalline silicon layer 7 toward the upper surface of each element isolation region 5 is formed inside the lower alumina film 51. A plurality of lower silicon oxide films 13 are formed at positions corresponding to the respective recesses. Here, each concave portion 53 is formed in an inverted trapezoidal shape whose side surfaces 53 a are inclined obliquely downward from the upper surface of the phosphorus-doped polycrystalline silicon layer 7 toward the upper surface of each element isolation region 5. As a result, the upper surface of the lower alumina film 51 constituting the side surface (inclined surface) 53a of each recess 53 from each corner 7a on the side facing each control gate electrode (interelectrode insulating film) of each phosphorus-doped polycrystalline silicon layer 7 Is smaller than the distance from the upper surface of each phosphorus-doped polycrystalline silicon layer 7 to the upper surface of the lower alumina film 51 thereabove.

  Further, the bottom 53 b which is the lowest part of each recess 53 is formed at a position lower than the upper surface of each phosphorus-doped polycrystalline silicon layer 7. However, at this time, the lower silicon oxide film 13 on each corner 7a on the side facing each control gate electrode of each phosphorus-doped polycrystalline silicon layer 7 is not exposed in each recess 53 and is covered with the lower alumina film 51. Leave it alone.

  In addition, each recessed part 53 which has the shape mentioned above performs isotropic etching, such as wet etching, with respect to the lower layer alumina film 51 on each element isolation region 5 exposed from the 3rd resist pattern 52, for example. Can be formed more easily. Alternatively, on each element isolation region 5 exposed from the third resist pattern 52 obliquely above each corner 7a on the side facing each control gate electrode of each phosphorus-doped polycrystalline silicon layer 7 It can be easily formed by supplying an etching gas for anisotropic etching such as dry etching toward the lower alumina film 51. After each recess 53 is formed, the third resist pattern (third resist mask) 52 is peeled off from the upper surface of the lower alumina film 51 and removed.

  Next, as shown in FIG. 16A, a film thickness of about 0.4 nm is formed on the upper surface of the lower alumina film 51 in which the inverted trapezoidal concave portions 53 are formed by the same process as in the first embodiment. A hafnium oxide film 54 is formed. As a result, the lower alumina film 51 is formed of the hafnium oxide film 54 having the reversely tapered portion 54a in which the position of the upper surface becomes lower from the upper surface of each phosphorus-doped polycrystalline silicon layer 7 toward the upper surface of each element isolation region 5. On the top surface of the substrate. Therefore, the hafnium oxide film 54 of the present embodiment is inclined obliquely downward from the upper surface of each phosphorus-doped polycrystalline silicon layer 7 toward the upper surface of each element isolation region 5 along the side surface 53a of each recess 53 described above. An inclined portion 54a is provided.

  As a result, the distance from each corner 7a on the side facing each control gate electrode of each phosphorus-doped polycrystalline silicon layer 7 to the inclined portion 54a of the hafnium oxide film 54 is above the upper surface of each phosphorus-doped polycrystalline silicon layer 7 and above it. It becomes smaller than the distance to the highest flat portion 54b excluding the inclined portion 54a of the hafnium oxide film 54. In other words, the hafnium oxide film 54 of the present embodiment has each corner portion as it goes from the position other than each corner portion 7a on the side facing the control gate electrode of each phosphorus-doped polycrystalline silicon layer 7 toward each corner portion 7a. It is formed in a shape closer to 7a. Further, the lowest flat portion 54c of the hafnium oxide film 54 excluding the inclined portion 54a and the highest flat portion 54b of the hafnium oxide film 54 is formed at a position lower than the upper surface of each phosphorus-doped polycrystalline silicon layer 7.

  Subsequently, the upper alumina film 55 is formed on the surface of the hafnium oxide film 54 by the same process as in the first embodiment. However, in the first embodiment, the upper alumina film 16 having a uniform film thickness of about 1.8 nm is formed, whereas in the present embodiment, each of the lower alumina films 51 whose surfaces are covered with the hafnium oxide film 54 are formed. An upper alumina film 55 is deposited on the surface of the hafnium oxide film 54 until it fills the recess 53 and reaches a height that covers the surface of each protrusion of the lower alumina film 51. Thereafter, the upper surface (surface) of the upper alumina film 55 is flattened by, eg, CMP. At this time, the film thickness of the portion of the upper alumina film 55 located above the upper surface of each phosphorus-doped polycrystalline silicon layer 7 becomes about 1.8 nm after the planarization, as in the first embodiment. The CMP process is performed as described above.

  Subsequently, a fourth resist mask 56 for processing the upper alumina film 55 is provided on the planarized upper surface of the upper alumina film 55. Subsequently, the fourth resist mask 56 is patterned so that the upper surface of the upper alumina film 55 on the side facing the upper surface of each phosphorus-doped polycrystalline silicon layer 7 and the control gate electrode of each phosphorus-doped polycrystalline silicon layer 7. A fourth resist pattern 56 is formed which covers each corner 7a and exposes the upper part of the center of each element isolation region 5.

  Next, as shown in FIG. 16B, the upper alumina film 55 is etched based on the fourth resist pattern 56 by, for example, the RIE method, and a plurality of layers are formed at positions corresponding to the respective recesses 53 of the lower alumina film 51. The recess 57 is formed. Specifically, a plurality of recesses 57 having a depth reaching the vicinity of the lowest flat portion 54 c of the hafnium oxide film 54 are formed above the central portion of each element isolation region 5. At this time, the inclined portion 54 a of the hafnium oxide film 54 is not exposed in each concave portion 57 but remains covered with the upper alumina film 55. After each recess 57 is formed, the fourth resist pattern (fourth resist mask) 56 is peeled off from the upper surface of the upper alumina film 55 and removed.

  Next, as shown in FIG. 17, on the surface of the upper alumina film 55 in which each recess 57 is formed, an upper silicon film having a film thickness of about 3 nm is formed by the same process as in the first embodiment. An oxide film 17 is formed.

  By the steps so far, the lower silicon oxide film 13, the lower alumina film 51, the hafnium oxide film 54, the upper alumina film 55, and the upper silicon oxide film are formed on the surface of each phosphorus-doped polycrystalline silicon layer 7 and the surface of each element isolation region 5. The base of the interelectrode insulating film 58 made of the five-layer laminated insulating film of the film 17 is formed. Further, the intermediate layer (charge trap layer) 59 of the present embodiment is composed of the lower layer alumina film 51, the hafnium oxide film 54, and the upper layer alumina film 55.

  Subsequently, as shown in FIG. 17, the polycrystalline silicon layer (polysilicon layer) 18 is filled with the upper silicon while filling the inside of each recess 57 formed in the upper alumina film 55 by the same process as in the first embodiment. A film is formed on the surface of the oxide film 17. Subsequently, a tungsten silicide layer 19 is formed on the surface of the polycrystalline silicon layer 18 by the same process as in the first embodiment. According to such a process, among the corners of the polycrystalline silicon layer 18 (control gate electrode 9), the corners 18a (9a) on the side protruding toward the silicon substrate 2 are formed on the hafnium oxide film 54. It is formed close to the inclined portion 54a. In other words, the inclined portion 54a of the hafnium oxide film 54 has each corner 18a (9a) on the side protruding toward the silicon substrate 2 among the corners of the polycrystalline silicon layer 18 (control gate electrode 9). It is formed in the vicinity.

  Further, each corner portion 9 a on the side of the polycrystalline silicon layer 18 that protrudes toward the silicon substrate 2 is formed such that the lower end portion thereof is located in the middle portion of the inclined portion 54 a of the hafnium oxide film 54. That is, each corner 18a on the side of the polycrystalline silicon layer 18 that protrudes toward the silicon substrate 2 has the lower end portion of the hafnium oxide film 54 excluding the inclined portion 54a of the hafnium oxide film 54 and the lowest flat portion 54c. It is formed at a position lower than the high flat portion 54b. In other words, the highest flat portion 54b of the hafnium oxide film 54 excluding the inclined portion 54a and the lowest flat portion 54c of the hafnium oxide film 54 is formed on each side of the polycrystalline silicon layer 18 that protrudes toward the silicon substrate 2. It is formed at a position higher than the lower end of the corner 18a.

  Thereafter, although a specific and detailed description accompanying illustration is omitted, an interlayer insulating film, a bit line, and the like are formed using a known technique as in the first and second embodiments. Thereby, the nonvolatile memory of this embodiment having the memory cell structure shown in FIG. 17 is manufactured.

  As described above, according to the fourth embodiment, the same effects as those of the first to third embodiments described above can be obtained. In the first embodiment, the main charge trap layer (hafnium oxide film) 15 in the intermediate layer 24 of the interelectrode insulating film 8 is formed in the central portion between the floating gate electrode 7 and the control gate electrode 9. In each of the second and third embodiments, the main charge trap layer 15 in the intermediate layers 34 and 44 of the interelectrode insulating films 31 and 41 is entirely connected to the floating gate electrode 7 and the control gate electrode 9 respectively. It was formed close to the floating gate electrode 7 or close to the control gate electrode 9 from the central portion between them.

  On the other hand, in the present embodiment, as described above, the vicinity of each corner 7a on the side of each phosphorus-doped polycrystalline silicon layer (floating gate electrode) 7 facing the control gate electrode 9 (interelectrode insulating film 58). Then, the main charge trap layer 54 in the intermediate layer 59 of the interelectrode insulating film 58 is formed close to the phosphorus-doped polycrystalline silicon layer 7 from the central portion between the floating gate electrode 7 and the control gate electrode 9. At the same time, in the vicinity of each corner 18a (9a) on the side of the polycrystalline silicon layer 18 (control gate electrode 9) protruding toward the silicon substrate 2, the main charge trap layer 54 is connected to the floating gate electrode 7 and the control gate electrode. 9 is formed close to the polycrystalline silicon layer 18 from the central portion between the two. Each phosphorus-doped polycrystalline silicon layer (floating gate electrode) 7 protrudes toward the silicon substrate 2 in the vicinity of each corner 7a on the side facing the control gate electrode 9 and in the polycrystalline silicon layer 18 (control gate electrode 9). The main charge trap layer 54 is formed in the central portion between the floating gate electrode 7 and the control gate electrode 9 as in the first embodiment, except for the vicinity of each corner 18a (9a) on the side to be processed.

  According to such a configuration, the effects of the second and third embodiments can be obtained together. That is, according to the present embodiment, the leakage current at the corner of the floating gate electrode 7 at the time of writing data to the memory cell and the leakage current at the corner of the control gate electrode 9 at the time of erasing the data in the memory cell. In addition, it is possible to obtain an extremely excellent effect that it can be reduced as compared with the first embodiment.

  Note that the nonvolatile semiconductor memory device and the manufacturing method thereof according to the present invention are not limited to the first to fourth embodiments described above. Without departing from the spirit of the present invention, a part of the configuration or manufacturing process can be changed to various settings, or various settings can be appropriately combined and used. .

  For example, in each of the first to fourth embodiments, a hafnium oxide layer serving as a main charge trapping layer is provided in the middle of the two upper and lower alumina films 14, 16, 32, 33, 42, 43, 51, 55. By sandwiching 15 and 54, charge trap layers (intermediate layers) 24, 34, 44 and 59 of the interelectrode insulating films 8, 31, 41 and 58 are formed. However, the configuration and formation method of the intermediate layer are not limited to these. As long as the intermediate layer is configured and formed by a combination of a film having a high charge trap density and a film having a low charge trap density, other materials may be used, or other formation methods may be used.

  In general, hafnium oxide, which is an oxide of hafnium (Hf), which is an element of group IV-A, has many defects such as oxygen vacancies in the bulk and has a high charge trap density. Therefore, it is suitable for use as a main charge trap layer as in the first to fourth embodiments. However, according to the results investigated by the inventors of the present application, even if the main charge trapping layer is formed using an oxide containing an IV-A group element other than hafnium, the same effect as hafnium oxide is obtained. Turned out to be. Examples of such elements include zirconium (Zr) and titanium (Ti). In addition to the IV-A group, the main charge trapping layer can obtain the same effect as hafnium oxide even if it is formed using an oxide containing a group III-A or VA group element, for example. I understood. Examples of such an element include lanthanum (La) in the case of a group III-A element. Moreover, tantalum (Ta) etc. are mentioned if it is a VA group element. Further, even if the main charge trap layer is formed using a film containing silicon and nitrogen (N) such as a silicon nitride film (SiN film) instead of hafnium oxide, each of the first to fourth embodiments. It was found that the same effect can be obtained.

  Further, the method of forming the main charge trap layer in the intermediate layer is not limited to the ALD method described above. The main charge trap layer may be formed by other methods. For example, the main charge trap layer may be formed by radical nitriding the central portion of the alumina film. More preferably, the charge retention characteristics can be further improved by forming the main charge trap layer into an isolated island shape and forming an island.

  In each of the first to fourth embodiments, the nonvolatile memory 1 that mainly uses the floating gate electrode 7 for the charge storage layer and the interelectrode insulating films 8, 31, and 41 have been described. However, the present invention is not limited to this. Not. In the present invention, for example, the charge storage layer is formed using a silicon nitride film which is a kind of insulating film instead of the phosphorus-doped polycrystalline silicon layer 7 and the control gate electrode is formed of a metal (conductor). It can also be applied to a non-volatile memory having a mold structure. The interelectrode insulating films 8, 31, 41 according to the present invention can also be applied to a charge block insulating film in a MONOS type nonvolatile memory.

  Further, by providing a nitride film at the interface between the upper and lower silicon oxide films 13, 17 and the floating gate electrode 9 and the control gate electrode 9, bird's beaks in the interelectrode insulating films 8, 31, 41, 58 may be suppressed. Absent. Such a configuration is particularly effective for suppressing bird's beaks in the upper and lower silicon oxide films 13 and 17.

  Furthermore, the shape of each recessed part 53 of 4th Embodiment is not limited to the inverted trapezoid shape mentioned above. Each recess 53 may be formed in a so-called bowl shape in which a side surface and a bottom surface are curved. At the same time, the shape of the hafnium oxide film (fourth insulating film) 54 formed so as to cover the lower alumina film 51 in which the respective recesses 53 are formed is also obtained by bending a straight line as described above at a plurality of positions in the intermediate portion. It is not limited to a polygonal line shape. The hafnium oxide film 54 may be formed, for example, in a curved shape represented by a so-called wave shape in which the entire upwardly convex curve and downwardly convex curve are alternately and smoothly connected. Absent. The hafnium oxide film 54 is close to the floating gate electrode 7 from the central portion between the floating gate electrode 7 and the control gate electrode 9 at least in the vicinity of each corner 7a on the side of the floating gate electrode 7 facing the control gate electrode 9. The control gate electrode 9 is formed from the central portion between the floating gate electrode 7 and the control gate electrode 9 in the vicinity of each corner portion 9a on the side of the control gate electrode 9 protruding toward the silicon substrate 2. What is necessary is just to form near.

1 is a cross-sectional view schematically showing the structure of a nonvolatile semiconductor memory device according to a first embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on 1st Embodiment. The figure which shows typically the state of the energy band at the time of the write-in and the erase | elimination of the non-volatile semiconductor memory device which concerns on the comparative example with respect to 1st Embodiment. The figure which shows typically the state of the energy band at the time of the write-in and the erase | elimination of the non-volatile semiconductor memory device which concerns on 1st Embodiment. The figure which shows the CV curve showing the relationship between the electric capacity of an insulating film, and the gate voltage applied to an insulating film by a graph for every kind of insulating film. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on 2nd Embodiment. The figure which shows typically the state of the energy band at the time of writing of the non-volatile semiconductor memory device which concerns on 2nd Embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on 3rd Embodiment. The figure which shows typically the state of the energy band at the time of the erase | elimination of the non-volatile semiconductor memory device concerning 3rd Embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on 4th Embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on 4th Embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on 4th Embodiment.

Explanation of symbols

1 ... nonvolatile memory (nonvolatile semiconductor memory device), 2 ... silicon substrate (semiconductor substrate), 6 ... silicon oxide film (SiO ₂ film, the tunnel insulating film, a first insulating film), 7 ... phosphorus-doped polycrystalline silicon layer (Floating gate electrode, charge storage layer), 7a... Corner of the floating gate electrode facing the control gate electrode (corner of the charge storage layer facing the control gate electrode), 8, 31, 41. Interlayer insulating film, 9... Control gate electrode, 13... Lower silicon oxide film (SiO ₂ film, first layer interelectrode insulating film, second insulating film), 9 a. Corners (corners on the side of the control gate electrode protruding toward the semiconductor substrate), 14, 32, 42, 51... Lower alumina film (Al ₂ O ₃ film, second-layer inter-electrode insulating film) , Third insulating film), 15, 54... Hafni oxide Arm film (HfO ₂ film, a third layer insulating film, the fourth insulating film), 16,33,43,55 ... upper alumina film (Al ₂ O ₃ film, between the fourth layer of the electrode insulating Film, fifth insulating film), 17 ... upper silicon oxide film (SiO ₂ film, fifth inter-electrode insulating film, sixth insulating film), 18 ... polycrystalline silicon layer (lower control gate electrode), 18a: Corner portions of the polycrystalline silicon layer protruding toward the silicon substrate (corner portions of the control gate electrode protruding toward the semiconductor substrate), 19 ... Tungsten silicide layer (upper control gate electrode)

Claims (5)

A charge storage layer provided on a semiconductor substrate via a first insulating film;
A second insulating film provided on the charge storage layer and made of a material containing silicon and oxygen;
A third insulating film provided on the second insulating film;
A fourth insulation made of a material provided on the third insulating film, having a charge trap density higher than that of the third insulating film and having a relative dielectric constant higher than that of the second insulating film; A membrane,
A fifth insulating film made of a material provided on the fourth insulating film and having a charge trap density lower than that of the fourth insulating film;
A sixth insulating film provided on the fifth insulating film and having a relative dielectric constant lower than that of the fourth insulating film and made of a material containing silicon and oxygen;
A control gate electrode provided on the sixth insulating film;
A non-volatile semiconductor memory device comprising:   The nonvolatile semiconductor memory device according to claim 1, wherein the fourth insulating film is provided in a central portion between the charge storage layer and the control gate electrode.   The fourth insulating film is provided closer to the charge storage layer side than the central portion between the charge storage layer and the control gate electrode, or the fourth insulating film is the charge storage layer The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is provided closer to the control gate electrode side than a central portion between the control gate electrode and the control gate electrode. On the corner of the charge storage layer on the side facing the control gate electrode, the fourth insulating film is closer to the charge storage layer side than the center between the charge storage layer and the control gate electrode. Is formed,
On the corner portion of the control gate electrode that protrudes toward the semiconductor substrate, the fourth insulating film is closer to the control gate electrode than the central portion between the charge storage layer and the control gate electrode. It ’s formed close together,
Except for the corner portion of the charge storage layer facing the control gate electrode and the corner portion of the control gate electrode projecting toward the semiconductor substrate, the fourth insulating film is connected to the charge storage layer and the charge storage layer. Formed in the center between the control gate electrode,
The nonvolatile semiconductor memory device according to claim 1. A charge storage layer is provided on the semiconductor substrate via the first insulating film,
A second insulating film made of a material containing silicon and oxygen is provided on the charge storage layer,
A third insulating film is provided on the second insulating film,
A fourth insulating film made of a material having a charge trap density higher than that of the third insulating film and a relative dielectric constant higher than that of the second insulating film is provided on the third insulating film,
A fifth insulating film made of a material having a charge trap density lower than that of the fourth insulating film is provided on the fourth insulating film,
On the fifth insulating film, a sixth insulating film having a relative dielectric constant lower than that of the fourth insulating film and made of a material containing silicon and oxygen is provided.
A control gate electrode is provided on the sixth insulating film;
A method for manufacturing a nonvolatile semiconductor memory device.

Images