JP2010034139A - Thin-film transistor and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce gate/drain overlap capacity of a thin-film transistor having a GOLD structure. <P>SOLUTION: The transistor is provided with a semiconductor layer 12, having a channel region 3, a source region and a drain region 5, which are positioned on both sides of the channel region 3, and at least one lightly-doped region 4, which is sandwiched between the channel region 3 and the source region or the drain region 5 and has a lower concentration than the source region and the drain region 5; a gate insulating film 7, which is formed on the semiconductor layer 12 and is brought into contact with the channel region 3; a gate electrode 8 arranged on the gate insulating film 7 so that it is overlapped; with at least one lightly-doped region 4 and the channel region 3; and the other insulating film 6 formed between the gate insulating film 7 and the semiconductor layer 12 so that it covers at least one lightly-doped region 4. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a thin film transistor and a method for manufacturing the same.

  In recent years, a semiconductor device including a thin film transistor (TFT) has been developed. Typical examples of such a semiconductor device include an active matrix liquid crystal display device and an organic EL display device. Such a display device is used in various electronic devices including portable electronic devices such as mobile phones.

  In an active matrix display device, a number of thin film transistors (TFTs) are provided as switching elements in a display region. TFTs are roughly classified into amorphous silicon TFTs and crystalline silicon TFTs according to the crystallinity of the silicon thin film used. In general, since the field effect mobility of the crystalline silicon film is higher than that of the amorphous silicon film, the crystalline silicon TFT can operate faster than the amorphous silicon TFT.

  Therefore, when a crystalline silicon film is used, not only TFTs provided for each pixel as switching elements (referred to as “pixel TFTs”), but also peripheral circuits such as drive circuits and various functional circuits formed around the display region. TFTs constituting a circuit (referred to as “driving circuit TFTs”) can also be formed on the same substrate (monolithic).

  TFTs used for peripheral circuits are required to have high on-current characteristics (current driving capability), low off-leakage current, and high long-term reliability in addition to high operating speed.

  A conventional TFT having a single drain structure has a relatively large current driving capability, but is easily deteriorated by hot carriers. Therefore, in order to ensure long-term reliability, the driving voltage must be limited to a low voltage of several volts. I must. In addition, there is a problem that off-leakage current is large.

  On the other hand, a structure in which a low concentration impurity region (Lightly Doped Drain, hereinafter abbreviated as “LDD region”) is formed in at least one of a TFT channel region and a source region / drain region is known. Yes. Such a structure is referred to as an “LDD structure”. Since the LDD region can alleviate electric field concentration near the drain, hot carrier deterioration resistance (that is, long-term reliability) and off-leakage current can be improved as compared with the TFT having the single drain structure. However, since the LDD region becomes a resistance, the current driving capability is reduced as compared with a single drain TFT.

  Therefore, a structure in which a gate electrode is arranged so as to overlap with the LDD region via a gate insulating film has been proposed. Such a structure is referred to as a “GOLD (Gate-drain Overlapped LDD) structure”. In a TFT having a GOLD structure, when a voltage is applied to a gate electrode, electrons serving as carriers accumulate in an LDD region overlapping with the gate electrode. Therefore, since the resistance of the LDD region can be reduced without increasing the impurity concentration of the LDD region, it is possible to suppress a decrease in the current driving capability of the TFT.

However, in the TFT having the GOLD structure, the gate electrode and the LDD region are overlapped with each other via the gate insulating film, so that a so-called gate / drain overlap capacitance _Cov is generated, and a parasitic capacitance between the gate and the drain (“C _gd parasitic capacitance” ") Also increases. As a result, there is a problem that the operation speed is lower than that of the TFT having the LDD structure (a structure in which the gate electrode and the LDD region do not overlap).

  On the other hand, in Patent Document 1 and Patent Document 2, a gate electrode (referred to as “main gate electrode”) is provided so as to cover only the channel region, and on the interlayer insulating film formed on the gate electrode. , A configuration in which another gate electrode (hereinafter referred to as “sub-gate electrode”) is provided so as to overlap with the LDD region is disclosed. In the present specification, such a configuration is referred to as a double gate GOLD structure.

  Hereinafter, an example of a TFT having a double gate GOLD structure will be specifically described. FIG. 9 is a schematic cross-sectional view for explaining the configuration of the TFT disclosed in Patent Document 2. In FIG.

  A thin film transistor 500 having a double gate GOLD structure includes a semiconductor layer 110 having a channel region 102, an LDD region 104, and a source / drain region 106, a main gate electrode 112 covering the channel region 102, a main gate electrode 112, and a semiconductor layer 110. And a gate insulating film 114 provided between them and interlayer insulating films 116a and 116b covering the semiconductor layer 110 and the main gate electrode 112. A source / drain electrode 118 and a sub-gate electrode 120 are provided on the interlayer insulating films 116a and 116b. The sub-gate electrode 120 is disposed so as to overlap with the channel region 102 and the LDD region 104, and is electrically connected to the main gate electrode 112 through contact holes formed in the interlayer insulating films 116a and 116b. On the other hand, the source / drain electrodes 118 are electrically connected to the source / drain regions 106 through contact holes formed in the interlayer insulating films 116a and 116b and the gate insulating film 114, respectively.

In the thin film transistor 500 having such a double gate GOLD structure, the relatively thick interlayer insulating films 116 a and 116 b exist between the LDD region 104 and the sub-gate electrode 120 in addition to the gate insulating film 114. C _gd parasitic capacitance can be made smaller than that of the GOLD structure.
JP 2003-17502 A JP 2004-247536 A

  According to the double gate GOLD structure as illustrated in FIG. 9, since the sub-gate electrode 120 is disposed on the interlayer insulating film 116b, ion implantation cannot be performed on the semiconductor layer 110 using the sub-gate electrode 120 as a mask. Therefore, it is difficult to arrange the LDD region 104 so as to overlap the sub-gate electrode 120 by self-alignment. For this reason, the TFT characteristics may vary due to the misalignment between the LDD region 104 and the sub-gate electrode 120.

  Further, since it is necessary to contact the main gate electrode 112 and the sub-gate electrode 120 through contact holes formed in the interlayer insulating films 116a and 116b, the device size is increased.

In addition, there are the following problems. According to the GOLD structure, as described above, there is an advantage that the resistance of the LDD region at the time of TFT operation is suppressed and the current driving force is increased. However, the desired operating speed can be realized while fully utilizing this advantage. In order to reduce the C _gd parasitic capacitance, it is necessary to optimize the thickness of the insulating layer between the sub-gate electrode 120 and the LDD region 104. If the insulating layer between them becomes too thick, the resistance of the LDD region, which is the merit of the GOLD structure, cannot be lowered sufficiently. Conversely, if the insulating layer becomes too thin, the C _gd parasitic capacitance cannot be reduced sufficiently. It is. However, in the conventional TFT shown in FIG. 9, the thickness of the insulating layer between the sub-gate electrode 120 and the LDD region 104 (the total thickness of the gate insulating film 114 and the interlayer insulating films 116a and 116b) is the same as the interlayer insulating film 116a. , 116b, and it is difficult to set the optimum value in consideration of the resistance of the LDD region and the C _gd parasitic capacitance.

  The present invention has been made in view of the above circumstances, and its main object is to reduce gate / drain overlap capacitance while securing high current driving capability in a thin film transistor having a GOLD structure.

  The thin film transistor of the present invention is sandwiched between a channel region, a source region and a drain region located on both sides of the channel region, and at least one of the channel region, the source region, and the drain region, A semiconductor layer having at least one low-concentration impurity region having an impurity concentration lower than that of the drain region; a gate insulating film formed on the semiconductor layer and in contact with the channel region; and the at least one on the gate insulating film Another insulation formed so as to cover the at least one low-concentration impurity region between the low-concentration impurity region and the gate electrode arranged to overlap the channel region, the gate insulating film, and the semiconductor layer And a membrane.

  In a preferred embodiment, the gate electrode is formed from a single conductive film.

  The thickness of the other insulating film may be equal to or greater than the thickness of the gate insulating film.

  In a preferred embodiment, an end portion of the gate electrode is aligned with an end portion of the at least one low-concentration impurity region opposite to the channel region.

  Another thin film transistor of the present invention is formed on a substrate and includes a channel region, a source region and a drain region located on both sides of the channel region, and at least one of the channel region, the source region, and the drain region, respectively. A semiconductor layer sandwiched between and having at least one low-concentration impurity region having an impurity concentration lower than that of the source region and the drain region, a gate insulating film formed on the substrate side of the semiconductor layer, and the gate insulating film And at least part of the low-concentration impurity region and the channel region, and overlaps the at least one low-concentration impurity region between the gate insulating film and the gate electrode. And the gate electrode is formed on the front side of the gate insulating film. It is in contact with the portion located below the channel region.

  The method of manufacturing a thin film transistor of the present invention includes a step of forming a semiconductor layer on a substrate, a step of forming an insulating film on the semiconductor layer, and at least a portion of the semiconductor layer that becomes a channel region in the insulating film. Forming a partly exposed opening; forming a gate insulating film on the insulating film so as to be in contact with the semiconductor layer in the opening of the insulating film; and a conductive film on the gate insulating film Forming a gate electrode that overlaps a portion that becomes a channel region and a portion that becomes a low-concentration impurity region in the semiconductor layer.

  In a preferred embodiment, the step of forming an opening in the insulating film includes a step of performing wet etching on the insulating film using the semiconductor layer as an etch stop layer.

  In a preferred embodiment, the method further includes forming a source region and a drain region in the semiconductor layer by implanting impurity ions into the semiconductor layer using the gate electrode as a mask.

  According to the present invention, in the thin film transistor having the GOLD structure, the gate / drain overlap capacitance can be reduced while ensuring the on-current characteristics of the thin film transistor. Therefore, it is possible to provide a thin film transistor capable of operating at a higher speed than conventional.

  In addition, according to the present invention, since the LDD region of the thin film transistor can be formed by self-alignment, variations in transistor characteristics due to misalignment can be suppressed.

  Furthermore, since the thickness of the insulating layer between the LDD region and the gate electrode can be easily optimized, the gate / drain overlap capacitance can be reduced to a desired value while suppressing the resistance of the LDD region.

(Embodiment 1)
Hereinafter, a first embodiment of a thin film transistor according to the present invention will be described with reference to the drawings. The present embodiment is widely applied to various functional circuits using thin film transistors, active matrix substrates, display devices such as liquid crystal display devices and organic EL display devices, and devices including thin film transistors including contact image sensors. In particular, it is suitably used for a drive circuit and a functional circuit of a liquid crystal display device or an organic EL display device.

  1A and 1B are a schematic cross-sectional view and a plan view, respectively, of the thin film transistor of this embodiment. FIG. 1A shows a cross section taken along line 1A-1A ′ of FIG.

  The thin film transistor 100 includes a substrate 1, an insulating base film 2 formed on the surface of the substrate 1, a semiconductor layer 12 formed on the base film 2, and a gate insulating film 7 on the semiconductor layer 12. The gate electrode 8 and the source / drain electrode 10 are provided. The semiconductor layer 12 is located between the channel region 3, the source / drain region (high-concentration impurity region) 5 located on both sides of the channel region 3, and the channel region 3 and the source / drain region 5, respectively. A low-concentration impurity (LDD) region 4 having an impurity concentration lower than that of the drain region 5; An insulating film 6 is formed between the gate insulating film 7 and the semiconductor layer 12 so as to cover the LDD region 4. The insulating film 6 is patterned so as to have an opening on the channel region 3, and the gate insulating film 7 formed on the insulating film 6 is connected to the channel region 3 of the semiconductor layer 12 within the opening of the insulating film 6. It touches.

  The gate electrode 8 is disposed on the gate insulating film 7 so as to overlap the channel region 3 and the LDD region 4. Here, the end of the gate electrode 8 and the end of the LDD region 4 on the source / drain region 5 side (end opposite to the channel region 3) are aligned, and the entire LDD region 4 is the gate electrode 8. Covered with.

  An interlayer insulating film 9 is formed on the gate electrode 8 so as to cover the semiconductor layer 12, and a source / drain electrode 10 is provided on the interlayer insulating film 9. The source / drain electrodes 10 are electrically connected to the source / drain regions 5 of the semiconductor layer 12 through contact holes formed in the interlayer insulating film 9, the gate insulating film 7 and the insulating film 6, respectively.

In the thin film transistor 100, the thickness of the insulating layer between the channel region 3 and the gate electrode 8 is the thickness t1 of the gate insulating film 7, and the thickness of the insulating layer between the LDD region 4 and the gate electrode 8 is the gate insulation. The total thickness (t1 + t2) of the thickness t1 of the film 7 and the thickness t2 of the insulating film 6 is obtained. Thus, since the thickness of the insulating layer between the LDD region 4 and the gate electrode 8 can be made larger than the thickness of the insulating layer between the channel region 3 and the gate electrode 8, the drain-side LDD region 4 and The overlapping capacitance C _ov generated between the gate electrode 8 can be reduced.

  In the thin film transistor 100, the LDD regions 4 are formed on both sides of the channel region 3, but the LDD regions 4 are provided at positions sandwiched between at least one of the source / drain regions 5 and the channel region 3. It may be provided only on one side of the channel region 3. When the source side and the drain side of the thin film transistor 100 are sometimes used interchangeably, it is preferable to provide the LDD region 4 between the channel region 3 and the source / drain region 5, respectively. In the case where the drain side and the drain side are not interchanged, it is preferable to form the LDD region 4 only between the channel region 3 and the drain region 5 in order to suppress a decrease in current driving force. In addition, the gate electrode 8 in the present embodiment may be disposed so as to overlap the LDD region 4 (GOLD structure), and may overlap the entire LDD region 4 as illustrated, or the LDD region 4 It may overlap with only a part.

  The insulating film 6 only needs to be patterned so as to cover at least part of the LDD region 4 and open at least part of the channel region 3. If at least a part of the LDD region 4 is covered, the gate / drain overlap capacitance can be reduced. Further, if patterning is performed so that at least a part of the channel region 3 is opened, the gate insulating film 7 can be disposed so as to be in contact with the channel region 3, so that a decrease in on-current due to the insulating film 6 can be suppressed. . However, the insulating film 6 is preferably designed so as to cover the LDD region 4 and not to overlap the channel region 3 as shown in FIG. 1, thereby ensuring high on-current characteristics, Gate / drain overlap capacitance can be reduced more effectively. Alternatively, the insulating film 6 may be patterned so as not to overlap with the channel region 3 and the source / drain region 5 but only with the LDD region 4. Even in this case, the same effect as the configuration shown in FIG. can get.

  Hereinafter, the effect of reducing the gate / drain overlap capacitance of the present embodiment will be described in more detail with reference to the drawings. 2A and 2B are a cross-sectional view and a plan view of a general thin film transistor having a GOLD structure. For simplicity, the same components as those in FIG.

In the conventional thin film transistor 600 shown in FIGS. 2A and 2B, the thickness of the insulating layer between the gate electrode 8 and the LDD region 4 is the same as the thickness of the insulating layer between the gate electrode 8 and the channel region 3. Equal to the thickness t1 of the gate insulating film 7. The gate / drain overlap capacitance C _ov ′ of the thin film transistor 600 is proportional to the area of the overlapping portion between the gate electrode 8 and the LDD region 4 and inversely proportional to the thickness of the gate insulating film 7. When the length in the channel direction of the LDD region 4 is L _ov , the width perpendicular to the channel direction of the semiconductor layer 12 is W, and the relative dielectric constant of the gate insulating film 7 is ε _ox , the gate / drain overlap capacitance C _ov ′ is It is expressed by a formula.

C _ov '= ε _ox × L _ov × W / t1 (1)
On the other hand, in the thin film transistor 100 of this embodiment shown in FIGS. 1A and 1B, the gate / drain overlap capacitance _Cov is proportional to the area of the overlapping portion of the gate electrode 8 and the LDD region 4. The thickness of the insulating layer between the gate electrode 8 and the LDD region 4, that is, the total thickness (t 1 + t 2) of the gate insulating film 7 and the insulating film 6 is inversely proportional. Therefore, the length in the channel direction of the LDD region 4 is L _ov , the width perpendicular to the channel direction of the semiconductor layer 12 is W, and the relative dielectric constant of the gate insulating film 7 and the insulating film 6 (for simplicity, the gate insulating film 7 and It is assumed that the insulating film 6 is made of the same material and has the same dielectric constant.) Ε _ox , the gate / drain overlap capacitance C _ov is expressed by the following equation.

C _ov = ε _ox × L _ov × W / (t1 + t2) (2)
Thus, according to the present embodiment, the gate / drain overlap capacitance C _ov (Equation (2)) can be made significantly smaller than the conventional gate / drain overlap capacitance C _ov ′ (Equation (1)). Therefore, it is possible to improve the decrease in operation speed due to the gate / drain overlap capacitance.

  Further, according to the present embodiment, there are the following merits as compared with the TFT having the double gate GOLD structure described above with reference to FIG.

  In the TFT having the double gate GOLD structure, as described above, since the sub gate electrode is formed on the interlayer insulating film, the LDD region cannot be formed by self-alignment using the pattern of the sub gate electrode. For this reason, there is a possibility that characteristic variation due to misalignment may occur between the LDD region and the sub-gate electrode. On the other hand, according to the present embodiment, as will be described later, it becomes possible to perform ion implantation for forming the LDD region 4 using the gate electrode 8 as a mask, and alignment deviation does not occur.

  In the present embodiment, the thickness of the insulating layer between the LDD region 4 and the gate electrode 8 can be set with a high degree of freedom separately from the thickness of the interlayer insulating film 9. Specifically, since the thickness of the insulating layer is easily adjusted by controlling the thickness of the insulating film 6, the resistance of the LDD region 4 is lowered by the GOLD structure to ensure a high on-current. The gate / drain overlap capacitance can be reduced to a desired range.

  The gate electrode 8 in this embodiment is preferably formed from a single conductive film. Here, “formed from a single conductive film” is not only formed by patterning a single conductive film, but also formed by patterning a conductive film having a laminated structure. Including cases. This eliminates the need to contact the two gate electrodes unlike the TFT having the double gate GOLD structure, so that the gate / drain overlap capacitance can be reduced without complicating the manufacturing process. Further, in the TFT having the double gate GOLD structure, it is necessary to provide a region for contacting the main gate electrode and the sub gate electrode in the element. However, in this embodiment, it is not necessary to provide such a region. The size can be reduced.

  Next, a method for manufacturing the thin film transistor 100 of this embodiment will be described. 3A to 3H are process cross-sectional views for explaining an example of a method for manufacturing the thin film transistor 100. FIG. In the illustrated example, one TFT is formed on a substrate (support). Typically, a plurality of TFTs are formed on the same substrate.

First, as shown in FIG. 3A, the semiconductor layer 12 is formed on the substrate 1. Although not shown, an insulating base film may be formed on the surface of the substrate 1. When the base film is not formed, a substrate having an insulating surface such as a quartz substrate or a glass substrate can be used as the substrate 1. When the base film is formed, the substrate 1 may be a Si substrate or a metal substrate in addition to the quartz substrate and the glass substrate. For example, a laminated film composed of a SiN film and a SiO ₂ film may be deposited on the substrate 1 by a CVD method or a sputtering method, and the semiconductor layer 12 may be formed thereon.

  The semiconductor layer 12 is formed by forming a crystalline silicon film (thickness: for example, 40 nm or more and 200 nm or less) and patterning as necessary. The crystalline silicon film can be formed as follows. First, an amorphous silicon film is deposited on the substrate 1 by the CVD method. Thereafter, the amorphous silicon film is crystallized by irradiating with laser light. As the laser beam, a pulse oscillation type or continuous oscillation type excimer laser beam is desirable, but a continuous oscillation type argon laser beam may be used. In addition, after a catalytic element for promoting crystallization, such as Ni, is attached to the surface of the amorphous silicon film, the amorphous silicon film may be crystallized by heat treatment (for example, laser irradiation).

Subsequently, as shown in FIG. 3B, an insulating film 6 made of, for example, a SiO ₂ film (relative dielectric constant: 3.9) (thickness t2: 50 nm) is formed on the semiconductor layer 12 by a CVD method or the like. Form. Thereafter, if necessary, channel doping for adjusting the threshold voltage of the transistor may be performed.

Next, as shown in FIG. 3C, a resist layer 22 is formed on the insulating film 6, and impurity ions (for example, phosphorus) are implanted into the semiconductor layer 12 using the resist layer 22 as a mask (first implantation). Process). In the present embodiment, the acceleration voltage when phosphorus ions are implanted is 50 kV, and the phosphorus dose is 3 × 10 ¹³ atoms / cm ² . As a result, impurity ions are implanted at a low concentration into the region 4 ′ of the semiconductor layer 12 that does not overlap the resist layer 22. A region of the semiconductor layer 12 that overlaps the resist layer 22 is a channel region (channel length: 4 μm, for example) 3. Thereafter, the resist layer 22 is removed.

  Next, as shown in FIG. 3D, a resist layer 24 that opens the channel region 3 in the semiconductor layer 12 is newly formed, and on the channel region 3 in the insulating film 6 using the resist layer 24 as a mask. Remove the located part. As a removal method, a known etching method can be applied, but wet etching is preferably used. For example, when wet etching is performed using hydrogen fluoride as an etchant, the semiconductor layer (Si layer) 12 functions as an etch stop layer, so that only the insulating film 6 can be easily formed without damaging the surface of the semiconductor layer 12. Can be etched. In addition, although dry etching can be applied instead of wet etching, in that case, it is preferable to form a protective film on the semiconductor layer 12.

  By the etching, an opening that exposes at least a part of the channel region 3 is formed in the insulating film 6. The insulating film 6 only needs to cover at least a part of the region that becomes the LDD region of the semiconductor layer 12, and may not cover the region that becomes the source / drain region, for example.

Next, after removing the resist layer 24, as shown in FIG. 3E, a gate insulating film (thickness t1: 30 nm) 7 made of, for example, a SiO ₂ film (relative dielectric constant: 3.9) is formed. The gate insulating film 7 is formed in contact with the channel region 3 of the semiconductor layer 12 within the opening of the insulating film 6.

  Subsequently, as shown in FIG. 3F, a conductive film (thickness: 200 nm) is formed on the gate insulating film 7, and the conductive film is patterned to form the gate electrode 8. The gate electrode 8 is formed so as to cover the region serving as the LDD region and the channel region 3 in the semiconductor layer 12. The gate electrode 8 may have a single layer structure formed using a W film or the like, for example, a TaN film, a two layer structure formed by stacking a W film, or a stack of three or more layers. You may have a structure.

Next, as shown in FIG. 3G, impurity ions (for example, phosphorus ions) are implanted into the semiconductor layer 12 using the gate electrode 8 as a mask (second implantation step). In this embodiment, the acceleration voltage when phosphorus ions are implanted is set to 50 kV, and the dose amount of phosphorus is set to 3 × 10 ¹⁵ atoms / cm ² or less. As a result, the source / drain regions 5 are formed in the semiconductor layer 12. On the other hand, in the semiconductor layer 12, impurity ions are implanted at a low concentration in the first implantation step described above, and in this step, the region 4 masked by the gate electrode 8 and not implanted with impurity ions becomes an LDD region. Here, an LDD region 4 having a length of 2 μm in the channel direction is formed between the channel region 3 and the source / drain regions 5, respectively. The length of the LDD region 4 in the channel direction is not limited to the above length, and can be appropriately selected depending on the power supply voltage used and the alignment accuracy during photoengraving. The LDD region 4 may be formed only on the drain side of the channel region 3.

  After the second implantation step, heat treatment is preferably performed to reduce the resistance of the source / drain region 5. As the heat treatment, furnace annealing, laser annealing, or lamp annealing can be performed.

Thereafter, as shown in FIG. 3 (h), an interlayer insulating film 9 is formed so as to cover the gate electrode 8, and then the interlayer insulating film 9, the gate insulating film 7 and the insulating film 6 are formed in the source / drain region 5. Each contact hole is formed. In the present embodiment, a laminated film composed of a SiN film (thickness: 300 nm) and a SiO ₂ film (thickness: 700 nm) is used as the interlayer insulating film 9. The structure of the interlayer insulating film 9 is not limited to this, and for example, a single layer structure of a SiO ₂ film may be used. Thereafter, a conductive film is formed on the interlayer insulating film 9 (including the inside of the contact hole) by, for example, sputtering, and the conductive film is patterned to form the source / drain electrodes 10. The conductive film may be a laminated film of TiN / Al / TiN / Ti from the upper layer, or may be a single layer film of Al, Cu or the like. In this way, the thin film transistor 100 is obtained.

The material and thickness of each layer included in the thin film transistor 100 are not limited to the materials and thicknesses exemplified by the above method. For example, as the insulating film 6 and the gate insulating film 7, an SiON film may be used in addition to the SiO ₂ film. The materials of the insulating film 6 and the gate insulating film 7 may be different from each other. As the material of the insulating film 6, a material having a relative dielectric constant ε smaller than that of the material of the gate insulating film 7 may be selected, thereby reducing the gate / drain overlap capacitance while suppressing the thickness of the insulating film 6. Is possible.

  The thickness t2 of the insulating film 6 is not particularly limited, but is preferably equal to or greater than the thickness t1 of the gate insulating film 7 (t2 ≧ t1). Thereby, the gate-drain overlap capacitance can be more effectively reduced. On the other hand, if the insulating film 6 is too thick, the on-resistance of the LDD region 4 cannot be sufficiently reduced, and a high current driving force cannot be obtained.

  Moreover, the manufacturing method of this embodiment is not limited to the said method. For example, when the channel length is sufficiently large, the patterning step of the insulating film 6 (FIG. 3D) can be performed by lift-up. Further, a P-channel thin film transistor can be manufactured by doping the semiconductor layer 12 with boron or the like as an impurity instead of phosphorus.

  Next, a simulation for comparing the operation speed between the thin film transistor 100 of the present embodiment and the conventional thin film transistor 600 shown in FIG. 2 was performed, and the result will be described.

  In the simulation, as shown in FIG. 4, the input / output delay time of a model in which 10 stages of inverters are connected in series was obtained. Specifically, the thin film transistor 100 (FIG. 1) is used as the N-channel TFT of each inverter, the conventional thin film transistor 600 (FIG. 2) is used as the P-channel TFT, and the N-channel and P-channel of each inverter. The delay between the signal input to the first-stage inverter and the signal output from the tenth-stage inverter is compared to the comparative model 2 using the conventional thin film transistor 600 (FIG. 2) as the type TFT. Time was calculated. Note that the thickness t1 of the gate insulating film and the thickness t2 of the insulating film of the thin film transistor 100 in the model 1 are the same (t1 = t2 = tm). In addition, the thickness t1 of the gate insulating film of the thin film transistor 600 in the models 1 and 2 is the same as the thickness of the gate insulating film t1 in the thin film transistor 100 (t1 = tm).

  The simulation result is shown in FIG. From this result, it was confirmed that the delay time TD1 of the output signal with respect to the input signal of the model 1 is shorter than the delay time TD2 of the model 2 for comparison.

(Embodiment 2)
Hereinafter, a second embodiment of a thin film transistor according to the present invention will be described. The thin film transistor of this embodiment is different from the thin film transistor 100 shown in FIG. 1 in that the gate electrode partially covers the LDD region.

  FIGS. 6A and 6B are a schematic cross-sectional view and a plan view illustrating the thin film transistor of this embodiment, respectively. For simplicity, the same components as those in FIG.

In the thin film transistor 200, the gate electrode 8 is disposed so as to overlap a part of the LDD region 4 and the channel region 3. With such a configuration, not only can the thickness (t1 + t2) of the insulating layer between the gate electrode 8 and the LDD region 4 be increased, but also the area of the portion where the gate electrode 9 and the LDD region 4 overlap (L _ov × Since W) can be reduced, the gate / drain overlap capacitance can be further reduced.

  The thin film transistor 200 can be manufactured by a method similar to the method described above with reference to FIG. However, the second implantation process cannot be performed in a self-aligning manner using the gate electrode 8 as a mask. Therefore, for example, after the gate electrode 8 is formed, a resist layer is formed to cover the portion of the semiconductor layer 12 that becomes the LDD region, and impurity ions are implanted using the resist layer as a mask.

(Embodiment 3)
Hereinafter, a third embodiment of the thin film transistor according to the present invention will be described. The thin film transistor of this embodiment is different from the thin film transistor 100 having a top gate structure in that a gate electrode is provided between a semiconductor layer and a substrate (bottom gate structure).

  FIG. 7 is a schematic cross-sectional view illustrating the thin film transistor of this embodiment. For simplicity, the same components as those in FIG.

  In the thin film transistor 300, a semiconductor layer 12 is formed on a gate electrode 8 provided on a substrate 1 via a base film 2 via a gate insulating film 7. An insulating film 6 is formed between the gate insulating film 7 and the base film 2 so as not to overlap with the channel region 3 in the semiconductor layer 12 and with the LDD region 4.

  Also in this embodiment, the thickness (t1 + t2) of the insulating layer between the gate electrode 8 and the LDD region 4 is set to the insulating layer (gate) between the gate electrode 8 and the channel region 3 as in the above-described embodiment. By making it larger than the thickness t1 of the insulating film 7), it is possible to reduce the gate / drain overlap capacitance while suppressing a decrease in on-current.

  The thin film transistor 300 is manufactured by a known method. Specifically, the base film 2 and the gate electrode 8 are provided in this order on the substrate 1, and the insulating film 6 is formed thereon. The insulating film 6 is patterned so as to have an opening in a portion overlapping with the channel region. Thereafter, the gate insulating film 7 and the semiconductor layer 12 are formed. Subsequently, an LDD region 4 and source / drain regions 5 are formed in the semiconductor layer 12 by ion implantation. Further, source / drain electrodes 10 electrically connected to the source / drain regions 5 are formed. In this way, the thin film transistor 300 is obtained.

  The thin film transistor of the above-described embodiment can be applied to various display devices and semiconductor devices such as an active matrix substrate used for display devices. In such a semiconductor device, for example, as shown in FIG. 8, the above-described thin film transistor 100 and the thin film transistor 100 and another thin film transistor 400 having a different gate insulating film thickness may be formed on the same support.

  In the example shown in FIG. 8, a thin film transistor 100 and another thin film transistor 400 using a stacked film of a gate insulating film 7 and an insulating film 6 as a gate insulating film are formed on a substrate 1. The thin film transistor 400 includes a semiconductor layer 32 having a channel region 33 and source / drain regions 35, a gate electrode 38, and a source / drain electrode 39 provided on the interlayer insulating film 9. The gate electrode 38 is disposed so as to overlap the channel region 33 with the gate insulating film 2 and the insulating film 6 interposed therebetween. Although not shown, the semiconductor layer 32 may have an LDD region. In the thin film transistor 400, for example, a portion of the gate insulating film 2 located above the channel region 33 can be removed, and only the insulating film 6 can be used as the gate insulating film.

  As described above, according to the present invention, in a circuit including a plurality of thin film transistors, the thin film transistors 100 and 400 having different structures according to required characteristics can be formed over the same substrate. In addition, these thin film transistors 100 and 400 can be manufactured by the same process, which is advantageous without complicating the manufacturing process.

  The present invention can be widely applied to devices (semiconductor devices) including thin film transistors such as active matrix substrates, display devices such as liquid crystal display devices and organic EL display devices, and various integrated circuits. In particular, it can be suitably used for applications that require high current driving capability and high-speed operation, such as a display device driving circuit.

(A) And (b) is respectively typical sectional drawing and top view of the thin-film transistor of Embodiment 1 by this invention. (A) And (b) is a typical sectional view and a top view of a conventional thin-film transistor, respectively. (A)-(h) is process sectional drawing for demonstrating the manufacturing method of the thin-film transistor of Embodiment 1 by this invention. It is a figure which shows the structure of the model used by simulation. It is a figure which shows the simulation result of the input / output delay time of the model shown in FIG. (A) And (b) is a typical sectional view and a top view of a thin-film transistor of Embodiment 2 by the present invention, respectively. It is typical sectional drawing of the thin-film transistor of Embodiment 3 by this invention. It is typical sectional drawing which illustrates the apparatus provided with the thin-film transistor of this invention. It is typical sectional drawing of the conventional TFT which has a GOLD structure.

Explanation of symbols

1 Substrate 2 Base film 3 Channel region 4 LDD region (low concentration impurity region)
5 Source / drain regions (high-concentration impurity regions)
6 Insulating film 7 Gate insulating film 8 Gate electrode 9 Interlayer insulating film 10 Source / drain electrode 12 Semiconductor layer 22, 24 Resist layer 100, 200, 300, 400, 500, 600 Thin film transistor

Claims (8)

Impurity concentration between the channel region, the source region and the drain region located on both sides of the channel region, and at least one of the channel region, the source region, and the drain region. A semiconductor layer having at least one low-concentration impurity region having a low
A gate insulating film formed on the semiconductor layer and in contact with the channel region;
The at least one low concentration impurity region is disposed between the gate insulating film and the semiconductor layer on the gate insulating film so as to overlap the at least one low concentration impurity region and the channel region. A thin film transistor provided with another insulating film formed so as to cover.   The thin film transistor according to claim 1, wherein the gate electrode is formed of a single conductive film.   The thin film transistor according to claim 1, wherein a thickness of the other insulating film is equal to or greater than a thickness of the gate insulating film.   4. The thin film transistor according to claim 1, wherein an end of the gate electrode is aligned with an end of the at least one low-concentration impurity region opposite to the channel region. Formed on a substrate, sandwiched between a channel region, a source region and a drain region located on both sides of the channel region, and at least one of the channel region and the source region and the drain region, and the source region and the A semiconductor layer having at least one low-concentration impurity region having an impurity concentration lower than that of the drain region;
A gate insulating film formed on the substrate side of the semiconductor layer;
A gate electrode disposed so as to overlap at least a part of the low-concentration impurity region and the channel region via the gate insulating film;
Another insulating film formed between the gate insulating film and the gate electrode so as to overlap the at least one low-concentration impurity region;
The thin film transistor in which the gate electrode is in contact with a portion of the gate insulating film located under the channel region. Forming a semiconductor layer on the substrate;
Forming an insulating film on the semiconductor layer;
Forming an opening in the insulating film to expose at least a part of a portion of the semiconductor layer that becomes a channel region;
Forming a gate insulating film on the insulating film so as to be in contact with the semiconductor layer within the opening of the insulating film;
Forming a conductive film on the gate insulating film, and patterning the conductive film, thereby forming a gate electrode overlapping with a portion to be a channel region and a portion to be a low-concentration impurity region in the semiconductor layer. A method for manufacturing a thin film transistor.   The method of manufacturing a thin film transistor according to claim 6, wherein the step of forming an opening in the insulating film includes a step of performing wet etching on the insulating film using the semiconductor layer as an etch stop layer.   8. The method of manufacturing a thin film transistor according to claim 6, further comprising a step of forming a source region and a drain region in the semiconductor layer by implanting impurity ions into the semiconductor layer using the gate electrode as a mask.

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